1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * High Speed Serial Ports on NXP LPC32xx SoC 4 * 5 * Authors: Kevin Wells <kevin.wells@nxp.com> 6 * Roland Stigge <stigge@antcom.de> 7 * 8 * Copyright (C) 2010 NXP Semiconductors 9 * Copyright (C) 2012 Roland Stigge 10 */ 11 12 #include <linux/module.h> 13 #include <linux/ioport.h> 14 #include <linux/init.h> 15 #include <linux/console.h> 16 #include <linux/sysrq.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/platform_device.h> 22 #include <linux/delay.h> 23 #include <linux/nmi.h> 24 #include <linux/io.h> 25 #include <linux/irq.h> 26 #include <linux/of.h> 27 #include <linux/sizes.h> 28 #include <linux/soc/nxp/lpc32xx-misc.h> 29 30 /* 31 * High Speed UART register offsets 32 */ 33 #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00) 34 #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04) 35 #define LPC32XX_HSUART_IIR(x) ((x) + 0x08) 36 #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C) 37 #define LPC32XX_HSUART_RATE(x) ((x) + 0x10) 38 39 #define LPC32XX_HSU_BREAK_DATA (1 << 10) 40 #define LPC32XX_HSU_ERROR_DATA (1 << 9) 41 #define LPC32XX_HSU_RX_EMPTY (1 << 8) 42 43 #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF) 44 #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF) 45 46 #define LPC32XX_HSU_TX_INT_SET (1 << 6) 47 #define LPC32XX_HSU_RX_OE_INT (1 << 5) 48 #define LPC32XX_HSU_BRK_INT (1 << 4) 49 #define LPC32XX_HSU_FE_INT (1 << 3) 50 #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2) 51 #define LPC32XX_HSU_RX_TRIG_INT (1 << 1) 52 #define LPC32XX_HSU_TX_INT (1 << 0) 53 54 #define LPC32XX_HSU_HRTS_INV (1 << 21) 55 #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19) 56 #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19) 57 #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19) 58 #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19) 59 #define LPC32XX_HSU_HRTS_EN (1 << 18) 60 #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16) 61 #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16) 62 #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16) 63 #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16) 64 #define LPC32XX_HSU_HCTS_INV (1 << 15) 65 #define LPC32XX_HSU_HCTS_EN (1 << 14) 66 #define LPC32XX_HSU_OFFSET(n) ((n) << 9) 67 #define LPC32XX_HSU_BREAK (1 << 8) 68 #define LPC32XX_HSU_ERR_INT_EN (1 << 7) 69 #define LPC32XX_HSU_RX_INT_EN (1 << 6) 70 #define LPC32XX_HSU_TX_INT_EN (1 << 5) 71 #define LPC32XX_HSU_RX_TL1B (0x0 << 2) 72 #define LPC32XX_HSU_RX_TL4B (0x1 << 2) 73 #define LPC32XX_HSU_RX_TL8B (0x2 << 2) 74 #define LPC32XX_HSU_RX_TL16B (0x3 << 2) 75 #define LPC32XX_HSU_RX_TL32B (0x4 << 2) 76 #define LPC32XX_HSU_RX_TL48B (0x5 << 2) 77 #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0) 78 #define LPC32XX_HSU_TX_TL0B (0x0 << 0) 79 #define LPC32XX_HSU_TX_TL4B (0x1 << 0) 80 #define LPC32XX_HSU_TX_TL8B (0x2 << 0) 81 #define LPC32XX_HSU_TX_TL16B (0x3 << 0) 82 83 #define LPC32XX_MAIN_OSC_FREQ 13000000 84 85 #define MODNAME "lpc32xx_hsuart" 86 87 struct lpc32xx_hsuart_port { 88 struct uart_port port; 89 }; 90 91 #define FIFO_READ_LIMIT 128 92 #define MAX_PORTS 3 93 #define LPC32XX_TTY_NAME "ttyTX" 94 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS]; 95 96 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE 97 static void wait_for_xmit_empty(struct uart_port *port) 98 { 99 unsigned int timeout = 10000; 100 101 do { 102 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 103 port->membase))) == 0) 104 break; 105 if (--timeout == 0) 106 break; 107 udelay(1); 108 } while (1); 109 } 110 111 static void wait_for_xmit_ready(struct uart_port *port) 112 { 113 unsigned int timeout = 10000; 114 115 while (1) { 116 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 117 port->membase))) < 32) 118 break; 119 if (--timeout == 0) 120 break; 121 udelay(1); 122 } 123 } 124 125 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch) 126 { 127 wait_for_xmit_ready(port); 128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); 129 } 130 131 static void lpc32xx_hsuart_console_write(struct console *co, const char *s, 132 unsigned int count) 133 { 134 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index]; 135 unsigned long flags; 136 int locked = 1; 137 138 touch_nmi_watchdog(); 139 local_irq_save(flags); 140 if (up->port.sysrq) 141 locked = 0; 142 else if (oops_in_progress) 143 locked = spin_trylock(&up->port.lock); 144 else 145 spin_lock(&up->port.lock); 146 147 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar); 148 wait_for_xmit_empty(&up->port); 149 150 if (locked) 151 spin_unlock(&up->port.lock); 152 local_irq_restore(flags); 153 } 154 155 static int __init lpc32xx_hsuart_console_setup(struct console *co, 156 char *options) 157 { 158 struct uart_port *port; 159 int baud = 115200; 160 int bits = 8; 161 int parity = 'n'; 162 int flow = 'n'; 163 164 if (co->index >= MAX_PORTS) 165 co->index = 0; 166 167 port = &lpc32xx_hs_ports[co->index].port; 168 if (!port->membase) 169 return -ENODEV; 170 171 if (options) 172 uart_parse_options(options, &baud, &parity, &bits, &flow); 173 174 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 175 176 return uart_set_options(port, co, baud, parity, bits, flow); 177 } 178 179 static struct uart_driver lpc32xx_hsuart_reg; 180 static struct console lpc32xx_hsuart_console = { 181 .name = LPC32XX_TTY_NAME, 182 .write = lpc32xx_hsuart_console_write, 183 .device = uart_console_device, 184 .setup = lpc32xx_hsuart_console_setup, 185 .flags = CON_PRINTBUFFER, 186 .index = -1, 187 .data = &lpc32xx_hsuart_reg, 188 }; 189 190 static int __init lpc32xx_hsuart_console_init(void) 191 { 192 register_console(&lpc32xx_hsuart_console); 193 return 0; 194 } 195 console_initcall(lpc32xx_hsuart_console_init); 196 197 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console) 198 #else 199 #define LPC32XX_HSUART_CONSOLE NULL 200 #endif 201 202 static struct uart_driver lpc32xx_hs_reg = { 203 .owner = THIS_MODULE, 204 .driver_name = MODNAME, 205 .dev_name = LPC32XX_TTY_NAME, 206 .nr = MAX_PORTS, 207 .cons = LPC32XX_HSUART_CONSOLE, 208 }; 209 static int uarts_registered; 210 211 static unsigned int __serial_get_clock_div(unsigned long uartclk, 212 unsigned long rate) 213 { 214 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate; 215 u32 rate_diff; 216 217 /* Find the closest divider to get the desired clock rate */ 218 div = uartclk / rate; 219 goodrate = hsu_rate = (div / 14) - 1; 220 if (hsu_rate != 0) 221 hsu_rate--; 222 223 /* Tweak divider */ 224 l_hsu_rate = hsu_rate + 3; 225 rate_diff = 0xFFFFFFFF; 226 227 while (hsu_rate < l_hsu_rate) { 228 comprate = uartclk / ((hsu_rate + 1) * 14); 229 if (abs(comprate - rate) < rate_diff) { 230 goodrate = hsu_rate; 231 rate_diff = abs(comprate - rate); 232 } 233 234 hsu_rate++; 235 } 236 if (hsu_rate > 0xFF) 237 hsu_rate = 0xFF; 238 239 return goodrate; 240 } 241 242 static void __serial_uart_flush(struct uart_port *port) 243 { 244 int cnt = 0; 245 246 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && 247 (cnt++ < FIFO_READ_LIMIT)) 248 readl(LPC32XX_HSUART_FIFO(port->membase)); 249 } 250 251 static void __serial_lpc32xx_rx(struct uart_port *port) 252 { 253 struct tty_port *tport = &port->state->port; 254 unsigned int tmp, flag; 255 256 /* Read data from FIFO and push into terminal */ 257 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 258 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) { 259 flag = TTY_NORMAL; 260 port->icount.rx++; 261 262 if (tmp & LPC32XX_HSU_ERROR_DATA) { 263 /* Framing error */ 264 writel(LPC32XX_HSU_FE_INT, 265 LPC32XX_HSUART_IIR(port->membase)); 266 port->icount.frame++; 267 flag = TTY_FRAME; 268 tty_insert_flip_char(tport, 0, TTY_FRAME); 269 } 270 271 tty_insert_flip_char(tport, (tmp & 0xFF), flag); 272 273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 274 } 275 276 spin_unlock(&port->lock); 277 tty_flip_buffer_push(tport); 278 spin_lock(&port->lock); 279 } 280 281 static void __serial_lpc32xx_tx(struct uart_port *port) 282 { 283 struct circ_buf *xmit = &port->state->xmit; 284 unsigned int tmp; 285 286 if (port->x_char) { 287 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); 288 port->icount.tx++; 289 port->x_char = 0; 290 return; 291 } 292 293 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 294 goto exit_tx; 295 296 /* Transfer data */ 297 while (LPC32XX_HSU_TX_LEV(readl( 298 LPC32XX_HSUART_LEVEL(port->membase))) < 64) { 299 writel((u32) xmit->buf[xmit->tail], 300 LPC32XX_HSUART_FIFO(port->membase)); 301 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 302 port->icount.tx++; 303 if (uart_circ_empty(xmit)) 304 break; 305 } 306 307 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 308 uart_write_wakeup(port); 309 310 exit_tx: 311 if (uart_circ_empty(xmit)) { 312 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 313 tmp &= ~LPC32XX_HSU_TX_INT_EN; 314 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 315 } 316 } 317 318 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id) 319 { 320 struct uart_port *port = dev_id; 321 struct tty_port *tport = &port->state->port; 322 u32 status; 323 324 spin_lock(&port->lock); 325 326 /* Read UART status and clear latched interrupts */ 327 status = readl(LPC32XX_HSUART_IIR(port->membase)); 328 329 if (status & LPC32XX_HSU_BRK_INT) { 330 /* Break received */ 331 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); 332 port->icount.brk++; 333 uart_handle_break(port); 334 } 335 336 /* Framing error */ 337 if (status & LPC32XX_HSU_FE_INT) 338 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); 339 340 if (status & LPC32XX_HSU_RX_OE_INT) { 341 /* Receive FIFO overrun */ 342 writel(LPC32XX_HSU_RX_OE_INT, 343 LPC32XX_HSUART_IIR(port->membase)); 344 port->icount.overrun++; 345 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 346 tty_schedule_flip(tport); 347 } 348 349 /* Data received? */ 350 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) 351 __serial_lpc32xx_rx(port); 352 353 /* Transmit data request? */ 354 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) { 355 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); 356 __serial_lpc32xx_tx(port); 357 } 358 359 spin_unlock(&port->lock); 360 361 return IRQ_HANDLED; 362 } 363 364 /* port->lock is not held. */ 365 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port) 366 { 367 unsigned int ret = 0; 368 369 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) 370 ret = TIOCSER_TEMT; 371 372 return ret; 373 } 374 375 /* port->lock held by caller. */ 376 static void serial_lpc32xx_set_mctrl(struct uart_port *port, 377 unsigned int mctrl) 378 { 379 /* No signals are supported on HS UARTs */ 380 } 381 382 /* port->lock is held by caller and interrupts are disabled. */ 383 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port) 384 { 385 /* No signals are supported on HS UARTs */ 386 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 387 } 388 389 /* port->lock held by caller. */ 390 static void serial_lpc32xx_stop_tx(struct uart_port *port) 391 { 392 u32 tmp; 393 394 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 395 tmp &= ~LPC32XX_HSU_TX_INT_EN; 396 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 397 } 398 399 /* port->lock held by caller. */ 400 static void serial_lpc32xx_start_tx(struct uart_port *port) 401 { 402 u32 tmp; 403 404 __serial_lpc32xx_tx(port); 405 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 406 tmp |= LPC32XX_HSU_TX_INT_EN; 407 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 408 } 409 410 /* port->lock held by caller. */ 411 static void serial_lpc32xx_stop_rx(struct uart_port *port) 412 { 413 u32 tmp; 414 415 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 416 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 417 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 418 419 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT | 420 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase)); 421 } 422 423 /* port->lock is not held. */ 424 static void serial_lpc32xx_break_ctl(struct uart_port *port, 425 int break_state) 426 { 427 unsigned long flags; 428 u32 tmp; 429 430 spin_lock_irqsave(&port->lock, flags); 431 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 432 if (break_state != 0) 433 tmp |= LPC32XX_HSU_BREAK; 434 else 435 tmp &= ~LPC32XX_HSU_BREAK; 436 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 437 spin_unlock_irqrestore(&port->lock, flags); 438 } 439 440 /* port->lock is not held. */ 441 static int serial_lpc32xx_startup(struct uart_port *port) 442 { 443 int retval; 444 unsigned long flags; 445 u32 tmp; 446 447 spin_lock_irqsave(&port->lock, flags); 448 449 __serial_uart_flush(port); 450 451 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 452 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 453 LPC32XX_HSUART_IIR(port->membase)); 454 455 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 456 457 /* 458 * Set receiver timeout, HSU offset of 20, no break, no interrupts, 459 * and default FIFO trigger levels 460 */ 461 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 462 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 463 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 464 465 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 466 467 spin_unlock_irqrestore(&port->lock, flags); 468 469 retval = request_irq(port->irq, serial_lpc32xx_interrupt, 470 0, MODNAME, port); 471 if (!retval) 472 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN), 473 LPC32XX_HSUART_CTRL(port->membase)); 474 475 return retval; 476 } 477 478 /* port->lock is not held. */ 479 static void serial_lpc32xx_shutdown(struct uart_port *port) 480 { 481 u32 tmp; 482 unsigned long flags; 483 484 spin_lock_irqsave(&port->lock, flags); 485 486 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 487 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 488 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 489 490 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */ 491 492 spin_unlock_irqrestore(&port->lock, flags); 493 494 free_irq(port->irq, port); 495 } 496 497 /* port->lock is not held. */ 498 static void serial_lpc32xx_set_termios(struct uart_port *port, 499 struct ktermios *termios, 500 struct ktermios *old) 501 { 502 unsigned long flags; 503 unsigned int baud, quot; 504 u32 tmp; 505 506 /* Always 8-bit, no parity, 1 stop bit */ 507 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 508 termios->c_cflag |= CS8; 509 510 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS); 511 512 baud = uart_get_baud_rate(port, termios, old, 0, 513 port->uartclk / 14); 514 515 quot = __serial_get_clock_div(port->uartclk, baud); 516 517 spin_lock_irqsave(&port->lock, flags); 518 519 /* Ignore characters? */ 520 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 521 if ((termios->c_cflag & CREAD) == 0) 522 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 523 else 524 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN; 525 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 526 527 writel(quot, LPC32XX_HSUART_RATE(port->membase)); 528 529 uart_update_timeout(port, termios->c_cflag, baud); 530 531 spin_unlock_irqrestore(&port->lock, flags); 532 533 /* Don't rewrite B0 */ 534 if (tty_termios_baud_rate(termios)) 535 tty_termios_encode_baud_rate(termios, baud, baud); 536 } 537 538 static const char *serial_lpc32xx_type(struct uart_port *port) 539 { 540 return MODNAME; 541 } 542 543 static void serial_lpc32xx_release_port(struct uart_port *port) 544 { 545 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 546 if (port->flags & UPF_IOREMAP) { 547 iounmap(port->membase); 548 port->membase = NULL; 549 } 550 551 release_mem_region(port->mapbase, SZ_4K); 552 } 553 } 554 555 static int serial_lpc32xx_request_port(struct uart_port *port) 556 { 557 int ret = -ENODEV; 558 559 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 560 ret = 0; 561 562 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME)) 563 ret = -EBUSY; 564 else if (port->flags & UPF_IOREMAP) { 565 port->membase = ioremap(port->mapbase, SZ_4K); 566 if (!port->membase) { 567 release_mem_region(port->mapbase, SZ_4K); 568 ret = -ENOMEM; 569 } 570 } 571 } 572 573 return ret; 574 } 575 576 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags) 577 { 578 int ret; 579 580 ret = serial_lpc32xx_request_port(port); 581 if (ret < 0) 582 return; 583 port->type = PORT_UART00; 584 port->fifosize = 64; 585 586 __serial_uart_flush(port); 587 588 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 589 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 590 LPC32XX_HSUART_IIR(port->membase)); 591 592 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 593 594 /* Set receiver timeout, HSU offset of 20, no break, no interrupts, 595 and default FIFO trigger levels */ 596 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 597 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B, 598 LPC32XX_HSUART_CTRL(port->membase)); 599 } 600 601 static int serial_lpc32xx_verify_port(struct uart_port *port, 602 struct serial_struct *ser) 603 { 604 int ret = 0; 605 606 if (ser->type != PORT_UART00) 607 ret = -EINVAL; 608 609 return ret; 610 } 611 612 static const struct uart_ops serial_lpc32xx_pops = { 613 .tx_empty = serial_lpc32xx_tx_empty, 614 .set_mctrl = serial_lpc32xx_set_mctrl, 615 .get_mctrl = serial_lpc32xx_get_mctrl, 616 .stop_tx = serial_lpc32xx_stop_tx, 617 .start_tx = serial_lpc32xx_start_tx, 618 .stop_rx = serial_lpc32xx_stop_rx, 619 .break_ctl = serial_lpc32xx_break_ctl, 620 .startup = serial_lpc32xx_startup, 621 .shutdown = serial_lpc32xx_shutdown, 622 .set_termios = serial_lpc32xx_set_termios, 623 .type = serial_lpc32xx_type, 624 .release_port = serial_lpc32xx_release_port, 625 .request_port = serial_lpc32xx_request_port, 626 .config_port = serial_lpc32xx_config_port, 627 .verify_port = serial_lpc32xx_verify_port, 628 }; 629 630 /* 631 * Register a set of serial devices attached to a platform device 632 */ 633 static int serial_hs_lpc32xx_probe(struct platform_device *pdev) 634 { 635 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered]; 636 int ret = 0; 637 struct resource *res; 638 639 if (uarts_registered >= MAX_PORTS) { 640 dev_err(&pdev->dev, 641 "Error: Number of possible ports exceeded (%d)!\n", 642 uarts_registered + 1); 643 return -ENXIO; 644 } 645 646 memset(p, 0, sizeof(*p)); 647 648 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 649 if (!res) { 650 dev_err(&pdev->dev, 651 "Error getting mem resource for HS UART port %d\n", 652 uarts_registered); 653 return -ENXIO; 654 } 655 p->port.mapbase = res->start; 656 p->port.membase = NULL; 657 658 ret = platform_get_irq(pdev, 0); 659 if (ret < 0) 660 return ret; 661 p->port.irq = ret; 662 663 p->port.iotype = UPIO_MEM32; 664 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ; 665 p->port.regshift = 2; 666 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; 667 p->port.dev = &pdev->dev; 668 p->port.ops = &serial_lpc32xx_pops; 669 p->port.line = uarts_registered++; 670 spin_lock_init(&p->port.lock); 671 672 /* send port to loopback mode by default */ 673 lpc32xx_loopback_set(p->port.mapbase, 1); 674 675 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port); 676 677 platform_set_drvdata(pdev, p); 678 679 return ret; 680 } 681 682 /* 683 * Remove serial ports registered against a platform device. 684 */ 685 static int serial_hs_lpc32xx_remove(struct platform_device *pdev) 686 { 687 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 688 689 uart_remove_one_port(&lpc32xx_hs_reg, &p->port); 690 691 return 0; 692 } 693 694 695 #ifdef CONFIG_PM 696 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev, 697 pm_message_t state) 698 { 699 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 700 701 uart_suspend_port(&lpc32xx_hs_reg, &p->port); 702 703 return 0; 704 } 705 706 static int serial_hs_lpc32xx_resume(struct platform_device *pdev) 707 { 708 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 709 710 uart_resume_port(&lpc32xx_hs_reg, &p->port); 711 712 return 0; 713 } 714 #else 715 #define serial_hs_lpc32xx_suspend NULL 716 #define serial_hs_lpc32xx_resume NULL 717 #endif 718 719 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = { 720 { .compatible = "nxp,lpc3220-hsuart" }, 721 { /* sentinel */ } 722 }; 723 724 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids); 725 726 static struct platform_driver serial_hs_lpc32xx_driver = { 727 .probe = serial_hs_lpc32xx_probe, 728 .remove = serial_hs_lpc32xx_remove, 729 .suspend = serial_hs_lpc32xx_suspend, 730 .resume = serial_hs_lpc32xx_resume, 731 .driver = { 732 .name = MODNAME, 733 .of_match_table = serial_hs_lpc32xx_dt_ids, 734 }, 735 }; 736 737 static int __init lpc32xx_hsuart_init(void) 738 { 739 int ret; 740 741 ret = uart_register_driver(&lpc32xx_hs_reg); 742 if (ret) 743 return ret; 744 745 ret = platform_driver_register(&serial_hs_lpc32xx_driver); 746 if (ret) 747 uart_unregister_driver(&lpc32xx_hs_reg); 748 749 return ret; 750 } 751 752 static void __exit lpc32xx_hsuart_exit(void) 753 { 754 platform_driver_unregister(&serial_hs_lpc32xx_driver); 755 uart_unregister_driver(&lpc32xx_hs_reg); 756 } 757 758 module_init(lpc32xx_hsuart_init); 759 module_exit(lpc32xx_hsuart_exit); 760 761 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 762 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 763 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver"); 764 MODULE_LICENSE("GPL"); 765