1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2596f93f5SRoland Stigge /* 3596f93f5SRoland Stigge * High Speed Serial Ports on NXP LPC32xx SoC 4596f93f5SRoland Stigge * 5596f93f5SRoland Stigge * Authors: Kevin Wells <kevin.wells@nxp.com> 6596f93f5SRoland Stigge * Roland Stigge <stigge@antcom.de> 7596f93f5SRoland Stigge * 8596f93f5SRoland Stigge * Copyright (C) 2010 NXP Semiconductors 9596f93f5SRoland Stigge * Copyright (C) 2012 Roland Stigge 10596f93f5SRoland Stigge */ 11596f93f5SRoland Stigge 12596f93f5SRoland Stigge #include <linux/module.h> 13596f93f5SRoland Stigge #include <linux/ioport.h> 14596f93f5SRoland Stigge #include <linux/init.h> 15596f93f5SRoland Stigge #include <linux/console.h> 16596f93f5SRoland Stigge #include <linux/sysrq.h> 17596f93f5SRoland Stigge #include <linux/tty.h> 18596f93f5SRoland Stigge #include <linux/tty_flip.h> 19596f93f5SRoland Stigge #include <linux/serial_core.h> 20596f93f5SRoland Stigge #include <linux/serial.h> 21596f93f5SRoland Stigge #include <linux/platform_device.h> 22596f93f5SRoland Stigge #include <linux/delay.h> 23596f93f5SRoland Stigge #include <linux/nmi.h> 24596f93f5SRoland Stigge #include <linux/io.h> 25596f93f5SRoland Stigge #include <linux/irq.h> 26596f93f5SRoland Stigge #include <linux/gpio.h> 27596f93f5SRoland Stigge #include <linux/of.h> 28ffba29c9SArnd Bergmann #include <linux/sizes.h> 29ffba29c9SArnd Bergmann #include <linux/soc/nxp/lpc32xx-misc.h> 30596f93f5SRoland Stigge 31596f93f5SRoland Stigge /* 32596f93f5SRoland Stigge * High Speed UART register offsets 33596f93f5SRoland Stigge */ 34596f93f5SRoland Stigge #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00) 35596f93f5SRoland Stigge #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04) 36596f93f5SRoland Stigge #define LPC32XX_HSUART_IIR(x) ((x) + 0x08) 37596f93f5SRoland Stigge #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C) 38596f93f5SRoland Stigge #define LPC32XX_HSUART_RATE(x) ((x) + 0x10) 39596f93f5SRoland Stigge 40596f93f5SRoland Stigge #define LPC32XX_HSU_BREAK_DATA (1 << 10) 41596f93f5SRoland Stigge #define LPC32XX_HSU_ERROR_DATA (1 << 9) 42596f93f5SRoland Stigge #define LPC32XX_HSU_RX_EMPTY (1 << 8) 43596f93f5SRoland Stigge 44596f93f5SRoland Stigge #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF) 45596f93f5SRoland Stigge #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF) 46596f93f5SRoland Stigge 47596f93f5SRoland Stigge #define LPC32XX_HSU_TX_INT_SET (1 << 6) 48596f93f5SRoland Stigge #define LPC32XX_HSU_RX_OE_INT (1 << 5) 49596f93f5SRoland Stigge #define LPC32XX_HSU_BRK_INT (1 << 4) 50596f93f5SRoland Stigge #define LPC32XX_HSU_FE_INT (1 << 3) 51596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2) 52596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TRIG_INT (1 << 1) 53596f93f5SRoland Stigge #define LPC32XX_HSU_TX_INT (1 << 0) 54596f93f5SRoland Stigge 55596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_INV (1 << 21) 56596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19) 57596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19) 58596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19) 59596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19) 60596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_EN (1 << 18) 61596f93f5SRoland Stigge #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16) 62596f93f5SRoland Stigge #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16) 63596f93f5SRoland Stigge #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16) 64596f93f5SRoland Stigge #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16) 65596f93f5SRoland Stigge #define LPC32XX_HSU_HCTS_INV (1 << 15) 66596f93f5SRoland Stigge #define LPC32XX_HSU_HCTS_EN (1 << 14) 67596f93f5SRoland Stigge #define LPC32XX_HSU_OFFSET(n) ((n) << 9) 68596f93f5SRoland Stigge #define LPC32XX_HSU_BREAK (1 << 8) 69596f93f5SRoland Stigge #define LPC32XX_HSU_ERR_INT_EN (1 << 7) 70596f93f5SRoland Stigge #define LPC32XX_HSU_RX_INT_EN (1 << 6) 71596f93f5SRoland Stigge #define LPC32XX_HSU_TX_INT_EN (1 << 5) 72596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL1B (0x0 << 2) 73596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL4B (0x1 << 2) 74596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL8B (0x2 << 2) 75596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL16B (0x3 << 2) 76596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL32B (0x4 << 2) 77596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL48B (0x5 << 2) 78596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0) 79596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TL0B (0x0 << 0) 80596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TL4B (0x1 << 0) 81596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TL8B (0x2 << 0) 82596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TL16B (0x3 << 0) 83596f93f5SRoland Stigge 84ffba29c9SArnd Bergmann #define LPC32XX_MAIN_OSC_FREQ 13000000 85ffba29c9SArnd Bergmann 86596f93f5SRoland Stigge #define MODNAME "lpc32xx_hsuart" 87596f93f5SRoland Stigge 88596f93f5SRoland Stigge struct lpc32xx_hsuart_port { 89596f93f5SRoland Stigge struct uart_port port; 90596f93f5SRoland Stigge }; 91596f93f5SRoland Stigge 92596f93f5SRoland Stigge #define FIFO_READ_LIMIT 128 93596f93f5SRoland Stigge #define MAX_PORTS 3 94596f93f5SRoland Stigge #define LPC32XX_TTY_NAME "ttyTX" 95596f93f5SRoland Stigge static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS]; 96596f93f5SRoland Stigge 97596f93f5SRoland Stigge #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE 98596f93f5SRoland Stigge static void wait_for_xmit_empty(struct uart_port *port) 99596f93f5SRoland Stigge { 100596f93f5SRoland Stigge unsigned int timeout = 10000; 101596f93f5SRoland Stigge 102596f93f5SRoland Stigge do { 103596f93f5SRoland Stigge if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 104596f93f5SRoland Stigge port->membase))) == 0) 105596f93f5SRoland Stigge break; 106596f93f5SRoland Stigge if (--timeout == 0) 107596f93f5SRoland Stigge break; 108596f93f5SRoland Stigge udelay(1); 109596f93f5SRoland Stigge } while (1); 110596f93f5SRoland Stigge } 111596f93f5SRoland Stigge 112596f93f5SRoland Stigge static void wait_for_xmit_ready(struct uart_port *port) 113596f93f5SRoland Stigge { 114596f93f5SRoland Stigge unsigned int timeout = 10000; 115596f93f5SRoland Stigge 116596f93f5SRoland Stigge while (1) { 117596f93f5SRoland Stigge if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 118596f93f5SRoland Stigge port->membase))) < 32) 119596f93f5SRoland Stigge break; 120596f93f5SRoland Stigge if (--timeout == 0) 121596f93f5SRoland Stigge break; 122596f93f5SRoland Stigge udelay(1); 123596f93f5SRoland Stigge } 124596f93f5SRoland Stigge } 125596f93f5SRoland Stigge 126596f93f5SRoland Stigge static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch) 127596f93f5SRoland Stigge { 128596f93f5SRoland Stigge wait_for_xmit_ready(port); 129596f93f5SRoland Stigge writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); 130596f93f5SRoland Stigge } 131596f93f5SRoland Stigge 132596f93f5SRoland Stigge static void lpc32xx_hsuart_console_write(struct console *co, const char *s, 133596f93f5SRoland Stigge unsigned int count) 134596f93f5SRoland Stigge { 135596f93f5SRoland Stigge struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index]; 136596f93f5SRoland Stigge unsigned long flags; 137596f93f5SRoland Stigge int locked = 1; 138596f93f5SRoland Stigge 139596f93f5SRoland Stigge touch_nmi_watchdog(); 140596f93f5SRoland Stigge local_irq_save(flags); 141596f93f5SRoland Stigge if (up->port.sysrq) 142596f93f5SRoland Stigge locked = 0; 143596f93f5SRoland Stigge else if (oops_in_progress) 144596f93f5SRoland Stigge locked = spin_trylock(&up->port.lock); 145596f93f5SRoland Stigge else 146596f93f5SRoland Stigge spin_lock(&up->port.lock); 147596f93f5SRoland Stigge 148596f93f5SRoland Stigge uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar); 149596f93f5SRoland Stigge wait_for_xmit_empty(&up->port); 150596f93f5SRoland Stigge 151596f93f5SRoland Stigge if (locked) 152596f93f5SRoland Stigge spin_unlock(&up->port.lock); 153596f93f5SRoland Stigge local_irq_restore(flags); 154596f93f5SRoland Stigge } 155596f93f5SRoland Stigge 156596f93f5SRoland Stigge static int __init lpc32xx_hsuart_console_setup(struct console *co, 157596f93f5SRoland Stigge char *options) 158596f93f5SRoland Stigge { 159596f93f5SRoland Stigge struct uart_port *port; 160596f93f5SRoland Stigge int baud = 115200; 161596f93f5SRoland Stigge int bits = 8; 162596f93f5SRoland Stigge int parity = 'n'; 163596f93f5SRoland Stigge int flow = 'n'; 164596f93f5SRoland Stigge 165596f93f5SRoland Stigge if (co->index >= MAX_PORTS) 166596f93f5SRoland Stigge co->index = 0; 167596f93f5SRoland Stigge 168596f93f5SRoland Stigge port = &lpc32xx_hs_ports[co->index].port; 169596f93f5SRoland Stigge if (!port->membase) 170596f93f5SRoland Stigge return -ENODEV; 171596f93f5SRoland Stigge 172596f93f5SRoland Stigge if (options) 173596f93f5SRoland Stigge uart_parse_options(options, &baud, &parity, &bits, &flow); 174596f93f5SRoland Stigge 175b30fd1a6SAlexandre Belloni lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 176b30fd1a6SAlexandre Belloni 177596f93f5SRoland Stigge return uart_set_options(port, co, baud, parity, bits, flow); 178596f93f5SRoland Stigge } 179596f93f5SRoland Stigge 180596f93f5SRoland Stigge static struct uart_driver lpc32xx_hsuart_reg; 181596f93f5SRoland Stigge static struct console lpc32xx_hsuart_console = { 182596f93f5SRoland Stigge .name = LPC32XX_TTY_NAME, 183596f93f5SRoland Stigge .write = lpc32xx_hsuart_console_write, 184596f93f5SRoland Stigge .device = uart_console_device, 185596f93f5SRoland Stigge .setup = lpc32xx_hsuart_console_setup, 186596f93f5SRoland Stigge .flags = CON_PRINTBUFFER, 187596f93f5SRoland Stigge .index = -1, 188596f93f5SRoland Stigge .data = &lpc32xx_hsuart_reg, 189596f93f5SRoland Stigge }; 190596f93f5SRoland Stigge 191596f93f5SRoland Stigge static int __init lpc32xx_hsuart_console_init(void) 192596f93f5SRoland Stigge { 193596f93f5SRoland Stigge register_console(&lpc32xx_hsuart_console); 194596f93f5SRoland Stigge return 0; 195596f93f5SRoland Stigge } 196596f93f5SRoland Stigge console_initcall(lpc32xx_hsuart_console_init); 197596f93f5SRoland Stigge 198596f93f5SRoland Stigge #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console) 199596f93f5SRoland Stigge #else 200596f93f5SRoland Stigge #define LPC32XX_HSUART_CONSOLE NULL 201596f93f5SRoland Stigge #endif 202596f93f5SRoland Stigge 203596f93f5SRoland Stigge static struct uart_driver lpc32xx_hs_reg = { 204596f93f5SRoland Stigge .owner = THIS_MODULE, 205596f93f5SRoland Stigge .driver_name = MODNAME, 206596f93f5SRoland Stigge .dev_name = LPC32XX_TTY_NAME, 207596f93f5SRoland Stigge .nr = MAX_PORTS, 208596f93f5SRoland Stigge .cons = LPC32XX_HSUART_CONSOLE, 209596f93f5SRoland Stigge }; 210596f93f5SRoland Stigge static int uarts_registered; 211596f93f5SRoland Stigge 212596f93f5SRoland Stigge static unsigned int __serial_get_clock_div(unsigned long uartclk, 213596f93f5SRoland Stigge unsigned long rate) 214596f93f5SRoland Stigge { 215596f93f5SRoland Stigge u32 div, goodrate, hsu_rate, l_hsu_rate, comprate; 216596f93f5SRoland Stigge u32 rate_diff; 217596f93f5SRoland Stigge 218596f93f5SRoland Stigge /* Find the closest divider to get the desired clock rate */ 219596f93f5SRoland Stigge div = uartclk / rate; 220596f93f5SRoland Stigge goodrate = hsu_rate = (div / 14) - 1; 221596f93f5SRoland Stigge if (hsu_rate != 0) 222596f93f5SRoland Stigge hsu_rate--; 223596f93f5SRoland Stigge 224596f93f5SRoland Stigge /* Tweak divider */ 225596f93f5SRoland Stigge l_hsu_rate = hsu_rate + 3; 226596f93f5SRoland Stigge rate_diff = 0xFFFFFFFF; 227596f93f5SRoland Stigge 228596f93f5SRoland Stigge while (hsu_rate < l_hsu_rate) { 229596f93f5SRoland Stigge comprate = uartclk / ((hsu_rate + 1) * 14); 230596f93f5SRoland Stigge if (abs(comprate - rate) < rate_diff) { 231596f93f5SRoland Stigge goodrate = hsu_rate; 232596f93f5SRoland Stigge rate_diff = abs(comprate - rate); 233596f93f5SRoland Stigge } 234596f93f5SRoland Stigge 235596f93f5SRoland Stigge hsu_rate++; 236596f93f5SRoland Stigge } 237596f93f5SRoland Stigge if (hsu_rate > 0xFF) 238596f93f5SRoland Stigge hsu_rate = 0xFF; 239596f93f5SRoland Stigge 240596f93f5SRoland Stigge return goodrate; 241596f93f5SRoland Stigge } 242596f93f5SRoland Stigge 243596f93f5SRoland Stigge static void __serial_uart_flush(struct uart_port *port) 244596f93f5SRoland Stigge { 245596f93f5SRoland Stigge u32 tmp; 246596f93f5SRoland Stigge int cnt = 0; 247596f93f5SRoland Stigge 248596f93f5SRoland Stigge while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && 249596f93f5SRoland Stigge (cnt++ < FIFO_READ_LIMIT)) 250596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 251596f93f5SRoland Stigge } 252596f93f5SRoland Stigge 253596f93f5SRoland Stigge static void __serial_lpc32xx_rx(struct uart_port *port) 254596f93f5SRoland Stigge { 25592a19f9cSJiri Slaby struct tty_port *tport = &port->state->port; 256596f93f5SRoland Stigge unsigned int tmp, flag; 257596f93f5SRoland Stigge 258596f93f5SRoland Stigge /* Read data from FIFO and push into terminal */ 259596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 260596f93f5SRoland Stigge while (!(tmp & LPC32XX_HSU_RX_EMPTY)) { 261596f93f5SRoland Stigge flag = TTY_NORMAL; 262596f93f5SRoland Stigge port->icount.rx++; 263596f93f5SRoland Stigge 264596f93f5SRoland Stigge if (tmp & LPC32XX_HSU_ERROR_DATA) { 265596f93f5SRoland Stigge /* Framing error */ 266596f93f5SRoland Stigge writel(LPC32XX_HSU_FE_INT, 267596f93f5SRoland Stigge LPC32XX_HSUART_IIR(port->membase)); 268596f93f5SRoland Stigge port->icount.frame++; 269596f93f5SRoland Stigge flag = TTY_FRAME; 27092a19f9cSJiri Slaby tty_insert_flip_char(tport, 0, TTY_FRAME); 271596f93f5SRoland Stigge } 272596f93f5SRoland Stigge 27392a19f9cSJiri Slaby tty_insert_flip_char(tport, (tmp & 0xFF), flag); 274596f93f5SRoland Stigge 275596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 276596f93f5SRoland Stigge } 277ec128510SViresh Kumar 278ec128510SViresh Kumar spin_unlock(&port->lock); 2792e124b4aSJiri Slaby tty_flip_buffer_push(tport); 280ec128510SViresh Kumar spin_lock(&port->lock); 281596f93f5SRoland Stigge } 282596f93f5SRoland Stigge 283596f93f5SRoland Stigge static void __serial_lpc32xx_tx(struct uart_port *port) 284596f93f5SRoland Stigge { 285596f93f5SRoland Stigge struct circ_buf *xmit = &port->state->xmit; 286596f93f5SRoland Stigge unsigned int tmp; 287596f93f5SRoland Stigge 288596f93f5SRoland Stigge if (port->x_char) { 289596f93f5SRoland Stigge writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); 290596f93f5SRoland Stigge port->icount.tx++; 291596f93f5SRoland Stigge port->x_char = 0; 292596f93f5SRoland Stigge return; 293596f93f5SRoland Stigge } 294596f93f5SRoland Stigge 295596f93f5SRoland Stigge if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 296596f93f5SRoland Stigge goto exit_tx; 297596f93f5SRoland Stigge 298596f93f5SRoland Stigge /* Transfer data */ 299596f93f5SRoland Stigge while (LPC32XX_HSU_TX_LEV(readl( 300596f93f5SRoland Stigge LPC32XX_HSUART_LEVEL(port->membase))) < 64) { 301596f93f5SRoland Stigge writel((u32) xmit->buf[xmit->tail], 302596f93f5SRoland Stigge LPC32XX_HSUART_FIFO(port->membase)); 303596f93f5SRoland Stigge xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 304596f93f5SRoland Stigge port->icount.tx++; 305596f93f5SRoland Stigge if (uart_circ_empty(xmit)) 306596f93f5SRoland Stigge break; 307596f93f5SRoland Stigge } 308596f93f5SRoland Stigge 309596f93f5SRoland Stigge if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 310596f93f5SRoland Stigge uart_write_wakeup(port); 311596f93f5SRoland Stigge 312596f93f5SRoland Stigge exit_tx: 313596f93f5SRoland Stigge if (uart_circ_empty(xmit)) { 314596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 315596f93f5SRoland Stigge tmp &= ~LPC32XX_HSU_TX_INT_EN; 316596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 317596f93f5SRoland Stigge } 318596f93f5SRoland Stigge } 319596f93f5SRoland Stigge 320596f93f5SRoland Stigge static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id) 321596f93f5SRoland Stigge { 322596f93f5SRoland Stigge struct uart_port *port = dev_id; 32333aeb9daSThierry Reding struct tty_port *tport = &port->state->port; 324596f93f5SRoland Stigge u32 status; 325596f93f5SRoland Stigge 326596f93f5SRoland Stigge spin_lock(&port->lock); 327596f93f5SRoland Stigge 328596f93f5SRoland Stigge /* Read UART status and clear latched interrupts */ 329596f93f5SRoland Stigge status = readl(LPC32XX_HSUART_IIR(port->membase)); 330596f93f5SRoland Stigge 331596f93f5SRoland Stigge if (status & LPC32XX_HSU_BRK_INT) { 332596f93f5SRoland Stigge /* Break received */ 333596f93f5SRoland Stigge writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); 334596f93f5SRoland Stigge port->icount.brk++; 335596f93f5SRoland Stigge uart_handle_break(port); 336596f93f5SRoland Stigge } 337596f93f5SRoland Stigge 338596f93f5SRoland Stigge /* Framing error */ 339596f93f5SRoland Stigge if (status & LPC32XX_HSU_FE_INT) 340596f93f5SRoland Stigge writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); 341596f93f5SRoland Stigge 342596f93f5SRoland Stigge if (status & LPC32XX_HSU_RX_OE_INT) { 343596f93f5SRoland Stigge /* Receive FIFO overrun */ 344596f93f5SRoland Stigge writel(LPC32XX_HSU_RX_OE_INT, 345596f93f5SRoland Stigge LPC32XX_HSUART_IIR(port->membase)); 346596f93f5SRoland Stigge port->icount.overrun++; 34792a19f9cSJiri Slaby tty_insert_flip_char(tport, 0, TTY_OVERRUN); 3486732c8bbSJiri Slaby tty_schedule_flip(tport); 349596f93f5SRoland Stigge } 350596f93f5SRoland Stigge 351596f93f5SRoland Stigge /* Data received? */ 35297f2c428SViresh Kumar if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) 353596f93f5SRoland Stigge __serial_lpc32xx_rx(port); 354596f93f5SRoland Stigge 355596f93f5SRoland Stigge /* Transmit data request? */ 356596f93f5SRoland Stigge if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) { 357596f93f5SRoland Stigge writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); 358596f93f5SRoland Stigge __serial_lpc32xx_tx(port); 359596f93f5SRoland Stigge } 360596f93f5SRoland Stigge 361596f93f5SRoland Stigge spin_unlock(&port->lock); 362596f93f5SRoland Stigge 363596f93f5SRoland Stigge return IRQ_HANDLED; 364596f93f5SRoland Stigge } 365596f93f5SRoland Stigge 366596f93f5SRoland Stigge /* port->lock is not held. */ 367596f93f5SRoland Stigge static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port) 368596f93f5SRoland Stigge { 369596f93f5SRoland Stigge unsigned int ret = 0; 370596f93f5SRoland Stigge 371596f93f5SRoland Stigge if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) 372596f93f5SRoland Stigge ret = TIOCSER_TEMT; 373596f93f5SRoland Stigge 374596f93f5SRoland Stigge return ret; 375596f93f5SRoland Stigge } 376596f93f5SRoland Stigge 377596f93f5SRoland Stigge /* port->lock held by caller. */ 378596f93f5SRoland Stigge static void serial_lpc32xx_set_mctrl(struct uart_port *port, 379596f93f5SRoland Stigge unsigned int mctrl) 380596f93f5SRoland Stigge { 381596f93f5SRoland Stigge /* No signals are supported on HS UARTs */ 382596f93f5SRoland Stigge } 383596f93f5SRoland Stigge 384596f93f5SRoland Stigge /* port->lock is held by caller and interrupts are disabled. */ 385596f93f5SRoland Stigge static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port) 386596f93f5SRoland Stigge { 387596f93f5SRoland Stigge /* No signals are supported on HS UARTs */ 388596f93f5SRoland Stigge return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 389596f93f5SRoland Stigge } 390596f93f5SRoland Stigge 391596f93f5SRoland Stigge /* port->lock held by caller. */ 392596f93f5SRoland Stigge static void serial_lpc32xx_stop_tx(struct uart_port *port) 393596f93f5SRoland Stigge { 394596f93f5SRoland Stigge u32 tmp; 395596f93f5SRoland Stigge 396596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 397596f93f5SRoland Stigge tmp &= ~LPC32XX_HSU_TX_INT_EN; 398596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 399596f93f5SRoland Stigge } 400596f93f5SRoland Stigge 401596f93f5SRoland Stigge /* port->lock held by caller. */ 402596f93f5SRoland Stigge static void serial_lpc32xx_start_tx(struct uart_port *port) 403596f93f5SRoland Stigge { 404596f93f5SRoland Stigge u32 tmp; 405596f93f5SRoland Stigge 406596f93f5SRoland Stigge __serial_lpc32xx_tx(port); 407596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 408596f93f5SRoland Stigge tmp |= LPC32XX_HSU_TX_INT_EN; 409596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 410596f93f5SRoland Stigge } 411596f93f5SRoland Stigge 412596f93f5SRoland Stigge /* port->lock held by caller. */ 413596f93f5SRoland Stigge static void serial_lpc32xx_stop_rx(struct uart_port *port) 414596f93f5SRoland Stigge { 415596f93f5SRoland Stigge u32 tmp; 416596f93f5SRoland Stigge 417596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 418596f93f5SRoland Stigge tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 419596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 420596f93f5SRoland Stigge 421596f93f5SRoland Stigge writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT | 422596f93f5SRoland Stigge LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase)); 423596f93f5SRoland Stigge } 424596f93f5SRoland Stigge 425596f93f5SRoland Stigge /* port->lock is not held. */ 426596f93f5SRoland Stigge static void serial_lpc32xx_break_ctl(struct uart_port *port, 427596f93f5SRoland Stigge int break_state) 428596f93f5SRoland Stigge { 429596f93f5SRoland Stigge unsigned long flags; 430596f93f5SRoland Stigge u32 tmp; 431596f93f5SRoland Stigge 432596f93f5SRoland Stigge spin_lock_irqsave(&port->lock, flags); 433596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 434596f93f5SRoland Stigge if (break_state != 0) 435596f93f5SRoland Stigge tmp |= LPC32XX_HSU_BREAK; 436596f93f5SRoland Stigge else 437596f93f5SRoland Stigge tmp &= ~LPC32XX_HSU_BREAK; 438596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 439596f93f5SRoland Stigge spin_unlock_irqrestore(&port->lock, flags); 440596f93f5SRoland Stigge } 441596f93f5SRoland Stigge 442596f93f5SRoland Stigge /* port->lock is not held. */ 443596f93f5SRoland Stigge static int serial_lpc32xx_startup(struct uart_port *port) 444596f93f5SRoland Stigge { 445596f93f5SRoland Stigge int retval; 446596f93f5SRoland Stigge unsigned long flags; 447596f93f5SRoland Stigge u32 tmp; 448596f93f5SRoland Stigge 449596f93f5SRoland Stigge spin_lock_irqsave(&port->lock, flags); 450596f93f5SRoland Stigge 451596f93f5SRoland Stigge __serial_uart_flush(port); 452596f93f5SRoland Stigge 453596f93f5SRoland Stigge writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 454596f93f5SRoland Stigge LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 455596f93f5SRoland Stigge LPC32XX_HSUART_IIR(port->membase)); 456596f93f5SRoland Stigge 457596f93f5SRoland Stigge writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 458596f93f5SRoland Stigge 459596f93f5SRoland Stigge /* 460596f93f5SRoland Stigge * Set receiver timeout, HSU offset of 20, no break, no interrupts, 461596f93f5SRoland Stigge * and default FIFO trigger levels 462596f93f5SRoland Stigge */ 463596f93f5SRoland Stigge tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 464596f93f5SRoland Stigge LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 465596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 466596f93f5SRoland Stigge 467596f93f5SRoland Stigge lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 468596f93f5SRoland Stigge 469596f93f5SRoland Stigge spin_unlock_irqrestore(&port->lock, flags); 470596f93f5SRoland Stigge 471596f93f5SRoland Stigge retval = request_irq(port->irq, serial_lpc32xx_interrupt, 472596f93f5SRoland Stigge 0, MODNAME, port); 473596f93f5SRoland Stigge if (!retval) 474596f93f5SRoland Stigge writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN), 475596f93f5SRoland Stigge LPC32XX_HSUART_CTRL(port->membase)); 476596f93f5SRoland Stigge 477596f93f5SRoland Stigge return retval; 478596f93f5SRoland Stigge } 479596f93f5SRoland Stigge 480596f93f5SRoland Stigge /* port->lock is not held. */ 481596f93f5SRoland Stigge static void serial_lpc32xx_shutdown(struct uart_port *port) 482596f93f5SRoland Stigge { 483596f93f5SRoland Stigge u32 tmp; 484596f93f5SRoland Stigge unsigned long flags; 485596f93f5SRoland Stigge 486596f93f5SRoland Stigge spin_lock_irqsave(&port->lock, flags); 487596f93f5SRoland Stigge 488596f93f5SRoland Stigge tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 489596f93f5SRoland Stigge LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 490596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 491596f93f5SRoland Stigge 492596f93f5SRoland Stigge lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */ 493596f93f5SRoland Stigge 494596f93f5SRoland Stigge spin_unlock_irqrestore(&port->lock, flags); 495596f93f5SRoland Stigge 496596f93f5SRoland Stigge free_irq(port->irq, port); 497596f93f5SRoland Stigge } 498596f93f5SRoland Stigge 499596f93f5SRoland Stigge /* port->lock is not held. */ 500596f93f5SRoland Stigge static void serial_lpc32xx_set_termios(struct uart_port *port, 501596f93f5SRoland Stigge struct ktermios *termios, 502596f93f5SRoland Stigge struct ktermios *old) 503596f93f5SRoland Stigge { 504596f93f5SRoland Stigge unsigned long flags; 505596f93f5SRoland Stigge unsigned int baud, quot; 506596f93f5SRoland Stigge u32 tmp; 507596f93f5SRoland Stigge 508596f93f5SRoland Stigge /* Always 8-bit, no parity, 1 stop bit */ 509596f93f5SRoland Stigge termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 510596f93f5SRoland Stigge termios->c_cflag |= CS8; 511596f93f5SRoland Stigge 512596f93f5SRoland Stigge termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS); 513596f93f5SRoland Stigge 514596f93f5SRoland Stigge baud = uart_get_baud_rate(port, termios, old, 0, 515596f93f5SRoland Stigge port->uartclk / 14); 516596f93f5SRoland Stigge 517596f93f5SRoland Stigge quot = __serial_get_clock_div(port->uartclk, baud); 518596f93f5SRoland Stigge 519596f93f5SRoland Stigge spin_lock_irqsave(&port->lock, flags); 520596f93f5SRoland Stigge 521596f93f5SRoland Stigge /* Ignore characters? */ 522596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 523596f93f5SRoland Stigge if ((termios->c_cflag & CREAD) == 0) 524596f93f5SRoland Stigge tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 525596f93f5SRoland Stigge else 526596f93f5SRoland Stigge tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN; 527596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 528596f93f5SRoland Stigge 529596f93f5SRoland Stigge writel(quot, LPC32XX_HSUART_RATE(port->membase)); 530596f93f5SRoland Stigge 531596f93f5SRoland Stigge uart_update_timeout(port, termios->c_cflag, baud); 532596f93f5SRoland Stigge 533596f93f5SRoland Stigge spin_unlock_irqrestore(&port->lock, flags); 534596f93f5SRoland Stigge 535596f93f5SRoland Stigge /* Don't rewrite B0 */ 536596f93f5SRoland Stigge if (tty_termios_baud_rate(termios)) 537596f93f5SRoland Stigge tty_termios_encode_baud_rate(termios, baud, baud); 538596f93f5SRoland Stigge } 539596f93f5SRoland Stigge 540596f93f5SRoland Stigge static const char *serial_lpc32xx_type(struct uart_port *port) 541596f93f5SRoland Stigge { 542596f93f5SRoland Stigge return MODNAME; 543596f93f5SRoland Stigge } 544596f93f5SRoland Stigge 545596f93f5SRoland Stigge static void serial_lpc32xx_release_port(struct uart_port *port) 546596f93f5SRoland Stigge { 547596f93f5SRoland Stigge if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 548596f93f5SRoland Stigge if (port->flags & UPF_IOREMAP) { 549596f93f5SRoland Stigge iounmap(port->membase); 550596f93f5SRoland Stigge port->membase = NULL; 551596f93f5SRoland Stigge } 552596f93f5SRoland Stigge 553596f93f5SRoland Stigge release_mem_region(port->mapbase, SZ_4K); 554596f93f5SRoland Stigge } 555596f93f5SRoland Stigge } 556596f93f5SRoland Stigge 557596f93f5SRoland Stigge static int serial_lpc32xx_request_port(struct uart_port *port) 558596f93f5SRoland Stigge { 559596f93f5SRoland Stigge int ret = -ENODEV; 560596f93f5SRoland Stigge 561596f93f5SRoland Stigge if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 562596f93f5SRoland Stigge ret = 0; 563596f93f5SRoland Stigge 564596f93f5SRoland Stigge if (!request_mem_region(port->mapbase, SZ_4K, MODNAME)) 565596f93f5SRoland Stigge ret = -EBUSY; 566596f93f5SRoland Stigge else if (port->flags & UPF_IOREMAP) { 567596f93f5SRoland Stigge port->membase = ioremap(port->mapbase, SZ_4K); 568596f93f5SRoland Stigge if (!port->membase) { 569596f93f5SRoland Stigge release_mem_region(port->mapbase, SZ_4K); 570596f93f5SRoland Stigge ret = -ENOMEM; 571596f93f5SRoland Stigge } 572596f93f5SRoland Stigge } 573596f93f5SRoland Stigge } 574596f93f5SRoland Stigge 575596f93f5SRoland Stigge return ret; 576596f93f5SRoland Stigge } 577596f93f5SRoland Stigge 578596f93f5SRoland Stigge static void serial_lpc32xx_config_port(struct uart_port *port, int uflags) 579596f93f5SRoland Stigge { 580596f93f5SRoland Stigge int ret; 581596f93f5SRoland Stigge 582596f93f5SRoland Stigge ret = serial_lpc32xx_request_port(port); 583596f93f5SRoland Stigge if (ret < 0) 584596f93f5SRoland Stigge return; 585596f93f5SRoland Stigge port->type = PORT_UART00; 586596f93f5SRoland Stigge port->fifosize = 64; 587596f93f5SRoland Stigge 588596f93f5SRoland Stigge __serial_uart_flush(port); 589596f93f5SRoland Stigge 590596f93f5SRoland Stigge writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 591596f93f5SRoland Stigge LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 592596f93f5SRoland Stigge LPC32XX_HSUART_IIR(port->membase)); 593596f93f5SRoland Stigge 594596f93f5SRoland Stigge writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 595596f93f5SRoland Stigge 596596f93f5SRoland Stigge /* Set receiver timeout, HSU offset of 20, no break, no interrupts, 597596f93f5SRoland Stigge and default FIFO trigger levels */ 598596f93f5SRoland Stigge writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 599596f93f5SRoland Stigge LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B, 600596f93f5SRoland Stigge LPC32XX_HSUART_CTRL(port->membase)); 601596f93f5SRoland Stigge } 602596f93f5SRoland Stigge 603596f93f5SRoland Stigge static int serial_lpc32xx_verify_port(struct uart_port *port, 604596f93f5SRoland Stigge struct serial_struct *ser) 605596f93f5SRoland Stigge { 606596f93f5SRoland Stigge int ret = 0; 607596f93f5SRoland Stigge 608596f93f5SRoland Stigge if (ser->type != PORT_UART00) 609596f93f5SRoland Stigge ret = -EINVAL; 610596f93f5SRoland Stigge 611596f93f5SRoland Stigge return ret; 612596f93f5SRoland Stigge } 613596f93f5SRoland Stigge 6142331e068SBhumika Goyal static const struct uart_ops serial_lpc32xx_pops = { 615596f93f5SRoland Stigge .tx_empty = serial_lpc32xx_tx_empty, 616596f93f5SRoland Stigge .set_mctrl = serial_lpc32xx_set_mctrl, 617596f93f5SRoland Stigge .get_mctrl = serial_lpc32xx_get_mctrl, 618596f93f5SRoland Stigge .stop_tx = serial_lpc32xx_stop_tx, 619596f93f5SRoland Stigge .start_tx = serial_lpc32xx_start_tx, 620596f93f5SRoland Stigge .stop_rx = serial_lpc32xx_stop_rx, 621596f93f5SRoland Stigge .break_ctl = serial_lpc32xx_break_ctl, 622596f93f5SRoland Stigge .startup = serial_lpc32xx_startup, 623596f93f5SRoland Stigge .shutdown = serial_lpc32xx_shutdown, 624596f93f5SRoland Stigge .set_termios = serial_lpc32xx_set_termios, 625596f93f5SRoland Stigge .type = serial_lpc32xx_type, 626596f93f5SRoland Stigge .release_port = serial_lpc32xx_release_port, 627596f93f5SRoland Stigge .request_port = serial_lpc32xx_request_port, 628596f93f5SRoland Stigge .config_port = serial_lpc32xx_config_port, 629596f93f5SRoland Stigge .verify_port = serial_lpc32xx_verify_port, 630596f93f5SRoland Stigge }; 631596f93f5SRoland Stigge 632596f93f5SRoland Stigge /* 633596f93f5SRoland Stigge * Register a set of serial devices attached to a platform device 634596f93f5SRoland Stigge */ 6359671f099SBill Pemberton static int serial_hs_lpc32xx_probe(struct platform_device *pdev) 636596f93f5SRoland Stigge { 637596f93f5SRoland Stigge struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered]; 638596f93f5SRoland Stigge int ret = 0; 639596f93f5SRoland Stigge struct resource *res; 640596f93f5SRoland Stigge 641596f93f5SRoland Stigge if (uarts_registered >= MAX_PORTS) { 642596f93f5SRoland Stigge dev_err(&pdev->dev, 643596f93f5SRoland Stigge "Error: Number of possible ports exceeded (%d)!\n", 644596f93f5SRoland Stigge uarts_registered + 1); 645596f93f5SRoland Stigge return -ENXIO; 646596f93f5SRoland Stigge } 647596f93f5SRoland Stigge 648596f93f5SRoland Stigge memset(p, 0, sizeof(*p)); 649596f93f5SRoland Stigge 650596f93f5SRoland Stigge res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 651596f93f5SRoland Stigge if (!res) { 652596f93f5SRoland Stigge dev_err(&pdev->dev, 653596f93f5SRoland Stigge "Error getting mem resource for HS UART port %d\n", 654596f93f5SRoland Stigge uarts_registered); 655596f93f5SRoland Stigge return -ENXIO; 656596f93f5SRoland Stigge } 657596f93f5SRoland Stigge p->port.mapbase = res->start; 658596f93f5SRoland Stigge p->port.membase = NULL; 659596f93f5SRoland Stigge 66014996122SAndrzej Hajda ret = platform_get_irq(pdev, 0); 66114996122SAndrzej Hajda if (ret < 0) { 662596f93f5SRoland Stigge dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n", 663596f93f5SRoland Stigge uarts_registered); 66414996122SAndrzej Hajda return ret; 665596f93f5SRoland Stigge } 66614996122SAndrzej Hajda p->port.irq = ret; 667596f93f5SRoland Stigge 668596f93f5SRoland Stigge p->port.iotype = UPIO_MEM32; 669596f93f5SRoland Stigge p->port.uartclk = LPC32XX_MAIN_OSC_FREQ; 670596f93f5SRoland Stigge p->port.regshift = 2; 671596f93f5SRoland Stigge p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; 672596f93f5SRoland Stigge p->port.dev = &pdev->dev; 673596f93f5SRoland Stigge p->port.ops = &serial_lpc32xx_pops; 674596f93f5SRoland Stigge p->port.line = uarts_registered++; 675596f93f5SRoland Stigge spin_lock_init(&p->port.lock); 676596f93f5SRoland Stigge 677596f93f5SRoland Stigge /* send port to loopback mode by default */ 678596f93f5SRoland Stigge lpc32xx_loopback_set(p->port.mapbase, 1); 679596f93f5SRoland Stigge 680596f93f5SRoland Stigge ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port); 681596f93f5SRoland Stigge 682596f93f5SRoland Stigge platform_set_drvdata(pdev, p); 683596f93f5SRoland Stigge 684596f93f5SRoland Stigge return ret; 685596f93f5SRoland Stigge } 686596f93f5SRoland Stigge 687596f93f5SRoland Stigge /* 688596f93f5SRoland Stigge * Remove serial ports registered against a platform device. 689596f93f5SRoland Stigge */ 690ae8d8a14SBill Pemberton static int serial_hs_lpc32xx_remove(struct platform_device *pdev) 691596f93f5SRoland Stigge { 692596f93f5SRoland Stigge struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 693596f93f5SRoland Stigge 694596f93f5SRoland Stigge uart_remove_one_port(&lpc32xx_hs_reg, &p->port); 695596f93f5SRoland Stigge 696596f93f5SRoland Stigge return 0; 697596f93f5SRoland Stigge } 698596f93f5SRoland Stigge 699596f93f5SRoland Stigge 700596f93f5SRoland Stigge #ifdef CONFIG_PM 701596f93f5SRoland Stigge static int serial_hs_lpc32xx_suspend(struct platform_device *pdev, 702596f93f5SRoland Stigge pm_message_t state) 703596f93f5SRoland Stigge { 704596f93f5SRoland Stigge struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 705596f93f5SRoland Stigge 706596f93f5SRoland Stigge uart_suspend_port(&lpc32xx_hs_reg, &p->port); 707596f93f5SRoland Stigge 708596f93f5SRoland Stigge return 0; 709596f93f5SRoland Stigge } 710596f93f5SRoland Stigge 711596f93f5SRoland Stigge static int serial_hs_lpc32xx_resume(struct platform_device *pdev) 712596f93f5SRoland Stigge { 713596f93f5SRoland Stigge struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 714596f93f5SRoland Stigge 715596f93f5SRoland Stigge uart_resume_port(&lpc32xx_hs_reg, &p->port); 716596f93f5SRoland Stigge 717596f93f5SRoland Stigge return 0; 718596f93f5SRoland Stigge } 719596f93f5SRoland Stigge #else 720596f93f5SRoland Stigge #define serial_hs_lpc32xx_suspend NULL 721596f93f5SRoland Stigge #define serial_hs_lpc32xx_resume NULL 722596f93f5SRoland Stigge #endif 723596f93f5SRoland Stigge 724596f93f5SRoland Stigge static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = { 725596f93f5SRoland Stigge { .compatible = "nxp,lpc3220-hsuart" }, 726596f93f5SRoland Stigge { /* sentinel */ } 727596f93f5SRoland Stigge }; 728596f93f5SRoland Stigge 729596f93f5SRoland Stigge MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids); 730596f93f5SRoland Stigge 731596f93f5SRoland Stigge static struct platform_driver serial_hs_lpc32xx_driver = { 732596f93f5SRoland Stigge .probe = serial_hs_lpc32xx_probe, 7332d47b716SBill Pemberton .remove = serial_hs_lpc32xx_remove, 734596f93f5SRoland Stigge .suspend = serial_hs_lpc32xx_suspend, 735596f93f5SRoland Stigge .resume = serial_hs_lpc32xx_resume, 736596f93f5SRoland Stigge .driver = { 737596f93f5SRoland Stigge .name = MODNAME, 738596f93f5SRoland Stigge .of_match_table = serial_hs_lpc32xx_dt_ids, 739596f93f5SRoland Stigge }, 740596f93f5SRoland Stigge }; 741596f93f5SRoland Stigge 742596f93f5SRoland Stigge static int __init lpc32xx_hsuart_init(void) 743596f93f5SRoland Stigge { 744596f93f5SRoland Stigge int ret; 745596f93f5SRoland Stigge 746596f93f5SRoland Stigge ret = uart_register_driver(&lpc32xx_hs_reg); 747596f93f5SRoland Stigge if (ret) 748596f93f5SRoland Stigge return ret; 749596f93f5SRoland Stigge 750596f93f5SRoland Stigge ret = platform_driver_register(&serial_hs_lpc32xx_driver); 751596f93f5SRoland Stigge if (ret) 752596f93f5SRoland Stigge uart_unregister_driver(&lpc32xx_hs_reg); 753596f93f5SRoland Stigge 754596f93f5SRoland Stigge return ret; 755596f93f5SRoland Stigge } 756596f93f5SRoland Stigge 757596f93f5SRoland Stigge static void __exit lpc32xx_hsuart_exit(void) 758596f93f5SRoland Stigge { 759596f93f5SRoland Stigge platform_driver_unregister(&serial_hs_lpc32xx_driver); 760596f93f5SRoland Stigge uart_unregister_driver(&lpc32xx_hs_reg); 761596f93f5SRoland Stigge } 762596f93f5SRoland Stigge 763596f93f5SRoland Stigge module_init(lpc32xx_hsuart_init); 764596f93f5SRoland Stigge module_exit(lpc32xx_hsuart_exit); 765596f93f5SRoland Stigge 766596f93f5SRoland Stigge MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 767596f93f5SRoland Stigge MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 768596f93f5SRoland Stigge MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver"); 769596f93f5SRoland Stigge MODULE_LICENSE("GPL"); 770