1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+
2596f93f5SRoland Stigge /*
3596f93f5SRoland Stigge * High Speed Serial Ports on NXP LPC32xx SoC
4596f93f5SRoland Stigge *
5596f93f5SRoland Stigge * Authors: Kevin Wells <kevin.wells@nxp.com>
6596f93f5SRoland Stigge * Roland Stigge <stigge@antcom.de>
7596f93f5SRoland Stigge *
8596f93f5SRoland Stigge * Copyright (C) 2010 NXP Semiconductors
9596f93f5SRoland Stigge * Copyright (C) 2012 Roland Stigge
10596f93f5SRoland Stigge */
11596f93f5SRoland Stigge
12596f93f5SRoland Stigge #include <linux/module.h>
13596f93f5SRoland Stigge #include <linux/ioport.h>
14596f93f5SRoland Stigge #include <linux/init.h>
15596f93f5SRoland Stigge #include <linux/console.h>
16596f93f5SRoland Stigge #include <linux/sysrq.h>
17596f93f5SRoland Stigge #include <linux/tty.h>
18596f93f5SRoland Stigge #include <linux/tty_flip.h>
19596f93f5SRoland Stigge #include <linux/serial_core.h>
20596f93f5SRoland Stigge #include <linux/serial.h>
21596f93f5SRoland Stigge #include <linux/platform_device.h>
22596f93f5SRoland Stigge #include <linux/delay.h>
23596f93f5SRoland Stigge #include <linux/nmi.h>
24596f93f5SRoland Stigge #include <linux/io.h>
25596f93f5SRoland Stigge #include <linux/irq.h>
26596f93f5SRoland Stigge #include <linux/of.h>
27ffba29c9SArnd Bergmann #include <linux/sizes.h>
28ffba29c9SArnd Bergmann #include <linux/soc/nxp/lpc32xx-misc.h>
29596f93f5SRoland Stigge
30596f93f5SRoland Stigge /*
31596f93f5SRoland Stigge * High Speed UART register offsets
32596f93f5SRoland Stigge */
33596f93f5SRoland Stigge #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
34596f93f5SRoland Stigge #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
35596f93f5SRoland Stigge #define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
36596f93f5SRoland Stigge #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
37596f93f5SRoland Stigge #define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
38596f93f5SRoland Stigge
39596f93f5SRoland Stigge #define LPC32XX_HSU_BREAK_DATA (1 << 10)
40596f93f5SRoland Stigge #define LPC32XX_HSU_ERROR_DATA (1 << 9)
41596f93f5SRoland Stigge #define LPC32XX_HSU_RX_EMPTY (1 << 8)
42596f93f5SRoland Stigge
43596f93f5SRoland Stigge #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
44596f93f5SRoland Stigge #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
45596f93f5SRoland Stigge
46596f93f5SRoland Stigge #define LPC32XX_HSU_TX_INT_SET (1 << 6)
47596f93f5SRoland Stigge #define LPC32XX_HSU_RX_OE_INT (1 << 5)
48596f93f5SRoland Stigge #define LPC32XX_HSU_BRK_INT (1 << 4)
49596f93f5SRoland Stigge #define LPC32XX_HSU_FE_INT (1 << 3)
50596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
51596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
52596f93f5SRoland Stigge #define LPC32XX_HSU_TX_INT (1 << 0)
53596f93f5SRoland Stigge
54596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_INV (1 << 21)
55596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
56596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
57596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
58596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
59596f93f5SRoland Stigge #define LPC32XX_HSU_HRTS_EN (1 << 18)
60596f93f5SRoland Stigge #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
61596f93f5SRoland Stigge #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
62596f93f5SRoland Stigge #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
63596f93f5SRoland Stigge #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
64596f93f5SRoland Stigge #define LPC32XX_HSU_HCTS_INV (1 << 15)
65596f93f5SRoland Stigge #define LPC32XX_HSU_HCTS_EN (1 << 14)
66596f93f5SRoland Stigge #define LPC32XX_HSU_OFFSET(n) ((n) << 9)
67596f93f5SRoland Stigge #define LPC32XX_HSU_BREAK (1 << 8)
68596f93f5SRoland Stigge #define LPC32XX_HSU_ERR_INT_EN (1 << 7)
69596f93f5SRoland Stigge #define LPC32XX_HSU_RX_INT_EN (1 << 6)
70596f93f5SRoland Stigge #define LPC32XX_HSU_TX_INT_EN (1 << 5)
71596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL1B (0x0 << 2)
72596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL4B (0x1 << 2)
73596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL8B (0x2 << 2)
74596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL16B (0x3 << 2)
75596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL32B (0x4 << 2)
76596f93f5SRoland Stigge #define LPC32XX_HSU_RX_TL48B (0x5 << 2)
77596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
78596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TL0B (0x0 << 0)
79596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TL4B (0x1 << 0)
80596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TL8B (0x2 << 0)
81596f93f5SRoland Stigge #define LPC32XX_HSU_TX_TL16B (0x3 << 0)
82596f93f5SRoland Stigge
83ffba29c9SArnd Bergmann #define LPC32XX_MAIN_OSC_FREQ 13000000
84ffba29c9SArnd Bergmann
85596f93f5SRoland Stigge #define MODNAME "lpc32xx_hsuart"
86596f93f5SRoland Stigge
87596f93f5SRoland Stigge struct lpc32xx_hsuart_port {
88596f93f5SRoland Stigge struct uart_port port;
89596f93f5SRoland Stigge };
90596f93f5SRoland Stigge
91596f93f5SRoland Stigge #define FIFO_READ_LIMIT 128
92596f93f5SRoland Stigge #define MAX_PORTS 3
93596f93f5SRoland Stigge #define LPC32XX_TTY_NAME "ttyTX"
94596f93f5SRoland Stigge static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
95596f93f5SRoland Stigge
96596f93f5SRoland Stigge #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
wait_for_xmit_empty(struct uart_port * port)97596f93f5SRoland Stigge static void wait_for_xmit_empty(struct uart_port *port)
98596f93f5SRoland Stigge {
99596f93f5SRoland Stigge unsigned int timeout = 10000;
100596f93f5SRoland Stigge
101596f93f5SRoland Stigge do {
102596f93f5SRoland Stigge if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
103596f93f5SRoland Stigge port->membase))) == 0)
104596f93f5SRoland Stigge break;
105596f93f5SRoland Stigge if (--timeout == 0)
106596f93f5SRoland Stigge break;
107596f93f5SRoland Stigge udelay(1);
108596f93f5SRoland Stigge } while (1);
109596f93f5SRoland Stigge }
110596f93f5SRoland Stigge
wait_for_xmit_ready(struct uart_port * port)111596f93f5SRoland Stigge static void wait_for_xmit_ready(struct uart_port *port)
112596f93f5SRoland Stigge {
113596f93f5SRoland Stigge unsigned int timeout = 10000;
114596f93f5SRoland Stigge
115596f93f5SRoland Stigge while (1) {
116596f93f5SRoland Stigge if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
117596f93f5SRoland Stigge port->membase))) < 32)
118596f93f5SRoland Stigge break;
119596f93f5SRoland Stigge if (--timeout == 0)
120596f93f5SRoland Stigge break;
121596f93f5SRoland Stigge udelay(1);
122596f93f5SRoland Stigge }
123596f93f5SRoland Stigge }
124596f93f5SRoland Stigge
lpc32xx_hsuart_console_putchar(struct uart_port * port,unsigned char ch)1253f8bab17SJiri Slaby static void lpc32xx_hsuart_console_putchar(struct uart_port *port, unsigned char ch)
126596f93f5SRoland Stigge {
127596f93f5SRoland Stigge wait_for_xmit_ready(port);
128596f93f5SRoland Stigge writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
129596f93f5SRoland Stigge }
130596f93f5SRoland Stigge
lpc32xx_hsuart_console_write(struct console * co,const char * s,unsigned int count)131596f93f5SRoland Stigge static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
132596f93f5SRoland Stigge unsigned int count)
133596f93f5SRoland Stigge {
134596f93f5SRoland Stigge struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
135596f93f5SRoland Stigge unsigned long flags;
136596f93f5SRoland Stigge int locked = 1;
137596f93f5SRoland Stigge
138596f93f5SRoland Stigge touch_nmi_watchdog();
139596f93f5SRoland Stigge local_irq_save(flags);
140596f93f5SRoland Stigge if (up->port.sysrq)
141596f93f5SRoland Stigge locked = 0;
142596f93f5SRoland Stigge else if (oops_in_progress)
143596f93f5SRoland Stigge locked = spin_trylock(&up->port.lock);
144596f93f5SRoland Stigge else
145596f93f5SRoland Stigge spin_lock(&up->port.lock);
146596f93f5SRoland Stigge
147596f93f5SRoland Stigge uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
148596f93f5SRoland Stigge wait_for_xmit_empty(&up->port);
149596f93f5SRoland Stigge
150596f93f5SRoland Stigge if (locked)
151596f93f5SRoland Stigge spin_unlock(&up->port.lock);
152596f93f5SRoland Stigge local_irq_restore(flags);
153596f93f5SRoland Stigge }
154596f93f5SRoland Stigge
lpc32xx_hsuart_console_setup(struct console * co,char * options)155596f93f5SRoland Stigge static int __init lpc32xx_hsuart_console_setup(struct console *co,
156596f93f5SRoland Stigge char *options)
157596f93f5SRoland Stigge {
158596f93f5SRoland Stigge struct uart_port *port;
159596f93f5SRoland Stigge int baud = 115200;
160596f93f5SRoland Stigge int bits = 8;
161596f93f5SRoland Stigge int parity = 'n';
162596f93f5SRoland Stigge int flow = 'n';
163596f93f5SRoland Stigge
164596f93f5SRoland Stigge if (co->index >= MAX_PORTS)
165596f93f5SRoland Stigge co->index = 0;
166596f93f5SRoland Stigge
167596f93f5SRoland Stigge port = &lpc32xx_hs_ports[co->index].port;
168596f93f5SRoland Stigge if (!port->membase)
169596f93f5SRoland Stigge return -ENODEV;
170596f93f5SRoland Stigge
171596f93f5SRoland Stigge if (options)
172596f93f5SRoland Stigge uart_parse_options(options, &baud, &parity, &bits, &flow);
173596f93f5SRoland Stigge
174b30fd1a6SAlexandre Belloni lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
175b30fd1a6SAlexandre Belloni
176596f93f5SRoland Stigge return uart_set_options(port, co, baud, parity, bits, flow);
177596f93f5SRoland Stigge }
178596f93f5SRoland Stigge
179596f93f5SRoland Stigge static struct uart_driver lpc32xx_hsuart_reg;
180596f93f5SRoland Stigge static struct console lpc32xx_hsuart_console = {
181596f93f5SRoland Stigge .name = LPC32XX_TTY_NAME,
182596f93f5SRoland Stigge .write = lpc32xx_hsuart_console_write,
183596f93f5SRoland Stigge .device = uart_console_device,
184596f93f5SRoland Stigge .setup = lpc32xx_hsuart_console_setup,
185596f93f5SRoland Stigge .flags = CON_PRINTBUFFER,
186596f93f5SRoland Stigge .index = -1,
187596f93f5SRoland Stigge .data = &lpc32xx_hsuart_reg,
188596f93f5SRoland Stigge };
189596f93f5SRoland Stigge
lpc32xx_hsuart_console_init(void)190596f93f5SRoland Stigge static int __init lpc32xx_hsuart_console_init(void)
191596f93f5SRoland Stigge {
192596f93f5SRoland Stigge register_console(&lpc32xx_hsuart_console);
193596f93f5SRoland Stigge return 0;
194596f93f5SRoland Stigge }
195596f93f5SRoland Stigge console_initcall(lpc32xx_hsuart_console_init);
196596f93f5SRoland Stigge
197596f93f5SRoland Stigge #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
198596f93f5SRoland Stigge #else
199596f93f5SRoland Stigge #define LPC32XX_HSUART_CONSOLE NULL
200596f93f5SRoland Stigge #endif
201596f93f5SRoland Stigge
202596f93f5SRoland Stigge static struct uart_driver lpc32xx_hs_reg = {
203596f93f5SRoland Stigge .owner = THIS_MODULE,
204596f93f5SRoland Stigge .driver_name = MODNAME,
205596f93f5SRoland Stigge .dev_name = LPC32XX_TTY_NAME,
206596f93f5SRoland Stigge .nr = MAX_PORTS,
207596f93f5SRoland Stigge .cons = LPC32XX_HSUART_CONSOLE,
208596f93f5SRoland Stigge };
209596f93f5SRoland Stigge static int uarts_registered;
210596f93f5SRoland Stigge
__serial_get_clock_div(unsigned long uartclk,unsigned long rate)211596f93f5SRoland Stigge static unsigned int __serial_get_clock_div(unsigned long uartclk,
212596f93f5SRoland Stigge unsigned long rate)
213596f93f5SRoland Stigge {
214596f93f5SRoland Stigge u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
215596f93f5SRoland Stigge u32 rate_diff;
216596f93f5SRoland Stigge
217596f93f5SRoland Stigge /* Find the closest divider to get the desired clock rate */
218596f93f5SRoland Stigge div = uartclk / rate;
219596f93f5SRoland Stigge goodrate = hsu_rate = (div / 14) - 1;
220596f93f5SRoland Stigge if (hsu_rate != 0)
221596f93f5SRoland Stigge hsu_rate--;
222596f93f5SRoland Stigge
223596f93f5SRoland Stigge /* Tweak divider */
224596f93f5SRoland Stigge l_hsu_rate = hsu_rate + 3;
225596f93f5SRoland Stigge rate_diff = 0xFFFFFFFF;
226596f93f5SRoland Stigge
227596f93f5SRoland Stigge while (hsu_rate < l_hsu_rate) {
228596f93f5SRoland Stigge comprate = uartclk / ((hsu_rate + 1) * 14);
229596f93f5SRoland Stigge if (abs(comprate - rate) < rate_diff) {
230596f93f5SRoland Stigge goodrate = hsu_rate;
231596f93f5SRoland Stigge rate_diff = abs(comprate - rate);
232596f93f5SRoland Stigge }
233596f93f5SRoland Stigge
234596f93f5SRoland Stigge hsu_rate++;
235596f93f5SRoland Stigge }
236596f93f5SRoland Stigge if (hsu_rate > 0xFF)
237596f93f5SRoland Stigge hsu_rate = 0xFF;
238596f93f5SRoland Stigge
239596f93f5SRoland Stigge return goodrate;
240596f93f5SRoland Stigge }
241596f93f5SRoland Stigge
__serial_uart_flush(struct uart_port * port)242596f93f5SRoland Stigge static void __serial_uart_flush(struct uart_port *port)
243596f93f5SRoland Stigge {
244596f93f5SRoland Stigge int cnt = 0;
245596f93f5SRoland Stigge
246596f93f5SRoland Stigge while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
247596f93f5SRoland Stigge (cnt++ < FIFO_READ_LIMIT))
248c4e3f0c0SLee Jones readl(LPC32XX_HSUART_FIFO(port->membase));
249596f93f5SRoland Stigge }
250596f93f5SRoland Stigge
__serial_lpc32xx_rx(struct uart_port * port)251596f93f5SRoland Stigge static void __serial_lpc32xx_rx(struct uart_port *port)
252596f93f5SRoland Stigge {
25392a19f9cSJiri Slaby struct tty_port *tport = &port->state->port;
254596f93f5SRoland Stigge unsigned int tmp, flag;
255596f93f5SRoland Stigge
256596f93f5SRoland Stigge /* Read data from FIFO and push into terminal */
257596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
258596f93f5SRoland Stigge while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
259596f93f5SRoland Stigge flag = TTY_NORMAL;
260596f93f5SRoland Stigge port->icount.rx++;
261596f93f5SRoland Stigge
262596f93f5SRoland Stigge if (tmp & LPC32XX_HSU_ERROR_DATA) {
263596f93f5SRoland Stigge /* Framing error */
264596f93f5SRoland Stigge writel(LPC32XX_HSU_FE_INT,
265596f93f5SRoland Stigge LPC32XX_HSUART_IIR(port->membase));
266596f93f5SRoland Stigge port->icount.frame++;
267596f93f5SRoland Stigge flag = TTY_FRAME;
26892a19f9cSJiri Slaby tty_insert_flip_char(tport, 0, TTY_FRAME);
269596f93f5SRoland Stigge }
270596f93f5SRoland Stigge
27192a19f9cSJiri Slaby tty_insert_flip_char(tport, (tmp & 0xFF), flag);
272596f93f5SRoland Stigge
273596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
274596f93f5SRoland Stigge }
275ec128510SViresh Kumar
2762e124b4aSJiri Slaby tty_flip_buffer_push(tport);
277596f93f5SRoland Stigge }
278596f93f5SRoland Stigge
serial_lpc32xx_tx_ready(struct uart_port * port)2792a4be3a5SJiri Slaby static bool serial_lpc32xx_tx_ready(struct uart_port *port)
2802a4be3a5SJiri Slaby {
2812a4be3a5SJiri Slaby u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase));
2822a4be3a5SJiri Slaby
2832a4be3a5SJiri Slaby return LPC32XX_HSU_TX_LEV(level) < 64;
2842a4be3a5SJiri Slaby }
2852a4be3a5SJiri Slaby
__serial_lpc32xx_tx(struct uart_port * port)286596f93f5SRoland Stigge static void __serial_lpc32xx_tx(struct uart_port *port)
287596f93f5SRoland Stigge {
288*2d141e68SJiri Slaby (SUSE) u8 ch;
289596f93f5SRoland Stigge
290*2d141e68SJiri Slaby (SUSE) uart_port_tx(port, ch,
291*2d141e68SJiri Slaby (SUSE) serial_lpc32xx_tx_ready(port),
292*2d141e68SJiri Slaby (SUSE) writel(ch, LPC32XX_HSUART_FIFO(port->membase)));
293596f93f5SRoland Stigge }
294596f93f5SRoland Stigge
serial_lpc32xx_interrupt(int irq,void * dev_id)295596f93f5SRoland Stigge static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
296596f93f5SRoland Stigge {
297596f93f5SRoland Stigge struct uart_port *port = dev_id;
29833aeb9daSThierry Reding struct tty_port *tport = &port->state->port;
299596f93f5SRoland Stigge u32 status;
300596f93f5SRoland Stigge
301596f93f5SRoland Stigge spin_lock(&port->lock);
302596f93f5SRoland Stigge
303596f93f5SRoland Stigge /* Read UART status and clear latched interrupts */
304596f93f5SRoland Stigge status = readl(LPC32XX_HSUART_IIR(port->membase));
305596f93f5SRoland Stigge
306596f93f5SRoland Stigge if (status & LPC32XX_HSU_BRK_INT) {
307596f93f5SRoland Stigge /* Break received */
308596f93f5SRoland Stigge writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
309596f93f5SRoland Stigge port->icount.brk++;
310596f93f5SRoland Stigge uart_handle_break(port);
311596f93f5SRoland Stigge }
312596f93f5SRoland Stigge
313596f93f5SRoland Stigge /* Framing error */
314596f93f5SRoland Stigge if (status & LPC32XX_HSU_FE_INT)
315596f93f5SRoland Stigge writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
316596f93f5SRoland Stigge
317596f93f5SRoland Stigge if (status & LPC32XX_HSU_RX_OE_INT) {
318596f93f5SRoland Stigge /* Receive FIFO overrun */
319596f93f5SRoland Stigge writel(LPC32XX_HSU_RX_OE_INT,
320596f93f5SRoland Stigge LPC32XX_HSUART_IIR(port->membase));
321596f93f5SRoland Stigge port->icount.overrun++;
32292a19f9cSJiri Slaby tty_insert_flip_char(tport, 0, TTY_OVERRUN);
3235f6a8515SJiri Slaby tty_flip_buffer_push(tport);
324596f93f5SRoland Stigge }
325596f93f5SRoland Stigge
326596f93f5SRoland Stigge /* Data received? */
32797f2c428SViresh Kumar if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
328596f93f5SRoland Stigge __serial_lpc32xx_rx(port);
329596f93f5SRoland Stigge
330596f93f5SRoland Stigge /* Transmit data request? */
331596f93f5SRoland Stigge if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
332596f93f5SRoland Stigge writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
333596f93f5SRoland Stigge __serial_lpc32xx_tx(port);
334596f93f5SRoland Stigge }
335596f93f5SRoland Stigge
336596f93f5SRoland Stigge spin_unlock(&port->lock);
337596f93f5SRoland Stigge
338596f93f5SRoland Stigge return IRQ_HANDLED;
339596f93f5SRoland Stigge }
340596f93f5SRoland Stigge
341596f93f5SRoland Stigge /* port->lock is not held. */
serial_lpc32xx_tx_empty(struct uart_port * port)342596f93f5SRoland Stigge static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
343596f93f5SRoland Stigge {
344596f93f5SRoland Stigge unsigned int ret = 0;
345596f93f5SRoland Stigge
346596f93f5SRoland Stigge if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
347596f93f5SRoland Stigge ret = TIOCSER_TEMT;
348596f93f5SRoland Stigge
349596f93f5SRoland Stigge return ret;
350596f93f5SRoland Stigge }
351596f93f5SRoland Stigge
352596f93f5SRoland Stigge /* port->lock held by caller. */
serial_lpc32xx_set_mctrl(struct uart_port * port,unsigned int mctrl)353596f93f5SRoland Stigge static void serial_lpc32xx_set_mctrl(struct uart_port *port,
354596f93f5SRoland Stigge unsigned int mctrl)
355596f93f5SRoland Stigge {
356596f93f5SRoland Stigge /* No signals are supported on HS UARTs */
357596f93f5SRoland Stigge }
358596f93f5SRoland Stigge
359596f93f5SRoland Stigge /* port->lock is held by caller and interrupts are disabled. */
serial_lpc32xx_get_mctrl(struct uart_port * port)360596f93f5SRoland Stigge static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
361596f93f5SRoland Stigge {
362596f93f5SRoland Stigge /* No signals are supported on HS UARTs */
363596f93f5SRoland Stigge return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
364596f93f5SRoland Stigge }
365596f93f5SRoland Stigge
366596f93f5SRoland Stigge /* port->lock held by caller. */
serial_lpc32xx_stop_tx(struct uart_port * port)367596f93f5SRoland Stigge static void serial_lpc32xx_stop_tx(struct uart_port *port)
368596f93f5SRoland Stigge {
369596f93f5SRoland Stigge u32 tmp;
370596f93f5SRoland Stigge
371596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
372596f93f5SRoland Stigge tmp &= ~LPC32XX_HSU_TX_INT_EN;
373596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
374596f93f5SRoland Stigge }
375596f93f5SRoland Stigge
376596f93f5SRoland Stigge /* port->lock held by caller. */
serial_lpc32xx_start_tx(struct uart_port * port)377596f93f5SRoland Stigge static void serial_lpc32xx_start_tx(struct uart_port *port)
378596f93f5SRoland Stigge {
379596f93f5SRoland Stigge u32 tmp;
380596f93f5SRoland Stigge
381596f93f5SRoland Stigge __serial_lpc32xx_tx(port);
382596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
383596f93f5SRoland Stigge tmp |= LPC32XX_HSU_TX_INT_EN;
384596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
385596f93f5SRoland Stigge }
386596f93f5SRoland Stigge
387596f93f5SRoland Stigge /* port->lock held by caller. */
serial_lpc32xx_stop_rx(struct uart_port * port)388596f93f5SRoland Stigge static void serial_lpc32xx_stop_rx(struct uart_port *port)
389596f93f5SRoland Stigge {
390596f93f5SRoland Stigge u32 tmp;
391596f93f5SRoland Stigge
392596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
393596f93f5SRoland Stigge tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
394596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
395596f93f5SRoland Stigge
396596f93f5SRoland Stigge writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
397596f93f5SRoland Stigge LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
398596f93f5SRoland Stigge }
399596f93f5SRoland Stigge
400596f93f5SRoland Stigge /* port->lock is not held. */
serial_lpc32xx_break_ctl(struct uart_port * port,int break_state)401596f93f5SRoland Stigge static void serial_lpc32xx_break_ctl(struct uart_port *port,
402596f93f5SRoland Stigge int break_state)
403596f93f5SRoland Stigge {
404596f93f5SRoland Stigge unsigned long flags;
405596f93f5SRoland Stigge u32 tmp;
406596f93f5SRoland Stigge
407596f93f5SRoland Stigge spin_lock_irqsave(&port->lock, flags);
408596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
409596f93f5SRoland Stigge if (break_state != 0)
410596f93f5SRoland Stigge tmp |= LPC32XX_HSU_BREAK;
411596f93f5SRoland Stigge else
412596f93f5SRoland Stigge tmp &= ~LPC32XX_HSU_BREAK;
413596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
414596f93f5SRoland Stigge spin_unlock_irqrestore(&port->lock, flags);
415596f93f5SRoland Stigge }
416596f93f5SRoland Stigge
417596f93f5SRoland Stigge /* port->lock is not held. */
serial_lpc32xx_startup(struct uart_port * port)418596f93f5SRoland Stigge static int serial_lpc32xx_startup(struct uart_port *port)
419596f93f5SRoland Stigge {
420596f93f5SRoland Stigge int retval;
421596f93f5SRoland Stigge unsigned long flags;
422596f93f5SRoland Stigge u32 tmp;
423596f93f5SRoland Stigge
424596f93f5SRoland Stigge spin_lock_irqsave(&port->lock, flags);
425596f93f5SRoland Stigge
426596f93f5SRoland Stigge __serial_uart_flush(port);
427596f93f5SRoland Stigge
428596f93f5SRoland Stigge writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
429596f93f5SRoland Stigge LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
430596f93f5SRoland Stigge LPC32XX_HSUART_IIR(port->membase));
431596f93f5SRoland Stigge
432596f93f5SRoland Stigge writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
433596f93f5SRoland Stigge
434596f93f5SRoland Stigge /*
435596f93f5SRoland Stigge * Set receiver timeout, HSU offset of 20, no break, no interrupts,
436596f93f5SRoland Stigge * and default FIFO trigger levels
437596f93f5SRoland Stigge */
438596f93f5SRoland Stigge tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
439596f93f5SRoland Stigge LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
440596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
441596f93f5SRoland Stigge
442596f93f5SRoland Stigge lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
443596f93f5SRoland Stigge
444596f93f5SRoland Stigge spin_unlock_irqrestore(&port->lock, flags);
445596f93f5SRoland Stigge
446596f93f5SRoland Stigge retval = request_irq(port->irq, serial_lpc32xx_interrupt,
447596f93f5SRoland Stigge 0, MODNAME, port);
448596f93f5SRoland Stigge if (!retval)
449596f93f5SRoland Stigge writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
450596f93f5SRoland Stigge LPC32XX_HSUART_CTRL(port->membase));
451596f93f5SRoland Stigge
452596f93f5SRoland Stigge return retval;
453596f93f5SRoland Stigge }
454596f93f5SRoland Stigge
455596f93f5SRoland Stigge /* port->lock is not held. */
serial_lpc32xx_shutdown(struct uart_port * port)456596f93f5SRoland Stigge static void serial_lpc32xx_shutdown(struct uart_port *port)
457596f93f5SRoland Stigge {
458596f93f5SRoland Stigge u32 tmp;
459596f93f5SRoland Stigge unsigned long flags;
460596f93f5SRoland Stigge
461596f93f5SRoland Stigge spin_lock_irqsave(&port->lock, flags);
462596f93f5SRoland Stigge
463596f93f5SRoland Stigge tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
464596f93f5SRoland Stigge LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
465596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
466596f93f5SRoland Stigge
467596f93f5SRoland Stigge lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
468596f93f5SRoland Stigge
469596f93f5SRoland Stigge spin_unlock_irqrestore(&port->lock, flags);
470596f93f5SRoland Stigge
471596f93f5SRoland Stigge free_irq(port->irq, port);
472596f93f5SRoland Stigge }
473596f93f5SRoland Stigge
474596f93f5SRoland Stigge /* port->lock is not held. */
serial_lpc32xx_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)475596f93f5SRoland Stigge static void serial_lpc32xx_set_termios(struct uart_port *port,
476596f93f5SRoland Stigge struct ktermios *termios,
477bec5b814SIlpo Järvinen const struct ktermios *old)
478596f93f5SRoland Stigge {
479596f93f5SRoland Stigge unsigned long flags;
480596f93f5SRoland Stigge unsigned int baud, quot;
481596f93f5SRoland Stigge u32 tmp;
482596f93f5SRoland Stigge
483596f93f5SRoland Stigge /* Always 8-bit, no parity, 1 stop bit */
484596f93f5SRoland Stigge termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
485596f93f5SRoland Stigge termios->c_cflag |= CS8;
486596f93f5SRoland Stigge
487596f93f5SRoland Stigge termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
488596f93f5SRoland Stigge
489596f93f5SRoland Stigge baud = uart_get_baud_rate(port, termios, old, 0,
490596f93f5SRoland Stigge port->uartclk / 14);
491596f93f5SRoland Stigge
492596f93f5SRoland Stigge quot = __serial_get_clock_div(port->uartclk, baud);
493596f93f5SRoland Stigge
494596f93f5SRoland Stigge spin_lock_irqsave(&port->lock, flags);
495596f93f5SRoland Stigge
496596f93f5SRoland Stigge /* Ignore characters? */
497596f93f5SRoland Stigge tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
498596f93f5SRoland Stigge if ((termios->c_cflag & CREAD) == 0)
499596f93f5SRoland Stigge tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
500596f93f5SRoland Stigge else
501596f93f5SRoland Stigge tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
502596f93f5SRoland Stigge writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
503596f93f5SRoland Stigge
504596f93f5SRoland Stigge writel(quot, LPC32XX_HSUART_RATE(port->membase));
505596f93f5SRoland Stigge
506596f93f5SRoland Stigge uart_update_timeout(port, termios->c_cflag, baud);
507596f93f5SRoland Stigge
508596f93f5SRoland Stigge spin_unlock_irqrestore(&port->lock, flags);
509596f93f5SRoland Stigge
510596f93f5SRoland Stigge /* Don't rewrite B0 */
511596f93f5SRoland Stigge if (tty_termios_baud_rate(termios))
512596f93f5SRoland Stigge tty_termios_encode_baud_rate(termios, baud, baud);
513596f93f5SRoland Stigge }
514596f93f5SRoland Stigge
serial_lpc32xx_type(struct uart_port * port)515596f93f5SRoland Stigge static const char *serial_lpc32xx_type(struct uart_port *port)
516596f93f5SRoland Stigge {
517596f93f5SRoland Stigge return MODNAME;
518596f93f5SRoland Stigge }
519596f93f5SRoland Stigge
serial_lpc32xx_release_port(struct uart_port * port)520596f93f5SRoland Stigge static void serial_lpc32xx_release_port(struct uart_port *port)
521596f93f5SRoland Stigge {
522596f93f5SRoland Stigge if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
523596f93f5SRoland Stigge if (port->flags & UPF_IOREMAP) {
524596f93f5SRoland Stigge iounmap(port->membase);
525596f93f5SRoland Stigge port->membase = NULL;
526596f93f5SRoland Stigge }
527596f93f5SRoland Stigge
528596f93f5SRoland Stigge release_mem_region(port->mapbase, SZ_4K);
529596f93f5SRoland Stigge }
530596f93f5SRoland Stigge }
531596f93f5SRoland Stigge
serial_lpc32xx_request_port(struct uart_port * port)532596f93f5SRoland Stigge static int serial_lpc32xx_request_port(struct uart_port *port)
533596f93f5SRoland Stigge {
534596f93f5SRoland Stigge int ret = -ENODEV;
535596f93f5SRoland Stigge
536596f93f5SRoland Stigge if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
537596f93f5SRoland Stigge ret = 0;
538596f93f5SRoland Stigge
539596f93f5SRoland Stigge if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
540596f93f5SRoland Stigge ret = -EBUSY;
541596f93f5SRoland Stigge else if (port->flags & UPF_IOREMAP) {
542596f93f5SRoland Stigge port->membase = ioremap(port->mapbase, SZ_4K);
543596f93f5SRoland Stigge if (!port->membase) {
544596f93f5SRoland Stigge release_mem_region(port->mapbase, SZ_4K);
545596f93f5SRoland Stigge ret = -ENOMEM;
546596f93f5SRoland Stigge }
547596f93f5SRoland Stigge }
548596f93f5SRoland Stigge }
549596f93f5SRoland Stigge
550596f93f5SRoland Stigge return ret;
551596f93f5SRoland Stigge }
552596f93f5SRoland Stigge
serial_lpc32xx_config_port(struct uart_port * port,int uflags)553596f93f5SRoland Stigge static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
554596f93f5SRoland Stigge {
555596f93f5SRoland Stigge int ret;
556596f93f5SRoland Stigge
557596f93f5SRoland Stigge ret = serial_lpc32xx_request_port(port);
558596f93f5SRoland Stigge if (ret < 0)
559596f93f5SRoland Stigge return;
560596f93f5SRoland Stigge port->type = PORT_UART00;
561596f93f5SRoland Stigge port->fifosize = 64;
562596f93f5SRoland Stigge
563596f93f5SRoland Stigge __serial_uart_flush(port);
564596f93f5SRoland Stigge
565596f93f5SRoland Stigge writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
566596f93f5SRoland Stigge LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
567596f93f5SRoland Stigge LPC32XX_HSUART_IIR(port->membase));
568596f93f5SRoland Stigge
569596f93f5SRoland Stigge writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
570596f93f5SRoland Stigge
571596f93f5SRoland Stigge /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
572596f93f5SRoland Stigge and default FIFO trigger levels */
573596f93f5SRoland Stigge writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
574596f93f5SRoland Stigge LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
575596f93f5SRoland Stigge LPC32XX_HSUART_CTRL(port->membase));
576596f93f5SRoland Stigge }
577596f93f5SRoland Stigge
serial_lpc32xx_verify_port(struct uart_port * port,struct serial_struct * ser)578596f93f5SRoland Stigge static int serial_lpc32xx_verify_port(struct uart_port *port,
579596f93f5SRoland Stigge struct serial_struct *ser)
580596f93f5SRoland Stigge {
581596f93f5SRoland Stigge int ret = 0;
582596f93f5SRoland Stigge
583596f93f5SRoland Stigge if (ser->type != PORT_UART00)
584596f93f5SRoland Stigge ret = -EINVAL;
585596f93f5SRoland Stigge
586596f93f5SRoland Stigge return ret;
587596f93f5SRoland Stigge }
588596f93f5SRoland Stigge
5892331e068SBhumika Goyal static const struct uart_ops serial_lpc32xx_pops = {
590596f93f5SRoland Stigge .tx_empty = serial_lpc32xx_tx_empty,
591596f93f5SRoland Stigge .set_mctrl = serial_lpc32xx_set_mctrl,
592596f93f5SRoland Stigge .get_mctrl = serial_lpc32xx_get_mctrl,
593596f93f5SRoland Stigge .stop_tx = serial_lpc32xx_stop_tx,
594596f93f5SRoland Stigge .start_tx = serial_lpc32xx_start_tx,
595596f93f5SRoland Stigge .stop_rx = serial_lpc32xx_stop_rx,
596596f93f5SRoland Stigge .break_ctl = serial_lpc32xx_break_ctl,
597596f93f5SRoland Stigge .startup = serial_lpc32xx_startup,
598596f93f5SRoland Stigge .shutdown = serial_lpc32xx_shutdown,
599596f93f5SRoland Stigge .set_termios = serial_lpc32xx_set_termios,
600596f93f5SRoland Stigge .type = serial_lpc32xx_type,
601596f93f5SRoland Stigge .release_port = serial_lpc32xx_release_port,
602596f93f5SRoland Stigge .request_port = serial_lpc32xx_request_port,
603596f93f5SRoland Stigge .config_port = serial_lpc32xx_config_port,
604596f93f5SRoland Stigge .verify_port = serial_lpc32xx_verify_port,
605596f93f5SRoland Stigge };
606596f93f5SRoland Stigge
607596f93f5SRoland Stigge /*
608596f93f5SRoland Stigge * Register a set of serial devices attached to a platform device
609596f93f5SRoland Stigge */
serial_hs_lpc32xx_probe(struct platform_device * pdev)6109671f099SBill Pemberton static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
611596f93f5SRoland Stigge {
612596f93f5SRoland Stigge struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
613596f93f5SRoland Stigge int ret = 0;
614596f93f5SRoland Stigge struct resource *res;
615596f93f5SRoland Stigge
616596f93f5SRoland Stigge if (uarts_registered >= MAX_PORTS) {
617596f93f5SRoland Stigge dev_err(&pdev->dev,
618596f93f5SRoland Stigge "Error: Number of possible ports exceeded (%d)!\n",
619596f93f5SRoland Stigge uarts_registered + 1);
620596f93f5SRoland Stigge return -ENXIO;
621596f93f5SRoland Stigge }
622596f93f5SRoland Stigge
623596f93f5SRoland Stigge memset(p, 0, sizeof(*p));
624596f93f5SRoland Stigge
625596f93f5SRoland Stigge res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626596f93f5SRoland Stigge if (!res) {
627596f93f5SRoland Stigge dev_err(&pdev->dev,
628596f93f5SRoland Stigge "Error getting mem resource for HS UART port %d\n",
629596f93f5SRoland Stigge uarts_registered);
630596f93f5SRoland Stigge return -ENXIO;
631596f93f5SRoland Stigge }
632596f93f5SRoland Stigge p->port.mapbase = res->start;
633596f93f5SRoland Stigge p->port.membase = NULL;
634596f93f5SRoland Stigge
63514996122SAndrzej Hajda ret = platform_get_irq(pdev, 0);
6361df21786SStephen Boyd if (ret < 0)
63714996122SAndrzej Hajda return ret;
63814996122SAndrzej Hajda p->port.irq = ret;
639596f93f5SRoland Stigge
640596f93f5SRoland Stigge p->port.iotype = UPIO_MEM32;
641596f93f5SRoland Stigge p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
642596f93f5SRoland Stigge p->port.regshift = 2;
643596f93f5SRoland Stigge p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
644596f93f5SRoland Stigge p->port.dev = &pdev->dev;
645596f93f5SRoland Stigge p->port.ops = &serial_lpc32xx_pops;
646596f93f5SRoland Stigge p->port.line = uarts_registered++;
647596f93f5SRoland Stigge spin_lock_init(&p->port.lock);
648596f93f5SRoland Stigge
649596f93f5SRoland Stigge /* send port to loopback mode by default */
650596f93f5SRoland Stigge lpc32xx_loopback_set(p->port.mapbase, 1);
651596f93f5SRoland Stigge
652596f93f5SRoland Stigge ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
653596f93f5SRoland Stigge
654596f93f5SRoland Stigge platform_set_drvdata(pdev, p);
655596f93f5SRoland Stigge
656596f93f5SRoland Stigge return ret;
657596f93f5SRoland Stigge }
658596f93f5SRoland Stigge
659596f93f5SRoland Stigge /*
660596f93f5SRoland Stigge * Remove serial ports registered against a platform device.
661596f93f5SRoland Stigge */
serial_hs_lpc32xx_remove(struct platform_device * pdev)662ae8d8a14SBill Pemberton static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
663596f93f5SRoland Stigge {
664596f93f5SRoland Stigge struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
665596f93f5SRoland Stigge
666596f93f5SRoland Stigge uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
667596f93f5SRoland Stigge
668596f93f5SRoland Stigge return 0;
669596f93f5SRoland Stigge }
670596f93f5SRoland Stigge
671596f93f5SRoland Stigge
672596f93f5SRoland Stigge #ifdef CONFIG_PM
serial_hs_lpc32xx_suspend(struct platform_device * pdev,pm_message_t state)673596f93f5SRoland Stigge static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
674596f93f5SRoland Stigge pm_message_t state)
675596f93f5SRoland Stigge {
676596f93f5SRoland Stigge struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
677596f93f5SRoland Stigge
678596f93f5SRoland Stigge uart_suspend_port(&lpc32xx_hs_reg, &p->port);
679596f93f5SRoland Stigge
680596f93f5SRoland Stigge return 0;
681596f93f5SRoland Stigge }
682596f93f5SRoland Stigge
serial_hs_lpc32xx_resume(struct platform_device * pdev)683596f93f5SRoland Stigge static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
684596f93f5SRoland Stigge {
685596f93f5SRoland Stigge struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
686596f93f5SRoland Stigge
687596f93f5SRoland Stigge uart_resume_port(&lpc32xx_hs_reg, &p->port);
688596f93f5SRoland Stigge
689596f93f5SRoland Stigge return 0;
690596f93f5SRoland Stigge }
691596f93f5SRoland Stigge #else
692596f93f5SRoland Stigge #define serial_hs_lpc32xx_suspend NULL
693596f93f5SRoland Stigge #define serial_hs_lpc32xx_resume NULL
694596f93f5SRoland Stigge #endif
695596f93f5SRoland Stigge
696596f93f5SRoland Stigge static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
697596f93f5SRoland Stigge { .compatible = "nxp,lpc3220-hsuart" },
698596f93f5SRoland Stigge { /* sentinel */ }
699596f93f5SRoland Stigge };
700596f93f5SRoland Stigge
701596f93f5SRoland Stigge MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
702596f93f5SRoland Stigge
703596f93f5SRoland Stigge static struct platform_driver serial_hs_lpc32xx_driver = {
704596f93f5SRoland Stigge .probe = serial_hs_lpc32xx_probe,
7052d47b716SBill Pemberton .remove = serial_hs_lpc32xx_remove,
706596f93f5SRoland Stigge .suspend = serial_hs_lpc32xx_suspend,
707596f93f5SRoland Stigge .resume = serial_hs_lpc32xx_resume,
708596f93f5SRoland Stigge .driver = {
709596f93f5SRoland Stigge .name = MODNAME,
710596f93f5SRoland Stigge .of_match_table = serial_hs_lpc32xx_dt_ids,
711596f93f5SRoland Stigge },
712596f93f5SRoland Stigge };
713596f93f5SRoland Stigge
lpc32xx_hsuart_init(void)714596f93f5SRoland Stigge static int __init lpc32xx_hsuart_init(void)
715596f93f5SRoland Stigge {
716596f93f5SRoland Stigge int ret;
717596f93f5SRoland Stigge
718596f93f5SRoland Stigge ret = uart_register_driver(&lpc32xx_hs_reg);
719596f93f5SRoland Stigge if (ret)
720596f93f5SRoland Stigge return ret;
721596f93f5SRoland Stigge
722596f93f5SRoland Stigge ret = platform_driver_register(&serial_hs_lpc32xx_driver);
723596f93f5SRoland Stigge if (ret)
724596f93f5SRoland Stigge uart_unregister_driver(&lpc32xx_hs_reg);
725596f93f5SRoland Stigge
726596f93f5SRoland Stigge return ret;
727596f93f5SRoland Stigge }
728596f93f5SRoland Stigge
lpc32xx_hsuart_exit(void)729596f93f5SRoland Stigge static void __exit lpc32xx_hsuart_exit(void)
730596f93f5SRoland Stigge {
731596f93f5SRoland Stigge platform_driver_unregister(&serial_hs_lpc32xx_driver);
732596f93f5SRoland Stigge uart_unregister_driver(&lpc32xx_hs_reg);
733596f93f5SRoland Stigge }
734596f93f5SRoland Stigge
735596f93f5SRoland Stigge module_init(lpc32xx_hsuart_init);
736596f93f5SRoland Stigge module_exit(lpc32xx_hsuart_exit);
737596f93f5SRoland Stigge
738596f93f5SRoland Stigge MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
739596f93f5SRoland Stigge MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
740596f93f5SRoland Stigge MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
741596f93f5SRoland Stigge MODULE_LICENSE("GPL");
742