1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 4 * 5 * Copyright (C) 2004 Infineon IFAP DC COM CPE 6 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 7 * Copyright (C) 2007 John Crispin <john@phrozen.org> 8 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/device.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/lantiq.h> 19 #include <linux/module.h> 20 #include <linux/of_platform.h> 21 #include <linux/serial.h> 22 #include <linux/serial_core.h> 23 #include <linux/slab.h> 24 #include <linux/sysrq.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 28 #define PORT_LTQ_ASC 111 29 #define MAXPORTS 2 30 #define UART_DUMMY_UER_RX 1 31 #define DRVNAME "lantiq,asc" 32 #ifdef __BIG_ENDIAN 33 #define LTQ_ASC_TBUF (0x0020 + 3) 34 #define LTQ_ASC_RBUF (0x0024 + 3) 35 #else 36 #define LTQ_ASC_TBUF 0x0020 37 #define LTQ_ASC_RBUF 0x0024 38 #endif 39 #define LTQ_ASC_FSTAT 0x0048 40 #define LTQ_ASC_WHBSTATE 0x0018 41 #define LTQ_ASC_STATE 0x0014 42 #define LTQ_ASC_IRNCR 0x00F8 43 #define LTQ_ASC_CLC 0x0000 44 #define LTQ_ASC_ID 0x0008 45 #define LTQ_ASC_PISEL 0x0004 46 #define LTQ_ASC_TXFCON 0x0044 47 #define LTQ_ASC_RXFCON 0x0040 48 #define LTQ_ASC_CON 0x0010 49 #define LTQ_ASC_BG 0x0050 50 #define LTQ_ASC_IRNREN 0x00F4 51 52 #define ASC_IRNREN_TX 0x1 53 #define ASC_IRNREN_RX 0x2 54 #define ASC_IRNREN_ERR 0x4 55 #define ASC_IRNREN_TX_BUF 0x8 56 #define ASC_IRNCR_TIR 0x1 57 #define ASC_IRNCR_RIR 0x2 58 #define ASC_IRNCR_EIR 0x4 59 #define ASC_IRNCR_MASK GENMASK(2, 0) 60 61 #define ASCOPT_CSIZE 0x3 62 #define TXFIFO_FL 1 63 #define RXFIFO_FL 1 64 #define ASCCLC_DISS 0x2 65 #define ASCCLC_RMCMASK 0x0000FF00 66 #define ASCCLC_RMCOFFSET 8 67 #define ASCCON_M_8ASYNC 0x0 68 #define ASCCON_M_7ASYNC 0x2 69 #define ASCCON_ODD 0x00000020 70 #define ASCCON_STP 0x00000080 71 #define ASCCON_BRS 0x00000100 72 #define ASCCON_FDE 0x00000200 73 #define ASCCON_R 0x00008000 74 #define ASCCON_FEN 0x00020000 75 #define ASCCON_ROEN 0x00080000 76 #define ASCCON_TOEN 0x00100000 77 #define ASCSTATE_PE 0x00010000 78 #define ASCSTATE_FE 0x00020000 79 #define ASCSTATE_ROE 0x00080000 80 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) 81 #define ASCWHBSTATE_CLRREN 0x00000001 82 #define ASCWHBSTATE_SETREN 0x00000002 83 #define ASCWHBSTATE_CLRPE 0x00000004 84 #define ASCWHBSTATE_CLRFE 0x00000008 85 #define ASCWHBSTATE_CLRROE 0x00000020 86 #define ASCTXFCON_TXFEN 0x0001 87 #define ASCTXFCON_TXFFLU 0x0002 88 #define ASCTXFCON_TXFITLMASK 0x3F00 89 #define ASCTXFCON_TXFITLOFF 8 90 #define ASCRXFCON_RXFEN 0x0001 91 #define ASCRXFCON_RXFFLU 0x0002 92 #define ASCRXFCON_RXFITLMASK 0x3F00 93 #define ASCRXFCON_RXFITLOFF 8 94 #define ASCFSTAT_RXFFLMASK 0x003F 95 #define ASCFSTAT_TXFFLMASK 0x3F00 96 #define ASCFSTAT_TXFREEMASK 0x3F000000 97 98 static struct ltq_uart_port *lqasc_port[MAXPORTS]; 99 static struct uart_driver lqasc_reg; 100 101 struct ltq_soc_data { 102 int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port); 103 int (*request_irq)(struct uart_port *port); 104 void (*free_irq)(struct uart_port *port); 105 }; 106 107 struct ltq_uart_port { 108 struct uart_port port; 109 /* clock used to derive divider */ 110 struct clk *freqclk; 111 /* clock gating of the ASC core */ 112 struct clk *clk; 113 unsigned int tx_irq; 114 unsigned int rx_irq; 115 unsigned int err_irq; 116 unsigned int common_irq; 117 spinlock_t lock; /* exclusive access for multi core */ 118 119 const struct ltq_soc_data *soc; 120 }; 121 122 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) 123 { 124 u32 tmp = __raw_readl(reg); 125 126 __raw_writel((tmp & ~clear) | set, reg); 127 } 128 129 static inline struct 130 ltq_uart_port *to_ltq_uart_port(struct uart_port *port) 131 { 132 return container_of(port, struct ltq_uart_port, port); 133 } 134 135 static void 136 lqasc_stop_tx(struct uart_port *port) 137 { 138 return; 139 } 140 141 static bool lqasc_tx_ready(struct uart_port *port) 142 { 143 u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT); 144 145 return FIELD_GET(ASCFSTAT_TXFREEMASK, fstat); 146 } 147 148 static void 149 lqasc_start_tx(struct uart_port *port) 150 { 151 unsigned long flags; 152 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 153 u8 ch; 154 155 spin_lock_irqsave(<q_port->lock, flags); 156 uart_port_tx(port, ch, 157 lqasc_tx_ready(port), 158 writeb(ch, port->membase + LTQ_ASC_TBUF)); 159 spin_unlock_irqrestore(<q_port->lock, flags); 160 return; 161 } 162 163 static void 164 lqasc_stop_rx(struct uart_port *port) 165 { 166 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 167 } 168 169 static int 170 lqasc_rx_chars(struct uart_port *port) 171 { 172 struct tty_port *tport = &port->state->port; 173 unsigned int ch = 0, rsr = 0, fifocnt; 174 175 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 176 ASCFSTAT_RXFFLMASK; 177 while (fifocnt--) { 178 u8 flag = TTY_NORMAL; 179 ch = readb(port->membase + LTQ_ASC_RBUF); 180 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) 181 & ASCSTATE_ANY) | UART_DUMMY_UER_RX; 182 tty_flip_buffer_push(tport); 183 port->icount.rx++; 184 185 /* 186 * Note that the error handling code is 187 * out of the main execution path 188 */ 189 if (rsr & ASCSTATE_ANY) { 190 if (rsr & ASCSTATE_PE) { 191 port->icount.parity++; 192 asc_update_bits(0, ASCWHBSTATE_CLRPE, 193 port->membase + LTQ_ASC_WHBSTATE); 194 } else if (rsr & ASCSTATE_FE) { 195 port->icount.frame++; 196 asc_update_bits(0, ASCWHBSTATE_CLRFE, 197 port->membase + LTQ_ASC_WHBSTATE); 198 } 199 if (rsr & ASCSTATE_ROE) { 200 port->icount.overrun++; 201 asc_update_bits(0, ASCWHBSTATE_CLRROE, 202 port->membase + LTQ_ASC_WHBSTATE); 203 } 204 205 rsr &= port->read_status_mask; 206 207 if (rsr & ASCSTATE_PE) 208 flag = TTY_PARITY; 209 else if (rsr & ASCSTATE_FE) 210 flag = TTY_FRAME; 211 } 212 213 if ((rsr & port->ignore_status_mask) == 0) 214 tty_insert_flip_char(tport, ch, flag); 215 216 if (rsr & ASCSTATE_ROE) 217 /* 218 * Overrun is special, since it's reported 219 * immediately, and doesn't affect the current 220 * character 221 */ 222 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 223 } 224 225 if (ch != 0) 226 tty_flip_buffer_push(tport); 227 228 return 0; 229 } 230 231 static irqreturn_t 232 lqasc_tx_int(int irq, void *_port) 233 { 234 unsigned long flags; 235 struct uart_port *port = (struct uart_port *)_port; 236 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 237 238 spin_lock_irqsave(<q_port->lock, flags); 239 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); 240 spin_unlock_irqrestore(<q_port->lock, flags); 241 lqasc_start_tx(port); 242 return IRQ_HANDLED; 243 } 244 245 static irqreturn_t 246 lqasc_err_int(int irq, void *_port) 247 { 248 unsigned long flags; 249 struct uart_port *port = (struct uart_port *)_port; 250 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 251 252 spin_lock_irqsave(<q_port->lock, flags); 253 __raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR); 254 /* clear any pending interrupts */ 255 asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | 256 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); 257 spin_unlock_irqrestore(<q_port->lock, flags); 258 return IRQ_HANDLED; 259 } 260 261 static irqreturn_t 262 lqasc_rx_int(int irq, void *_port) 263 { 264 unsigned long flags; 265 struct uart_port *port = (struct uart_port *)_port; 266 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 267 268 spin_lock_irqsave(<q_port->lock, flags); 269 __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); 270 lqasc_rx_chars(port); 271 spin_unlock_irqrestore(<q_port->lock, flags); 272 return IRQ_HANDLED; 273 } 274 275 static irqreturn_t lqasc_irq(int irq, void *p) 276 { 277 unsigned long flags; 278 u32 stat; 279 struct uart_port *port = p; 280 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 281 282 spin_lock_irqsave(<q_port->lock, flags); 283 stat = readl(port->membase + LTQ_ASC_IRNCR); 284 spin_unlock_irqrestore(<q_port->lock, flags); 285 if (!(stat & ASC_IRNCR_MASK)) 286 return IRQ_NONE; 287 288 if (stat & ASC_IRNCR_TIR) 289 lqasc_tx_int(irq, p); 290 291 if (stat & ASC_IRNCR_RIR) 292 lqasc_rx_int(irq, p); 293 294 if (stat & ASC_IRNCR_EIR) 295 lqasc_err_int(irq, p); 296 297 return IRQ_HANDLED; 298 } 299 300 static unsigned int 301 lqasc_tx_empty(struct uart_port *port) 302 { 303 int status; 304 status = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 305 ASCFSTAT_TXFFLMASK; 306 return status ? 0 : TIOCSER_TEMT; 307 } 308 309 static unsigned int 310 lqasc_get_mctrl(struct uart_port *port) 311 { 312 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; 313 } 314 315 static void 316 lqasc_set_mctrl(struct uart_port *port, u_int mctrl) 317 { 318 } 319 320 static void 321 lqasc_break_ctl(struct uart_port *port, int break_state) 322 { 323 } 324 325 static int 326 lqasc_startup(struct uart_port *port) 327 { 328 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 329 int retval; 330 unsigned long flags; 331 332 if (!IS_ERR(ltq_port->clk)) 333 clk_prepare_enable(ltq_port->clk); 334 port->uartclk = clk_get_rate(ltq_port->freqclk); 335 336 spin_lock_irqsave(<q_port->lock, flags); 337 asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), 338 port->membase + LTQ_ASC_CLC); 339 340 __raw_writel(0, port->membase + LTQ_ASC_PISEL); 341 __raw_writel( 342 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | 343 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, 344 port->membase + LTQ_ASC_TXFCON); 345 __raw_writel( 346 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) 347 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, 348 port->membase + LTQ_ASC_RXFCON); 349 /* make sure other settings are written to hardware before 350 * setting enable bits 351 */ 352 wmb(); 353 asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | 354 ASCCON_ROEN, port->membase + LTQ_ASC_CON); 355 356 spin_unlock_irqrestore(<q_port->lock, flags); 357 358 retval = ltq_port->soc->request_irq(port); 359 if (retval) 360 return retval; 361 362 __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, 363 port->membase + LTQ_ASC_IRNREN); 364 return retval; 365 } 366 367 static void 368 lqasc_shutdown(struct uart_port *port) 369 { 370 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 371 unsigned long flags; 372 373 ltq_port->soc->free_irq(port); 374 375 spin_lock_irqsave(<q_port->lock, flags); 376 __raw_writel(0, port->membase + LTQ_ASC_CON); 377 asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, 378 port->membase + LTQ_ASC_RXFCON); 379 asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, 380 port->membase + LTQ_ASC_TXFCON); 381 spin_unlock_irqrestore(<q_port->lock, flags); 382 if (!IS_ERR(ltq_port->clk)) 383 clk_disable_unprepare(ltq_port->clk); 384 } 385 386 static void 387 lqasc_set_termios(struct uart_port *port, struct ktermios *new, 388 const struct ktermios *old) 389 { 390 unsigned int cflag; 391 unsigned int iflag; 392 unsigned int divisor; 393 unsigned int baud; 394 unsigned int con = 0; 395 unsigned long flags; 396 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 397 398 cflag = new->c_cflag; 399 iflag = new->c_iflag; 400 401 switch (cflag & CSIZE) { 402 case CS7: 403 con = ASCCON_M_7ASYNC; 404 break; 405 406 case CS5: 407 case CS6: 408 default: 409 new->c_cflag &= ~ CSIZE; 410 new->c_cflag |= CS8; 411 con = ASCCON_M_8ASYNC; 412 break; 413 } 414 415 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 416 417 if (cflag & CSTOPB) 418 con |= ASCCON_STP; 419 420 if (cflag & PARENB) { 421 if (!(cflag & PARODD)) 422 con &= ~ASCCON_ODD; 423 else 424 con |= ASCCON_ODD; 425 } 426 427 port->read_status_mask = ASCSTATE_ROE; 428 if (iflag & INPCK) 429 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 430 431 port->ignore_status_mask = 0; 432 if (iflag & IGNPAR) 433 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 434 435 if (iflag & IGNBRK) { 436 /* 437 * If we're ignoring parity and break indicators, 438 * ignore overruns too (for real raw support). 439 */ 440 if (iflag & IGNPAR) 441 port->ignore_status_mask |= ASCSTATE_ROE; 442 } 443 444 if ((cflag & CREAD) == 0) 445 port->ignore_status_mask |= UART_DUMMY_UER_RX; 446 447 /* set error signals - framing, parity and overrun, enable receiver */ 448 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; 449 450 spin_lock_irqsave(<q_port->lock, flags); 451 452 /* set up CON */ 453 asc_update_bits(0, con, port->membase + LTQ_ASC_CON); 454 455 /* Set baud rate - take a divider of 2 into account */ 456 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 457 divisor = uart_get_divisor(port, baud); 458 divisor = divisor / 2 - 1; 459 460 /* disable the baudrate generator */ 461 asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON); 462 463 /* make sure the fractional divider is off */ 464 asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); 465 466 /* set up to use divisor of 2 */ 467 asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); 468 469 /* now we can write the new baudrate into the register */ 470 __raw_writel(divisor, port->membase + LTQ_ASC_BG); 471 472 /* turn the baudrate generator back on */ 473 asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); 474 475 /* enable rx */ 476 __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); 477 478 spin_unlock_irqrestore(<q_port->lock, flags); 479 480 /* Don't rewrite B0 */ 481 if (tty_termios_baud_rate(new)) 482 tty_termios_encode_baud_rate(new, baud, baud); 483 484 uart_update_timeout(port, cflag, baud); 485 } 486 487 static const char* 488 lqasc_type(struct uart_port *port) 489 { 490 if (port->type == PORT_LTQ_ASC) 491 return DRVNAME; 492 else 493 return NULL; 494 } 495 496 static void 497 lqasc_release_port(struct uart_port *port) 498 { 499 struct platform_device *pdev = to_platform_device(port->dev); 500 501 if (port->flags & UPF_IOREMAP) { 502 devm_iounmap(&pdev->dev, port->membase); 503 port->membase = NULL; 504 } 505 } 506 507 static int 508 lqasc_request_port(struct uart_port *port) 509 { 510 struct platform_device *pdev = to_platform_device(port->dev); 511 struct resource *res; 512 int size; 513 514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 515 if (!res) { 516 dev_err(&pdev->dev, "cannot obtain I/O memory region"); 517 return -ENODEV; 518 } 519 size = resource_size(res); 520 521 res = devm_request_mem_region(&pdev->dev, res->start, 522 size, dev_name(&pdev->dev)); 523 if (!res) { 524 dev_err(&pdev->dev, "cannot request I/O memory region"); 525 return -EBUSY; 526 } 527 528 if (port->flags & UPF_IOREMAP) { 529 port->membase = devm_ioremap(&pdev->dev, 530 port->mapbase, size); 531 if (port->membase == NULL) 532 return -ENOMEM; 533 } 534 return 0; 535 } 536 537 static void 538 lqasc_config_port(struct uart_port *port, int flags) 539 { 540 if (flags & UART_CONFIG_TYPE) { 541 port->type = PORT_LTQ_ASC; 542 lqasc_request_port(port); 543 } 544 } 545 546 static int 547 lqasc_verify_port(struct uart_port *port, 548 struct serial_struct *ser) 549 { 550 int ret = 0; 551 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) 552 ret = -EINVAL; 553 if (ser->irq < 0 || ser->irq >= NR_IRQS) 554 ret = -EINVAL; 555 if (ser->baud_base < 9600) 556 ret = -EINVAL; 557 return ret; 558 } 559 560 static const struct uart_ops lqasc_pops = { 561 .tx_empty = lqasc_tx_empty, 562 .set_mctrl = lqasc_set_mctrl, 563 .get_mctrl = lqasc_get_mctrl, 564 .stop_tx = lqasc_stop_tx, 565 .start_tx = lqasc_start_tx, 566 .stop_rx = lqasc_stop_rx, 567 .break_ctl = lqasc_break_ctl, 568 .startup = lqasc_startup, 569 .shutdown = lqasc_shutdown, 570 .set_termios = lqasc_set_termios, 571 .type = lqasc_type, 572 .release_port = lqasc_release_port, 573 .request_port = lqasc_request_port, 574 .config_port = lqasc_config_port, 575 .verify_port = lqasc_verify_port, 576 }; 577 578 #ifdef CONFIG_SERIAL_LANTIQ_CONSOLE 579 static void 580 lqasc_console_putchar(struct uart_port *port, unsigned char ch) 581 { 582 if (!port->membase) 583 return; 584 585 while (!lqasc_tx_ready(port)) 586 ; 587 588 writeb(ch, port->membase + LTQ_ASC_TBUF); 589 } 590 591 static void lqasc_serial_port_write(struct uart_port *port, const char *s, 592 u_int count) 593 { 594 uart_console_write(port, s, count, lqasc_console_putchar); 595 } 596 597 static void 598 lqasc_console_write(struct console *co, const char *s, u_int count) 599 { 600 struct ltq_uart_port *ltq_port; 601 unsigned long flags; 602 603 if (co->index >= MAXPORTS) 604 return; 605 606 ltq_port = lqasc_port[co->index]; 607 if (!ltq_port) 608 return; 609 610 spin_lock_irqsave(<q_port->lock, flags); 611 lqasc_serial_port_write(<q_port->port, s, count); 612 spin_unlock_irqrestore(<q_port->lock, flags); 613 } 614 615 static int __init 616 lqasc_console_setup(struct console *co, char *options) 617 { 618 struct ltq_uart_port *ltq_port; 619 struct uart_port *port; 620 int baud = 115200; 621 int bits = 8; 622 int parity = 'n'; 623 int flow = 'n'; 624 625 if (co->index >= MAXPORTS) 626 return -ENODEV; 627 628 ltq_port = lqasc_port[co->index]; 629 if (!ltq_port) 630 return -ENODEV; 631 632 port = <q_port->port; 633 634 if (!IS_ERR(ltq_port->clk)) 635 clk_prepare_enable(ltq_port->clk); 636 637 port->uartclk = clk_get_rate(ltq_port->freqclk); 638 639 if (options) 640 uart_parse_options(options, &baud, &parity, &bits, &flow); 641 return uart_set_options(port, co, baud, parity, bits, flow); 642 } 643 644 static struct console lqasc_console = { 645 .name = "ttyLTQ", 646 .write = lqasc_console_write, 647 .device = uart_console_device, 648 .setup = lqasc_console_setup, 649 .flags = CON_PRINTBUFFER, 650 .index = -1, 651 .data = &lqasc_reg, 652 }; 653 654 static int __init 655 lqasc_console_init(void) 656 { 657 register_console(&lqasc_console); 658 return 0; 659 } 660 console_initcall(lqasc_console_init); 661 662 static void lqasc_serial_early_console_write(struct console *co, 663 const char *s, 664 u_int count) 665 { 666 struct earlycon_device *dev = co->data; 667 668 lqasc_serial_port_write(&dev->port, s, count); 669 } 670 671 static int __init 672 lqasc_serial_early_console_setup(struct earlycon_device *device, 673 const char *opt) 674 { 675 if (!device->port.membase) 676 return -ENODEV; 677 678 device->con->write = lqasc_serial_early_console_write; 679 return 0; 680 } 681 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup); 682 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup); 683 684 #define LANTIQ_SERIAL_CONSOLE (&lqasc_console) 685 686 #else 687 688 #define LANTIQ_SERIAL_CONSOLE NULL 689 690 #endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */ 691 692 static struct uart_driver lqasc_reg = { 693 .owner = THIS_MODULE, 694 .driver_name = DRVNAME, 695 .dev_name = "ttyLTQ", 696 .major = 0, 697 .minor = 0, 698 .nr = MAXPORTS, 699 .cons = LANTIQ_SERIAL_CONSOLE, 700 }; 701 702 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port) 703 { 704 struct uart_port *port = <q_port->port; 705 struct platform_device *pdev = to_platform_device(dev); 706 int irq; 707 708 irq = platform_get_irq(pdev, 0); 709 if (irq < 0) 710 return irq; 711 ltq_port->tx_irq = irq; 712 irq = platform_get_irq(pdev, 1); 713 if (irq < 0) 714 return irq; 715 ltq_port->rx_irq = irq; 716 irq = platform_get_irq(pdev, 2); 717 if (irq < 0) 718 return irq; 719 ltq_port->err_irq = irq; 720 721 port->irq = ltq_port->tx_irq; 722 723 return 0; 724 } 725 726 static int request_irq_lantiq(struct uart_port *port) 727 { 728 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 729 int retval; 730 731 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, 732 0, "asc_tx", port); 733 if (retval) { 734 dev_err(port->dev, "failed to request asc_tx\n"); 735 return retval; 736 } 737 738 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, 739 0, "asc_rx", port); 740 if (retval) { 741 dev_err(port->dev, "failed to request asc_rx\n"); 742 goto err1; 743 } 744 745 retval = request_irq(ltq_port->err_irq, lqasc_err_int, 746 0, "asc_err", port); 747 if (retval) { 748 dev_err(port->dev, "failed to request asc_err\n"); 749 goto err2; 750 } 751 return 0; 752 753 err2: 754 free_irq(ltq_port->rx_irq, port); 755 err1: 756 free_irq(ltq_port->tx_irq, port); 757 return retval; 758 } 759 760 static void free_irq_lantiq(struct uart_port *port) 761 { 762 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 763 764 free_irq(ltq_port->tx_irq, port); 765 free_irq(ltq_port->rx_irq, port); 766 free_irq(ltq_port->err_irq, port); 767 } 768 769 static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port) 770 { 771 struct uart_port *port = <q_port->port; 772 int ret; 773 774 ret = platform_get_irq(to_platform_device(dev), 0); 775 if (ret < 0) { 776 dev_err(dev, "failed to fetch IRQ for serial port\n"); 777 return ret; 778 } 779 ltq_port->common_irq = ret; 780 port->irq = ret; 781 782 return 0; 783 } 784 785 static int request_irq_intel(struct uart_port *port) 786 { 787 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 788 int retval; 789 790 retval = request_irq(ltq_port->common_irq, lqasc_irq, 0, 791 "asc_irq", port); 792 if (retval) 793 dev_err(port->dev, "failed to request asc_irq\n"); 794 795 return retval; 796 } 797 798 static void free_irq_intel(struct uart_port *port) 799 { 800 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 801 802 free_irq(ltq_port->common_irq, port); 803 } 804 805 static int lqasc_probe(struct platform_device *pdev) 806 { 807 struct device_node *node = pdev->dev.of_node; 808 struct ltq_uart_port *ltq_port; 809 struct uart_port *port; 810 struct resource *mmres; 811 int line; 812 int ret; 813 814 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 815 if (!mmres) { 816 dev_err(&pdev->dev, 817 "failed to get memory for serial port\n"); 818 return -ENODEV; 819 } 820 821 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port), 822 GFP_KERNEL); 823 if (!ltq_port) 824 return -ENOMEM; 825 826 port = <q_port->port; 827 828 ltq_port->soc = of_device_get_match_data(&pdev->dev); 829 ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port); 830 if (ret) 831 return ret; 832 833 /* get serial id */ 834 line = of_alias_get_id(node, "serial"); 835 if (line < 0) { 836 if (IS_ENABLED(CONFIG_LANTIQ)) { 837 if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC)) 838 line = 0; 839 else 840 line = 1; 841 } else { 842 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 843 line); 844 return line; 845 } 846 } 847 848 if (lqasc_port[line]) { 849 dev_err(&pdev->dev, "port %d already allocated\n", line); 850 return -EBUSY; 851 } 852 853 port->iotype = SERIAL_IO_MEM; 854 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 855 port->ops = &lqasc_pops; 856 port->fifosize = 16; 857 port->type = PORT_LTQ_ASC; 858 port->line = line; 859 port->dev = &pdev->dev; 860 /* unused, just to be backward-compatible */ 861 port->mapbase = mmres->start; 862 863 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 864 ltq_port->freqclk = clk_get_fpi(); 865 else 866 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq"); 867 868 869 if (IS_ERR(ltq_port->freqclk)) { 870 pr_err("failed to get fpi clk\n"); 871 return -ENOENT; 872 } 873 874 /* not all asc ports have clock gates, lets ignore the return code */ 875 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 876 ltq_port->clk = clk_get(&pdev->dev, NULL); 877 else 878 ltq_port->clk = devm_clk_get(&pdev->dev, "asc"); 879 880 spin_lock_init(<q_port->lock); 881 lqasc_port[line] = ltq_port; 882 platform_set_drvdata(pdev, ltq_port); 883 884 ret = uart_add_one_port(&lqasc_reg, port); 885 886 return ret; 887 } 888 889 static int lqasc_remove(struct platform_device *pdev) 890 { 891 struct uart_port *port = platform_get_drvdata(pdev); 892 893 return uart_remove_one_port(&lqasc_reg, port); 894 } 895 896 static const struct ltq_soc_data soc_data_lantiq = { 897 .fetch_irq = fetch_irq_lantiq, 898 .request_irq = request_irq_lantiq, 899 .free_irq = free_irq_lantiq, 900 }; 901 902 static const struct ltq_soc_data soc_data_intel = { 903 .fetch_irq = fetch_irq_intel, 904 .request_irq = request_irq_intel, 905 .free_irq = free_irq_intel, 906 }; 907 908 static const struct of_device_id ltq_asc_match[] = { 909 { .compatible = "lantiq,asc", .data = &soc_data_lantiq }, 910 { .compatible = "intel,lgm-asc", .data = &soc_data_intel }, 911 {}, 912 }; 913 MODULE_DEVICE_TABLE(of, ltq_asc_match); 914 915 static struct platform_driver lqasc_driver = { 916 .probe = lqasc_probe, 917 .remove = lqasc_remove, 918 .driver = { 919 .name = DRVNAME, 920 .of_match_table = ltq_asc_match, 921 }, 922 }; 923 924 static int __init 925 init_lqasc(void) 926 { 927 int ret; 928 929 ret = uart_register_driver(&lqasc_reg); 930 if (ret != 0) 931 return ret; 932 933 ret = platform_driver_register(&lqasc_driver); 934 if (ret != 0) 935 uart_unregister_driver(&lqasc_reg); 936 937 return ret; 938 } 939 940 static void __exit exit_lqasc(void) 941 { 942 platform_driver_unregister(&lqasc_driver); 943 uart_unregister_driver(&lqasc_reg); 944 } 945 946 module_init(init_lqasc); 947 module_exit(exit_lqasc); 948 949 MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs"); 950 MODULE_LICENSE("GPL v2"); 951