1 /* 2 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 * 17 * Copyright (C) 2004 Infineon IFAP DC COM CPE 18 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 19 * Copyright (C) 2007 John Crispin <blogic@openwrt.org> 20 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com> 21 */ 22 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/ioport.h> 26 #include <linux/init.h> 27 #include <linux/console.h> 28 #include <linux/sysrq.h> 29 #include <linux/device.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial_core.h> 33 #include <linux/serial.h> 34 #include <linux/of_platform.h> 35 #include <linux/of_address.h> 36 #include <linux/of_irq.h> 37 #include <linux/io.h> 38 #include <linux/clk.h> 39 #include <linux/gpio.h> 40 41 #include <lantiq_soc.h> 42 43 #define PORT_LTQ_ASC 111 44 #define MAXPORTS 2 45 #define UART_DUMMY_UER_RX 1 46 #define DRVNAME "lantiq,asc" 47 #ifdef __BIG_ENDIAN 48 #define LTQ_ASC_TBUF (0x0020 + 3) 49 #define LTQ_ASC_RBUF (0x0024 + 3) 50 #else 51 #define LTQ_ASC_TBUF 0x0020 52 #define LTQ_ASC_RBUF 0x0024 53 #endif 54 #define LTQ_ASC_FSTAT 0x0048 55 #define LTQ_ASC_WHBSTATE 0x0018 56 #define LTQ_ASC_STATE 0x0014 57 #define LTQ_ASC_IRNCR 0x00F8 58 #define LTQ_ASC_CLC 0x0000 59 #define LTQ_ASC_ID 0x0008 60 #define LTQ_ASC_PISEL 0x0004 61 #define LTQ_ASC_TXFCON 0x0044 62 #define LTQ_ASC_RXFCON 0x0040 63 #define LTQ_ASC_CON 0x0010 64 #define LTQ_ASC_BG 0x0050 65 #define LTQ_ASC_IRNREN 0x00F4 66 67 #define ASC_IRNREN_TX 0x1 68 #define ASC_IRNREN_RX 0x2 69 #define ASC_IRNREN_ERR 0x4 70 #define ASC_IRNREN_TX_BUF 0x8 71 #define ASC_IRNCR_TIR 0x1 72 #define ASC_IRNCR_RIR 0x2 73 #define ASC_IRNCR_EIR 0x4 74 75 #define ASCOPT_CSIZE 0x3 76 #define TXFIFO_FL 1 77 #define RXFIFO_FL 1 78 #define ASCCLC_DISS 0x2 79 #define ASCCLC_RMCMASK 0x0000FF00 80 #define ASCCLC_RMCOFFSET 8 81 #define ASCCON_M_8ASYNC 0x0 82 #define ASCCON_M_7ASYNC 0x2 83 #define ASCCON_ODD 0x00000020 84 #define ASCCON_STP 0x00000080 85 #define ASCCON_BRS 0x00000100 86 #define ASCCON_FDE 0x00000200 87 #define ASCCON_R 0x00008000 88 #define ASCCON_FEN 0x00020000 89 #define ASCCON_ROEN 0x00080000 90 #define ASCCON_TOEN 0x00100000 91 #define ASCSTATE_PE 0x00010000 92 #define ASCSTATE_FE 0x00020000 93 #define ASCSTATE_ROE 0x00080000 94 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) 95 #define ASCWHBSTATE_CLRREN 0x00000001 96 #define ASCWHBSTATE_SETREN 0x00000002 97 #define ASCWHBSTATE_CLRPE 0x00000004 98 #define ASCWHBSTATE_CLRFE 0x00000008 99 #define ASCWHBSTATE_CLRROE 0x00000020 100 #define ASCTXFCON_TXFEN 0x0001 101 #define ASCTXFCON_TXFFLU 0x0002 102 #define ASCTXFCON_TXFITLMASK 0x3F00 103 #define ASCTXFCON_TXFITLOFF 8 104 #define ASCRXFCON_RXFEN 0x0001 105 #define ASCRXFCON_RXFFLU 0x0002 106 #define ASCRXFCON_RXFITLMASK 0x3F00 107 #define ASCRXFCON_RXFITLOFF 8 108 #define ASCFSTAT_RXFFLMASK 0x003F 109 #define ASCFSTAT_TXFFLMASK 0x3F00 110 #define ASCFSTAT_TXFREEMASK 0x3F000000 111 #define ASCFSTAT_TXFREEOFF 24 112 113 static void lqasc_tx_chars(struct uart_port *port); 114 static struct ltq_uart_port *lqasc_port[MAXPORTS]; 115 static struct uart_driver lqasc_reg; 116 static DEFINE_SPINLOCK(ltq_asc_lock); 117 118 struct ltq_uart_port { 119 struct uart_port port; 120 /* clock used to derive divider */ 121 struct clk *fpiclk; 122 /* clock gating of the ASC core */ 123 struct clk *clk; 124 unsigned int tx_irq; 125 unsigned int rx_irq; 126 unsigned int err_irq; 127 }; 128 129 static inline struct 130 ltq_uart_port *to_ltq_uart_port(struct uart_port *port) 131 { 132 return container_of(port, struct ltq_uart_port, port); 133 } 134 135 static void 136 lqasc_stop_tx(struct uart_port *port) 137 { 138 return; 139 } 140 141 static void 142 lqasc_start_tx(struct uart_port *port) 143 { 144 unsigned long flags; 145 spin_lock_irqsave(<q_asc_lock, flags); 146 lqasc_tx_chars(port); 147 spin_unlock_irqrestore(<q_asc_lock, flags); 148 return; 149 } 150 151 static void 152 lqasc_stop_rx(struct uart_port *port) 153 { 154 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 155 } 156 157 static void 158 lqasc_enable_ms(struct uart_port *port) 159 { 160 } 161 162 static int 163 lqasc_rx_chars(struct uart_port *port) 164 { 165 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 166 unsigned int ch = 0, rsr = 0, fifocnt; 167 168 if (!tty) { 169 dev_dbg(port->dev, "%s:tty is busy now", __func__); 170 return -EBUSY; 171 } 172 fifocnt = 173 ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; 174 while (fifocnt--) { 175 u8 flag = TTY_NORMAL; 176 ch = ltq_r8(port->membase + LTQ_ASC_RBUF); 177 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) 178 & ASCSTATE_ANY) | UART_DUMMY_UER_RX; 179 tty_flip_buffer_push(tty); 180 port->icount.rx++; 181 182 /* 183 * Note that the error handling code is 184 * out of the main execution path 185 */ 186 if (rsr & ASCSTATE_ANY) { 187 if (rsr & ASCSTATE_PE) { 188 port->icount.parity++; 189 ltq_w32_mask(0, ASCWHBSTATE_CLRPE, 190 port->membase + LTQ_ASC_WHBSTATE); 191 } else if (rsr & ASCSTATE_FE) { 192 port->icount.frame++; 193 ltq_w32_mask(0, ASCWHBSTATE_CLRFE, 194 port->membase + LTQ_ASC_WHBSTATE); 195 } 196 if (rsr & ASCSTATE_ROE) { 197 port->icount.overrun++; 198 ltq_w32_mask(0, ASCWHBSTATE_CLRROE, 199 port->membase + LTQ_ASC_WHBSTATE); 200 } 201 202 rsr &= port->read_status_mask; 203 204 if (rsr & ASCSTATE_PE) 205 flag = TTY_PARITY; 206 else if (rsr & ASCSTATE_FE) 207 flag = TTY_FRAME; 208 } 209 210 if ((rsr & port->ignore_status_mask) == 0) 211 tty_insert_flip_char(tty, ch, flag); 212 213 if (rsr & ASCSTATE_ROE) 214 /* 215 * Overrun is special, since it's reported 216 * immediately, and doesn't affect the current 217 * character 218 */ 219 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 220 } 221 if (ch != 0) 222 tty_flip_buffer_push(tty); 223 tty_kref_put(tty); 224 return 0; 225 } 226 227 static void 228 lqasc_tx_chars(struct uart_port *port) 229 { 230 struct circ_buf *xmit = &port->state->xmit; 231 if (uart_tx_stopped(port)) { 232 lqasc_stop_tx(port); 233 return; 234 } 235 236 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & 237 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { 238 if (port->x_char) { 239 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); 240 port->icount.tx++; 241 port->x_char = 0; 242 continue; 243 } 244 245 if (uart_circ_empty(xmit)) 246 break; 247 248 ltq_w8(port->state->xmit.buf[port->state->xmit.tail], 249 port->membase + LTQ_ASC_TBUF); 250 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 251 port->icount.tx++; 252 } 253 254 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 255 uart_write_wakeup(port); 256 } 257 258 static irqreturn_t 259 lqasc_tx_int(int irq, void *_port) 260 { 261 unsigned long flags; 262 struct uart_port *port = (struct uart_port *)_port; 263 spin_lock_irqsave(<q_asc_lock, flags); 264 ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); 265 spin_unlock_irqrestore(<q_asc_lock, flags); 266 lqasc_start_tx(port); 267 return IRQ_HANDLED; 268 } 269 270 static irqreturn_t 271 lqasc_err_int(int irq, void *_port) 272 { 273 unsigned long flags; 274 struct uart_port *port = (struct uart_port *)_port; 275 spin_lock_irqsave(<q_asc_lock, flags); 276 /* clear any pending interrupts */ 277 ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | 278 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); 279 spin_unlock_irqrestore(<q_asc_lock, flags); 280 return IRQ_HANDLED; 281 } 282 283 static irqreturn_t 284 lqasc_rx_int(int irq, void *_port) 285 { 286 unsigned long flags; 287 struct uart_port *port = (struct uart_port *)_port; 288 spin_lock_irqsave(<q_asc_lock, flags); 289 ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); 290 lqasc_rx_chars(port); 291 spin_unlock_irqrestore(<q_asc_lock, flags); 292 return IRQ_HANDLED; 293 } 294 295 static unsigned int 296 lqasc_tx_empty(struct uart_port *port) 297 { 298 int status; 299 status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; 300 return status ? 0 : TIOCSER_TEMT; 301 } 302 303 static unsigned int 304 lqasc_get_mctrl(struct uart_port *port) 305 { 306 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; 307 } 308 309 static void 310 lqasc_set_mctrl(struct uart_port *port, u_int mctrl) 311 { 312 } 313 314 static void 315 lqasc_break_ctl(struct uart_port *port, int break_state) 316 { 317 } 318 319 static int 320 lqasc_startup(struct uart_port *port) 321 { 322 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 323 int retval; 324 325 if (ltq_port->clk) 326 clk_enable(ltq_port->clk); 327 port->uartclk = clk_get_rate(ltq_port->fpiclk); 328 329 ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), 330 port->membase + LTQ_ASC_CLC); 331 332 ltq_w32(0, port->membase + LTQ_ASC_PISEL); 333 ltq_w32( 334 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | 335 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, 336 port->membase + LTQ_ASC_TXFCON); 337 ltq_w32( 338 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) 339 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, 340 port->membase + LTQ_ASC_RXFCON); 341 /* make sure other settings are written to hardware before 342 * setting enable bits 343 */ 344 wmb(); 345 ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | 346 ASCCON_ROEN, port->membase + LTQ_ASC_CON); 347 348 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, 349 0, "asc_tx", port); 350 if (retval) { 351 pr_err("failed to request lqasc_tx_int\n"); 352 return retval; 353 } 354 355 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, 356 0, "asc_rx", port); 357 if (retval) { 358 pr_err("failed to request lqasc_rx_int\n"); 359 goto err1; 360 } 361 362 retval = request_irq(ltq_port->err_irq, lqasc_err_int, 363 0, "asc_err", port); 364 if (retval) { 365 pr_err("failed to request lqasc_err_int\n"); 366 goto err2; 367 } 368 369 ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, 370 port->membase + LTQ_ASC_IRNREN); 371 return 0; 372 373 err2: 374 free_irq(ltq_port->rx_irq, port); 375 err1: 376 free_irq(ltq_port->tx_irq, port); 377 return retval; 378 } 379 380 static void 381 lqasc_shutdown(struct uart_port *port) 382 { 383 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 384 free_irq(ltq_port->tx_irq, port); 385 free_irq(ltq_port->rx_irq, port); 386 free_irq(ltq_port->err_irq, port); 387 388 ltq_w32(0, port->membase + LTQ_ASC_CON); 389 ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, 390 port->membase + LTQ_ASC_RXFCON); 391 ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, 392 port->membase + LTQ_ASC_TXFCON); 393 if (ltq_port->clk) 394 clk_disable(ltq_port->clk); 395 } 396 397 static void 398 lqasc_set_termios(struct uart_port *port, 399 struct ktermios *new, struct ktermios *old) 400 { 401 unsigned int cflag; 402 unsigned int iflag; 403 unsigned int divisor; 404 unsigned int baud; 405 unsigned int con = 0; 406 unsigned long flags; 407 408 cflag = new->c_cflag; 409 iflag = new->c_iflag; 410 411 switch (cflag & CSIZE) { 412 case CS7: 413 con = ASCCON_M_7ASYNC; 414 break; 415 416 case CS5: 417 case CS6: 418 default: 419 new->c_cflag &= ~ CSIZE; 420 new->c_cflag |= CS8; 421 con = ASCCON_M_8ASYNC; 422 break; 423 } 424 425 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 426 427 if (cflag & CSTOPB) 428 con |= ASCCON_STP; 429 430 if (cflag & PARENB) { 431 if (!(cflag & PARODD)) 432 con &= ~ASCCON_ODD; 433 else 434 con |= ASCCON_ODD; 435 } 436 437 port->read_status_mask = ASCSTATE_ROE; 438 if (iflag & INPCK) 439 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 440 441 port->ignore_status_mask = 0; 442 if (iflag & IGNPAR) 443 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 444 445 if (iflag & IGNBRK) { 446 /* 447 * If we're ignoring parity and break indicators, 448 * ignore overruns too (for real raw support). 449 */ 450 if (iflag & IGNPAR) 451 port->ignore_status_mask |= ASCSTATE_ROE; 452 } 453 454 if ((cflag & CREAD) == 0) 455 port->ignore_status_mask |= UART_DUMMY_UER_RX; 456 457 /* set error signals - framing, parity and overrun, enable receiver */ 458 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; 459 460 spin_lock_irqsave(<q_asc_lock, flags); 461 462 /* set up CON */ 463 ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); 464 465 /* Set baud rate - take a divider of 2 into account */ 466 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 467 divisor = uart_get_divisor(port, baud); 468 divisor = divisor / 2 - 1; 469 470 /* disable the baudrate generator */ 471 ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); 472 473 /* make sure the fractional divider is off */ 474 ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); 475 476 /* set up to use divisor of 2 */ 477 ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); 478 479 /* now we can write the new baudrate into the register */ 480 ltq_w32(divisor, port->membase + LTQ_ASC_BG); 481 482 /* turn the baudrate generator back on */ 483 ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); 484 485 /* enable rx */ 486 ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); 487 488 spin_unlock_irqrestore(<q_asc_lock, flags); 489 490 /* Don't rewrite B0 */ 491 if (tty_termios_baud_rate(new)) 492 tty_termios_encode_baud_rate(new, baud, baud); 493 494 uart_update_timeout(port, cflag, baud); 495 } 496 497 static const char* 498 lqasc_type(struct uart_port *port) 499 { 500 if (port->type == PORT_LTQ_ASC) 501 return DRVNAME; 502 else 503 return NULL; 504 } 505 506 static void 507 lqasc_release_port(struct uart_port *port) 508 { 509 if (port->flags & UPF_IOREMAP) { 510 iounmap(port->membase); 511 port->membase = NULL; 512 } 513 } 514 515 static int 516 lqasc_request_port(struct uart_port *port) 517 { 518 struct platform_device *pdev = to_platform_device(port->dev); 519 struct resource *res; 520 int size; 521 522 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 523 if (!res) { 524 dev_err(&pdev->dev, "cannot obtain I/O memory region"); 525 return -ENODEV; 526 } 527 size = resource_size(res); 528 529 res = devm_request_mem_region(&pdev->dev, res->start, 530 size, dev_name(&pdev->dev)); 531 if (!res) { 532 dev_err(&pdev->dev, "cannot request I/O memory region"); 533 return -EBUSY; 534 } 535 536 if (port->flags & UPF_IOREMAP) { 537 port->membase = devm_ioremap_nocache(&pdev->dev, 538 port->mapbase, size); 539 if (port->membase == NULL) 540 return -ENOMEM; 541 } 542 return 0; 543 } 544 545 static void 546 lqasc_config_port(struct uart_port *port, int flags) 547 { 548 if (flags & UART_CONFIG_TYPE) { 549 port->type = PORT_LTQ_ASC; 550 lqasc_request_port(port); 551 } 552 } 553 554 static int 555 lqasc_verify_port(struct uart_port *port, 556 struct serial_struct *ser) 557 { 558 int ret = 0; 559 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) 560 ret = -EINVAL; 561 if (ser->irq < 0 || ser->irq >= NR_IRQS) 562 ret = -EINVAL; 563 if (ser->baud_base < 9600) 564 ret = -EINVAL; 565 return ret; 566 } 567 568 static struct uart_ops lqasc_pops = { 569 .tx_empty = lqasc_tx_empty, 570 .set_mctrl = lqasc_set_mctrl, 571 .get_mctrl = lqasc_get_mctrl, 572 .stop_tx = lqasc_stop_tx, 573 .start_tx = lqasc_start_tx, 574 .stop_rx = lqasc_stop_rx, 575 .enable_ms = lqasc_enable_ms, 576 .break_ctl = lqasc_break_ctl, 577 .startup = lqasc_startup, 578 .shutdown = lqasc_shutdown, 579 .set_termios = lqasc_set_termios, 580 .type = lqasc_type, 581 .release_port = lqasc_release_port, 582 .request_port = lqasc_request_port, 583 .config_port = lqasc_config_port, 584 .verify_port = lqasc_verify_port, 585 }; 586 587 static void 588 lqasc_console_putchar(struct uart_port *port, int ch) 589 { 590 int fifofree; 591 592 if (!port->membase) 593 return; 594 595 do { 596 fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) 597 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; 598 } while (fifofree == 0); 599 ltq_w8(ch, port->membase + LTQ_ASC_TBUF); 600 } 601 602 603 static void 604 lqasc_console_write(struct console *co, const char *s, u_int count) 605 { 606 struct ltq_uart_port *ltq_port; 607 struct uart_port *port; 608 unsigned long flags; 609 610 if (co->index >= MAXPORTS) 611 return; 612 613 ltq_port = lqasc_port[co->index]; 614 if (!ltq_port) 615 return; 616 617 port = <q_port->port; 618 619 spin_lock_irqsave(<q_asc_lock, flags); 620 uart_console_write(port, s, count, lqasc_console_putchar); 621 spin_unlock_irqrestore(<q_asc_lock, flags); 622 } 623 624 static int __init 625 lqasc_console_setup(struct console *co, char *options) 626 { 627 struct ltq_uart_port *ltq_port; 628 struct uart_port *port; 629 int baud = 115200; 630 int bits = 8; 631 int parity = 'n'; 632 int flow = 'n'; 633 634 if (co->index >= MAXPORTS) 635 return -ENODEV; 636 637 ltq_port = lqasc_port[co->index]; 638 if (!ltq_port) 639 return -ENODEV; 640 641 port = <q_port->port; 642 643 port->uartclk = clk_get_rate(ltq_port->fpiclk); 644 645 if (options) 646 uart_parse_options(options, &baud, &parity, &bits, &flow); 647 return uart_set_options(port, co, baud, parity, bits, flow); 648 } 649 650 static struct console lqasc_console = { 651 .name = "ttyLTQ", 652 .write = lqasc_console_write, 653 .device = uart_console_device, 654 .setup = lqasc_console_setup, 655 .flags = CON_PRINTBUFFER, 656 .index = -1, 657 .data = &lqasc_reg, 658 }; 659 660 static int __init 661 lqasc_console_init(void) 662 { 663 register_console(&lqasc_console); 664 return 0; 665 } 666 console_initcall(lqasc_console_init); 667 668 static struct uart_driver lqasc_reg = { 669 .owner = THIS_MODULE, 670 .driver_name = DRVNAME, 671 .dev_name = "ttyLTQ", 672 .major = 0, 673 .minor = 0, 674 .nr = MAXPORTS, 675 .cons = &lqasc_console, 676 }; 677 678 static int __init 679 lqasc_probe(struct platform_device *pdev) 680 { 681 struct device_node *node = pdev->dev.of_node; 682 struct ltq_uart_port *ltq_port; 683 struct uart_port *port; 684 struct resource *mmres, irqres[3]; 685 int line = 0; 686 int ret; 687 688 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 689 ret = of_irq_to_resource_table(node, irqres, 3); 690 if (!mmres || (ret != 3)) { 691 dev_err(&pdev->dev, 692 "failed to get memory/irq for serial port\n"); 693 return -ENODEV; 694 } 695 696 /* check if this is the console port */ 697 if (mmres->start != CPHYSADDR(LTQ_EARLY_ASC)) 698 line = 1; 699 700 if (lqasc_port[line]) { 701 dev_err(&pdev->dev, "port %d already allocated\n", line); 702 return -EBUSY; 703 } 704 705 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port), 706 GFP_KERNEL); 707 if (!ltq_port) 708 return -ENOMEM; 709 710 port = <q_port->port; 711 712 port->iotype = SERIAL_IO_MEM; 713 port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP; 714 port->ops = &lqasc_pops; 715 port->fifosize = 16; 716 port->type = PORT_LTQ_ASC, 717 port->line = line; 718 port->dev = &pdev->dev; 719 /* unused, just to be backward-compatible */ 720 port->irq = irqres[0].start; 721 port->mapbase = mmres->start; 722 723 ltq_port->fpiclk = clk_get_fpi(); 724 if (IS_ERR(ltq_port->fpiclk)) { 725 pr_err("failed to get fpi clk\n"); 726 return -ENOENT; 727 } 728 729 /* not all asc ports have clock gates, lets ignore the return code */ 730 ltq_port->clk = clk_get(&pdev->dev, NULL); 731 732 ltq_port->tx_irq = irqres[0].start; 733 ltq_port->rx_irq = irqres[1].start; 734 ltq_port->err_irq = irqres[2].start; 735 736 lqasc_port[line] = ltq_port; 737 platform_set_drvdata(pdev, ltq_port); 738 739 ret = uart_add_one_port(&lqasc_reg, port); 740 741 return ret; 742 } 743 744 static const struct of_device_id ltq_asc_match[] = { 745 { .compatible = DRVNAME }, 746 {}, 747 }; 748 MODULE_DEVICE_TABLE(of, ltq_asc_match); 749 750 static struct platform_driver lqasc_driver = { 751 .driver = { 752 .name = DRVNAME, 753 .owner = THIS_MODULE, 754 .of_match_table = ltq_asc_match, 755 }, 756 }; 757 758 int __init 759 init_lqasc(void) 760 { 761 int ret; 762 763 ret = uart_register_driver(&lqasc_reg); 764 if (ret != 0) 765 return ret; 766 767 ret = platform_driver_probe(&lqasc_driver, lqasc_probe); 768 if (ret != 0) 769 uart_unregister_driver(&lqasc_reg); 770 771 return ret; 772 } 773 774 module_init(init_lqasc); 775 776 MODULE_DESCRIPTION("Lantiq serial port driver"); 777 MODULE_LICENSE("GPL"); 778