1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 4 * 5 * Copyright (C) 2004 Infineon IFAP DC COM CPE 6 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 7 * Copyright (C) 2007 John Crispin <john@phrozen.org> 8 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/console.h> 13 #include <linux/device.h> 14 #include <linux/gpio.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/lantiq.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_platform.h> 22 #include <linux/serial.h> 23 #include <linux/serial_core.h> 24 #include <linux/slab.h> 25 #include <linux/sysrq.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 29 #define PORT_LTQ_ASC 111 30 #define MAXPORTS 2 31 #define UART_DUMMY_UER_RX 1 32 #define DRVNAME "lantiq,asc" 33 #ifdef __BIG_ENDIAN 34 #define LTQ_ASC_TBUF (0x0020 + 3) 35 #define LTQ_ASC_RBUF (0x0024 + 3) 36 #else 37 #define LTQ_ASC_TBUF 0x0020 38 #define LTQ_ASC_RBUF 0x0024 39 #endif 40 #define LTQ_ASC_FSTAT 0x0048 41 #define LTQ_ASC_WHBSTATE 0x0018 42 #define LTQ_ASC_STATE 0x0014 43 #define LTQ_ASC_IRNCR 0x00F8 44 #define LTQ_ASC_CLC 0x0000 45 #define LTQ_ASC_ID 0x0008 46 #define LTQ_ASC_PISEL 0x0004 47 #define LTQ_ASC_TXFCON 0x0044 48 #define LTQ_ASC_RXFCON 0x0040 49 #define LTQ_ASC_CON 0x0010 50 #define LTQ_ASC_BG 0x0050 51 #define LTQ_ASC_IRNREN 0x00F4 52 53 #define ASC_IRNREN_TX 0x1 54 #define ASC_IRNREN_RX 0x2 55 #define ASC_IRNREN_ERR 0x4 56 #define ASC_IRNREN_TX_BUF 0x8 57 #define ASC_IRNCR_TIR 0x1 58 #define ASC_IRNCR_RIR 0x2 59 #define ASC_IRNCR_EIR 0x4 60 61 #define ASCOPT_CSIZE 0x3 62 #define TXFIFO_FL 1 63 #define RXFIFO_FL 1 64 #define ASCCLC_DISS 0x2 65 #define ASCCLC_RMCMASK 0x0000FF00 66 #define ASCCLC_RMCOFFSET 8 67 #define ASCCON_M_8ASYNC 0x0 68 #define ASCCON_M_7ASYNC 0x2 69 #define ASCCON_ODD 0x00000020 70 #define ASCCON_STP 0x00000080 71 #define ASCCON_BRS 0x00000100 72 #define ASCCON_FDE 0x00000200 73 #define ASCCON_R 0x00008000 74 #define ASCCON_FEN 0x00020000 75 #define ASCCON_ROEN 0x00080000 76 #define ASCCON_TOEN 0x00100000 77 #define ASCSTATE_PE 0x00010000 78 #define ASCSTATE_FE 0x00020000 79 #define ASCSTATE_ROE 0x00080000 80 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) 81 #define ASCWHBSTATE_CLRREN 0x00000001 82 #define ASCWHBSTATE_SETREN 0x00000002 83 #define ASCWHBSTATE_CLRPE 0x00000004 84 #define ASCWHBSTATE_CLRFE 0x00000008 85 #define ASCWHBSTATE_CLRROE 0x00000020 86 #define ASCTXFCON_TXFEN 0x0001 87 #define ASCTXFCON_TXFFLU 0x0002 88 #define ASCTXFCON_TXFITLMASK 0x3F00 89 #define ASCTXFCON_TXFITLOFF 8 90 #define ASCRXFCON_RXFEN 0x0001 91 #define ASCRXFCON_RXFFLU 0x0002 92 #define ASCRXFCON_RXFITLMASK 0x3F00 93 #define ASCRXFCON_RXFITLOFF 8 94 #define ASCFSTAT_RXFFLMASK 0x003F 95 #define ASCFSTAT_TXFFLMASK 0x3F00 96 #define ASCFSTAT_TXFREEMASK 0x3F000000 97 #define ASCFSTAT_TXFREEOFF 24 98 99 static void lqasc_tx_chars(struct uart_port *port); 100 static struct ltq_uart_port *lqasc_port[MAXPORTS]; 101 static struct uart_driver lqasc_reg; 102 static DEFINE_SPINLOCK(ltq_asc_lock); 103 104 struct ltq_uart_port { 105 struct uart_port port; 106 /* clock used to derive divider */ 107 struct clk *freqclk; 108 /* clock gating of the ASC core */ 109 struct clk *clk; 110 unsigned int tx_irq; 111 unsigned int rx_irq; 112 unsigned int err_irq; 113 }; 114 115 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) 116 { 117 u32 tmp = __raw_readl(reg); 118 119 __raw_writel((tmp & ~clear) | set, reg); 120 } 121 122 static inline struct 123 ltq_uart_port *to_ltq_uart_port(struct uart_port *port) 124 { 125 return container_of(port, struct ltq_uart_port, port); 126 } 127 128 static void 129 lqasc_stop_tx(struct uart_port *port) 130 { 131 return; 132 } 133 134 static void 135 lqasc_start_tx(struct uart_port *port) 136 { 137 unsigned long flags; 138 spin_lock_irqsave(<q_asc_lock, flags); 139 lqasc_tx_chars(port); 140 spin_unlock_irqrestore(<q_asc_lock, flags); 141 return; 142 } 143 144 static void 145 lqasc_stop_rx(struct uart_port *port) 146 { 147 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 148 } 149 150 static int 151 lqasc_rx_chars(struct uart_port *port) 152 { 153 struct tty_port *tport = &port->state->port; 154 unsigned int ch = 0, rsr = 0, fifocnt; 155 156 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 157 ASCFSTAT_RXFFLMASK; 158 while (fifocnt--) { 159 u8 flag = TTY_NORMAL; 160 ch = readb(port->membase + LTQ_ASC_RBUF); 161 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) 162 & ASCSTATE_ANY) | UART_DUMMY_UER_RX; 163 tty_flip_buffer_push(tport); 164 port->icount.rx++; 165 166 /* 167 * Note that the error handling code is 168 * out of the main execution path 169 */ 170 if (rsr & ASCSTATE_ANY) { 171 if (rsr & ASCSTATE_PE) { 172 port->icount.parity++; 173 asc_update_bits(0, ASCWHBSTATE_CLRPE, 174 port->membase + LTQ_ASC_WHBSTATE); 175 } else if (rsr & ASCSTATE_FE) { 176 port->icount.frame++; 177 asc_update_bits(0, ASCWHBSTATE_CLRFE, 178 port->membase + LTQ_ASC_WHBSTATE); 179 } 180 if (rsr & ASCSTATE_ROE) { 181 port->icount.overrun++; 182 asc_update_bits(0, ASCWHBSTATE_CLRROE, 183 port->membase + LTQ_ASC_WHBSTATE); 184 } 185 186 rsr &= port->read_status_mask; 187 188 if (rsr & ASCSTATE_PE) 189 flag = TTY_PARITY; 190 else if (rsr & ASCSTATE_FE) 191 flag = TTY_FRAME; 192 } 193 194 if ((rsr & port->ignore_status_mask) == 0) 195 tty_insert_flip_char(tport, ch, flag); 196 197 if (rsr & ASCSTATE_ROE) 198 /* 199 * Overrun is special, since it's reported 200 * immediately, and doesn't affect the current 201 * character 202 */ 203 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 204 } 205 206 if (ch != 0) 207 tty_flip_buffer_push(tport); 208 209 return 0; 210 } 211 212 static void 213 lqasc_tx_chars(struct uart_port *port) 214 { 215 struct circ_buf *xmit = &port->state->xmit; 216 if (uart_tx_stopped(port)) { 217 lqasc_stop_tx(port); 218 return; 219 } 220 221 while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) & 222 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { 223 if (port->x_char) { 224 writeb(port->x_char, port->membase + LTQ_ASC_TBUF); 225 port->icount.tx++; 226 port->x_char = 0; 227 continue; 228 } 229 230 if (uart_circ_empty(xmit)) 231 break; 232 233 writeb(port->state->xmit.buf[port->state->xmit.tail], 234 port->membase + LTQ_ASC_TBUF); 235 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 236 port->icount.tx++; 237 } 238 239 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 240 uart_write_wakeup(port); 241 } 242 243 static irqreturn_t 244 lqasc_tx_int(int irq, void *_port) 245 { 246 unsigned long flags; 247 struct uart_port *port = (struct uart_port *)_port; 248 spin_lock_irqsave(<q_asc_lock, flags); 249 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); 250 spin_unlock_irqrestore(<q_asc_lock, flags); 251 lqasc_start_tx(port); 252 return IRQ_HANDLED; 253 } 254 255 static irqreturn_t 256 lqasc_err_int(int irq, void *_port) 257 { 258 unsigned long flags; 259 struct uart_port *port = (struct uart_port *)_port; 260 spin_lock_irqsave(<q_asc_lock, flags); 261 /* clear any pending interrupts */ 262 asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | 263 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); 264 spin_unlock_irqrestore(<q_asc_lock, flags); 265 return IRQ_HANDLED; 266 } 267 268 static irqreturn_t 269 lqasc_rx_int(int irq, void *_port) 270 { 271 unsigned long flags; 272 struct uart_port *port = (struct uart_port *)_port; 273 spin_lock_irqsave(<q_asc_lock, flags); 274 __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); 275 lqasc_rx_chars(port); 276 spin_unlock_irqrestore(<q_asc_lock, flags); 277 return IRQ_HANDLED; 278 } 279 280 static unsigned int 281 lqasc_tx_empty(struct uart_port *port) 282 { 283 int status; 284 status = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 285 ASCFSTAT_TXFFLMASK; 286 return status ? 0 : TIOCSER_TEMT; 287 } 288 289 static unsigned int 290 lqasc_get_mctrl(struct uart_port *port) 291 { 292 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; 293 } 294 295 static void 296 lqasc_set_mctrl(struct uart_port *port, u_int mctrl) 297 { 298 } 299 300 static void 301 lqasc_break_ctl(struct uart_port *port, int break_state) 302 { 303 } 304 305 static int 306 lqasc_startup(struct uart_port *port) 307 { 308 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 309 int retval; 310 311 if (!IS_ERR(ltq_port->clk)) 312 clk_prepare_enable(ltq_port->clk); 313 port->uartclk = clk_get_rate(ltq_port->freqclk); 314 315 asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), 316 port->membase + LTQ_ASC_CLC); 317 318 __raw_writel(0, port->membase + LTQ_ASC_PISEL); 319 __raw_writel( 320 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | 321 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, 322 port->membase + LTQ_ASC_TXFCON); 323 __raw_writel( 324 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) 325 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, 326 port->membase + LTQ_ASC_RXFCON); 327 /* make sure other settings are written to hardware before 328 * setting enable bits 329 */ 330 wmb(); 331 asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | 332 ASCCON_ROEN, port->membase + LTQ_ASC_CON); 333 334 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, 335 0, "asc_tx", port); 336 if (retval) { 337 pr_err("failed to request lqasc_tx_int\n"); 338 return retval; 339 } 340 341 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, 342 0, "asc_rx", port); 343 if (retval) { 344 pr_err("failed to request lqasc_rx_int\n"); 345 goto err1; 346 } 347 348 retval = request_irq(ltq_port->err_irq, lqasc_err_int, 349 0, "asc_err", port); 350 if (retval) { 351 pr_err("failed to request lqasc_err_int\n"); 352 goto err2; 353 } 354 355 __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, 356 port->membase + LTQ_ASC_IRNREN); 357 return 0; 358 359 err2: 360 free_irq(ltq_port->rx_irq, port); 361 err1: 362 free_irq(ltq_port->tx_irq, port); 363 return retval; 364 } 365 366 static void 367 lqasc_shutdown(struct uart_port *port) 368 { 369 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 370 free_irq(ltq_port->tx_irq, port); 371 free_irq(ltq_port->rx_irq, port); 372 free_irq(ltq_port->err_irq, port); 373 374 __raw_writel(0, port->membase + LTQ_ASC_CON); 375 asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, 376 port->membase + LTQ_ASC_RXFCON); 377 asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, 378 port->membase + LTQ_ASC_TXFCON); 379 if (!IS_ERR(ltq_port->clk)) 380 clk_disable_unprepare(ltq_port->clk); 381 } 382 383 static void 384 lqasc_set_termios(struct uart_port *port, 385 struct ktermios *new, struct ktermios *old) 386 { 387 unsigned int cflag; 388 unsigned int iflag; 389 unsigned int divisor; 390 unsigned int baud; 391 unsigned int con = 0; 392 unsigned long flags; 393 394 cflag = new->c_cflag; 395 iflag = new->c_iflag; 396 397 switch (cflag & CSIZE) { 398 case CS7: 399 con = ASCCON_M_7ASYNC; 400 break; 401 402 case CS5: 403 case CS6: 404 default: 405 new->c_cflag &= ~ CSIZE; 406 new->c_cflag |= CS8; 407 con = ASCCON_M_8ASYNC; 408 break; 409 } 410 411 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 412 413 if (cflag & CSTOPB) 414 con |= ASCCON_STP; 415 416 if (cflag & PARENB) { 417 if (!(cflag & PARODD)) 418 con &= ~ASCCON_ODD; 419 else 420 con |= ASCCON_ODD; 421 } 422 423 port->read_status_mask = ASCSTATE_ROE; 424 if (iflag & INPCK) 425 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 426 427 port->ignore_status_mask = 0; 428 if (iflag & IGNPAR) 429 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 430 431 if (iflag & IGNBRK) { 432 /* 433 * If we're ignoring parity and break indicators, 434 * ignore overruns too (for real raw support). 435 */ 436 if (iflag & IGNPAR) 437 port->ignore_status_mask |= ASCSTATE_ROE; 438 } 439 440 if ((cflag & CREAD) == 0) 441 port->ignore_status_mask |= UART_DUMMY_UER_RX; 442 443 /* set error signals - framing, parity and overrun, enable receiver */ 444 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; 445 446 spin_lock_irqsave(<q_asc_lock, flags); 447 448 /* set up CON */ 449 asc_update_bits(0, con, port->membase + LTQ_ASC_CON); 450 451 /* Set baud rate - take a divider of 2 into account */ 452 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 453 divisor = uart_get_divisor(port, baud); 454 divisor = divisor / 2 - 1; 455 456 /* disable the baudrate generator */ 457 asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON); 458 459 /* make sure the fractional divider is off */ 460 asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); 461 462 /* set up to use divisor of 2 */ 463 asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); 464 465 /* now we can write the new baudrate into the register */ 466 __raw_writel(divisor, port->membase + LTQ_ASC_BG); 467 468 /* turn the baudrate generator back on */ 469 asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); 470 471 /* enable rx */ 472 __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); 473 474 spin_unlock_irqrestore(<q_asc_lock, flags); 475 476 /* Don't rewrite B0 */ 477 if (tty_termios_baud_rate(new)) 478 tty_termios_encode_baud_rate(new, baud, baud); 479 480 uart_update_timeout(port, cflag, baud); 481 } 482 483 static const char* 484 lqasc_type(struct uart_port *port) 485 { 486 if (port->type == PORT_LTQ_ASC) 487 return DRVNAME; 488 else 489 return NULL; 490 } 491 492 static void 493 lqasc_release_port(struct uart_port *port) 494 { 495 struct platform_device *pdev = to_platform_device(port->dev); 496 497 if (port->flags & UPF_IOREMAP) { 498 devm_iounmap(&pdev->dev, port->membase); 499 port->membase = NULL; 500 } 501 } 502 503 static int 504 lqasc_request_port(struct uart_port *port) 505 { 506 struct platform_device *pdev = to_platform_device(port->dev); 507 struct resource *res; 508 int size; 509 510 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 511 if (!res) { 512 dev_err(&pdev->dev, "cannot obtain I/O memory region"); 513 return -ENODEV; 514 } 515 size = resource_size(res); 516 517 res = devm_request_mem_region(&pdev->dev, res->start, 518 size, dev_name(&pdev->dev)); 519 if (!res) { 520 dev_err(&pdev->dev, "cannot request I/O memory region"); 521 return -EBUSY; 522 } 523 524 if (port->flags & UPF_IOREMAP) { 525 port->membase = devm_ioremap_nocache(&pdev->dev, 526 port->mapbase, size); 527 if (port->membase == NULL) 528 return -ENOMEM; 529 } 530 return 0; 531 } 532 533 static void 534 lqasc_config_port(struct uart_port *port, int flags) 535 { 536 if (flags & UART_CONFIG_TYPE) { 537 port->type = PORT_LTQ_ASC; 538 lqasc_request_port(port); 539 } 540 } 541 542 static int 543 lqasc_verify_port(struct uart_port *port, 544 struct serial_struct *ser) 545 { 546 int ret = 0; 547 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) 548 ret = -EINVAL; 549 if (ser->irq < 0 || ser->irq >= NR_IRQS) 550 ret = -EINVAL; 551 if (ser->baud_base < 9600) 552 ret = -EINVAL; 553 return ret; 554 } 555 556 static const struct uart_ops lqasc_pops = { 557 .tx_empty = lqasc_tx_empty, 558 .set_mctrl = lqasc_set_mctrl, 559 .get_mctrl = lqasc_get_mctrl, 560 .stop_tx = lqasc_stop_tx, 561 .start_tx = lqasc_start_tx, 562 .stop_rx = lqasc_stop_rx, 563 .break_ctl = lqasc_break_ctl, 564 .startup = lqasc_startup, 565 .shutdown = lqasc_shutdown, 566 .set_termios = lqasc_set_termios, 567 .type = lqasc_type, 568 .release_port = lqasc_release_port, 569 .request_port = lqasc_request_port, 570 .config_port = lqasc_config_port, 571 .verify_port = lqasc_verify_port, 572 }; 573 574 static void 575 lqasc_console_putchar(struct uart_port *port, int ch) 576 { 577 int fifofree; 578 579 if (!port->membase) 580 return; 581 582 do { 583 fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT) 584 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; 585 } while (fifofree == 0); 586 writeb(ch, port->membase + LTQ_ASC_TBUF); 587 } 588 589 static void lqasc_serial_port_write(struct uart_port *port, const char *s, 590 u_int count) 591 { 592 unsigned long flags; 593 594 spin_lock_irqsave(<q_asc_lock, flags); 595 uart_console_write(port, s, count, lqasc_console_putchar); 596 spin_unlock_irqrestore(<q_asc_lock, flags); 597 } 598 599 static void 600 lqasc_console_write(struct console *co, const char *s, u_int count) 601 { 602 struct ltq_uart_port *ltq_port; 603 604 if (co->index >= MAXPORTS) 605 return; 606 607 ltq_port = lqasc_port[co->index]; 608 if (!ltq_port) 609 return; 610 611 lqasc_serial_port_write(<q_port->port, s, count); 612 } 613 614 static int __init 615 lqasc_console_setup(struct console *co, char *options) 616 { 617 struct ltq_uart_port *ltq_port; 618 struct uart_port *port; 619 int baud = 115200; 620 int bits = 8; 621 int parity = 'n'; 622 int flow = 'n'; 623 624 if (co->index >= MAXPORTS) 625 return -ENODEV; 626 627 ltq_port = lqasc_port[co->index]; 628 if (!ltq_port) 629 return -ENODEV; 630 631 port = <q_port->port; 632 633 if (!IS_ERR(ltq_port->clk)) 634 clk_prepare_enable(ltq_port->clk); 635 636 port->uartclk = clk_get_rate(ltq_port->freqclk); 637 638 if (options) 639 uart_parse_options(options, &baud, &parity, &bits, &flow); 640 return uart_set_options(port, co, baud, parity, bits, flow); 641 } 642 643 static struct console lqasc_console = { 644 .name = "ttyLTQ", 645 .write = lqasc_console_write, 646 .device = uart_console_device, 647 .setup = lqasc_console_setup, 648 .flags = CON_PRINTBUFFER, 649 .index = -1, 650 .data = &lqasc_reg, 651 }; 652 653 static int __init 654 lqasc_console_init(void) 655 { 656 register_console(&lqasc_console); 657 return 0; 658 } 659 console_initcall(lqasc_console_init); 660 661 static void lqasc_serial_early_console_write(struct console *co, 662 const char *s, 663 u_int count) 664 { 665 struct earlycon_device *dev = co->data; 666 667 lqasc_serial_port_write(&dev->port, s, count); 668 } 669 670 static int __init 671 lqasc_serial_early_console_setup(struct earlycon_device *device, 672 const char *opt) 673 { 674 if (!device->port.membase) 675 return -ENODEV; 676 677 device->con->write = lqasc_serial_early_console_write; 678 return 0; 679 } 680 OF_EARLYCON_DECLARE(lantiq, DRVNAME, lqasc_serial_early_console_setup); 681 682 static struct uart_driver lqasc_reg = { 683 .owner = THIS_MODULE, 684 .driver_name = DRVNAME, 685 .dev_name = "ttyLTQ", 686 .major = 0, 687 .minor = 0, 688 .nr = MAXPORTS, 689 .cons = &lqasc_console, 690 }; 691 692 static int __init 693 lqasc_probe(struct platform_device *pdev) 694 { 695 struct device_node *node = pdev->dev.of_node; 696 struct ltq_uart_port *ltq_port; 697 struct uart_port *port; 698 struct resource *mmres, irqres[3]; 699 int line; 700 int ret; 701 702 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 703 ret = of_irq_to_resource_table(node, irqres, 3); 704 if (!mmres || (ret != 3)) { 705 dev_err(&pdev->dev, 706 "failed to get memory/irq for serial port\n"); 707 return -ENODEV; 708 } 709 710 /* get serial id */ 711 line = of_alias_get_id(node, "serial"); 712 if (line < 0) { 713 if (IS_ENABLED(CONFIG_LANTIQ)) { 714 if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC)) 715 line = 0; 716 else 717 line = 1; 718 } else { 719 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 720 line); 721 return line; 722 } 723 } 724 725 if (lqasc_port[line]) { 726 dev_err(&pdev->dev, "port %d already allocated\n", line); 727 return -EBUSY; 728 } 729 730 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port), 731 GFP_KERNEL); 732 if (!ltq_port) 733 return -ENOMEM; 734 735 port = <q_port->port; 736 737 port->iotype = SERIAL_IO_MEM; 738 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 739 port->ops = &lqasc_pops; 740 port->fifosize = 16; 741 port->type = PORT_LTQ_ASC, 742 port->line = line; 743 port->dev = &pdev->dev; 744 /* unused, just to be backward-compatible */ 745 port->irq = irqres[0].start; 746 port->mapbase = mmres->start; 747 748 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 749 ltq_port->freqclk = clk_get_fpi(); 750 else 751 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq"); 752 753 754 if (IS_ERR(ltq_port->freqclk)) { 755 pr_err("failed to get fpi clk\n"); 756 return -ENOENT; 757 } 758 759 /* not all asc ports have clock gates, lets ignore the return code */ 760 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 761 ltq_port->clk = clk_get(&pdev->dev, NULL); 762 else 763 ltq_port->clk = devm_clk_get(&pdev->dev, "asc"); 764 765 ltq_port->tx_irq = irqres[0].start; 766 ltq_port->rx_irq = irqres[1].start; 767 ltq_port->err_irq = irqres[2].start; 768 769 lqasc_port[line] = ltq_port; 770 platform_set_drvdata(pdev, ltq_port); 771 772 ret = uart_add_one_port(&lqasc_reg, port); 773 774 return ret; 775 } 776 777 static const struct of_device_id ltq_asc_match[] = { 778 { .compatible = DRVNAME }, 779 {}, 780 }; 781 782 static struct platform_driver lqasc_driver = { 783 .driver = { 784 .name = DRVNAME, 785 .of_match_table = ltq_asc_match, 786 }, 787 }; 788 789 static int __init 790 init_lqasc(void) 791 { 792 int ret; 793 794 ret = uart_register_driver(&lqasc_reg); 795 if (ret != 0) 796 return ret; 797 798 ret = platform_driver_probe(&lqasc_driver, lqasc_probe); 799 if (ret != 0) 800 uart_unregister_driver(&lqasc_reg); 801 802 return ret; 803 } 804 device_initcall(init_lqasc); 805