xref: /openbmc/linux/drivers/tty/serial/lantiq.c (revision adb57164) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
4  *
5  * Copyright (C) 2004 Infineon IFAP DC COM CPE
6  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
7  * Copyright (C) 2007 John Crispin <john@phrozen.org>
8  * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
9  */
10 
11 #include <linux/clk.h>
12 #include <linux/console.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/lantiq.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/serial.h>
22 #include <linux/serial_core.h>
23 #include <linux/slab.h>
24 #include <linux/sysrq.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 
28 #define PORT_LTQ_ASC		111
29 #define MAXPORTS		2
30 #define UART_DUMMY_UER_RX	1
31 #define DRVNAME			"lantiq,asc"
32 #ifdef __BIG_ENDIAN
33 #define LTQ_ASC_TBUF		(0x0020 + 3)
34 #define LTQ_ASC_RBUF		(0x0024 + 3)
35 #else
36 #define LTQ_ASC_TBUF		0x0020
37 #define LTQ_ASC_RBUF		0x0024
38 #endif
39 #define LTQ_ASC_FSTAT		0x0048
40 #define LTQ_ASC_WHBSTATE	0x0018
41 #define LTQ_ASC_STATE		0x0014
42 #define LTQ_ASC_IRNCR		0x00F8
43 #define LTQ_ASC_CLC		0x0000
44 #define LTQ_ASC_ID		0x0008
45 #define LTQ_ASC_PISEL		0x0004
46 #define LTQ_ASC_TXFCON		0x0044
47 #define LTQ_ASC_RXFCON		0x0040
48 #define LTQ_ASC_CON		0x0010
49 #define LTQ_ASC_BG		0x0050
50 #define LTQ_ASC_IRNREN		0x00F4
51 
52 #define ASC_IRNREN_TX		0x1
53 #define ASC_IRNREN_RX		0x2
54 #define ASC_IRNREN_ERR		0x4
55 #define ASC_IRNREN_TX_BUF	0x8
56 #define ASC_IRNCR_TIR		0x1
57 #define ASC_IRNCR_RIR		0x2
58 #define ASC_IRNCR_EIR		0x4
59 #define ASC_IRNCR_MASK		GENMASK(2, 0)
60 
61 #define ASCOPT_CSIZE		0x3
62 #define TXFIFO_FL		1
63 #define RXFIFO_FL		1
64 #define ASCCLC_DISS		0x2
65 #define ASCCLC_RMCMASK		0x0000FF00
66 #define ASCCLC_RMCOFFSET	8
67 #define ASCCON_M_8ASYNC		0x0
68 #define ASCCON_M_7ASYNC		0x2
69 #define ASCCON_ODD		0x00000020
70 #define ASCCON_STP		0x00000080
71 #define ASCCON_BRS		0x00000100
72 #define ASCCON_FDE		0x00000200
73 #define ASCCON_R		0x00008000
74 #define ASCCON_FEN		0x00020000
75 #define ASCCON_ROEN		0x00080000
76 #define ASCCON_TOEN		0x00100000
77 #define ASCSTATE_PE		0x00010000
78 #define ASCSTATE_FE		0x00020000
79 #define ASCSTATE_ROE		0x00080000
80 #define ASCSTATE_ANY		(ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
81 #define ASCWHBSTATE_CLRREN	0x00000001
82 #define ASCWHBSTATE_SETREN	0x00000002
83 #define ASCWHBSTATE_CLRPE	0x00000004
84 #define ASCWHBSTATE_CLRFE	0x00000008
85 #define ASCWHBSTATE_CLRROE	0x00000020
86 #define ASCTXFCON_TXFEN		0x0001
87 #define ASCTXFCON_TXFFLU	0x0002
88 #define ASCTXFCON_TXFITLMASK	0x3F00
89 #define ASCTXFCON_TXFITLOFF	8
90 #define ASCRXFCON_RXFEN		0x0001
91 #define ASCRXFCON_RXFFLU	0x0002
92 #define ASCRXFCON_RXFITLMASK	0x3F00
93 #define ASCRXFCON_RXFITLOFF	8
94 #define ASCFSTAT_RXFFLMASK	0x003F
95 #define ASCFSTAT_TXFFLMASK	0x3F00
96 #define ASCFSTAT_TXFREEMASK	0x3F000000
97 #define ASCFSTAT_TXFREEOFF	24
98 
99 static void lqasc_tx_chars(struct uart_port *port);
100 static struct ltq_uart_port *lqasc_port[MAXPORTS];
101 static struct uart_driver lqasc_reg;
102 
103 struct ltq_soc_data {
104 	int	(*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port);
105 	int	(*request_irq)(struct uart_port *port);
106 	void	(*free_irq)(struct uart_port *port);
107 };
108 
109 struct ltq_uart_port {
110 	struct uart_port	port;
111 	/* clock used to derive divider */
112 	struct clk		*freqclk;
113 	/* clock gating of the ASC core */
114 	struct clk		*clk;
115 	unsigned int		tx_irq;
116 	unsigned int		rx_irq;
117 	unsigned int		err_irq;
118 	unsigned int		common_irq;
119 	spinlock_t		lock; /* exclusive access for multi core */
120 
121 	const struct ltq_soc_data	*soc;
122 };
123 
124 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
125 {
126 	u32 tmp = __raw_readl(reg);
127 
128 	__raw_writel((tmp & ~clear) | set, reg);
129 }
130 
131 static inline struct
132 ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
133 {
134 	return container_of(port, struct ltq_uart_port, port);
135 }
136 
137 static void
138 lqasc_stop_tx(struct uart_port *port)
139 {
140 	return;
141 }
142 
143 static void
144 lqasc_start_tx(struct uart_port *port)
145 {
146 	unsigned long flags;
147 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
148 
149 	spin_lock_irqsave(&ltq_port->lock, flags);
150 	lqasc_tx_chars(port);
151 	spin_unlock_irqrestore(&ltq_port->lock, flags);
152 	return;
153 }
154 
155 static void
156 lqasc_stop_rx(struct uart_port *port)
157 {
158 	__raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
159 }
160 
161 static int
162 lqasc_rx_chars(struct uart_port *port)
163 {
164 	struct tty_port *tport = &port->state->port;
165 	unsigned int ch = 0, rsr = 0, fifocnt;
166 
167 	fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
168 		  ASCFSTAT_RXFFLMASK;
169 	while (fifocnt--) {
170 		u8 flag = TTY_NORMAL;
171 		ch = readb(port->membase + LTQ_ASC_RBUF);
172 		rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
173 			& ASCSTATE_ANY) | UART_DUMMY_UER_RX;
174 		tty_flip_buffer_push(tport);
175 		port->icount.rx++;
176 
177 		/*
178 		 * Note that the error handling code is
179 		 * out of the main execution path
180 		 */
181 		if (rsr & ASCSTATE_ANY) {
182 			if (rsr & ASCSTATE_PE) {
183 				port->icount.parity++;
184 				asc_update_bits(0, ASCWHBSTATE_CLRPE,
185 					port->membase + LTQ_ASC_WHBSTATE);
186 			} else if (rsr & ASCSTATE_FE) {
187 				port->icount.frame++;
188 				asc_update_bits(0, ASCWHBSTATE_CLRFE,
189 					port->membase + LTQ_ASC_WHBSTATE);
190 			}
191 			if (rsr & ASCSTATE_ROE) {
192 				port->icount.overrun++;
193 				asc_update_bits(0, ASCWHBSTATE_CLRROE,
194 					port->membase + LTQ_ASC_WHBSTATE);
195 			}
196 
197 			rsr &= port->read_status_mask;
198 
199 			if (rsr & ASCSTATE_PE)
200 				flag = TTY_PARITY;
201 			else if (rsr & ASCSTATE_FE)
202 				flag = TTY_FRAME;
203 		}
204 
205 		if ((rsr & port->ignore_status_mask) == 0)
206 			tty_insert_flip_char(tport, ch, flag);
207 
208 		if (rsr & ASCSTATE_ROE)
209 			/*
210 			 * Overrun is special, since it's reported
211 			 * immediately, and doesn't affect the current
212 			 * character
213 			 */
214 			tty_insert_flip_char(tport, 0, TTY_OVERRUN);
215 	}
216 
217 	if (ch != 0)
218 		tty_flip_buffer_push(tport);
219 
220 	return 0;
221 }
222 
223 static void
224 lqasc_tx_chars(struct uart_port *port)
225 {
226 	struct circ_buf *xmit = &port->state->xmit;
227 	if (uart_tx_stopped(port)) {
228 		lqasc_stop_tx(port);
229 		return;
230 	}
231 
232 	while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) &
233 		ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
234 		if (port->x_char) {
235 			writeb(port->x_char, port->membase + LTQ_ASC_TBUF);
236 			port->icount.tx++;
237 			port->x_char = 0;
238 			continue;
239 		}
240 
241 		if (uart_circ_empty(xmit))
242 			break;
243 
244 		writeb(port->state->xmit.buf[port->state->xmit.tail],
245 			port->membase + LTQ_ASC_TBUF);
246 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
247 		port->icount.tx++;
248 	}
249 
250 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
251 		uart_write_wakeup(port);
252 }
253 
254 static irqreturn_t
255 lqasc_tx_int(int irq, void *_port)
256 {
257 	unsigned long flags;
258 	struct uart_port *port = (struct uart_port *)_port;
259 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
260 
261 	spin_lock_irqsave(&ltq_port->lock, flags);
262 	__raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
263 	spin_unlock_irqrestore(&ltq_port->lock, flags);
264 	lqasc_start_tx(port);
265 	return IRQ_HANDLED;
266 }
267 
268 static irqreturn_t
269 lqasc_err_int(int irq, void *_port)
270 {
271 	unsigned long flags;
272 	struct uart_port *port = (struct uart_port *)_port;
273 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
274 
275 	spin_lock_irqsave(&ltq_port->lock, flags);
276 	/* clear any pending interrupts */
277 	asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
278 		ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
279 	spin_unlock_irqrestore(&ltq_port->lock, flags);
280 	return IRQ_HANDLED;
281 }
282 
283 static irqreturn_t
284 lqasc_rx_int(int irq, void *_port)
285 {
286 	unsigned long flags;
287 	struct uart_port *port = (struct uart_port *)_port;
288 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
289 
290 	spin_lock_irqsave(&ltq_port->lock, flags);
291 	__raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
292 	lqasc_rx_chars(port);
293 	spin_unlock_irqrestore(&ltq_port->lock, flags);
294 	return IRQ_HANDLED;
295 }
296 
297 static irqreturn_t lqasc_irq(int irq, void *p)
298 {
299 	unsigned long flags;
300 	u32 stat;
301 	struct uart_port *port = p;
302 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
303 
304 	spin_lock_irqsave(&ltq_port->lock, flags);
305 	stat = readl(port->membase + LTQ_ASC_IRNCR);
306 	spin_unlock_irqrestore(&ltq_port->lock, flags);
307 	if (!(stat & ASC_IRNCR_MASK))
308 		return IRQ_NONE;
309 
310 	if (stat & ASC_IRNCR_TIR)
311 		lqasc_tx_int(irq, p);
312 
313 	if (stat & ASC_IRNCR_RIR)
314 		lqasc_rx_int(irq, p);
315 
316 	if (stat & ASC_IRNCR_EIR)
317 		lqasc_err_int(irq, p);
318 
319 	return IRQ_HANDLED;
320 }
321 
322 static unsigned int
323 lqasc_tx_empty(struct uart_port *port)
324 {
325 	int status;
326 	status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
327 		 ASCFSTAT_TXFFLMASK;
328 	return status ? 0 : TIOCSER_TEMT;
329 }
330 
331 static unsigned int
332 lqasc_get_mctrl(struct uart_port *port)
333 {
334 	return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
335 }
336 
337 static void
338 lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
339 {
340 }
341 
342 static void
343 lqasc_break_ctl(struct uart_port *port, int break_state)
344 {
345 }
346 
347 static int
348 lqasc_startup(struct uart_port *port)
349 {
350 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
351 	int retval;
352 	unsigned long flags;
353 
354 	if (!IS_ERR(ltq_port->clk))
355 		clk_prepare_enable(ltq_port->clk);
356 	port->uartclk = clk_get_rate(ltq_port->freqclk);
357 
358 	spin_lock_irqsave(&ltq_port->lock, flags);
359 	asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
360 		port->membase + LTQ_ASC_CLC);
361 
362 	__raw_writel(0, port->membase + LTQ_ASC_PISEL);
363 	__raw_writel(
364 		((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
365 		ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
366 		port->membase + LTQ_ASC_TXFCON);
367 	__raw_writel(
368 		((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
369 		| ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
370 		port->membase + LTQ_ASC_RXFCON);
371 	/* make sure other settings are written to hardware before
372 	 * setting enable bits
373 	 */
374 	wmb();
375 	asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
376 		ASCCON_ROEN, port->membase + LTQ_ASC_CON);
377 
378 	spin_unlock_irqrestore(&ltq_port->lock, flags);
379 
380 	retval = ltq_port->soc->request_irq(port);
381 	if (retval)
382 		return retval;
383 
384 	__raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
385 		port->membase + LTQ_ASC_IRNREN);
386 	return retval;
387 }
388 
389 static void
390 lqasc_shutdown(struct uart_port *port)
391 {
392 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
393 	unsigned long flags;
394 
395 	ltq_port->soc->free_irq(port);
396 
397 	spin_lock_irqsave(&ltq_port->lock, flags);
398 	__raw_writel(0, port->membase + LTQ_ASC_CON);
399 	asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
400 		port->membase + LTQ_ASC_RXFCON);
401 	asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
402 		port->membase + LTQ_ASC_TXFCON);
403 	spin_unlock_irqrestore(&ltq_port->lock, flags);
404 	if (!IS_ERR(ltq_port->clk))
405 		clk_disable_unprepare(ltq_port->clk);
406 }
407 
408 static void
409 lqasc_set_termios(struct uart_port *port,
410 	struct ktermios *new, struct ktermios *old)
411 {
412 	unsigned int cflag;
413 	unsigned int iflag;
414 	unsigned int divisor;
415 	unsigned int baud;
416 	unsigned int con = 0;
417 	unsigned long flags;
418 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
419 
420 	cflag = new->c_cflag;
421 	iflag = new->c_iflag;
422 
423 	switch (cflag & CSIZE) {
424 	case CS7:
425 		con = ASCCON_M_7ASYNC;
426 		break;
427 
428 	case CS5:
429 	case CS6:
430 	default:
431 		new->c_cflag &= ~ CSIZE;
432 		new->c_cflag |= CS8;
433 		con = ASCCON_M_8ASYNC;
434 		break;
435 	}
436 
437 	cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
438 
439 	if (cflag & CSTOPB)
440 		con |= ASCCON_STP;
441 
442 	if (cflag & PARENB) {
443 		if (!(cflag & PARODD))
444 			con &= ~ASCCON_ODD;
445 		else
446 			con |= ASCCON_ODD;
447 	}
448 
449 	port->read_status_mask = ASCSTATE_ROE;
450 	if (iflag & INPCK)
451 		port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
452 
453 	port->ignore_status_mask = 0;
454 	if (iflag & IGNPAR)
455 		port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
456 
457 	if (iflag & IGNBRK) {
458 		/*
459 		 * If we're ignoring parity and break indicators,
460 		 * ignore overruns too (for real raw support).
461 		 */
462 		if (iflag & IGNPAR)
463 			port->ignore_status_mask |= ASCSTATE_ROE;
464 	}
465 
466 	if ((cflag & CREAD) == 0)
467 		port->ignore_status_mask |= UART_DUMMY_UER_RX;
468 
469 	/* set error signals  - framing, parity  and overrun, enable receiver */
470 	con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
471 
472 	spin_lock_irqsave(&ltq_port->lock, flags);
473 
474 	/* set up CON */
475 	asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
476 
477 	/* Set baud rate - take a divider of 2 into account */
478 	baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
479 	divisor = uart_get_divisor(port, baud);
480 	divisor = divisor / 2 - 1;
481 
482 	/* disable the baudrate generator */
483 	asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
484 
485 	/* make sure the fractional divider is off */
486 	asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
487 
488 	/* set up to use divisor of 2 */
489 	asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
490 
491 	/* now we can write the new baudrate into the register */
492 	__raw_writel(divisor, port->membase + LTQ_ASC_BG);
493 
494 	/* turn the baudrate generator back on */
495 	asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
496 
497 	/* enable rx */
498 	__raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
499 
500 	spin_unlock_irqrestore(&ltq_port->lock, flags);
501 
502 	/* Don't rewrite B0 */
503 	if (tty_termios_baud_rate(new))
504 		tty_termios_encode_baud_rate(new, baud, baud);
505 
506 	uart_update_timeout(port, cflag, baud);
507 }
508 
509 static const char*
510 lqasc_type(struct uart_port *port)
511 {
512 	if (port->type == PORT_LTQ_ASC)
513 		return DRVNAME;
514 	else
515 		return NULL;
516 }
517 
518 static void
519 lqasc_release_port(struct uart_port *port)
520 {
521 	struct platform_device *pdev = to_platform_device(port->dev);
522 
523 	if (port->flags & UPF_IOREMAP) {
524 		devm_iounmap(&pdev->dev, port->membase);
525 		port->membase = NULL;
526 	}
527 }
528 
529 static int
530 lqasc_request_port(struct uart_port *port)
531 {
532 	struct platform_device *pdev = to_platform_device(port->dev);
533 	struct resource *res;
534 	int size;
535 
536 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
537 	if (!res) {
538 		dev_err(&pdev->dev, "cannot obtain I/O memory region");
539 		return -ENODEV;
540 	}
541 	size = resource_size(res);
542 
543 	res = devm_request_mem_region(&pdev->dev, res->start,
544 		size, dev_name(&pdev->dev));
545 	if (!res) {
546 		dev_err(&pdev->dev, "cannot request I/O memory region");
547 		return -EBUSY;
548 	}
549 
550 	if (port->flags & UPF_IOREMAP) {
551 		port->membase = devm_ioremap(&pdev->dev,
552 			port->mapbase, size);
553 		if (port->membase == NULL)
554 			return -ENOMEM;
555 	}
556 	return 0;
557 }
558 
559 static void
560 lqasc_config_port(struct uart_port *port, int flags)
561 {
562 	if (flags & UART_CONFIG_TYPE) {
563 		port->type = PORT_LTQ_ASC;
564 		lqasc_request_port(port);
565 	}
566 }
567 
568 static int
569 lqasc_verify_port(struct uart_port *port,
570 	struct serial_struct *ser)
571 {
572 	int ret = 0;
573 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
574 		ret = -EINVAL;
575 	if (ser->irq < 0 || ser->irq >= NR_IRQS)
576 		ret = -EINVAL;
577 	if (ser->baud_base < 9600)
578 		ret = -EINVAL;
579 	return ret;
580 }
581 
582 static const struct uart_ops lqasc_pops = {
583 	.tx_empty =	lqasc_tx_empty,
584 	.set_mctrl =	lqasc_set_mctrl,
585 	.get_mctrl =	lqasc_get_mctrl,
586 	.stop_tx =	lqasc_stop_tx,
587 	.start_tx =	lqasc_start_tx,
588 	.stop_rx =	lqasc_stop_rx,
589 	.break_ctl =	lqasc_break_ctl,
590 	.startup =	lqasc_startup,
591 	.shutdown =	lqasc_shutdown,
592 	.set_termios =	lqasc_set_termios,
593 	.type =		lqasc_type,
594 	.release_port =	lqasc_release_port,
595 	.request_port =	lqasc_request_port,
596 	.config_port =	lqasc_config_port,
597 	.verify_port =	lqasc_verify_port,
598 };
599 
600 static void
601 lqasc_console_putchar(struct uart_port *port, int ch)
602 {
603 	int fifofree;
604 
605 	if (!port->membase)
606 		return;
607 
608 	do {
609 		fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT)
610 			& ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
611 	} while (fifofree == 0);
612 	writeb(ch, port->membase + LTQ_ASC_TBUF);
613 }
614 
615 static void lqasc_serial_port_write(struct uart_port *port, const char *s,
616 				    u_int count)
617 {
618 	uart_console_write(port, s, count, lqasc_console_putchar);
619 }
620 
621 static void
622 lqasc_console_write(struct console *co, const char *s, u_int count)
623 {
624 	struct ltq_uart_port *ltq_port;
625 	unsigned long flags;
626 
627 	if (co->index >= MAXPORTS)
628 		return;
629 
630 	ltq_port = lqasc_port[co->index];
631 	if (!ltq_port)
632 		return;
633 
634 	spin_lock_irqsave(&ltq_port->lock, flags);
635 	lqasc_serial_port_write(&ltq_port->port, s, count);
636 	spin_unlock_irqrestore(&ltq_port->lock, flags);
637 }
638 
639 static int __init
640 lqasc_console_setup(struct console *co, char *options)
641 {
642 	struct ltq_uart_port *ltq_port;
643 	struct uart_port *port;
644 	int baud = 115200;
645 	int bits = 8;
646 	int parity = 'n';
647 	int flow = 'n';
648 
649 	if (co->index >= MAXPORTS)
650 		return -ENODEV;
651 
652 	ltq_port = lqasc_port[co->index];
653 	if (!ltq_port)
654 		return -ENODEV;
655 
656 	port = &ltq_port->port;
657 
658 	if (!IS_ERR(ltq_port->clk))
659 		clk_prepare_enable(ltq_port->clk);
660 
661 	port->uartclk = clk_get_rate(ltq_port->freqclk);
662 
663 	if (options)
664 		uart_parse_options(options, &baud, &parity, &bits, &flow);
665 	return uart_set_options(port, co, baud, parity, bits, flow);
666 }
667 
668 static struct console lqasc_console = {
669 	.name =		"ttyLTQ",
670 	.write =	lqasc_console_write,
671 	.device =	uart_console_device,
672 	.setup =	lqasc_console_setup,
673 	.flags =	CON_PRINTBUFFER,
674 	.index =	-1,
675 	.data =		&lqasc_reg,
676 };
677 
678 static int __init
679 lqasc_console_init(void)
680 {
681 	register_console(&lqasc_console);
682 	return 0;
683 }
684 console_initcall(lqasc_console_init);
685 
686 static void lqasc_serial_early_console_write(struct console *co,
687 					     const char *s,
688 					     u_int count)
689 {
690 	struct earlycon_device *dev = co->data;
691 
692 	lqasc_serial_port_write(&dev->port, s, count);
693 }
694 
695 static int __init
696 lqasc_serial_early_console_setup(struct earlycon_device *device,
697 				 const char *opt)
698 {
699 	if (!device->port.membase)
700 		return -ENODEV;
701 
702 	device->con->write = lqasc_serial_early_console_write;
703 	return 0;
704 }
705 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
706 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
707 
708 static struct uart_driver lqasc_reg = {
709 	.owner =	THIS_MODULE,
710 	.driver_name =	DRVNAME,
711 	.dev_name =	"ttyLTQ",
712 	.major =	0,
713 	.minor =	0,
714 	.nr =		MAXPORTS,
715 	.cons =		&lqasc_console,
716 };
717 
718 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
719 {
720 	struct uart_port *port = &ltq_port->port;
721 	struct resource irqres[3];
722 	int ret;
723 
724 	ret = of_irq_to_resource_table(dev->of_node, irqres, 3);
725 	if (ret != 3) {
726 		dev_err(dev,
727 			"failed to get IRQs for serial port\n");
728 		return -ENODEV;
729 	}
730 	ltq_port->tx_irq = irqres[0].start;
731 	ltq_port->rx_irq = irqres[1].start;
732 	ltq_port->err_irq = irqres[2].start;
733 	port->irq = irqres[0].start;
734 
735 	return 0;
736 }
737 
738 static int request_irq_lantiq(struct uart_port *port)
739 {
740 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
741 	int retval;
742 
743 	retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
744 			     0, "asc_tx", port);
745 	if (retval) {
746 		dev_err(port->dev, "failed to request asc_tx\n");
747 		return retval;
748 	}
749 
750 	retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
751 			     0, "asc_rx", port);
752 	if (retval) {
753 		dev_err(port->dev, "failed to request asc_rx\n");
754 		goto err1;
755 	}
756 
757 	retval = request_irq(ltq_port->err_irq, lqasc_err_int,
758 			     0, "asc_err", port);
759 	if (retval) {
760 		dev_err(port->dev, "failed to request asc_err\n");
761 		goto err2;
762 	}
763 	return 0;
764 
765 err2:
766 	free_irq(ltq_port->rx_irq, port);
767 err1:
768 	free_irq(ltq_port->tx_irq, port);
769 	return retval;
770 }
771 
772 static void free_irq_lantiq(struct uart_port *port)
773 {
774 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
775 
776 	free_irq(ltq_port->tx_irq, port);
777 	free_irq(ltq_port->rx_irq, port);
778 	free_irq(ltq_port->err_irq, port);
779 }
780 
781 static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port)
782 {
783 	struct uart_port *port = &ltq_port->port;
784 	int ret;
785 
786 	ret = of_irq_get(dev->of_node, 0);
787 	if (ret < 0) {
788 		dev_err(dev, "failed to fetch IRQ for serial port\n");
789 		return ret;
790 	}
791 	ltq_port->common_irq = ret;
792 	port->irq = ret;
793 
794 	return 0;
795 }
796 
797 static int request_irq_intel(struct uart_port *port)
798 {
799 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
800 	int retval;
801 
802 	retval = request_irq(ltq_port->common_irq, lqasc_irq, 0,
803 			     "asc_irq", port);
804 	if (retval)
805 		dev_err(port->dev, "failed to request asc_irq\n");
806 
807 	return retval;
808 }
809 
810 static void free_irq_intel(struct uart_port *port)
811 {
812 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
813 
814 	free_irq(ltq_port->common_irq, port);
815 }
816 
817 static int __init
818 lqasc_probe(struct platform_device *pdev)
819 {
820 	struct device_node *node = pdev->dev.of_node;
821 	struct ltq_uart_port *ltq_port;
822 	struct uart_port *port;
823 	struct resource *mmres;
824 	int line;
825 	int ret;
826 
827 	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
828 	if (!mmres) {
829 		dev_err(&pdev->dev,
830 			"failed to get memory for serial port\n");
831 		return -ENODEV;
832 	}
833 
834 	ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
835 				GFP_KERNEL);
836 	if (!ltq_port)
837 		return -ENOMEM;
838 
839 	port = &ltq_port->port;
840 
841 	ltq_port->soc = of_device_get_match_data(&pdev->dev);
842 	ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port);
843 	if (ret)
844 		return ret;
845 
846 	/* get serial id */
847 	line = of_alias_get_id(node, "serial");
848 	if (line < 0) {
849 		if (IS_ENABLED(CONFIG_LANTIQ)) {
850 			if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
851 				line = 0;
852 			else
853 				line = 1;
854 		} else {
855 			dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
856 				line);
857 			return line;
858 		}
859 	}
860 
861 	if (lqasc_port[line]) {
862 		dev_err(&pdev->dev, "port %d already allocated\n", line);
863 		return -EBUSY;
864 	}
865 
866 	port->iotype	= SERIAL_IO_MEM;
867 	port->flags	= UPF_BOOT_AUTOCONF | UPF_IOREMAP;
868 	port->ops	= &lqasc_pops;
869 	port->fifosize	= 16;
870 	port->type	= PORT_LTQ_ASC,
871 	port->line	= line;
872 	port->dev	= &pdev->dev;
873 	/* unused, just to be backward-compatible */
874 	port->mapbase	= mmres->start;
875 
876 	if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
877 		ltq_port->freqclk = clk_get_fpi();
878 	else
879 		ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
880 
881 
882 	if (IS_ERR(ltq_port->freqclk)) {
883 		pr_err("failed to get fpi clk\n");
884 		return -ENOENT;
885 	}
886 
887 	/* not all asc ports have clock gates, lets ignore the return code */
888 	if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
889 		ltq_port->clk = clk_get(&pdev->dev, NULL);
890 	else
891 		ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
892 
893 	spin_lock_init(&ltq_port->lock);
894 	lqasc_port[line] = ltq_port;
895 	platform_set_drvdata(pdev, ltq_port);
896 
897 	ret = uart_add_one_port(&lqasc_reg, port);
898 
899 	return ret;
900 }
901 
902 static const struct ltq_soc_data soc_data_lantiq = {
903 	.fetch_irq = fetch_irq_lantiq,
904 	.request_irq = request_irq_lantiq,
905 	.free_irq = free_irq_lantiq,
906 };
907 
908 static const struct ltq_soc_data soc_data_intel = {
909 	.fetch_irq = fetch_irq_intel,
910 	.request_irq = request_irq_intel,
911 	.free_irq = free_irq_intel,
912 };
913 
914 static const struct of_device_id ltq_asc_match[] = {
915 	{ .compatible = "lantiq,asc", .data = &soc_data_lantiq },
916 	{ .compatible = "intel,lgm-asc", .data = &soc_data_intel },
917 	{},
918 };
919 
920 static struct platform_driver lqasc_driver = {
921 	.driver		= {
922 		.name	= DRVNAME,
923 		.of_match_table = ltq_asc_match,
924 	},
925 };
926 
927 static int __init
928 init_lqasc(void)
929 {
930 	int ret;
931 
932 	ret = uart_register_driver(&lqasc_reg);
933 	if (ret != 0)
934 		return ret;
935 
936 	ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
937 	if (ret != 0)
938 		uart_unregister_driver(&lqasc_reg);
939 
940 	return ret;
941 }
942 device_initcall(init_lqasc);
943