1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 4 * 5 * Copyright (C) 2004 Infineon IFAP DC COM CPE 6 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 7 * Copyright (C) 2007 John Crispin <john@phrozen.org> 8 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/device.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/lantiq.h> 19 #include <linux/module.h> 20 #include <linux/of_platform.h> 21 #include <linux/serial.h> 22 #include <linux/serial_core.h> 23 #include <linux/slab.h> 24 #include <linux/sysrq.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 28 #define PORT_LTQ_ASC 111 29 #define MAXPORTS 2 30 #define UART_DUMMY_UER_RX 1 31 #define DRVNAME "lantiq,asc" 32 #ifdef __BIG_ENDIAN 33 #define LTQ_ASC_TBUF (0x0020 + 3) 34 #define LTQ_ASC_RBUF (0x0024 + 3) 35 #else 36 #define LTQ_ASC_TBUF 0x0020 37 #define LTQ_ASC_RBUF 0x0024 38 #endif 39 #define LTQ_ASC_FSTAT 0x0048 40 #define LTQ_ASC_WHBSTATE 0x0018 41 #define LTQ_ASC_STATE 0x0014 42 #define LTQ_ASC_IRNCR 0x00F8 43 #define LTQ_ASC_CLC 0x0000 44 #define LTQ_ASC_ID 0x0008 45 #define LTQ_ASC_PISEL 0x0004 46 #define LTQ_ASC_TXFCON 0x0044 47 #define LTQ_ASC_RXFCON 0x0040 48 #define LTQ_ASC_CON 0x0010 49 #define LTQ_ASC_BG 0x0050 50 #define LTQ_ASC_IRNREN 0x00F4 51 52 #define ASC_IRNREN_TX 0x1 53 #define ASC_IRNREN_RX 0x2 54 #define ASC_IRNREN_ERR 0x4 55 #define ASC_IRNREN_TX_BUF 0x8 56 #define ASC_IRNCR_TIR 0x1 57 #define ASC_IRNCR_RIR 0x2 58 #define ASC_IRNCR_EIR 0x4 59 #define ASC_IRNCR_MASK GENMASK(2, 0) 60 61 #define ASCOPT_CSIZE 0x3 62 #define TXFIFO_FL 1 63 #define RXFIFO_FL 1 64 #define ASCCLC_DISS 0x2 65 #define ASCCLC_RMCMASK 0x0000FF00 66 #define ASCCLC_RMCOFFSET 8 67 #define ASCCON_M_8ASYNC 0x0 68 #define ASCCON_M_7ASYNC 0x2 69 #define ASCCON_ODD 0x00000020 70 #define ASCCON_STP 0x00000080 71 #define ASCCON_BRS 0x00000100 72 #define ASCCON_FDE 0x00000200 73 #define ASCCON_R 0x00008000 74 #define ASCCON_FEN 0x00020000 75 #define ASCCON_ROEN 0x00080000 76 #define ASCCON_TOEN 0x00100000 77 #define ASCSTATE_PE 0x00010000 78 #define ASCSTATE_FE 0x00020000 79 #define ASCSTATE_ROE 0x00080000 80 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) 81 #define ASCWHBSTATE_CLRREN 0x00000001 82 #define ASCWHBSTATE_SETREN 0x00000002 83 #define ASCWHBSTATE_CLRPE 0x00000004 84 #define ASCWHBSTATE_CLRFE 0x00000008 85 #define ASCWHBSTATE_CLRROE 0x00000020 86 #define ASCTXFCON_TXFEN 0x0001 87 #define ASCTXFCON_TXFFLU 0x0002 88 #define ASCTXFCON_TXFITLMASK 0x3F00 89 #define ASCTXFCON_TXFITLOFF 8 90 #define ASCRXFCON_RXFEN 0x0001 91 #define ASCRXFCON_RXFFLU 0x0002 92 #define ASCRXFCON_RXFITLMASK 0x3F00 93 #define ASCRXFCON_RXFITLOFF 8 94 #define ASCFSTAT_RXFFLMASK 0x003F 95 #define ASCFSTAT_TXFFLMASK 0x3F00 96 #define ASCFSTAT_TXFREEMASK 0x3F000000 97 98 static void lqasc_tx_chars(struct uart_port *port); 99 static struct ltq_uart_port *lqasc_port[MAXPORTS]; 100 static struct uart_driver lqasc_reg; 101 102 struct ltq_soc_data { 103 int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port); 104 int (*request_irq)(struct uart_port *port); 105 void (*free_irq)(struct uart_port *port); 106 }; 107 108 struct ltq_uart_port { 109 struct uart_port port; 110 /* clock used to derive divider */ 111 struct clk *freqclk; 112 /* clock gating of the ASC core */ 113 struct clk *clk; 114 unsigned int tx_irq; 115 unsigned int rx_irq; 116 unsigned int err_irq; 117 unsigned int common_irq; 118 spinlock_t lock; /* exclusive access for multi core */ 119 120 const struct ltq_soc_data *soc; 121 }; 122 123 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) 124 { 125 u32 tmp = __raw_readl(reg); 126 127 __raw_writel((tmp & ~clear) | set, reg); 128 } 129 130 static inline struct 131 ltq_uart_port *to_ltq_uart_port(struct uart_port *port) 132 { 133 return container_of(port, struct ltq_uart_port, port); 134 } 135 136 static void 137 lqasc_stop_tx(struct uart_port *port) 138 { 139 return; 140 } 141 142 static bool lqasc_tx_ready(struct uart_port *port) 143 { 144 u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT); 145 146 return FIELD_GET(ASCFSTAT_TXFREEMASK, fstat); 147 } 148 149 static void 150 lqasc_start_tx(struct uart_port *port) 151 { 152 unsigned long flags; 153 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 154 155 spin_lock_irqsave(<q_port->lock, flags); 156 lqasc_tx_chars(port); 157 spin_unlock_irqrestore(<q_port->lock, flags); 158 return; 159 } 160 161 static void 162 lqasc_stop_rx(struct uart_port *port) 163 { 164 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 165 } 166 167 static int 168 lqasc_rx_chars(struct uart_port *port) 169 { 170 struct tty_port *tport = &port->state->port; 171 unsigned int ch = 0, rsr = 0, fifocnt; 172 173 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 174 ASCFSTAT_RXFFLMASK; 175 while (fifocnt--) { 176 u8 flag = TTY_NORMAL; 177 ch = readb(port->membase + LTQ_ASC_RBUF); 178 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) 179 & ASCSTATE_ANY) | UART_DUMMY_UER_RX; 180 tty_flip_buffer_push(tport); 181 port->icount.rx++; 182 183 /* 184 * Note that the error handling code is 185 * out of the main execution path 186 */ 187 if (rsr & ASCSTATE_ANY) { 188 if (rsr & ASCSTATE_PE) { 189 port->icount.parity++; 190 asc_update_bits(0, ASCWHBSTATE_CLRPE, 191 port->membase + LTQ_ASC_WHBSTATE); 192 } else if (rsr & ASCSTATE_FE) { 193 port->icount.frame++; 194 asc_update_bits(0, ASCWHBSTATE_CLRFE, 195 port->membase + LTQ_ASC_WHBSTATE); 196 } 197 if (rsr & ASCSTATE_ROE) { 198 port->icount.overrun++; 199 asc_update_bits(0, ASCWHBSTATE_CLRROE, 200 port->membase + LTQ_ASC_WHBSTATE); 201 } 202 203 rsr &= port->read_status_mask; 204 205 if (rsr & ASCSTATE_PE) 206 flag = TTY_PARITY; 207 else if (rsr & ASCSTATE_FE) 208 flag = TTY_FRAME; 209 } 210 211 if ((rsr & port->ignore_status_mask) == 0) 212 tty_insert_flip_char(tport, ch, flag); 213 214 if (rsr & ASCSTATE_ROE) 215 /* 216 * Overrun is special, since it's reported 217 * immediately, and doesn't affect the current 218 * character 219 */ 220 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 221 } 222 223 if (ch != 0) 224 tty_flip_buffer_push(tport); 225 226 return 0; 227 } 228 229 static void 230 lqasc_tx_chars(struct uart_port *port) 231 { 232 struct circ_buf *xmit = &port->state->xmit; 233 if (uart_tx_stopped(port)) { 234 lqasc_stop_tx(port); 235 return; 236 } 237 238 while (lqasc_tx_ready(port)) { 239 if (port->x_char) { 240 writeb(port->x_char, port->membase + LTQ_ASC_TBUF); 241 port->icount.tx++; 242 port->x_char = 0; 243 continue; 244 } 245 246 if (uart_circ_empty(xmit)) 247 break; 248 249 writeb(port->state->xmit.buf[port->state->xmit.tail], 250 port->membase + LTQ_ASC_TBUF); 251 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 252 port->icount.tx++; 253 } 254 255 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 256 uart_write_wakeup(port); 257 } 258 259 static irqreturn_t 260 lqasc_tx_int(int irq, void *_port) 261 { 262 unsigned long flags; 263 struct uart_port *port = (struct uart_port *)_port; 264 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 265 266 spin_lock_irqsave(<q_port->lock, flags); 267 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); 268 spin_unlock_irqrestore(<q_port->lock, flags); 269 lqasc_start_tx(port); 270 return IRQ_HANDLED; 271 } 272 273 static irqreturn_t 274 lqasc_err_int(int irq, void *_port) 275 { 276 unsigned long flags; 277 struct uart_port *port = (struct uart_port *)_port; 278 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 279 280 spin_lock_irqsave(<q_port->lock, flags); 281 /* clear any pending interrupts */ 282 asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | 283 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); 284 spin_unlock_irqrestore(<q_port->lock, flags); 285 return IRQ_HANDLED; 286 } 287 288 static irqreturn_t 289 lqasc_rx_int(int irq, void *_port) 290 { 291 unsigned long flags; 292 struct uart_port *port = (struct uart_port *)_port; 293 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 294 295 spin_lock_irqsave(<q_port->lock, flags); 296 __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); 297 lqasc_rx_chars(port); 298 spin_unlock_irqrestore(<q_port->lock, flags); 299 return IRQ_HANDLED; 300 } 301 302 static irqreturn_t lqasc_irq(int irq, void *p) 303 { 304 unsigned long flags; 305 u32 stat; 306 struct uart_port *port = p; 307 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 308 309 spin_lock_irqsave(<q_port->lock, flags); 310 stat = readl(port->membase + LTQ_ASC_IRNCR); 311 spin_unlock_irqrestore(<q_port->lock, flags); 312 if (!(stat & ASC_IRNCR_MASK)) 313 return IRQ_NONE; 314 315 if (stat & ASC_IRNCR_TIR) 316 lqasc_tx_int(irq, p); 317 318 if (stat & ASC_IRNCR_RIR) 319 lqasc_rx_int(irq, p); 320 321 if (stat & ASC_IRNCR_EIR) 322 lqasc_err_int(irq, p); 323 324 return IRQ_HANDLED; 325 } 326 327 static unsigned int 328 lqasc_tx_empty(struct uart_port *port) 329 { 330 int status; 331 status = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 332 ASCFSTAT_TXFFLMASK; 333 return status ? 0 : TIOCSER_TEMT; 334 } 335 336 static unsigned int 337 lqasc_get_mctrl(struct uart_port *port) 338 { 339 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; 340 } 341 342 static void 343 lqasc_set_mctrl(struct uart_port *port, u_int mctrl) 344 { 345 } 346 347 static void 348 lqasc_break_ctl(struct uart_port *port, int break_state) 349 { 350 } 351 352 static int 353 lqasc_startup(struct uart_port *port) 354 { 355 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 356 int retval; 357 unsigned long flags; 358 359 if (!IS_ERR(ltq_port->clk)) 360 clk_prepare_enable(ltq_port->clk); 361 port->uartclk = clk_get_rate(ltq_port->freqclk); 362 363 spin_lock_irqsave(<q_port->lock, flags); 364 asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), 365 port->membase + LTQ_ASC_CLC); 366 367 __raw_writel(0, port->membase + LTQ_ASC_PISEL); 368 __raw_writel( 369 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | 370 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, 371 port->membase + LTQ_ASC_TXFCON); 372 __raw_writel( 373 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) 374 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, 375 port->membase + LTQ_ASC_RXFCON); 376 /* make sure other settings are written to hardware before 377 * setting enable bits 378 */ 379 wmb(); 380 asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | 381 ASCCON_ROEN, port->membase + LTQ_ASC_CON); 382 383 spin_unlock_irqrestore(<q_port->lock, flags); 384 385 retval = ltq_port->soc->request_irq(port); 386 if (retval) 387 return retval; 388 389 __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, 390 port->membase + LTQ_ASC_IRNREN); 391 return retval; 392 } 393 394 static void 395 lqasc_shutdown(struct uart_port *port) 396 { 397 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 398 unsigned long flags; 399 400 ltq_port->soc->free_irq(port); 401 402 spin_lock_irqsave(<q_port->lock, flags); 403 __raw_writel(0, port->membase + LTQ_ASC_CON); 404 asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, 405 port->membase + LTQ_ASC_RXFCON); 406 asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, 407 port->membase + LTQ_ASC_TXFCON); 408 spin_unlock_irqrestore(<q_port->lock, flags); 409 if (!IS_ERR(ltq_port->clk)) 410 clk_disable_unprepare(ltq_port->clk); 411 } 412 413 static void 414 lqasc_set_termios(struct uart_port *port, struct ktermios *new, 415 const struct ktermios *old) 416 { 417 unsigned int cflag; 418 unsigned int iflag; 419 unsigned int divisor; 420 unsigned int baud; 421 unsigned int con = 0; 422 unsigned long flags; 423 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 424 425 cflag = new->c_cflag; 426 iflag = new->c_iflag; 427 428 switch (cflag & CSIZE) { 429 case CS7: 430 con = ASCCON_M_7ASYNC; 431 break; 432 433 case CS5: 434 case CS6: 435 default: 436 new->c_cflag &= ~ CSIZE; 437 new->c_cflag |= CS8; 438 con = ASCCON_M_8ASYNC; 439 break; 440 } 441 442 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 443 444 if (cflag & CSTOPB) 445 con |= ASCCON_STP; 446 447 if (cflag & PARENB) { 448 if (!(cflag & PARODD)) 449 con &= ~ASCCON_ODD; 450 else 451 con |= ASCCON_ODD; 452 } 453 454 port->read_status_mask = ASCSTATE_ROE; 455 if (iflag & INPCK) 456 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 457 458 port->ignore_status_mask = 0; 459 if (iflag & IGNPAR) 460 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 461 462 if (iflag & IGNBRK) { 463 /* 464 * If we're ignoring parity and break indicators, 465 * ignore overruns too (for real raw support). 466 */ 467 if (iflag & IGNPAR) 468 port->ignore_status_mask |= ASCSTATE_ROE; 469 } 470 471 if ((cflag & CREAD) == 0) 472 port->ignore_status_mask |= UART_DUMMY_UER_RX; 473 474 /* set error signals - framing, parity and overrun, enable receiver */ 475 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; 476 477 spin_lock_irqsave(<q_port->lock, flags); 478 479 /* set up CON */ 480 asc_update_bits(0, con, port->membase + LTQ_ASC_CON); 481 482 /* Set baud rate - take a divider of 2 into account */ 483 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 484 divisor = uart_get_divisor(port, baud); 485 divisor = divisor / 2 - 1; 486 487 /* disable the baudrate generator */ 488 asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON); 489 490 /* make sure the fractional divider is off */ 491 asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); 492 493 /* set up to use divisor of 2 */ 494 asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); 495 496 /* now we can write the new baudrate into the register */ 497 __raw_writel(divisor, port->membase + LTQ_ASC_BG); 498 499 /* turn the baudrate generator back on */ 500 asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); 501 502 /* enable rx */ 503 __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); 504 505 spin_unlock_irqrestore(<q_port->lock, flags); 506 507 /* Don't rewrite B0 */ 508 if (tty_termios_baud_rate(new)) 509 tty_termios_encode_baud_rate(new, baud, baud); 510 511 uart_update_timeout(port, cflag, baud); 512 } 513 514 static const char* 515 lqasc_type(struct uart_port *port) 516 { 517 if (port->type == PORT_LTQ_ASC) 518 return DRVNAME; 519 else 520 return NULL; 521 } 522 523 static void 524 lqasc_release_port(struct uart_port *port) 525 { 526 struct platform_device *pdev = to_platform_device(port->dev); 527 528 if (port->flags & UPF_IOREMAP) { 529 devm_iounmap(&pdev->dev, port->membase); 530 port->membase = NULL; 531 } 532 } 533 534 static int 535 lqasc_request_port(struct uart_port *port) 536 { 537 struct platform_device *pdev = to_platform_device(port->dev); 538 struct resource *res; 539 int size; 540 541 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 542 if (!res) { 543 dev_err(&pdev->dev, "cannot obtain I/O memory region"); 544 return -ENODEV; 545 } 546 size = resource_size(res); 547 548 res = devm_request_mem_region(&pdev->dev, res->start, 549 size, dev_name(&pdev->dev)); 550 if (!res) { 551 dev_err(&pdev->dev, "cannot request I/O memory region"); 552 return -EBUSY; 553 } 554 555 if (port->flags & UPF_IOREMAP) { 556 port->membase = devm_ioremap(&pdev->dev, 557 port->mapbase, size); 558 if (port->membase == NULL) 559 return -ENOMEM; 560 } 561 return 0; 562 } 563 564 static void 565 lqasc_config_port(struct uart_port *port, int flags) 566 { 567 if (flags & UART_CONFIG_TYPE) { 568 port->type = PORT_LTQ_ASC; 569 lqasc_request_port(port); 570 } 571 } 572 573 static int 574 lqasc_verify_port(struct uart_port *port, 575 struct serial_struct *ser) 576 { 577 int ret = 0; 578 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) 579 ret = -EINVAL; 580 if (ser->irq < 0 || ser->irq >= NR_IRQS) 581 ret = -EINVAL; 582 if (ser->baud_base < 9600) 583 ret = -EINVAL; 584 return ret; 585 } 586 587 static const struct uart_ops lqasc_pops = { 588 .tx_empty = lqasc_tx_empty, 589 .set_mctrl = lqasc_set_mctrl, 590 .get_mctrl = lqasc_get_mctrl, 591 .stop_tx = lqasc_stop_tx, 592 .start_tx = lqasc_start_tx, 593 .stop_rx = lqasc_stop_rx, 594 .break_ctl = lqasc_break_ctl, 595 .startup = lqasc_startup, 596 .shutdown = lqasc_shutdown, 597 .set_termios = lqasc_set_termios, 598 .type = lqasc_type, 599 .release_port = lqasc_release_port, 600 .request_port = lqasc_request_port, 601 .config_port = lqasc_config_port, 602 .verify_port = lqasc_verify_port, 603 }; 604 605 #ifdef CONFIG_SERIAL_LANTIQ_CONSOLE 606 static void 607 lqasc_console_putchar(struct uart_port *port, unsigned char ch) 608 { 609 if (!port->membase) 610 return; 611 612 while (!lqasc_tx_ready(port)) 613 ; 614 615 writeb(ch, port->membase + LTQ_ASC_TBUF); 616 } 617 618 static void lqasc_serial_port_write(struct uart_port *port, const char *s, 619 u_int count) 620 { 621 uart_console_write(port, s, count, lqasc_console_putchar); 622 } 623 624 static void 625 lqasc_console_write(struct console *co, const char *s, u_int count) 626 { 627 struct ltq_uart_port *ltq_port; 628 unsigned long flags; 629 630 if (co->index >= MAXPORTS) 631 return; 632 633 ltq_port = lqasc_port[co->index]; 634 if (!ltq_port) 635 return; 636 637 spin_lock_irqsave(<q_port->lock, flags); 638 lqasc_serial_port_write(<q_port->port, s, count); 639 spin_unlock_irqrestore(<q_port->lock, flags); 640 } 641 642 static int __init 643 lqasc_console_setup(struct console *co, char *options) 644 { 645 struct ltq_uart_port *ltq_port; 646 struct uart_port *port; 647 int baud = 115200; 648 int bits = 8; 649 int parity = 'n'; 650 int flow = 'n'; 651 652 if (co->index >= MAXPORTS) 653 return -ENODEV; 654 655 ltq_port = lqasc_port[co->index]; 656 if (!ltq_port) 657 return -ENODEV; 658 659 port = <q_port->port; 660 661 if (!IS_ERR(ltq_port->clk)) 662 clk_prepare_enable(ltq_port->clk); 663 664 port->uartclk = clk_get_rate(ltq_port->freqclk); 665 666 if (options) 667 uart_parse_options(options, &baud, &parity, &bits, &flow); 668 return uart_set_options(port, co, baud, parity, bits, flow); 669 } 670 671 static struct console lqasc_console = { 672 .name = "ttyLTQ", 673 .write = lqasc_console_write, 674 .device = uart_console_device, 675 .setup = lqasc_console_setup, 676 .flags = CON_PRINTBUFFER, 677 .index = -1, 678 .data = &lqasc_reg, 679 }; 680 681 static int __init 682 lqasc_console_init(void) 683 { 684 register_console(&lqasc_console); 685 return 0; 686 } 687 console_initcall(lqasc_console_init); 688 689 static void lqasc_serial_early_console_write(struct console *co, 690 const char *s, 691 u_int count) 692 { 693 struct earlycon_device *dev = co->data; 694 695 lqasc_serial_port_write(&dev->port, s, count); 696 } 697 698 static int __init 699 lqasc_serial_early_console_setup(struct earlycon_device *device, 700 const char *opt) 701 { 702 if (!device->port.membase) 703 return -ENODEV; 704 705 device->con->write = lqasc_serial_early_console_write; 706 return 0; 707 } 708 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup); 709 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup); 710 711 #define LANTIQ_SERIAL_CONSOLE (&lqasc_console) 712 713 #else 714 715 #define LANTIQ_SERIAL_CONSOLE NULL 716 717 #endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */ 718 719 static struct uart_driver lqasc_reg = { 720 .owner = THIS_MODULE, 721 .driver_name = DRVNAME, 722 .dev_name = "ttyLTQ", 723 .major = 0, 724 .minor = 0, 725 .nr = MAXPORTS, 726 .cons = LANTIQ_SERIAL_CONSOLE, 727 }; 728 729 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port) 730 { 731 struct uart_port *port = <q_port->port; 732 struct platform_device *pdev = to_platform_device(dev); 733 int irq; 734 735 irq = platform_get_irq(pdev, 0); 736 if (irq < 0) 737 return irq; 738 ltq_port->tx_irq = irq; 739 irq = platform_get_irq(pdev, 1); 740 if (irq < 0) 741 return irq; 742 ltq_port->rx_irq = irq; 743 irq = platform_get_irq(pdev, 2); 744 if (irq < 0) 745 return irq; 746 ltq_port->err_irq = irq; 747 748 port->irq = ltq_port->tx_irq; 749 750 return 0; 751 } 752 753 static int request_irq_lantiq(struct uart_port *port) 754 { 755 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 756 int retval; 757 758 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, 759 0, "asc_tx", port); 760 if (retval) { 761 dev_err(port->dev, "failed to request asc_tx\n"); 762 return retval; 763 } 764 765 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, 766 0, "asc_rx", port); 767 if (retval) { 768 dev_err(port->dev, "failed to request asc_rx\n"); 769 goto err1; 770 } 771 772 retval = request_irq(ltq_port->err_irq, lqasc_err_int, 773 0, "asc_err", port); 774 if (retval) { 775 dev_err(port->dev, "failed to request asc_err\n"); 776 goto err2; 777 } 778 return 0; 779 780 err2: 781 free_irq(ltq_port->rx_irq, port); 782 err1: 783 free_irq(ltq_port->tx_irq, port); 784 return retval; 785 } 786 787 static void free_irq_lantiq(struct uart_port *port) 788 { 789 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 790 791 free_irq(ltq_port->tx_irq, port); 792 free_irq(ltq_port->rx_irq, port); 793 free_irq(ltq_port->err_irq, port); 794 } 795 796 static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port) 797 { 798 struct uart_port *port = <q_port->port; 799 int ret; 800 801 ret = platform_get_irq(to_platform_device(dev), 0); 802 if (ret < 0) { 803 dev_err(dev, "failed to fetch IRQ for serial port\n"); 804 return ret; 805 } 806 ltq_port->common_irq = ret; 807 port->irq = ret; 808 809 return 0; 810 } 811 812 static int request_irq_intel(struct uart_port *port) 813 { 814 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 815 int retval; 816 817 retval = request_irq(ltq_port->common_irq, lqasc_irq, 0, 818 "asc_irq", port); 819 if (retval) 820 dev_err(port->dev, "failed to request asc_irq\n"); 821 822 return retval; 823 } 824 825 static void free_irq_intel(struct uart_port *port) 826 { 827 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 828 829 free_irq(ltq_port->common_irq, port); 830 } 831 832 static int lqasc_probe(struct platform_device *pdev) 833 { 834 struct device_node *node = pdev->dev.of_node; 835 struct ltq_uart_port *ltq_port; 836 struct uart_port *port; 837 struct resource *mmres; 838 int line; 839 int ret; 840 841 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 842 if (!mmres) { 843 dev_err(&pdev->dev, 844 "failed to get memory for serial port\n"); 845 return -ENODEV; 846 } 847 848 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port), 849 GFP_KERNEL); 850 if (!ltq_port) 851 return -ENOMEM; 852 853 port = <q_port->port; 854 855 ltq_port->soc = of_device_get_match_data(&pdev->dev); 856 ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port); 857 if (ret) 858 return ret; 859 860 /* get serial id */ 861 line = of_alias_get_id(node, "serial"); 862 if (line < 0) { 863 if (IS_ENABLED(CONFIG_LANTIQ)) { 864 if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC)) 865 line = 0; 866 else 867 line = 1; 868 } else { 869 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 870 line); 871 return line; 872 } 873 } 874 875 if (lqasc_port[line]) { 876 dev_err(&pdev->dev, "port %d already allocated\n", line); 877 return -EBUSY; 878 } 879 880 port->iotype = SERIAL_IO_MEM; 881 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 882 port->ops = &lqasc_pops; 883 port->fifosize = 16; 884 port->type = PORT_LTQ_ASC; 885 port->line = line; 886 port->dev = &pdev->dev; 887 /* unused, just to be backward-compatible */ 888 port->mapbase = mmres->start; 889 890 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 891 ltq_port->freqclk = clk_get_fpi(); 892 else 893 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq"); 894 895 896 if (IS_ERR(ltq_port->freqclk)) { 897 pr_err("failed to get fpi clk\n"); 898 return -ENOENT; 899 } 900 901 /* not all asc ports have clock gates, lets ignore the return code */ 902 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 903 ltq_port->clk = clk_get(&pdev->dev, NULL); 904 else 905 ltq_port->clk = devm_clk_get(&pdev->dev, "asc"); 906 907 spin_lock_init(<q_port->lock); 908 lqasc_port[line] = ltq_port; 909 platform_set_drvdata(pdev, ltq_port); 910 911 ret = uart_add_one_port(&lqasc_reg, port); 912 913 return ret; 914 } 915 916 static int lqasc_remove(struct platform_device *pdev) 917 { 918 struct uart_port *port = platform_get_drvdata(pdev); 919 920 return uart_remove_one_port(&lqasc_reg, port); 921 } 922 923 static const struct ltq_soc_data soc_data_lantiq = { 924 .fetch_irq = fetch_irq_lantiq, 925 .request_irq = request_irq_lantiq, 926 .free_irq = free_irq_lantiq, 927 }; 928 929 static const struct ltq_soc_data soc_data_intel = { 930 .fetch_irq = fetch_irq_intel, 931 .request_irq = request_irq_intel, 932 .free_irq = free_irq_intel, 933 }; 934 935 static const struct of_device_id ltq_asc_match[] = { 936 { .compatible = "lantiq,asc", .data = &soc_data_lantiq }, 937 { .compatible = "intel,lgm-asc", .data = &soc_data_intel }, 938 {}, 939 }; 940 MODULE_DEVICE_TABLE(of, ltq_asc_match); 941 942 static struct platform_driver lqasc_driver = { 943 .probe = lqasc_probe, 944 .remove = lqasc_remove, 945 .driver = { 946 .name = DRVNAME, 947 .of_match_table = ltq_asc_match, 948 }, 949 }; 950 951 static int __init 952 init_lqasc(void) 953 { 954 int ret; 955 956 ret = uart_register_driver(&lqasc_reg); 957 if (ret != 0) 958 return ret; 959 960 ret = platform_driver_register(&lqasc_driver); 961 if (ret != 0) 962 uart_unregister_driver(&lqasc_reg); 963 964 return ret; 965 } 966 967 static void __exit exit_lqasc(void) 968 { 969 platform_driver_unregister(&lqasc_driver); 970 uart_unregister_driver(&lqasc_reg); 971 } 972 973 module_init(init_lqasc); 974 module_exit(exit_lqasc); 975 976 MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs"); 977 MODULE_LICENSE("GPL v2"); 978