1 /************************************************************************ 2 * Copyright 2003 Digi International (www.digi.com) 3 * 4 * Copyright (C) 2004 IBM Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 14 * PURPOSE. See the GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston, 19 * MA 02111-1307, USA. 20 * 21 * Contact Information: 22 * Scott H Kilau <Scott_Kilau@digi.com> 23 * Wendy Xiong <wendyx@us.ibm.com> 24 * 25 ***********************************************************************/ 26 #include <linux/delay.h> /* For udelay */ 27 #include <linux/serial_reg.h> /* For the various UART offsets */ 28 #include <linux/tty.h> 29 #include <linux/pci.h> 30 #include <asm/io.h> 31 32 #include "jsm.h" /* Driver main header file */ 33 34 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; 35 36 /* 37 * This function allows calls to ensure that all outstanding 38 * PCI writes have been completed, by doing a PCI read against 39 * a non-destructive, read-only location on the Neo card. 40 * 41 * In this case, we are reading the DVID (Read-only Device Identification) 42 * value of the Neo card. 43 */ 44 static inline void neo_pci_posting_flush(struct jsm_board *bd) 45 { 46 readb(bd->re_map_membase + 0x8D); 47 } 48 49 static void neo_set_cts_flow_control(struct jsm_channel *ch) 50 { 51 u8 ier, efr; 52 ier = readb(&ch->ch_neo_uart->ier); 53 efr = readb(&ch->ch_neo_uart->efr); 54 55 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); 56 57 /* Turn on auto CTS flow control */ 58 ier |= (UART_17158_IER_CTSDSR); 59 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR); 60 61 /* Turn off auto Xon flow control */ 62 efr &= ~(UART_17158_EFR_IXON); 63 64 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 65 writeb(0, &ch->ch_neo_uart->efr); 66 67 /* Turn on UART enhanced bits */ 68 writeb(efr, &ch->ch_neo_uart->efr); 69 70 /* Turn on table D, with 8 char hi/low watermarks */ 71 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 72 73 /* Feed the UART our trigger levels */ 74 writeb(8, &ch->ch_neo_uart->tfifo); 75 ch->ch_t_tlevel = 8; 76 77 writeb(ier, &ch->ch_neo_uart->ier); 78 } 79 80 static void neo_set_rts_flow_control(struct jsm_channel *ch) 81 { 82 u8 ier, efr; 83 ier = readb(&ch->ch_neo_uart->ier); 84 efr = readb(&ch->ch_neo_uart->efr); 85 86 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); 87 88 /* Turn on auto RTS flow control */ 89 ier |= (UART_17158_IER_RTSDTR); 90 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR); 91 92 /* Turn off auto Xoff flow control */ 93 ier &= ~(UART_17158_IER_XOFF); 94 efr &= ~(UART_17158_EFR_IXOFF); 95 96 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 97 writeb(0, &ch->ch_neo_uart->efr); 98 99 /* Turn on UART enhanced bits */ 100 writeb(efr, &ch->ch_neo_uart->efr); 101 102 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 103 ch->ch_r_watermark = 4; 104 105 writeb(56, &ch->ch_neo_uart->rfifo); 106 ch->ch_r_tlevel = 56; 107 108 writeb(ier, &ch->ch_neo_uart->ier); 109 110 /* 111 * From the Neo UART spec sheet: 112 * The auto RTS/DTR function must be started by asserting 113 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after 114 * it is enabled. 115 */ 116 ch->ch_mostat |= (UART_MCR_RTS); 117 } 118 119 120 static void neo_set_ixon_flow_control(struct jsm_channel *ch) 121 { 122 u8 ier, efr; 123 ier = readb(&ch->ch_neo_uart->ier); 124 efr = readb(&ch->ch_neo_uart->efr); 125 126 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); 127 128 /* Turn off auto CTS flow control */ 129 ier &= ~(UART_17158_IER_CTSDSR); 130 efr &= ~(UART_17158_EFR_CTSDSR); 131 132 /* Turn on auto Xon flow control */ 133 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON); 134 135 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 136 writeb(0, &ch->ch_neo_uart->efr); 137 138 /* Turn on UART enhanced bits */ 139 writeb(efr, &ch->ch_neo_uart->efr); 140 141 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 142 ch->ch_r_watermark = 4; 143 144 writeb(32, &ch->ch_neo_uart->rfifo); 145 ch->ch_r_tlevel = 32; 146 147 /* Tell UART what start/stop chars it should be looking for */ 148 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 149 writeb(0, &ch->ch_neo_uart->xonchar2); 150 151 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 152 writeb(0, &ch->ch_neo_uart->xoffchar2); 153 154 writeb(ier, &ch->ch_neo_uart->ier); 155 } 156 157 static void neo_set_ixoff_flow_control(struct jsm_channel *ch) 158 { 159 u8 ier, efr; 160 ier = readb(&ch->ch_neo_uart->ier); 161 efr = readb(&ch->ch_neo_uart->efr); 162 163 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); 164 165 /* Turn off auto RTS flow control */ 166 ier &= ~(UART_17158_IER_RTSDTR); 167 efr &= ~(UART_17158_EFR_RTSDTR); 168 169 /* Turn on auto Xoff flow control */ 170 ier |= (UART_17158_IER_XOFF); 171 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 172 173 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 174 writeb(0, &ch->ch_neo_uart->efr); 175 176 /* Turn on UART enhanced bits */ 177 writeb(efr, &ch->ch_neo_uart->efr); 178 179 /* Turn on table D, with 8 char hi/low watermarks */ 180 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 181 182 writeb(8, &ch->ch_neo_uart->tfifo); 183 ch->ch_t_tlevel = 8; 184 185 /* Tell UART what start/stop chars it should be looking for */ 186 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 187 writeb(0, &ch->ch_neo_uart->xonchar2); 188 189 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 190 writeb(0, &ch->ch_neo_uart->xoffchar2); 191 192 writeb(ier, &ch->ch_neo_uart->ier); 193 } 194 195 static void neo_set_no_input_flow_control(struct jsm_channel *ch) 196 { 197 u8 ier, efr; 198 ier = readb(&ch->ch_neo_uart->ier); 199 efr = readb(&ch->ch_neo_uart->efr); 200 201 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); 202 203 /* Turn off auto RTS flow control */ 204 ier &= ~(UART_17158_IER_RTSDTR); 205 efr &= ~(UART_17158_EFR_RTSDTR); 206 207 /* Turn off auto Xoff flow control */ 208 ier &= ~(UART_17158_IER_XOFF); 209 if (ch->ch_c_iflag & IXON) 210 efr &= ~(UART_17158_EFR_IXOFF); 211 else 212 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 213 214 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 215 writeb(0, &ch->ch_neo_uart->efr); 216 217 /* Turn on UART enhanced bits */ 218 writeb(efr, &ch->ch_neo_uart->efr); 219 220 /* Turn on table D, with 8 char hi/low watermarks */ 221 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 222 223 ch->ch_r_watermark = 0; 224 225 writeb(16, &ch->ch_neo_uart->tfifo); 226 ch->ch_t_tlevel = 16; 227 228 writeb(16, &ch->ch_neo_uart->rfifo); 229 ch->ch_r_tlevel = 16; 230 231 writeb(ier, &ch->ch_neo_uart->ier); 232 } 233 234 static void neo_set_no_output_flow_control(struct jsm_channel *ch) 235 { 236 u8 ier, efr; 237 ier = readb(&ch->ch_neo_uart->ier); 238 efr = readb(&ch->ch_neo_uart->efr); 239 240 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); 241 242 /* Turn off auto CTS flow control */ 243 ier &= ~(UART_17158_IER_CTSDSR); 244 efr &= ~(UART_17158_EFR_CTSDSR); 245 246 /* Turn off auto Xon flow control */ 247 if (ch->ch_c_iflag & IXOFF) 248 efr &= ~(UART_17158_EFR_IXON); 249 else 250 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON); 251 252 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 253 writeb(0, &ch->ch_neo_uart->efr); 254 255 /* Turn on UART enhanced bits */ 256 writeb(efr, &ch->ch_neo_uart->efr); 257 258 /* Turn on table D, with 8 char hi/low watermarks */ 259 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 260 261 ch->ch_r_watermark = 0; 262 263 writeb(16, &ch->ch_neo_uart->tfifo); 264 ch->ch_t_tlevel = 16; 265 266 writeb(16, &ch->ch_neo_uart->rfifo); 267 ch->ch_r_tlevel = 16; 268 269 writeb(ier, &ch->ch_neo_uart->ier); 270 } 271 272 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch) 273 { 274 275 /* if hardware flow control is set, then skip this whole thing */ 276 if (ch->ch_c_cflag & CRTSCTS) 277 return; 278 279 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "start\n"); 280 281 /* Tell UART what start/stop chars it should be looking for */ 282 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 283 writeb(0, &ch->ch_neo_uart->xonchar2); 284 285 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 286 writeb(0, &ch->ch_neo_uart->xoffchar2); 287 } 288 289 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch) 290 { 291 int qleft = 0; 292 u8 linestatus = 0; 293 u8 error_mask = 0; 294 int n = 0; 295 int total = 0; 296 u16 head; 297 u16 tail; 298 299 if (!ch) 300 return; 301 302 /* cache head and tail of queue */ 303 head = ch->ch_r_head & RQUEUEMASK; 304 tail = ch->ch_r_tail & RQUEUEMASK; 305 306 /* Get our cached LSR */ 307 linestatus = ch->ch_cached_lsr; 308 ch->ch_cached_lsr = 0; 309 310 /* Store how much space we have left in the queue */ 311 if ((qleft = tail - head - 1) < 0) 312 qleft += RQUEUEMASK + 1; 313 314 /* 315 * If the UART is not in FIFO mode, force the FIFO copy to 316 * NOT be run, by setting total to 0. 317 * 318 * On the other hand, if the UART IS in FIFO mode, then ask 319 * the UART to give us an approximation of data it has RX'ed. 320 */ 321 if (!(ch->ch_flags & CH_FIFO_ENABLED)) 322 total = 0; 323 else { 324 total = readb(&ch->ch_neo_uart->rfifo); 325 326 /* 327 * EXAR chip bug - RX FIFO COUNT - Fudge factor. 328 * 329 * This resolves a problem/bug with the Exar chip that sometimes 330 * returns a bogus value in the rfifo register. 331 * The count can be any where from 0-3 bytes "off". 332 * Bizarre, but true. 333 */ 334 total -= 3; 335 } 336 337 /* 338 * Finally, bound the copy to make sure we don't overflow 339 * our own queue... 340 * The byte by byte copy loop below this loop this will 341 * deal with the queue overflow possibility. 342 */ 343 total = min(total, qleft); 344 345 while (total > 0) { 346 /* 347 * Grab the linestatus register, we need to check 348 * to see if there are any errors in the FIFO. 349 */ 350 linestatus = readb(&ch->ch_neo_uart->lsr); 351 352 /* 353 * Break out if there is a FIFO error somewhere. 354 * This will allow us to go byte by byte down below, 355 * finding the exact location of the error. 356 */ 357 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 358 break; 359 360 /* Make sure we don't go over the end of our queue */ 361 n = min(((u32) total), (RQUEUESIZE - (u32) head)); 362 363 /* 364 * Cut down n even further if needed, this is to fix 365 * a problem with memcpy_fromio() with the Neo on the 366 * IBM pSeries platform. 367 * 15 bytes max appears to be the magic number. 368 */ 369 n = min((u32) n, (u32) 12); 370 371 /* 372 * Since we are grabbing the linestatus register, which 373 * will reset some bits after our read, we need to ensure 374 * we don't miss our TX FIFO emptys. 375 */ 376 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) 377 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 378 379 linestatus = 0; 380 381 /* Copy data from uart to the queue */ 382 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); 383 /* 384 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed 385 * that all the data currently in the FIFO is free of 386 * breaks and parity/frame/orun errors. 387 */ 388 memset(ch->ch_equeue + head, 0, n); 389 390 /* Add to and flip head if needed */ 391 head = (head + n) & RQUEUEMASK; 392 total -= n; 393 qleft -= n; 394 ch->ch_rxcount += n; 395 } 396 397 /* 398 * Create a mask to determine whether we should 399 * insert the character (if any) into our queue. 400 */ 401 if (ch->ch_c_iflag & IGNBRK) 402 error_mask |= UART_LSR_BI; 403 404 /* 405 * Now cleanup any leftover bytes still in the UART. 406 * Also deal with any possible queue overflow here as well. 407 */ 408 while (1) { 409 410 /* 411 * Its possible we have a linestatus from the loop above 412 * this, so we "OR" on any extra bits. 413 */ 414 linestatus |= readb(&ch->ch_neo_uart->lsr); 415 416 /* 417 * If the chip tells us there is no more data pending to 418 * be read, we can then leave. 419 * But before we do, cache the linestatus, just in case. 420 */ 421 if (!(linestatus & UART_LSR_DR)) { 422 ch->ch_cached_lsr = linestatus; 423 break; 424 } 425 426 /* No need to store this bit */ 427 linestatus &= ~UART_LSR_DR; 428 429 /* 430 * Since we are grabbing the linestatus register, which 431 * will reset some bits after our read, we need to ensure 432 * we don't miss our TX FIFO emptys. 433 */ 434 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { 435 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); 436 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 437 } 438 439 /* 440 * Discard character if we are ignoring the error mask. 441 */ 442 if (linestatus & error_mask) { 443 u8 discard; 444 linestatus = 0; 445 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); 446 continue; 447 } 448 449 /* 450 * If our queue is full, we have no choice but to drop some data. 451 * The assumption is that HWFLOW or SWFLOW should have stopped 452 * things way way before we got to this point. 453 * 454 * I decided that I wanted to ditch the oldest data first, 455 * I hope thats okay with everyone? Yes? Good. 456 */ 457 while (qleft < 1) { 458 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, 459 "Queue full, dropping DATA:%x LSR:%x\n", 460 ch->ch_rqueue[tail], ch->ch_equeue[tail]); 461 462 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; 463 ch->ch_err_overrun++; 464 qleft++; 465 } 466 467 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); 468 ch->ch_equeue[head] = (u8) linestatus; 469 470 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, 471 "DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]); 472 473 /* Ditch any remaining linestatus value. */ 474 linestatus = 0; 475 476 /* Add to and flip head if needed */ 477 head = (head + 1) & RQUEUEMASK; 478 479 qleft--; 480 ch->ch_rxcount++; 481 } 482 483 /* 484 * Write new final heads to channel structure. 485 */ 486 ch->ch_r_head = head & RQUEUEMASK; 487 ch->ch_e_head = head & EQUEUEMASK; 488 jsm_input(ch); 489 } 490 491 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch) 492 { 493 u16 head; 494 u16 tail; 495 int n; 496 int s; 497 int qlen; 498 u32 len_written = 0; 499 500 if (!ch) 501 return; 502 503 /* No data to write to the UART */ 504 if (ch->ch_w_tail == ch->ch_w_head) 505 return; 506 507 /* If port is "stopped", don't send any data to the UART */ 508 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) 509 return; 510 /* 511 * If FIFOs are disabled. Send data directly to txrx register 512 */ 513 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { 514 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); 515 516 ch->ch_cached_lsr |= lsrbits; 517 if (ch->ch_cached_lsr & UART_LSR_THRE) { 518 ch->ch_cached_lsr &= ~(UART_LSR_THRE); 519 520 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx); 521 jsm_printk(WRITE, INFO, &ch->ch_bd->pci_dev, 522 "Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]); 523 ch->ch_w_tail++; 524 ch->ch_w_tail &= WQUEUEMASK; 525 ch->ch_txcount++; 526 } 527 return; 528 } 529 530 /* 531 * We have to do it this way, because of the EXAR TXFIFO count bug. 532 */ 533 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 534 return; 535 536 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 537 538 /* cache head and tail of queue */ 539 head = ch->ch_w_head & WQUEUEMASK; 540 tail = ch->ch_w_tail & WQUEUEMASK; 541 qlen = (head - tail) & WQUEUEMASK; 542 543 /* Find minimum of the FIFO space, versus queue length */ 544 n = min(n, qlen); 545 546 while (n > 0) { 547 548 s = ((head >= tail) ? head : WQUEUESIZE) - tail; 549 s = min(s, n); 550 551 if (s <= 0) 552 break; 553 554 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s); 555 /* Add and flip queue if needed */ 556 tail = (tail + s) & WQUEUEMASK; 557 n -= s; 558 ch->ch_txcount += s; 559 len_written += s; 560 } 561 562 /* Update the final tail */ 563 ch->ch_w_tail = tail & WQUEUEMASK; 564 565 if (len_written >= ch->ch_t_tlevel) 566 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 567 568 if (!jsm_tty_write(&ch->uart_port)) 569 uart_write_wakeup(&ch->uart_port); 570 } 571 572 static void neo_parse_modem(struct jsm_channel *ch, u8 signals) 573 { 574 u8 msignals = signals; 575 576 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev, 577 "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals); 578 579 /* Scrub off lower bits. They signify delta's, which I don't care about */ 580 /* Keep DDCD and DDSR though */ 581 msignals &= 0xf8; 582 583 if (msignals & UART_MSR_DDCD) 584 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); 585 if (msignals & UART_MSR_DDSR) 586 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); 587 if (msignals & UART_MSR_DCD) 588 ch->ch_mistat |= UART_MSR_DCD; 589 else 590 ch->ch_mistat &= ~UART_MSR_DCD; 591 592 if (msignals & UART_MSR_DSR) 593 ch->ch_mistat |= UART_MSR_DSR; 594 else 595 ch->ch_mistat &= ~UART_MSR_DSR; 596 597 if (msignals & UART_MSR_RI) 598 ch->ch_mistat |= UART_MSR_RI; 599 else 600 ch->ch_mistat &= ~UART_MSR_RI; 601 602 if (msignals & UART_MSR_CTS) 603 ch->ch_mistat |= UART_MSR_CTS; 604 else 605 ch->ch_mistat &= ~UART_MSR_CTS; 606 607 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev, 608 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n", 609 ch->ch_portnum, 610 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), 611 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), 612 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), 613 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), 614 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), 615 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); 616 } 617 618 /* Make the UART raise any of the output signals we want up */ 619 static void neo_assert_modem_signals(struct jsm_channel *ch) 620 { 621 if (!ch) 622 return; 623 624 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 625 626 /* flush write operation */ 627 neo_pci_posting_flush(ch->ch_bd); 628 } 629 630 /* 631 * Flush the WRITE FIFO on the Neo. 632 * 633 * NOTE: Channel lock MUST be held before calling this function! 634 */ 635 static void neo_flush_uart_write(struct jsm_channel *ch) 636 { 637 u8 tmp = 0; 638 int i = 0; 639 640 if (!ch) 641 return; 642 643 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 644 645 for (i = 0; i < 10; i++) { 646 647 /* Check to see if the UART feels it completely flushed the FIFO. */ 648 tmp = readb(&ch->ch_neo_uart->isr_fcr); 649 if (tmp & 4) { 650 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, 651 "Still flushing TX UART... i: %d\n", i); 652 udelay(10); 653 } 654 else 655 break; 656 } 657 658 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 659 } 660 661 662 /* 663 * Flush the READ FIFO on the Neo. 664 * 665 * NOTE: Channel lock MUST be held before calling this function! 666 */ 667 static void neo_flush_uart_read(struct jsm_channel *ch) 668 { 669 u8 tmp = 0; 670 int i = 0; 671 672 if (!ch) 673 return; 674 675 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); 676 677 for (i = 0; i < 10; i++) { 678 679 /* Check to see if the UART feels it completely flushed the FIFO. */ 680 tmp = readb(&ch->ch_neo_uart->isr_fcr); 681 if (tmp & 2) { 682 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, 683 "Still flushing RX UART... i: %d\n", i); 684 udelay(10); 685 } 686 else 687 break; 688 } 689 } 690 691 /* 692 * No locks are assumed to be held when calling this function. 693 */ 694 static void neo_clear_break(struct jsm_channel *ch, int force) 695 { 696 unsigned long lock_flags; 697 698 spin_lock_irqsave(&ch->ch_lock, lock_flags); 699 700 /* Turn break off, and unset some variables */ 701 if (ch->ch_flags & CH_BREAK_SENDING) { 702 u8 temp = readb(&ch->ch_neo_uart->lcr); 703 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 704 705 ch->ch_flags &= ~(CH_BREAK_SENDING); 706 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, 707 "clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies); 708 709 /* flush write operation */ 710 neo_pci_posting_flush(ch->ch_bd); 711 } 712 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 713 } 714 715 /* 716 * Parse the ISR register. 717 */ 718 static inline void neo_parse_isr(struct jsm_board *brd, u32 port) 719 { 720 struct jsm_channel *ch; 721 u8 isr; 722 u8 cause; 723 unsigned long lock_flags; 724 725 if (!brd) 726 return; 727 728 if (port > brd->maxports) 729 return; 730 731 ch = brd->channels[port]; 732 if (!ch) 733 return; 734 735 /* Here we try to figure out what caused the interrupt to happen */ 736 while (1) { 737 738 isr = readb(&ch->ch_neo_uart->isr_fcr); 739 740 /* Bail if no pending interrupt */ 741 if (isr & UART_IIR_NO_INT) 742 break; 743 744 /* 745 * Yank off the upper 2 bits, which just show that the FIFO's are enabled. 746 */ 747 isr &= ~(UART_17158_IIR_FIFO_ENABLED); 748 749 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 750 "%s:%d isr: %x\n", __FILE__, __LINE__, isr); 751 752 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) { 753 /* Read data from uart -> queue */ 754 neo_copy_data_from_uart_to_queue(ch); 755 756 /* Call our tty layer to enforce queue flow control if needed. */ 757 spin_lock_irqsave(&ch->ch_lock, lock_flags); 758 jsm_check_queue_flow_control(ch); 759 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 760 } 761 762 if (isr & UART_IIR_THRI) { 763 /* Transfer data (if any) from Write Queue -> UART. */ 764 spin_lock_irqsave(&ch->ch_lock, lock_flags); 765 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 766 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 767 neo_copy_data_from_queue_to_uart(ch); 768 } 769 770 if (isr & UART_17158_IIR_XONXOFF) { 771 cause = readb(&ch->ch_neo_uart->xoffchar1); 772 773 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 774 "Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause); 775 776 /* 777 * Since the UART detected either an XON or 778 * XOFF match, we need to figure out which 779 * one it was, so we can suspend or resume data flow. 780 */ 781 spin_lock_irqsave(&ch->ch_lock, lock_flags); 782 if (cause == UART_17158_XON_DETECT) { 783 /* Is output stopped right now, if so, resume it */ 784 if (brd->channels[port]->ch_flags & CH_STOP) { 785 ch->ch_flags &= ~(CH_STOP); 786 } 787 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 788 "Port %d. XON detected in incoming data\n", port); 789 } 790 else if (cause == UART_17158_XOFF_DETECT) { 791 if (!(brd->channels[port]->ch_flags & CH_STOP)) { 792 ch->ch_flags |= CH_STOP; 793 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 794 "Setting CH_STOP\n"); 795 } 796 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 797 "Port: %d. XOFF detected in incoming data\n", port); 798 } 799 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 800 } 801 802 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) { 803 /* 804 * If we get here, this means the hardware is doing auto flow control. 805 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt. 806 */ 807 cause = readb(&ch->ch_neo_uart->mcr); 808 809 /* Which pin is doing auto flow? RTS or DTR? */ 810 spin_lock_irqsave(&ch->ch_lock, lock_flags); 811 if ((cause & 0x4) == 0) { 812 if (cause & UART_MCR_RTS) 813 ch->ch_mostat |= UART_MCR_RTS; 814 else 815 ch->ch_mostat &= ~(UART_MCR_RTS); 816 } else { 817 if (cause & UART_MCR_DTR) 818 ch->ch_mostat |= UART_MCR_DTR; 819 else 820 ch->ch_mostat &= ~(UART_MCR_DTR); 821 } 822 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 823 } 824 825 /* Parse any modem signal changes */ 826 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 827 "MOD_STAT: sending to parse_modem_sigs\n"); 828 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 829 } 830 } 831 832 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port) 833 { 834 struct jsm_channel *ch; 835 int linestatus; 836 unsigned long lock_flags; 837 838 if (!brd) 839 return; 840 841 if (port > brd->maxports) 842 return; 843 844 ch = brd->channels[port]; 845 if (!ch) 846 return; 847 848 linestatus = readb(&ch->ch_neo_uart->lsr); 849 850 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 851 "%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus); 852 853 ch->ch_cached_lsr |= linestatus; 854 855 if (ch->ch_cached_lsr & UART_LSR_DR) { 856 /* Read data from uart -> queue */ 857 neo_copy_data_from_uart_to_queue(ch); 858 spin_lock_irqsave(&ch->ch_lock, lock_flags); 859 jsm_check_queue_flow_control(ch); 860 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 861 } 862 863 /* 864 * This is a special flag. It indicates that at least 1 865 * RX error (parity, framing, or break) has happened. 866 * Mark this in our struct, which will tell me that I have 867 *to do the special RX+LSR read for this FIFO load. 868 */ 869 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 870 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 871 "%s:%d Port: %d Got an RX error, need to parse LSR\n", 872 __FILE__, __LINE__, port); 873 874 /* 875 * The next 3 tests should *NOT* happen, as the above test 876 * should encapsulate all 3... At least, thats what Exar says. 877 */ 878 879 if (linestatus & UART_LSR_PE) { 880 ch->ch_err_parity++; 881 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 882 "%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port); 883 } 884 885 if (linestatus & UART_LSR_FE) { 886 ch->ch_err_frame++; 887 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 888 "%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port); 889 } 890 891 if (linestatus & UART_LSR_BI) { 892 ch->ch_err_break++; 893 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 894 "%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port); 895 } 896 897 if (linestatus & UART_LSR_OE) { 898 /* 899 * Rx Oruns. Exar says that an orun will NOT corrupt 900 * the FIFO. It will just replace the holding register 901 * with this new data byte. So basically just ignore this. 902 * Probably we should eventually have an orun stat in our driver... 903 */ 904 ch->ch_err_overrun++; 905 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 906 "%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port); 907 } 908 909 if (linestatus & UART_LSR_THRE) { 910 spin_lock_irqsave(&ch->ch_lock, lock_flags); 911 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 912 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 913 914 /* Transfer data (if any) from Write Queue -> UART. */ 915 neo_copy_data_from_queue_to_uart(ch); 916 } 917 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) { 918 spin_lock_irqsave(&ch->ch_lock, lock_flags); 919 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 920 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 921 922 /* Transfer data (if any) from Write Queue -> UART. */ 923 neo_copy_data_from_queue_to_uart(ch); 924 } 925 } 926 927 /* 928 * neo_param() 929 * Send any/all changes to the line to the UART. 930 */ 931 static void neo_param(struct jsm_channel *ch) 932 { 933 u8 lcr = 0; 934 u8 uart_lcr, ier; 935 u32 baud; 936 int quot; 937 struct jsm_board *bd; 938 939 bd = ch->ch_bd; 940 if (!bd) 941 return; 942 943 /* 944 * If baud rate is zero, flush queues, and set mval to drop DTR. 945 */ 946 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 947 ch->ch_r_head = ch->ch_r_tail = 0; 948 ch->ch_e_head = ch->ch_e_tail = 0; 949 ch->ch_w_head = ch->ch_w_tail = 0; 950 951 neo_flush_uart_write(ch); 952 neo_flush_uart_read(ch); 953 954 ch->ch_flags |= (CH_BAUD0); 955 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 956 neo_assert_modem_signals(ch); 957 return; 958 959 } else { 960 int i; 961 unsigned int cflag; 962 static struct { 963 unsigned int rate; 964 unsigned int cflag; 965 } baud_rates[] = { 966 { 921600, B921600 }, 967 { 460800, B460800 }, 968 { 230400, B230400 }, 969 { 115200, B115200 }, 970 { 57600, B57600 }, 971 { 38400, B38400 }, 972 { 19200, B19200 }, 973 { 9600, B9600 }, 974 { 4800, B4800 }, 975 { 2400, B2400 }, 976 { 1200, B1200 }, 977 { 600, B600 }, 978 { 300, B300 }, 979 { 200, B200 }, 980 { 150, B150 }, 981 { 134, B134 }, 982 { 110, B110 }, 983 { 75, B75 }, 984 { 50, B50 }, 985 }; 986 987 cflag = C_BAUD(ch->uart_port.state->port.tty); 988 baud = 9600; 989 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) { 990 if (baud_rates[i].cflag == cflag) { 991 baud = baud_rates[i].rate; 992 break; 993 } 994 } 995 996 if (ch->ch_flags & CH_BAUD0) 997 ch->ch_flags &= ~(CH_BAUD0); 998 } 999 1000 if (ch->ch_c_cflag & PARENB) 1001 lcr |= UART_LCR_PARITY; 1002 1003 if (!(ch->ch_c_cflag & PARODD)) 1004 lcr |= UART_LCR_EPAR; 1005 1006 /* 1007 * Not all platforms support mark/space parity, 1008 * so this will hide behind an ifdef. 1009 */ 1010 #ifdef CMSPAR 1011 if (ch->ch_c_cflag & CMSPAR) 1012 lcr |= UART_LCR_SPAR; 1013 #endif 1014 1015 if (ch->ch_c_cflag & CSTOPB) 1016 lcr |= UART_LCR_STOP; 1017 1018 switch (ch->ch_c_cflag & CSIZE) { 1019 case CS5: 1020 lcr |= UART_LCR_WLEN5; 1021 break; 1022 case CS6: 1023 lcr |= UART_LCR_WLEN6; 1024 break; 1025 case CS7: 1026 lcr |= UART_LCR_WLEN7; 1027 break; 1028 case CS8: 1029 default: 1030 lcr |= UART_LCR_WLEN8; 1031 break; 1032 } 1033 1034 ier = readb(&ch->ch_neo_uart->ier); 1035 uart_lcr = readb(&ch->ch_neo_uart->lcr); 1036 1037 if (baud == 0) 1038 baud = 9600; 1039 1040 quot = ch->ch_bd->bd_dividend / baud; 1041 1042 if (quot != 0) { 1043 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); 1044 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); 1045 writeb((quot >> 8), &ch->ch_neo_uart->ier); 1046 writeb(lcr, &ch->ch_neo_uart->lcr); 1047 } 1048 1049 if (uart_lcr != lcr) 1050 writeb(lcr, &ch->ch_neo_uart->lcr); 1051 1052 if (ch->ch_c_cflag & CREAD) 1053 ier |= (UART_IER_RDI | UART_IER_RLSI); 1054 1055 ier |= (UART_IER_THRI | UART_IER_MSI); 1056 1057 writeb(ier, &ch->ch_neo_uart->ier); 1058 1059 /* Set new start/stop chars */ 1060 neo_set_new_start_stop_chars(ch); 1061 1062 if (ch->ch_c_cflag & CRTSCTS) 1063 neo_set_cts_flow_control(ch); 1064 else if (ch->ch_c_iflag & IXON) { 1065 /* If start/stop is set to disable, then we should disable flow control */ 1066 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1067 neo_set_no_output_flow_control(ch); 1068 else 1069 neo_set_ixon_flow_control(ch); 1070 } 1071 else 1072 neo_set_no_output_flow_control(ch); 1073 1074 if (ch->ch_c_cflag & CRTSCTS) 1075 neo_set_rts_flow_control(ch); 1076 else if (ch->ch_c_iflag & IXOFF) { 1077 /* If start/stop is set to disable, then we should disable flow control */ 1078 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1079 neo_set_no_input_flow_control(ch); 1080 else 1081 neo_set_ixoff_flow_control(ch); 1082 } 1083 else 1084 neo_set_no_input_flow_control(ch); 1085 /* 1086 * Adjust the RX FIFO Trigger level if baud is less than 9600. 1087 * Not exactly elegant, but this is needed because of the Exar chip's 1088 * delay on firing off the RX FIFO interrupt on slower baud rates. 1089 */ 1090 if (baud < 9600) { 1091 writeb(1, &ch->ch_neo_uart->rfifo); 1092 ch->ch_r_tlevel = 1; 1093 } 1094 1095 neo_assert_modem_signals(ch); 1096 1097 /* Get current status of the modem signals now */ 1098 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 1099 return; 1100 } 1101 1102 /* 1103 * jsm_neo_intr() 1104 * 1105 * Neo specific interrupt handler. 1106 */ 1107 static irqreturn_t neo_intr(int irq, void *voidbrd) 1108 { 1109 struct jsm_board *brd = voidbrd; 1110 struct jsm_channel *ch; 1111 int port = 0; 1112 int type = 0; 1113 int current_port; 1114 u32 tmp; 1115 u32 uart_poll; 1116 unsigned long lock_flags; 1117 unsigned long lock_flags2; 1118 int outofloop_count = 0; 1119 1120 /* Lock out the slow poller from running on this board. */ 1121 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); 1122 1123 /* 1124 * Read in "extended" IRQ information from the 32bit Neo register. 1125 * Bits 0-7: What port triggered the interrupt. 1126 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. 1127 */ 1128 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); 1129 1130 jsm_printk(INTR, INFO, &brd->pci_dev, 1131 "%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll); 1132 1133 if (!uart_poll) { 1134 jsm_printk(INTR, INFO, &brd->pci_dev, 1135 "Kernel interrupted to me, but no pending interrupts...\n"); 1136 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1137 return IRQ_NONE; 1138 } 1139 1140 /* At this point, we have at least SOMETHING to service, dig further... */ 1141 1142 current_port = 0; 1143 1144 /* Loop on each port */ 1145 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){ 1146 1147 tmp = uart_poll; 1148 outofloop_count++; 1149 1150 /* Check current port to see if it has interrupt pending */ 1151 if ((tmp & jsm_offset_table[current_port]) != 0) { 1152 port = current_port; 1153 type = tmp >> (8 + (port * 3)); 1154 type &= 0x7; 1155 } else { 1156 current_port++; 1157 continue; 1158 } 1159 1160 jsm_printk(INTR, INFO, &brd->pci_dev, 1161 "%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type); 1162 1163 /* Remove this port + type from uart_poll */ 1164 uart_poll &= ~(jsm_offset_table[port]); 1165 1166 if (!type) { 1167 /* If no type, just ignore it, and move onto next port */ 1168 jsm_printk(INTR, ERR, &brd->pci_dev, 1169 "Interrupt with no type! port: %d\n", port); 1170 continue; 1171 } 1172 1173 /* Switch on type of interrupt we have */ 1174 switch (type) { 1175 1176 case UART_17158_RXRDY_TIMEOUT: 1177 /* 1178 * RXRDY Time-out is cleared by reading data in the 1179 * RX FIFO until it falls below the trigger level. 1180 */ 1181 1182 /* Verify the port is in range. */ 1183 if (port > brd->nasync) 1184 continue; 1185 1186 ch = brd->channels[port]; 1187 neo_copy_data_from_uart_to_queue(ch); 1188 1189 /* Call our tty layer to enforce queue flow control if needed. */ 1190 spin_lock_irqsave(&ch->ch_lock, lock_flags2); 1191 jsm_check_queue_flow_control(ch); 1192 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); 1193 1194 continue; 1195 1196 case UART_17158_RX_LINE_STATUS: 1197 /* 1198 * RXRDY and RX LINE Status (logic OR of LSR[4:1]) 1199 */ 1200 neo_parse_lsr(brd, port); 1201 continue; 1202 1203 case UART_17158_TXRDY: 1204 /* 1205 * TXRDY interrupt clears after reading ISR register for the UART channel. 1206 */ 1207 1208 /* 1209 * Yes, this is odd... 1210 * Why would I check EVERY possibility of type of 1211 * interrupt, when we know its TXRDY??? 1212 * Becuz for some reason, even tho we got triggered for TXRDY, 1213 * it seems to be occasionally wrong. Instead of TX, which 1214 * it should be, I was getting things like RXDY too. Weird. 1215 */ 1216 neo_parse_isr(brd, port); 1217 continue; 1218 1219 case UART_17158_MSR: 1220 /* 1221 * MSR or flow control was seen. 1222 */ 1223 neo_parse_isr(brd, port); 1224 continue; 1225 1226 default: 1227 /* 1228 * The UART triggered us with a bogus interrupt type. 1229 * It appears the Exar chip, when REALLY bogged down, will throw 1230 * these once and awhile. 1231 * Its harmless, just ignore it and move on. 1232 */ 1233 jsm_printk(INTR, ERR, &brd->pci_dev, 1234 "%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type); 1235 continue; 1236 } 1237 } 1238 1239 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1240 1241 jsm_printk(INTR, INFO, &brd->pci_dev, "finish.\n"); 1242 return IRQ_HANDLED; 1243 } 1244 1245 /* 1246 * Neo specific way of turning off the receiver. 1247 * Used as a way to enforce queue flow control when in 1248 * hardware flow control mode. 1249 */ 1250 static void neo_disable_receiver(struct jsm_channel *ch) 1251 { 1252 u8 tmp = readb(&ch->ch_neo_uart->ier); 1253 tmp &= ~(UART_IER_RDI); 1254 writeb(tmp, &ch->ch_neo_uart->ier); 1255 1256 /* flush write operation */ 1257 neo_pci_posting_flush(ch->ch_bd); 1258 } 1259 1260 1261 /* 1262 * Neo specific way of turning on the receiver. 1263 * Used as a way to un-enforce queue flow control when in 1264 * hardware flow control mode. 1265 */ 1266 static void neo_enable_receiver(struct jsm_channel *ch) 1267 { 1268 u8 tmp = readb(&ch->ch_neo_uart->ier); 1269 tmp |= (UART_IER_RDI); 1270 writeb(tmp, &ch->ch_neo_uart->ier); 1271 1272 /* flush write operation */ 1273 neo_pci_posting_flush(ch->ch_bd); 1274 } 1275 1276 static void neo_send_start_character(struct jsm_channel *ch) 1277 { 1278 if (!ch) 1279 return; 1280 1281 if (ch->ch_startc != __DISABLED_CHAR) { 1282 ch->ch_xon_sends++; 1283 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); 1284 1285 /* flush write operation */ 1286 neo_pci_posting_flush(ch->ch_bd); 1287 } 1288 } 1289 1290 static void neo_send_stop_character(struct jsm_channel *ch) 1291 { 1292 if (!ch) 1293 return; 1294 1295 if (ch->ch_stopc != __DISABLED_CHAR) { 1296 ch->ch_xoff_sends++; 1297 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); 1298 1299 /* flush write operation */ 1300 neo_pci_posting_flush(ch->ch_bd); 1301 } 1302 } 1303 1304 /* 1305 * neo_uart_init 1306 */ 1307 static void neo_uart_init(struct jsm_channel *ch) 1308 { 1309 writeb(0, &ch->ch_neo_uart->ier); 1310 writeb(0, &ch->ch_neo_uart->efr); 1311 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); 1312 1313 /* Clear out UART and FIFO */ 1314 readb(&ch->ch_neo_uart->txrx); 1315 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1316 readb(&ch->ch_neo_uart->lsr); 1317 readb(&ch->ch_neo_uart->msr); 1318 1319 ch->ch_flags |= CH_FIFO_ENABLED; 1320 1321 /* Assert any signals we want up */ 1322 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 1323 } 1324 1325 /* 1326 * Make the UART completely turn off. 1327 */ 1328 static void neo_uart_off(struct jsm_channel *ch) 1329 { 1330 /* Turn off UART enhanced bits */ 1331 writeb(0, &ch->ch_neo_uart->efr); 1332 1333 /* Stop all interrupts from occurring. */ 1334 writeb(0, &ch->ch_neo_uart->ier); 1335 } 1336 1337 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch) 1338 { 1339 u8 left = 0; 1340 u8 lsr = readb(&ch->ch_neo_uart->lsr); 1341 1342 /* We must cache the LSR as some of the bits get reset once read... */ 1343 ch->ch_cached_lsr |= lsr; 1344 1345 /* Determine whether the Transmitter is empty or not */ 1346 if (!(lsr & UART_LSR_TEMT)) 1347 left = 1; 1348 else { 1349 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1350 left = 0; 1351 } 1352 1353 return left; 1354 } 1355 1356 /* Channel lock MUST be held by the calling function! */ 1357 static void neo_send_break(struct jsm_channel *ch) 1358 { 1359 /* 1360 * Set the time we should stop sending the break. 1361 * If we are already sending a break, toss away the existing 1362 * time to stop, and use this new value instead. 1363 */ 1364 1365 /* Tell the UART to start sending the break */ 1366 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1367 u8 temp = readb(&ch->ch_neo_uart->lcr); 1368 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1369 ch->ch_flags |= (CH_BREAK_SENDING); 1370 1371 /* flush write operation */ 1372 neo_pci_posting_flush(ch->ch_bd); 1373 } 1374 } 1375 1376 /* 1377 * neo_send_immediate_char. 1378 * 1379 * Sends a specific character as soon as possible to the UART, 1380 * jumping over any bytes that might be in the write queue. 1381 * 1382 * The channel lock MUST be held by the calling function. 1383 */ 1384 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c) 1385 { 1386 if (!ch) 1387 return; 1388 1389 writeb(c, &ch->ch_neo_uart->txrx); 1390 1391 /* flush write operation */ 1392 neo_pci_posting_flush(ch->ch_bd); 1393 } 1394 1395 struct board_ops jsm_neo_ops = { 1396 .intr = neo_intr, 1397 .uart_init = neo_uart_init, 1398 .uart_off = neo_uart_off, 1399 .param = neo_param, 1400 .assert_modem_signals = neo_assert_modem_signals, 1401 .flush_uart_write = neo_flush_uart_write, 1402 .flush_uart_read = neo_flush_uart_read, 1403 .disable_receiver = neo_disable_receiver, 1404 .enable_receiver = neo_enable_receiver, 1405 .send_break = neo_send_break, 1406 .clear_break = neo_clear_break, 1407 .send_start_character = neo_send_start_character, 1408 .send_stop_character = neo_send_stop_character, 1409 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart, 1410 .get_uart_bytes_left = neo_get_uart_bytes_left, 1411 .send_immediate_char = neo_send_immediate_char 1412 }; 1413