1 /************************************************************************ 2 * Copyright 2003 Digi International (www.digi.com) 3 * 4 * Copyright (C) 2004 IBM Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 14 * PURPOSE. See the GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston, 19 * MA 02111-1307, USA. 20 * 21 * Contact Information: 22 * Scott H Kilau <Scott_Kilau@digi.com> 23 * Wendy Xiong <wendyx@us.ibm.com> 24 * 25 ***********************************************************************/ 26 #include <linux/delay.h> /* For udelay */ 27 #include <linux/serial_reg.h> /* For the various UART offsets */ 28 #include <linux/tty.h> 29 #include <linux/pci.h> 30 #include <asm/io.h> 31 32 #include "jsm.h" /* Driver main header file */ 33 34 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; 35 36 /* 37 * This function allows calls to ensure that all outstanding 38 * PCI writes have been completed, by doing a PCI read against 39 * a non-destructive, read-only location on the Neo card. 40 * 41 * In this case, we are reading the DVID (Read-only Device Identification) 42 * value of the Neo card. 43 */ 44 static inline void neo_pci_posting_flush(struct jsm_board *bd) 45 { 46 readb(bd->re_map_membase + 0x8D); 47 } 48 49 static void neo_set_cts_flow_control(struct jsm_channel *ch) 50 { 51 u8 ier, efr; 52 ier = readb(&ch->ch_neo_uart->ier); 53 efr = readb(&ch->ch_neo_uart->efr); 54 55 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); 56 57 /* Turn on auto CTS flow control */ 58 ier |= (UART_17158_IER_CTSDSR); 59 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR); 60 61 /* Turn off auto Xon flow control */ 62 efr &= ~(UART_17158_EFR_IXON); 63 64 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 65 writeb(0, &ch->ch_neo_uart->efr); 66 67 /* Turn on UART enhanced bits */ 68 writeb(efr, &ch->ch_neo_uart->efr); 69 70 /* Turn on table D, with 8 char hi/low watermarks */ 71 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 72 73 /* Feed the UART our trigger levels */ 74 writeb(8, &ch->ch_neo_uart->tfifo); 75 ch->ch_t_tlevel = 8; 76 77 writeb(ier, &ch->ch_neo_uart->ier); 78 } 79 80 static void neo_set_rts_flow_control(struct jsm_channel *ch) 81 { 82 u8 ier, efr; 83 ier = readb(&ch->ch_neo_uart->ier); 84 efr = readb(&ch->ch_neo_uart->efr); 85 86 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); 87 88 /* Turn on auto RTS flow control */ 89 ier |= (UART_17158_IER_RTSDTR); 90 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR); 91 92 /* Turn off auto Xoff flow control */ 93 ier &= ~(UART_17158_IER_XOFF); 94 efr &= ~(UART_17158_EFR_IXOFF); 95 96 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 97 writeb(0, &ch->ch_neo_uart->efr); 98 99 /* Turn on UART enhanced bits */ 100 writeb(efr, &ch->ch_neo_uart->efr); 101 102 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 103 ch->ch_r_watermark = 4; 104 105 writeb(56, &ch->ch_neo_uart->rfifo); 106 ch->ch_r_tlevel = 56; 107 108 writeb(ier, &ch->ch_neo_uart->ier); 109 110 /* 111 * From the Neo UART spec sheet: 112 * The auto RTS/DTR function must be started by asserting 113 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after 114 * it is enabled. 115 */ 116 ch->ch_mostat |= (UART_MCR_RTS); 117 } 118 119 120 static void neo_set_ixon_flow_control(struct jsm_channel *ch) 121 { 122 u8 ier, efr; 123 ier = readb(&ch->ch_neo_uart->ier); 124 efr = readb(&ch->ch_neo_uart->efr); 125 126 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); 127 128 /* Turn off auto CTS flow control */ 129 ier &= ~(UART_17158_IER_CTSDSR); 130 efr &= ~(UART_17158_EFR_CTSDSR); 131 132 /* Turn on auto Xon flow control */ 133 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON); 134 135 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 136 writeb(0, &ch->ch_neo_uart->efr); 137 138 /* Turn on UART enhanced bits */ 139 writeb(efr, &ch->ch_neo_uart->efr); 140 141 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 142 ch->ch_r_watermark = 4; 143 144 writeb(32, &ch->ch_neo_uart->rfifo); 145 ch->ch_r_tlevel = 32; 146 147 /* Tell UART what start/stop chars it should be looking for */ 148 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 149 writeb(0, &ch->ch_neo_uart->xonchar2); 150 151 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 152 writeb(0, &ch->ch_neo_uart->xoffchar2); 153 154 writeb(ier, &ch->ch_neo_uart->ier); 155 } 156 157 static void neo_set_ixoff_flow_control(struct jsm_channel *ch) 158 { 159 u8 ier, efr; 160 ier = readb(&ch->ch_neo_uart->ier); 161 efr = readb(&ch->ch_neo_uart->efr); 162 163 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); 164 165 /* Turn off auto RTS flow control */ 166 ier &= ~(UART_17158_IER_RTSDTR); 167 efr &= ~(UART_17158_EFR_RTSDTR); 168 169 /* Turn on auto Xoff flow control */ 170 ier |= (UART_17158_IER_XOFF); 171 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 172 173 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 174 writeb(0, &ch->ch_neo_uart->efr); 175 176 /* Turn on UART enhanced bits */ 177 writeb(efr, &ch->ch_neo_uart->efr); 178 179 /* Turn on table D, with 8 char hi/low watermarks */ 180 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 181 182 writeb(8, &ch->ch_neo_uart->tfifo); 183 ch->ch_t_tlevel = 8; 184 185 /* Tell UART what start/stop chars it should be looking for */ 186 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 187 writeb(0, &ch->ch_neo_uart->xonchar2); 188 189 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 190 writeb(0, &ch->ch_neo_uart->xoffchar2); 191 192 writeb(ier, &ch->ch_neo_uart->ier); 193 } 194 195 static void neo_set_no_input_flow_control(struct jsm_channel *ch) 196 { 197 u8 ier, efr; 198 ier = readb(&ch->ch_neo_uart->ier); 199 efr = readb(&ch->ch_neo_uart->efr); 200 201 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); 202 203 /* Turn off auto RTS flow control */ 204 ier &= ~(UART_17158_IER_RTSDTR); 205 efr &= ~(UART_17158_EFR_RTSDTR); 206 207 /* Turn off auto Xoff flow control */ 208 ier &= ~(UART_17158_IER_XOFF); 209 if (ch->ch_c_iflag & IXON) 210 efr &= ~(UART_17158_EFR_IXOFF); 211 else 212 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 213 214 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 215 writeb(0, &ch->ch_neo_uart->efr); 216 217 /* Turn on UART enhanced bits */ 218 writeb(efr, &ch->ch_neo_uart->efr); 219 220 /* Turn on table D, with 8 char hi/low watermarks */ 221 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 222 223 ch->ch_r_watermark = 0; 224 225 writeb(16, &ch->ch_neo_uart->tfifo); 226 ch->ch_t_tlevel = 16; 227 228 writeb(16, &ch->ch_neo_uart->rfifo); 229 ch->ch_r_tlevel = 16; 230 231 writeb(ier, &ch->ch_neo_uart->ier); 232 } 233 234 static void neo_set_no_output_flow_control(struct jsm_channel *ch) 235 { 236 u8 ier, efr; 237 ier = readb(&ch->ch_neo_uart->ier); 238 efr = readb(&ch->ch_neo_uart->efr); 239 240 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); 241 242 /* Turn off auto CTS flow control */ 243 ier &= ~(UART_17158_IER_CTSDSR); 244 efr &= ~(UART_17158_EFR_CTSDSR); 245 246 /* Turn off auto Xon flow control */ 247 if (ch->ch_c_iflag & IXOFF) 248 efr &= ~(UART_17158_EFR_IXON); 249 else 250 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON); 251 252 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 253 writeb(0, &ch->ch_neo_uart->efr); 254 255 /* Turn on UART enhanced bits */ 256 writeb(efr, &ch->ch_neo_uart->efr); 257 258 /* Turn on table D, with 8 char hi/low watermarks */ 259 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 260 261 ch->ch_r_watermark = 0; 262 263 writeb(16, &ch->ch_neo_uart->tfifo); 264 ch->ch_t_tlevel = 16; 265 266 writeb(16, &ch->ch_neo_uart->rfifo); 267 ch->ch_r_tlevel = 16; 268 269 writeb(ier, &ch->ch_neo_uart->ier); 270 } 271 272 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch) 273 { 274 275 /* if hardware flow control is set, then skip this whole thing */ 276 if (ch->ch_c_cflag & CRTSCTS) 277 return; 278 279 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n"); 280 281 /* Tell UART what start/stop chars it should be looking for */ 282 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 283 writeb(0, &ch->ch_neo_uart->xonchar2); 284 285 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 286 writeb(0, &ch->ch_neo_uart->xoffchar2); 287 } 288 289 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch) 290 { 291 int qleft = 0; 292 u8 linestatus = 0; 293 u8 error_mask = 0; 294 int n = 0; 295 int total = 0; 296 u16 head; 297 u16 tail; 298 299 if (!ch) 300 return; 301 302 /* cache head and tail of queue */ 303 head = ch->ch_r_head & RQUEUEMASK; 304 tail = ch->ch_r_tail & RQUEUEMASK; 305 306 /* Get our cached LSR */ 307 linestatus = ch->ch_cached_lsr; 308 ch->ch_cached_lsr = 0; 309 310 /* Store how much space we have left in the queue */ 311 if ((qleft = tail - head - 1) < 0) 312 qleft += RQUEUEMASK + 1; 313 314 /* 315 * If the UART is not in FIFO mode, force the FIFO copy to 316 * NOT be run, by setting total to 0. 317 * 318 * On the other hand, if the UART IS in FIFO mode, then ask 319 * the UART to give us an approximation of data it has RX'ed. 320 */ 321 if (!(ch->ch_flags & CH_FIFO_ENABLED)) 322 total = 0; 323 else { 324 total = readb(&ch->ch_neo_uart->rfifo); 325 326 /* 327 * EXAR chip bug - RX FIFO COUNT - Fudge factor. 328 * 329 * This resolves a problem/bug with the Exar chip that sometimes 330 * returns a bogus value in the rfifo register. 331 * The count can be any where from 0-3 bytes "off". 332 * Bizarre, but true. 333 */ 334 total -= 3; 335 } 336 337 /* 338 * Finally, bound the copy to make sure we don't overflow 339 * our own queue... 340 * The byte by byte copy loop below this loop this will 341 * deal with the queue overflow possibility. 342 */ 343 total = min(total, qleft); 344 345 while (total > 0) { 346 /* 347 * Grab the linestatus register, we need to check 348 * to see if there are any errors in the FIFO. 349 */ 350 linestatus = readb(&ch->ch_neo_uart->lsr); 351 352 /* 353 * Break out if there is a FIFO error somewhere. 354 * This will allow us to go byte by byte down below, 355 * finding the exact location of the error. 356 */ 357 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 358 break; 359 360 /* Make sure we don't go over the end of our queue */ 361 n = min(((u32) total), (RQUEUESIZE - (u32) head)); 362 363 /* 364 * Cut down n even further if needed, this is to fix 365 * a problem with memcpy_fromio() with the Neo on the 366 * IBM pSeries platform. 367 * 15 bytes max appears to be the magic number. 368 */ 369 n = min((u32) n, (u32) 12); 370 371 /* 372 * Since we are grabbing the linestatus register, which 373 * will reset some bits after our read, we need to ensure 374 * we don't miss our TX FIFO emptys. 375 */ 376 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) 377 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 378 379 linestatus = 0; 380 381 /* Copy data from uart to the queue */ 382 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); 383 /* 384 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed 385 * that all the data currently in the FIFO is free of 386 * breaks and parity/frame/orun errors. 387 */ 388 memset(ch->ch_equeue + head, 0, n); 389 390 /* Add to and flip head if needed */ 391 head = (head + n) & RQUEUEMASK; 392 total -= n; 393 qleft -= n; 394 ch->ch_rxcount += n; 395 } 396 397 /* 398 * Create a mask to determine whether we should 399 * insert the character (if any) into our queue. 400 */ 401 if (ch->ch_c_iflag & IGNBRK) 402 error_mask |= UART_LSR_BI; 403 404 /* 405 * Now cleanup any leftover bytes still in the UART. 406 * Also deal with any possible queue overflow here as well. 407 */ 408 while (1) { 409 410 /* 411 * Its possible we have a linestatus from the loop above 412 * this, so we "OR" on any extra bits. 413 */ 414 linestatus |= readb(&ch->ch_neo_uart->lsr); 415 416 /* 417 * If the chip tells us there is no more data pending to 418 * be read, we can then leave. 419 * But before we do, cache the linestatus, just in case. 420 */ 421 if (!(linestatus & UART_LSR_DR)) { 422 ch->ch_cached_lsr = linestatus; 423 break; 424 } 425 426 /* No need to store this bit */ 427 linestatus &= ~UART_LSR_DR; 428 429 /* 430 * Since we are grabbing the linestatus register, which 431 * will reset some bits after our read, we need to ensure 432 * we don't miss our TX FIFO emptys. 433 */ 434 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { 435 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); 436 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 437 } 438 439 /* 440 * Discard character if we are ignoring the error mask. 441 */ 442 if (linestatus & error_mask) { 443 u8 discard; 444 linestatus = 0; 445 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); 446 continue; 447 } 448 449 /* 450 * If our queue is full, we have no choice but to drop some data. 451 * The assumption is that HWFLOW or SWFLOW should have stopped 452 * things way way before we got to this point. 453 * 454 * I decided that I wanted to ditch the oldest data first, 455 * I hope thats okay with everyone? Yes? Good. 456 */ 457 while (qleft < 1) { 458 jsm_dbg(READ, &ch->ch_bd->pci_dev, 459 "Queue full, dropping DATA:%x LSR:%x\n", 460 ch->ch_rqueue[tail], ch->ch_equeue[tail]); 461 462 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; 463 ch->ch_err_overrun++; 464 qleft++; 465 } 466 467 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); 468 ch->ch_equeue[head] = (u8) linestatus; 469 470 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n", 471 ch->ch_rqueue[head], ch->ch_equeue[head]); 472 473 /* Ditch any remaining linestatus value. */ 474 linestatus = 0; 475 476 /* Add to and flip head if needed */ 477 head = (head + 1) & RQUEUEMASK; 478 479 qleft--; 480 ch->ch_rxcount++; 481 } 482 483 /* 484 * Write new final heads to channel structure. 485 */ 486 ch->ch_r_head = head & RQUEUEMASK; 487 ch->ch_e_head = head & EQUEUEMASK; 488 jsm_input(ch); 489 } 490 491 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch) 492 { 493 u16 head; 494 u16 tail; 495 int n; 496 int s; 497 int qlen; 498 u32 len_written = 0; 499 struct circ_buf *circ; 500 501 if (!ch) 502 return; 503 504 circ = &ch->uart_port.state->xmit; 505 506 /* No data to write to the UART */ 507 if (uart_circ_empty(circ)) 508 return; 509 510 /* If port is "stopped", don't send any data to the UART */ 511 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) 512 return; 513 /* 514 * If FIFOs are disabled. Send data directly to txrx register 515 */ 516 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { 517 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); 518 519 ch->ch_cached_lsr |= lsrbits; 520 if (ch->ch_cached_lsr & UART_LSR_THRE) { 521 ch->ch_cached_lsr &= ~(UART_LSR_THRE); 522 523 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx); 524 jsm_dbg(WRITE, &ch->ch_bd->pci_dev, 525 "Tx data: %x\n", circ->buf[circ->tail]); 526 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1); 527 ch->ch_txcount++; 528 } 529 return; 530 } 531 532 /* 533 * We have to do it this way, because of the EXAR TXFIFO count bug. 534 */ 535 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 536 return; 537 538 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 539 540 /* cache head and tail of queue */ 541 head = circ->head & (UART_XMIT_SIZE - 1); 542 tail = circ->tail & (UART_XMIT_SIZE - 1); 543 qlen = uart_circ_chars_pending(circ); 544 545 /* Find minimum of the FIFO space, versus queue length */ 546 n = min(n, qlen); 547 548 while (n > 0) { 549 550 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail; 551 s = min(s, n); 552 553 if (s <= 0) 554 break; 555 556 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s); 557 /* Add and flip queue if needed */ 558 tail = (tail + s) & (UART_XMIT_SIZE - 1); 559 n -= s; 560 ch->ch_txcount += s; 561 len_written += s; 562 } 563 564 /* Update the final tail */ 565 circ->tail = tail & (UART_XMIT_SIZE - 1); 566 567 if (len_written >= ch->ch_t_tlevel) 568 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 569 570 if (uart_circ_empty(circ)) 571 uart_write_wakeup(&ch->uart_port); 572 } 573 574 static void neo_parse_modem(struct jsm_channel *ch, u8 signals) 575 { 576 u8 msignals = signals; 577 578 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 579 "neo_parse_modem: port: %d msignals: %x\n", 580 ch->ch_portnum, msignals); 581 582 /* Scrub off lower bits. They signify delta's, which I don't care about */ 583 /* Keep DDCD and DDSR though */ 584 msignals &= 0xf8; 585 586 if (msignals & UART_MSR_DDCD) 587 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); 588 if (msignals & UART_MSR_DDSR) 589 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); 590 if (msignals & UART_MSR_DCD) 591 ch->ch_mistat |= UART_MSR_DCD; 592 else 593 ch->ch_mistat &= ~UART_MSR_DCD; 594 595 if (msignals & UART_MSR_DSR) 596 ch->ch_mistat |= UART_MSR_DSR; 597 else 598 ch->ch_mistat &= ~UART_MSR_DSR; 599 600 if (msignals & UART_MSR_RI) 601 ch->ch_mistat |= UART_MSR_RI; 602 else 603 ch->ch_mistat &= ~UART_MSR_RI; 604 605 if (msignals & UART_MSR_CTS) 606 ch->ch_mistat |= UART_MSR_CTS; 607 else 608 ch->ch_mistat &= ~UART_MSR_CTS; 609 610 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 611 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n", 612 ch->ch_portnum, 613 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), 614 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), 615 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), 616 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), 617 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), 618 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); 619 } 620 621 /* Make the UART raise any of the output signals we want up */ 622 static void neo_assert_modem_signals(struct jsm_channel *ch) 623 { 624 if (!ch) 625 return; 626 627 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 628 629 /* flush write operation */ 630 neo_pci_posting_flush(ch->ch_bd); 631 } 632 633 /* 634 * Flush the WRITE FIFO on the Neo. 635 * 636 * NOTE: Channel lock MUST be held before calling this function! 637 */ 638 static void neo_flush_uart_write(struct jsm_channel *ch) 639 { 640 u8 tmp = 0; 641 int i = 0; 642 643 if (!ch) 644 return; 645 646 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 647 648 for (i = 0; i < 10; i++) { 649 650 /* Check to see if the UART feels it completely flushed the FIFO. */ 651 tmp = readb(&ch->ch_neo_uart->isr_fcr); 652 if (tmp & 4) { 653 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 654 "Still flushing TX UART... i: %d\n", i); 655 udelay(10); 656 } 657 else 658 break; 659 } 660 661 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 662 } 663 664 665 /* 666 * Flush the READ FIFO on the Neo. 667 * 668 * NOTE: Channel lock MUST be held before calling this function! 669 */ 670 static void neo_flush_uart_read(struct jsm_channel *ch) 671 { 672 u8 tmp = 0; 673 int i = 0; 674 675 if (!ch) 676 return; 677 678 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); 679 680 for (i = 0; i < 10; i++) { 681 682 /* Check to see if the UART feels it completely flushed the FIFO. */ 683 tmp = readb(&ch->ch_neo_uart->isr_fcr); 684 if (tmp & 2) { 685 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 686 "Still flushing RX UART... i: %d\n", i); 687 udelay(10); 688 } 689 else 690 break; 691 } 692 } 693 694 /* 695 * No locks are assumed to be held when calling this function. 696 */ 697 static void neo_clear_break(struct jsm_channel *ch, int force) 698 { 699 unsigned long lock_flags; 700 701 spin_lock_irqsave(&ch->ch_lock, lock_flags); 702 703 /* Turn break off, and unset some variables */ 704 if (ch->ch_flags & CH_BREAK_SENDING) { 705 u8 temp = readb(&ch->ch_neo_uart->lcr); 706 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 707 708 ch->ch_flags &= ~(CH_BREAK_SENDING); 709 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 710 "clear break Finishing UART_LCR_SBC! finished: %lx\n", 711 jiffies); 712 713 /* flush write operation */ 714 neo_pci_posting_flush(ch->ch_bd); 715 } 716 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 717 } 718 719 /* 720 * Parse the ISR register. 721 */ 722 static inline void neo_parse_isr(struct jsm_board *brd, u32 port) 723 { 724 struct jsm_channel *ch; 725 u8 isr; 726 u8 cause; 727 unsigned long lock_flags; 728 729 if (!brd) 730 return; 731 732 if (port > brd->maxports) 733 return; 734 735 ch = brd->channels[port]; 736 if (!ch) 737 return; 738 739 /* Here we try to figure out what caused the interrupt to happen */ 740 while (1) { 741 742 isr = readb(&ch->ch_neo_uart->isr_fcr); 743 744 /* Bail if no pending interrupt */ 745 if (isr & UART_IIR_NO_INT) 746 break; 747 748 /* 749 * Yank off the upper 2 bits, which just show that the FIFO's are enabled. 750 */ 751 isr &= ~(UART_17158_IIR_FIFO_ENABLED); 752 753 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n", 754 __FILE__, __LINE__, isr); 755 756 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) { 757 /* Read data from uart -> queue */ 758 neo_copy_data_from_uart_to_queue(ch); 759 760 /* Call our tty layer to enforce queue flow control if needed. */ 761 spin_lock_irqsave(&ch->ch_lock, lock_flags); 762 jsm_check_queue_flow_control(ch); 763 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 764 } 765 766 if (isr & UART_IIR_THRI) { 767 /* Transfer data (if any) from Write Queue -> UART. */ 768 spin_lock_irqsave(&ch->ch_lock, lock_flags); 769 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 770 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 771 neo_copy_data_from_queue_to_uart(ch); 772 } 773 774 if (isr & UART_17158_IIR_XONXOFF) { 775 cause = readb(&ch->ch_neo_uart->xoffchar1); 776 777 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 778 "Port %d. Got ISR_XONXOFF: cause:%x\n", 779 port, cause); 780 781 /* 782 * Since the UART detected either an XON or 783 * XOFF match, we need to figure out which 784 * one it was, so we can suspend or resume data flow. 785 */ 786 spin_lock_irqsave(&ch->ch_lock, lock_flags); 787 if (cause == UART_17158_XON_DETECT) { 788 /* Is output stopped right now, if so, resume it */ 789 if (brd->channels[port]->ch_flags & CH_STOP) { 790 ch->ch_flags &= ~(CH_STOP); 791 } 792 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 793 "Port %d. XON detected in incoming data\n", 794 port); 795 } 796 else if (cause == UART_17158_XOFF_DETECT) { 797 if (!(brd->channels[port]->ch_flags & CH_STOP)) { 798 ch->ch_flags |= CH_STOP; 799 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 800 "Setting CH_STOP\n"); 801 } 802 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 803 "Port: %d. XOFF detected in incoming data\n", 804 port); 805 } 806 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 807 } 808 809 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) { 810 /* 811 * If we get here, this means the hardware is doing auto flow control. 812 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt. 813 */ 814 cause = readb(&ch->ch_neo_uart->mcr); 815 816 /* Which pin is doing auto flow? RTS or DTR? */ 817 spin_lock_irqsave(&ch->ch_lock, lock_flags); 818 if ((cause & 0x4) == 0) { 819 if (cause & UART_MCR_RTS) 820 ch->ch_mostat |= UART_MCR_RTS; 821 else 822 ch->ch_mostat &= ~(UART_MCR_RTS); 823 } else { 824 if (cause & UART_MCR_DTR) 825 ch->ch_mostat |= UART_MCR_DTR; 826 else 827 ch->ch_mostat &= ~(UART_MCR_DTR); 828 } 829 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 830 } 831 832 /* Parse any modem signal changes */ 833 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 834 "MOD_STAT: sending to parse_modem_sigs\n"); 835 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 836 } 837 } 838 839 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port) 840 { 841 struct jsm_channel *ch; 842 int linestatus; 843 unsigned long lock_flags; 844 845 if (!brd) 846 return; 847 848 if (port > brd->maxports) 849 return; 850 851 ch = brd->channels[port]; 852 if (!ch) 853 return; 854 855 linestatus = readb(&ch->ch_neo_uart->lsr); 856 857 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n", 858 __FILE__, __LINE__, port, linestatus); 859 860 ch->ch_cached_lsr |= linestatus; 861 862 if (ch->ch_cached_lsr & UART_LSR_DR) { 863 /* Read data from uart -> queue */ 864 neo_copy_data_from_uart_to_queue(ch); 865 spin_lock_irqsave(&ch->ch_lock, lock_flags); 866 jsm_check_queue_flow_control(ch); 867 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 868 } 869 870 /* 871 * This is a special flag. It indicates that at least 1 872 * RX error (parity, framing, or break) has happened. 873 * Mark this in our struct, which will tell me that I have 874 *to do the special RX+LSR read for this FIFO load. 875 */ 876 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 877 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 878 "%s:%d Port: %d Got an RX error, need to parse LSR\n", 879 __FILE__, __LINE__, port); 880 881 /* 882 * The next 3 tests should *NOT* happen, as the above test 883 * should encapsulate all 3... At least, thats what Exar says. 884 */ 885 886 if (linestatus & UART_LSR_PE) { 887 ch->ch_err_parity++; 888 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n", 889 __FILE__, __LINE__, port); 890 } 891 892 if (linestatus & UART_LSR_FE) { 893 ch->ch_err_frame++; 894 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n", 895 __FILE__, __LINE__, port); 896 } 897 898 if (linestatus & UART_LSR_BI) { 899 ch->ch_err_break++; 900 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 901 "%s:%d Port: %d. BRK INTR!\n", 902 __FILE__, __LINE__, port); 903 } 904 905 if (linestatus & UART_LSR_OE) { 906 /* 907 * Rx Oruns. Exar says that an orun will NOT corrupt 908 * the FIFO. It will just replace the holding register 909 * with this new data byte. So basically just ignore this. 910 * Probably we should eventually have an orun stat in our driver... 911 */ 912 ch->ch_err_overrun++; 913 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 914 "%s:%d Port: %d. Rx Overrun!\n", 915 __FILE__, __LINE__, port); 916 } 917 918 if (linestatus & UART_LSR_THRE) { 919 spin_lock_irqsave(&ch->ch_lock, lock_flags); 920 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 921 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 922 923 /* Transfer data (if any) from Write Queue -> UART. */ 924 neo_copy_data_from_queue_to_uart(ch); 925 } 926 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) { 927 spin_lock_irqsave(&ch->ch_lock, lock_flags); 928 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 929 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 930 931 /* Transfer data (if any) from Write Queue -> UART. */ 932 neo_copy_data_from_queue_to_uart(ch); 933 } 934 } 935 936 /* 937 * neo_param() 938 * Send any/all changes to the line to the UART. 939 */ 940 static void neo_param(struct jsm_channel *ch) 941 { 942 u8 lcr = 0; 943 u8 uart_lcr, ier; 944 u32 baud; 945 int quot; 946 struct jsm_board *bd; 947 948 bd = ch->ch_bd; 949 if (!bd) 950 return; 951 952 /* 953 * If baud rate is zero, flush queues, and set mval to drop DTR. 954 */ 955 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 956 ch->ch_r_head = ch->ch_r_tail = 0; 957 ch->ch_e_head = ch->ch_e_tail = 0; 958 959 neo_flush_uart_write(ch); 960 neo_flush_uart_read(ch); 961 962 ch->ch_flags |= (CH_BAUD0); 963 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 964 neo_assert_modem_signals(ch); 965 return; 966 967 } else { 968 int i; 969 unsigned int cflag; 970 static struct { 971 unsigned int rate; 972 unsigned int cflag; 973 } baud_rates[] = { 974 { 921600, B921600 }, 975 { 460800, B460800 }, 976 { 230400, B230400 }, 977 { 115200, B115200 }, 978 { 57600, B57600 }, 979 { 38400, B38400 }, 980 { 19200, B19200 }, 981 { 9600, B9600 }, 982 { 4800, B4800 }, 983 { 2400, B2400 }, 984 { 1200, B1200 }, 985 { 600, B600 }, 986 { 300, B300 }, 987 { 200, B200 }, 988 { 150, B150 }, 989 { 134, B134 }, 990 { 110, B110 }, 991 { 75, B75 }, 992 { 50, B50 }, 993 }; 994 995 cflag = C_BAUD(ch->uart_port.state->port.tty); 996 baud = 9600; 997 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) { 998 if (baud_rates[i].cflag == cflag) { 999 baud = baud_rates[i].rate; 1000 break; 1001 } 1002 } 1003 1004 if (ch->ch_flags & CH_BAUD0) 1005 ch->ch_flags &= ~(CH_BAUD0); 1006 } 1007 1008 if (ch->ch_c_cflag & PARENB) 1009 lcr |= UART_LCR_PARITY; 1010 1011 if (!(ch->ch_c_cflag & PARODD)) 1012 lcr |= UART_LCR_EPAR; 1013 1014 /* 1015 * Not all platforms support mark/space parity, 1016 * so this will hide behind an ifdef. 1017 */ 1018 #ifdef CMSPAR 1019 if (ch->ch_c_cflag & CMSPAR) 1020 lcr |= UART_LCR_SPAR; 1021 #endif 1022 1023 if (ch->ch_c_cflag & CSTOPB) 1024 lcr |= UART_LCR_STOP; 1025 1026 switch (ch->ch_c_cflag & CSIZE) { 1027 case CS5: 1028 lcr |= UART_LCR_WLEN5; 1029 break; 1030 case CS6: 1031 lcr |= UART_LCR_WLEN6; 1032 break; 1033 case CS7: 1034 lcr |= UART_LCR_WLEN7; 1035 break; 1036 case CS8: 1037 default: 1038 lcr |= UART_LCR_WLEN8; 1039 break; 1040 } 1041 1042 ier = readb(&ch->ch_neo_uart->ier); 1043 uart_lcr = readb(&ch->ch_neo_uart->lcr); 1044 1045 if (baud == 0) 1046 baud = 9600; 1047 1048 quot = ch->ch_bd->bd_dividend / baud; 1049 1050 if (quot != 0) { 1051 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); 1052 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); 1053 writeb((quot >> 8), &ch->ch_neo_uart->ier); 1054 writeb(lcr, &ch->ch_neo_uart->lcr); 1055 } 1056 1057 if (uart_lcr != lcr) 1058 writeb(lcr, &ch->ch_neo_uart->lcr); 1059 1060 if (ch->ch_c_cflag & CREAD) 1061 ier |= (UART_IER_RDI | UART_IER_RLSI); 1062 1063 ier |= (UART_IER_THRI | UART_IER_MSI); 1064 1065 writeb(ier, &ch->ch_neo_uart->ier); 1066 1067 /* Set new start/stop chars */ 1068 neo_set_new_start_stop_chars(ch); 1069 1070 if (ch->ch_c_cflag & CRTSCTS) 1071 neo_set_cts_flow_control(ch); 1072 else if (ch->ch_c_iflag & IXON) { 1073 /* If start/stop is set to disable, then we should disable flow control */ 1074 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1075 neo_set_no_output_flow_control(ch); 1076 else 1077 neo_set_ixon_flow_control(ch); 1078 } 1079 else 1080 neo_set_no_output_flow_control(ch); 1081 1082 if (ch->ch_c_cflag & CRTSCTS) 1083 neo_set_rts_flow_control(ch); 1084 else if (ch->ch_c_iflag & IXOFF) { 1085 /* If start/stop is set to disable, then we should disable flow control */ 1086 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1087 neo_set_no_input_flow_control(ch); 1088 else 1089 neo_set_ixoff_flow_control(ch); 1090 } 1091 else 1092 neo_set_no_input_flow_control(ch); 1093 /* 1094 * Adjust the RX FIFO Trigger level if baud is less than 9600. 1095 * Not exactly elegant, but this is needed because of the Exar chip's 1096 * delay on firing off the RX FIFO interrupt on slower baud rates. 1097 */ 1098 if (baud < 9600) { 1099 writeb(1, &ch->ch_neo_uart->rfifo); 1100 ch->ch_r_tlevel = 1; 1101 } 1102 1103 neo_assert_modem_signals(ch); 1104 1105 /* Get current status of the modem signals now */ 1106 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 1107 return; 1108 } 1109 1110 /* 1111 * jsm_neo_intr() 1112 * 1113 * Neo specific interrupt handler. 1114 */ 1115 static irqreturn_t neo_intr(int irq, void *voidbrd) 1116 { 1117 struct jsm_board *brd = voidbrd; 1118 struct jsm_channel *ch; 1119 int port = 0; 1120 int type = 0; 1121 int current_port; 1122 u32 tmp; 1123 u32 uart_poll; 1124 unsigned long lock_flags; 1125 unsigned long lock_flags2; 1126 int outofloop_count = 0; 1127 1128 /* Lock out the slow poller from running on this board. */ 1129 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); 1130 1131 /* 1132 * Read in "extended" IRQ information from the 32bit Neo register. 1133 * Bits 0-7: What port triggered the interrupt. 1134 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. 1135 */ 1136 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); 1137 1138 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", 1139 __FILE__, __LINE__, uart_poll); 1140 1141 if (!uart_poll) { 1142 jsm_dbg(INTR, &brd->pci_dev, 1143 "Kernel interrupted to me, but no pending interrupts...\n"); 1144 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1145 return IRQ_NONE; 1146 } 1147 1148 /* At this point, we have at least SOMETHING to service, dig further... */ 1149 1150 current_port = 0; 1151 1152 /* Loop on each port */ 1153 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){ 1154 1155 tmp = uart_poll; 1156 outofloop_count++; 1157 1158 /* Check current port to see if it has interrupt pending */ 1159 if ((tmp & jsm_offset_table[current_port]) != 0) { 1160 port = current_port; 1161 type = tmp >> (8 + (port * 3)); 1162 type &= 0x7; 1163 } else { 1164 current_port++; 1165 continue; 1166 } 1167 1168 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n", 1169 __FILE__, __LINE__, port, type); 1170 1171 /* Remove this port + type from uart_poll */ 1172 uart_poll &= ~(jsm_offset_table[port]); 1173 1174 if (!type) { 1175 /* If no type, just ignore it, and move onto next port */ 1176 jsm_dbg(INTR, &brd->pci_dev, 1177 "Interrupt with no type! port: %d\n", port); 1178 continue; 1179 } 1180 1181 /* Switch on type of interrupt we have */ 1182 switch (type) { 1183 1184 case UART_17158_RXRDY_TIMEOUT: 1185 /* 1186 * RXRDY Time-out is cleared by reading data in the 1187 * RX FIFO until it falls below the trigger level. 1188 */ 1189 1190 /* Verify the port is in range. */ 1191 if (port > brd->nasync) 1192 continue; 1193 1194 ch = brd->channels[port]; 1195 neo_copy_data_from_uart_to_queue(ch); 1196 1197 /* Call our tty layer to enforce queue flow control if needed. */ 1198 spin_lock_irqsave(&ch->ch_lock, lock_flags2); 1199 jsm_check_queue_flow_control(ch); 1200 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); 1201 1202 continue; 1203 1204 case UART_17158_RX_LINE_STATUS: 1205 /* 1206 * RXRDY and RX LINE Status (logic OR of LSR[4:1]) 1207 */ 1208 neo_parse_lsr(brd, port); 1209 continue; 1210 1211 case UART_17158_TXRDY: 1212 /* 1213 * TXRDY interrupt clears after reading ISR register for the UART channel. 1214 */ 1215 1216 /* 1217 * Yes, this is odd... 1218 * Why would I check EVERY possibility of type of 1219 * interrupt, when we know its TXRDY??? 1220 * Becuz for some reason, even tho we got triggered for TXRDY, 1221 * it seems to be occasionally wrong. Instead of TX, which 1222 * it should be, I was getting things like RXDY too. Weird. 1223 */ 1224 neo_parse_isr(brd, port); 1225 continue; 1226 1227 case UART_17158_MSR: 1228 /* 1229 * MSR or flow control was seen. 1230 */ 1231 neo_parse_isr(brd, port); 1232 continue; 1233 1234 default: 1235 /* 1236 * The UART triggered us with a bogus interrupt type. 1237 * It appears the Exar chip, when REALLY bogged down, will throw 1238 * these once and awhile. 1239 * Its harmless, just ignore it and move on. 1240 */ 1241 jsm_dbg(INTR, &brd->pci_dev, 1242 "%s:%d Unknown Interrupt type: %x\n", 1243 __FILE__, __LINE__, type); 1244 continue; 1245 } 1246 } 1247 1248 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1249 1250 jsm_dbg(INTR, &brd->pci_dev, "finish\n"); 1251 return IRQ_HANDLED; 1252 } 1253 1254 /* 1255 * Neo specific way of turning off the receiver. 1256 * Used as a way to enforce queue flow control when in 1257 * hardware flow control mode. 1258 */ 1259 static void neo_disable_receiver(struct jsm_channel *ch) 1260 { 1261 u8 tmp = readb(&ch->ch_neo_uart->ier); 1262 tmp &= ~(UART_IER_RDI); 1263 writeb(tmp, &ch->ch_neo_uart->ier); 1264 1265 /* flush write operation */ 1266 neo_pci_posting_flush(ch->ch_bd); 1267 } 1268 1269 1270 /* 1271 * Neo specific way of turning on the receiver. 1272 * Used as a way to un-enforce queue flow control when in 1273 * hardware flow control mode. 1274 */ 1275 static void neo_enable_receiver(struct jsm_channel *ch) 1276 { 1277 u8 tmp = readb(&ch->ch_neo_uart->ier); 1278 tmp |= (UART_IER_RDI); 1279 writeb(tmp, &ch->ch_neo_uart->ier); 1280 1281 /* flush write operation */ 1282 neo_pci_posting_flush(ch->ch_bd); 1283 } 1284 1285 static void neo_send_start_character(struct jsm_channel *ch) 1286 { 1287 if (!ch) 1288 return; 1289 1290 if (ch->ch_startc != __DISABLED_CHAR) { 1291 ch->ch_xon_sends++; 1292 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); 1293 1294 /* flush write operation */ 1295 neo_pci_posting_flush(ch->ch_bd); 1296 } 1297 } 1298 1299 static void neo_send_stop_character(struct jsm_channel *ch) 1300 { 1301 if (!ch) 1302 return; 1303 1304 if (ch->ch_stopc != __DISABLED_CHAR) { 1305 ch->ch_xoff_sends++; 1306 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); 1307 1308 /* flush write operation */ 1309 neo_pci_posting_flush(ch->ch_bd); 1310 } 1311 } 1312 1313 /* 1314 * neo_uart_init 1315 */ 1316 static void neo_uart_init(struct jsm_channel *ch) 1317 { 1318 writeb(0, &ch->ch_neo_uart->ier); 1319 writeb(0, &ch->ch_neo_uart->efr); 1320 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); 1321 1322 /* Clear out UART and FIFO */ 1323 readb(&ch->ch_neo_uart->txrx); 1324 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1325 readb(&ch->ch_neo_uart->lsr); 1326 readb(&ch->ch_neo_uart->msr); 1327 1328 ch->ch_flags |= CH_FIFO_ENABLED; 1329 1330 /* Assert any signals we want up */ 1331 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 1332 } 1333 1334 /* 1335 * Make the UART completely turn off. 1336 */ 1337 static void neo_uart_off(struct jsm_channel *ch) 1338 { 1339 /* Turn off UART enhanced bits */ 1340 writeb(0, &ch->ch_neo_uart->efr); 1341 1342 /* Stop all interrupts from occurring. */ 1343 writeb(0, &ch->ch_neo_uart->ier); 1344 } 1345 1346 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch) 1347 { 1348 u8 left = 0; 1349 u8 lsr = readb(&ch->ch_neo_uart->lsr); 1350 1351 /* We must cache the LSR as some of the bits get reset once read... */ 1352 ch->ch_cached_lsr |= lsr; 1353 1354 /* Determine whether the Transmitter is empty or not */ 1355 if (!(lsr & UART_LSR_TEMT)) 1356 left = 1; 1357 else { 1358 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1359 left = 0; 1360 } 1361 1362 return left; 1363 } 1364 1365 /* Channel lock MUST be held by the calling function! */ 1366 static void neo_send_break(struct jsm_channel *ch) 1367 { 1368 /* 1369 * Set the time we should stop sending the break. 1370 * If we are already sending a break, toss away the existing 1371 * time to stop, and use this new value instead. 1372 */ 1373 1374 /* Tell the UART to start sending the break */ 1375 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1376 u8 temp = readb(&ch->ch_neo_uart->lcr); 1377 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1378 ch->ch_flags |= (CH_BREAK_SENDING); 1379 1380 /* flush write operation */ 1381 neo_pci_posting_flush(ch->ch_bd); 1382 } 1383 } 1384 1385 /* 1386 * neo_send_immediate_char. 1387 * 1388 * Sends a specific character as soon as possible to the UART, 1389 * jumping over any bytes that might be in the write queue. 1390 * 1391 * The channel lock MUST be held by the calling function. 1392 */ 1393 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c) 1394 { 1395 if (!ch) 1396 return; 1397 1398 writeb(c, &ch->ch_neo_uart->txrx); 1399 1400 /* flush write operation */ 1401 neo_pci_posting_flush(ch->ch_bd); 1402 } 1403 1404 struct board_ops jsm_neo_ops = { 1405 .intr = neo_intr, 1406 .uart_init = neo_uart_init, 1407 .uart_off = neo_uart_off, 1408 .param = neo_param, 1409 .assert_modem_signals = neo_assert_modem_signals, 1410 .flush_uart_write = neo_flush_uart_write, 1411 .flush_uart_read = neo_flush_uart_read, 1412 .disable_receiver = neo_disable_receiver, 1413 .enable_receiver = neo_enable_receiver, 1414 .send_break = neo_send_break, 1415 .clear_break = neo_clear_break, 1416 .send_start_character = neo_send_start_character, 1417 .send_stop_character = neo_send_stop_character, 1418 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart, 1419 .get_uart_bytes_left = neo_get_uart_bytes_left, 1420 .send_immediate_char = neo_send_immediate_char 1421 }; 1422