1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2003 Digi International (www.digi.com) 4 * Scott H Kilau <Scott_Kilau at digi dot com> 5 * 6 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE! 7 * 8 * This is shared code between Digi's CVS archive and the 9 * Linux Kernel sources. 10 * Changing the source just for reformatting needlessly breaks 11 * our CVS diff history. 12 * 13 * Send any bug fixes/changes to: Eng.Linux at digi dot com. 14 * Thank you. 15 * 16 */ 17 18 #include <linux/delay.h> /* For udelay */ 19 #include <linux/io.h> /* For read[bwl]/write[bwl] */ 20 #include <linux/serial.h> /* For struct async_serial */ 21 #include <linux/serial_reg.h> /* For the various UART offsets */ 22 #include <linux/pci.h> 23 #include <linux/tty.h> 24 25 #include "jsm.h" /* Driver main header file */ 26 27 static struct { 28 unsigned int rate; 29 unsigned int cflag; 30 } baud_rates[] = { 31 { 921600, B921600 }, 32 { 460800, B460800 }, 33 { 230400, B230400 }, 34 { 115200, B115200 }, 35 { 57600, B57600 }, 36 { 38400, B38400 }, 37 { 19200, B19200 }, 38 { 9600, B9600 }, 39 { 4800, B4800 }, 40 { 2400, B2400 }, 41 { 1200, B1200 }, 42 { 600, B600 }, 43 { 300, B300 }, 44 { 200, B200 }, 45 { 150, B150 }, 46 { 134, B134 }, 47 { 110, B110 }, 48 { 75, B75 }, 49 { 50, B50 }, 50 }; 51 52 static void cls_set_cts_flow_control(struct jsm_channel *ch) 53 { 54 u8 lcrb = readb(&ch->ch_cls_uart->lcr); 55 u8 ier = readb(&ch->ch_cls_uart->ier); 56 u8 isr_fcr = 0; 57 58 /* 59 * The Enhanced Register Set may only be accessed when 60 * the Line Control Register is set to 0xBFh. 61 */ 62 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 63 64 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 65 66 /* Turn on CTS flow control, turn off IXON flow control */ 67 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR); 68 isr_fcr &= ~(UART_EXAR654_EFR_IXON); 69 70 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 71 72 /* Write old LCR value back out, which turns enhanced access off */ 73 writeb(lcrb, &ch->ch_cls_uart->lcr); 74 75 /* 76 * Enable interrupts for CTS flow, turn off interrupts for 77 * received XOFF chars 78 */ 79 ier |= (UART_EXAR654_IER_CTSDSR); 80 ier &= ~(UART_EXAR654_IER_XOFF); 81 writeb(ier, &ch->ch_cls_uart->ier); 82 83 /* Set the usual FIFO values */ 84 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 85 86 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | 87 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 88 &ch->ch_cls_uart->isr_fcr); 89 90 ch->ch_t_tlevel = 16; 91 } 92 93 static void cls_set_ixon_flow_control(struct jsm_channel *ch) 94 { 95 u8 lcrb = readb(&ch->ch_cls_uart->lcr); 96 u8 ier = readb(&ch->ch_cls_uart->ier); 97 u8 isr_fcr = 0; 98 99 /* 100 * The Enhanced Register Set may only be accessed when 101 * the Line Control Register is set to 0xBFh. 102 */ 103 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 104 105 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 106 107 /* Turn on IXON flow control, turn off CTS flow control */ 108 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON); 109 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR); 110 111 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 112 113 /* Now set our current start/stop chars while in enhanced mode */ 114 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); 115 writeb(0, &ch->ch_cls_uart->lsr); 116 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); 117 writeb(0, &ch->ch_cls_uart->spr); 118 119 /* Write old LCR value back out, which turns enhanced access off */ 120 writeb(lcrb, &ch->ch_cls_uart->lcr); 121 122 /* 123 * Disable interrupts for CTS flow, turn on interrupts for 124 * received XOFF chars 125 */ 126 ier &= ~(UART_EXAR654_IER_CTSDSR); 127 ier |= (UART_EXAR654_IER_XOFF); 128 writeb(ier, &ch->ch_cls_uart->ier); 129 130 /* Set the usual FIFO values */ 131 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 132 133 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | 134 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 135 &ch->ch_cls_uart->isr_fcr); 136 } 137 138 static void cls_set_no_output_flow_control(struct jsm_channel *ch) 139 { 140 u8 lcrb = readb(&ch->ch_cls_uart->lcr); 141 u8 ier = readb(&ch->ch_cls_uart->ier); 142 u8 isr_fcr = 0; 143 144 /* 145 * The Enhanced Register Set may only be accessed when 146 * the Line Control Register is set to 0xBFh. 147 */ 148 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 149 150 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 151 152 /* Turn off IXON flow control, turn off CTS flow control */ 153 isr_fcr |= (UART_EXAR654_EFR_ECB); 154 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON); 155 156 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 157 158 /* Write old LCR value back out, which turns enhanced access off */ 159 writeb(lcrb, &ch->ch_cls_uart->lcr); 160 161 /* 162 * Disable interrupts for CTS flow, turn off interrupts for 163 * received XOFF chars 164 */ 165 ier &= ~(UART_EXAR654_IER_CTSDSR); 166 ier &= ~(UART_EXAR654_IER_XOFF); 167 writeb(ier, &ch->ch_cls_uart->ier); 168 169 /* Set the usual FIFO values */ 170 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 171 172 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | 173 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 174 &ch->ch_cls_uart->isr_fcr); 175 176 ch->ch_r_watermark = 0; 177 ch->ch_t_tlevel = 16; 178 ch->ch_r_tlevel = 16; 179 } 180 181 static void cls_set_rts_flow_control(struct jsm_channel *ch) 182 { 183 u8 lcrb = readb(&ch->ch_cls_uart->lcr); 184 u8 ier = readb(&ch->ch_cls_uart->ier); 185 u8 isr_fcr = 0; 186 187 /* 188 * The Enhanced Register Set may only be accessed when 189 * the Line Control Register is set to 0xBFh. 190 */ 191 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 192 193 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 194 195 /* Turn on RTS flow control, turn off IXOFF flow control */ 196 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR); 197 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF); 198 199 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 200 201 /* Write old LCR value back out, which turns enhanced access off */ 202 writeb(lcrb, &ch->ch_cls_uart->lcr); 203 204 /* Enable interrupts for RTS flow */ 205 ier |= (UART_EXAR654_IER_RTSDTR); 206 writeb(ier, &ch->ch_cls_uart->ier); 207 208 /* Set the usual FIFO values */ 209 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 210 211 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | 212 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 213 &ch->ch_cls_uart->isr_fcr); 214 215 ch->ch_r_watermark = 4; 216 ch->ch_r_tlevel = 8; 217 } 218 219 static void cls_set_ixoff_flow_control(struct jsm_channel *ch) 220 { 221 u8 lcrb = readb(&ch->ch_cls_uart->lcr); 222 u8 ier = readb(&ch->ch_cls_uart->ier); 223 u8 isr_fcr = 0; 224 225 /* 226 * The Enhanced Register Set may only be accessed when 227 * the Line Control Register is set to 0xBFh. 228 */ 229 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 230 231 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 232 233 /* Turn on IXOFF flow control, turn off RTS flow control */ 234 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF); 235 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR); 236 237 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 238 239 /* Now set our current start/stop chars while in enhanced mode */ 240 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); 241 writeb(0, &ch->ch_cls_uart->lsr); 242 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); 243 writeb(0, &ch->ch_cls_uart->spr); 244 245 /* Write old LCR value back out, which turns enhanced access off */ 246 writeb(lcrb, &ch->ch_cls_uart->lcr); 247 248 /* Disable interrupts for RTS flow */ 249 ier &= ~(UART_EXAR654_IER_RTSDTR); 250 writeb(ier, &ch->ch_cls_uart->ier); 251 252 /* Set the usual FIFO values */ 253 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 254 255 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | 256 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 257 &ch->ch_cls_uart->isr_fcr); 258 } 259 260 static void cls_set_no_input_flow_control(struct jsm_channel *ch) 261 { 262 u8 lcrb = readb(&ch->ch_cls_uart->lcr); 263 u8 ier = readb(&ch->ch_cls_uart->ier); 264 u8 isr_fcr = 0; 265 266 /* 267 * The Enhanced Register Set may only be accessed when 268 * the Line Control Register is set to 0xBFh. 269 */ 270 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 271 272 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 273 274 /* Turn off IXOFF flow control, turn off RTS flow control */ 275 isr_fcr |= (UART_EXAR654_EFR_ECB); 276 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF); 277 278 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 279 280 /* Write old LCR value back out, which turns enhanced access off */ 281 writeb(lcrb, &ch->ch_cls_uart->lcr); 282 283 /* Disable interrupts for RTS flow */ 284 ier &= ~(UART_EXAR654_IER_RTSDTR); 285 writeb(ier, &ch->ch_cls_uart->ier); 286 287 /* Set the usual FIFO values */ 288 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 289 290 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | 291 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 292 &ch->ch_cls_uart->isr_fcr); 293 294 ch->ch_t_tlevel = 16; 295 ch->ch_r_tlevel = 16; 296 } 297 298 /* 299 * cls_clear_break. 300 * Determines whether its time to shut off break condition. 301 * 302 * No locks are assumed to be held when calling this function. 303 * channel lock is held and released in this function. 304 */ 305 static void cls_clear_break(struct jsm_channel *ch) 306 { 307 unsigned long lock_flags; 308 309 spin_lock_irqsave(&ch->ch_lock, lock_flags); 310 311 /* Turn break off, and unset some variables */ 312 if (ch->ch_flags & CH_BREAK_SENDING) { 313 u8 temp = readb(&ch->ch_cls_uart->lcr); 314 315 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); 316 317 ch->ch_flags &= ~(CH_BREAK_SENDING); 318 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 319 "clear break Finishing UART_LCR_SBC! finished: %lx\n", 320 jiffies); 321 } 322 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 323 } 324 325 static void cls_disable_receiver(struct jsm_channel *ch) 326 { 327 u8 tmp = readb(&ch->ch_cls_uart->ier); 328 329 tmp &= ~(UART_IER_RDI); 330 writeb(tmp, &ch->ch_cls_uart->ier); 331 } 332 333 static void cls_enable_receiver(struct jsm_channel *ch) 334 { 335 u8 tmp = readb(&ch->ch_cls_uart->ier); 336 337 tmp |= (UART_IER_RDI); 338 writeb(tmp, &ch->ch_cls_uart->ier); 339 } 340 341 /* Make the UART raise any of the output signals we want up */ 342 static void cls_assert_modem_signals(struct jsm_channel *ch) 343 { 344 if (!ch) 345 return; 346 347 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr); 348 } 349 350 static void cls_copy_data_from_uart_to_queue(struct jsm_channel *ch) 351 { 352 int qleft = 0; 353 u8 linestatus = 0; 354 u8 error_mask = 0; 355 u16 head; 356 u16 tail; 357 unsigned long flags; 358 359 if (!ch) 360 return; 361 362 spin_lock_irqsave(&ch->ch_lock, flags); 363 364 /* cache head and tail of queue */ 365 head = ch->ch_r_head & RQUEUEMASK; 366 tail = ch->ch_r_tail & RQUEUEMASK; 367 368 /* Get our cached LSR */ 369 linestatus = ch->ch_cached_lsr; 370 ch->ch_cached_lsr = 0; 371 372 /* Store how much space we have left in the queue */ 373 qleft = tail - head - 1; 374 if (qleft < 0) 375 qleft += RQUEUEMASK + 1; 376 377 /* 378 * Create a mask to determine whether we should 379 * insert the character (if any) into our queue. 380 */ 381 if (ch->ch_c_iflag & IGNBRK) 382 error_mask |= UART_LSR_BI; 383 384 while (1) { 385 /* 386 * Grab the linestatus register, we need to 387 * check to see if there is any data to read 388 */ 389 linestatus = readb(&ch->ch_cls_uart->lsr); 390 391 /* Break out if there is no data to fetch */ 392 if (!(linestatus & UART_LSR_DR)) 393 break; 394 395 /* 396 * Discard character if we are ignoring the error mask 397 * which in this case is the break signal. 398 */ 399 if (linestatus & error_mask) { 400 linestatus = 0; 401 readb(&ch->ch_cls_uart->txrx); 402 continue; 403 } 404 405 /* 406 * If our queue is full, we have no choice but to drop some 407 * data. The assumption is that HWFLOW or SWFLOW should have 408 * stopped things way way before we got to this point. 409 * 410 * I decided that I wanted to ditch the oldest data first, 411 * I hope thats okay with everyone? Yes? Good. 412 */ 413 while (qleft < 1) { 414 tail = (tail + 1) & RQUEUEMASK; 415 ch->ch_r_tail = tail; 416 ch->ch_err_overrun++; 417 qleft++; 418 } 419 420 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE 421 | UART_LSR_FE); 422 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx); 423 424 qleft--; 425 426 if (ch->ch_equeue[head] & UART_LSR_PE) 427 ch->ch_err_parity++; 428 if (ch->ch_equeue[head] & UART_LSR_BI) 429 ch->ch_err_break++; 430 if (ch->ch_equeue[head] & UART_LSR_FE) 431 ch->ch_err_frame++; 432 433 /* Add to, and flip head if needed */ 434 head = (head + 1) & RQUEUEMASK; 435 ch->ch_rxcount++; 436 } 437 438 /* 439 * Write new final heads to channel structure. 440 */ 441 ch->ch_r_head = head & RQUEUEMASK; 442 ch->ch_e_head = head & EQUEUEMASK; 443 444 spin_unlock_irqrestore(&ch->ch_lock, flags); 445 } 446 447 static void cls_copy_data_from_queue_to_uart(struct jsm_channel *ch) 448 { 449 u16 tail; 450 int n; 451 int qlen; 452 u32 len_written = 0; 453 struct circ_buf *circ; 454 455 if (!ch) 456 return; 457 458 circ = &ch->uart_port.state->xmit; 459 460 /* No data to write to the UART */ 461 if (uart_circ_empty(circ)) 462 return; 463 464 /* If port is "stopped", don't send any data to the UART */ 465 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) 466 return; 467 468 /* We have to do it this way, because of the EXAR TXFIFO count bug. */ 469 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 470 return; 471 472 n = 32; 473 474 /* cache tail of queue */ 475 tail = circ->tail & (UART_XMIT_SIZE - 1); 476 qlen = uart_circ_chars_pending(circ); 477 478 /* Find minimum of the FIFO space, versus queue length */ 479 n = min(n, qlen); 480 481 while (n > 0) { 482 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx); 483 tail = (tail + 1) & (UART_XMIT_SIZE - 1); 484 n--; 485 ch->ch_txcount++; 486 len_written++; 487 } 488 489 /* Update the final tail */ 490 circ->tail = tail & (UART_XMIT_SIZE - 1); 491 492 if (len_written > ch->ch_t_tlevel) 493 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 494 495 if (uart_circ_empty(circ)) 496 uart_write_wakeup(&ch->uart_port); 497 } 498 499 static void cls_parse_modem(struct jsm_channel *ch, u8 signals) 500 { 501 u8 msignals = signals; 502 503 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 504 "neo_parse_modem: port: %d msignals: %x\n", 505 ch->ch_portnum, msignals); 506 507 /* 508 * Scrub off lower bits. 509 * They signify delta's, which I don't care about 510 * Keep DDCD and DDSR though 511 */ 512 msignals &= 0xf8; 513 514 if (msignals & UART_MSR_DDCD) 515 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); 516 if (msignals & UART_MSR_DDSR) 517 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS); 518 519 if (msignals & UART_MSR_DCD) 520 ch->ch_mistat |= UART_MSR_DCD; 521 else 522 ch->ch_mistat &= ~UART_MSR_DCD; 523 524 if (msignals & UART_MSR_DSR) 525 ch->ch_mistat |= UART_MSR_DSR; 526 else 527 ch->ch_mistat &= ~UART_MSR_DSR; 528 529 if (msignals & UART_MSR_RI) 530 ch->ch_mistat |= UART_MSR_RI; 531 else 532 ch->ch_mistat &= ~UART_MSR_RI; 533 534 if (msignals & UART_MSR_CTS) 535 ch->ch_mistat |= UART_MSR_CTS; 536 else 537 ch->ch_mistat &= ~UART_MSR_CTS; 538 539 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 540 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n", 541 ch->ch_portnum, 542 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), 543 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), 544 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), 545 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), 546 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), 547 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); 548 } 549 550 /* Parse the ISR register for the specific port */ 551 static inline void cls_parse_isr(struct jsm_board *brd, uint port) 552 { 553 struct jsm_channel *ch; 554 u8 isr = 0; 555 unsigned long flags; 556 557 /* 558 * No need to verify board pointer, it was already 559 * verified in the interrupt routine. 560 */ 561 562 if (port >= brd->nasync) 563 return; 564 565 ch = brd->channels[port]; 566 if (!ch) 567 return; 568 569 /* Here we try to figure out what caused the interrupt to happen */ 570 while (1) { 571 isr = readb(&ch->ch_cls_uart->isr_fcr); 572 573 /* Bail if no pending interrupt on port */ 574 if (isr & UART_IIR_NO_INT) 575 break; 576 577 /* Receive Interrupt pending */ 578 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) { 579 /* Read data from uart -> queue */ 580 cls_copy_data_from_uart_to_queue(ch); 581 jsm_check_queue_flow_control(ch); 582 } 583 584 /* Transmit Hold register empty pending */ 585 if (isr & UART_IIR_THRI) { 586 /* Transfer data (if any) from Write Queue -> UART. */ 587 spin_lock_irqsave(&ch->ch_lock, flags); 588 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 589 spin_unlock_irqrestore(&ch->ch_lock, flags); 590 cls_copy_data_from_queue_to_uart(ch); 591 } 592 593 /* 594 * CTS/RTS change of state: 595 * Don't need to do anything, the cls_parse_modem 596 * below will grab the updated modem signals. 597 */ 598 599 /* Parse any modem signal changes */ 600 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); 601 } 602 } 603 604 /* Channel lock MUST be held before calling this function! */ 605 static void cls_flush_uart_write(struct jsm_channel *ch) 606 { 607 u8 tmp = 0; 608 u8 i = 0; 609 610 if (!ch) 611 return; 612 613 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), 614 &ch->ch_cls_uart->isr_fcr); 615 616 for (i = 0; i < 10; i++) { 617 /* Check to see if the UART feels it completely flushed FIFO */ 618 tmp = readb(&ch->ch_cls_uart->isr_fcr); 619 if (tmp & UART_FCR_CLEAR_XMIT) { 620 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 621 "Still flushing TX UART... i: %d\n", i); 622 udelay(10); 623 } else 624 break; 625 } 626 627 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 628 } 629 630 /* Channel lock MUST be held before calling this function! */ 631 static void cls_flush_uart_read(struct jsm_channel *ch) 632 { 633 if (!ch) 634 return; 635 636 /* 637 * For complete POSIX compatibility, we should be purging the 638 * read FIFO in the UART here. 639 * 640 * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also 641 * incorrectly flushes write data as well as just basically trashing the 642 * FIFO. 643 * 644 * Presumably, this is a bug in this UART. 645 */ 646 647 udelay(10); 648 } 649 650 static void cls_send_start_character(struct jsm_channel *ch) 651 { 652 if (!ch) 653 return; 654 655 if (ch->ch_startc != __DISABLED_CHAR) { 656 ch->ch_xon_sends++; 657 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); 658 } 659 } 660 661 static void cls_send_stop_character(struct jsm_channel *ch) 662 { 663 if (!ch) 664 return; 665 666 if (ch->ch_stopc != __DISABLED_CHAR) { 667 ch->ch_xoff_sends++; 668 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); 669 } 670 } 671 672 /* 673 * cls_param() 674 * Send any/all changes to the line to the UART. 675 */ 676 static void cls_param(struct jsm_channel *ch) 677 { 678 u8 lcr = 0; 679 u8 uart_lcr = 0; 680 u8 ier = 0; 681 u32 baud = 9600; 682 int quot = 0; 683 struct jsm_board *bd; 684 int i; 685 unsigned int cflag; 686 687 bd = ch->ch_bd; 688 if (!bd) 689 return; 690 691 /* 692 * If baud rate is zero, flush queues, and set mval to drop DTR. 693 */ 694 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 695 ch->ch_r_head = 0; 696 ch->ch_r_tail = 0; 697 ch->ch_e_head = 0; 698 ch->ch_e_tail = 0; 699 700 cls_flush_uart_write(ch); 701 cls_flush_uart_read(ch); 702 703 /* The baudrate is B0 so all modem lines are to be dropped. */ 704 ch->ch_flags |= (CH_BAUD0); 705 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 706 cls_assert_modem_signals(ch); 707 return; 708 } 709 710 cflag = C_BAUD(ch->uart_port.state->port.tty); 711 baud = 9600; 712 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) { 713 if (baud_rates[i].cflag == cflag) { 714 baud = baud_rates[i].rate; 715 break; 716 } 717 } 718 719 if (ch->ch_flags & CH_BAUD0) 720 ch->ch_flags &= ~(CH_BAUD0); 721 722 if (ch->ch_c_cflag & PARENB) 723 lcr |= UART_LCR_PARITY; 724 725 if (!(ch->ch_c_cflag & PARODD)) 726 lcr |= UART_LCR_EPAR; 727 728 /* 729 * Not all platforms support mark/space parity, 730 * so this will hide behind an ifdef. 731 */ 732 #ifdef CMSPAR 733 if (ch->ch_c_cflag & CMSPAR) 734 lcr |= UART_LCR_SPAR; 735 #endif 736 737 if (ch->ch_c_cflag & CSTOPB) 738 lcr |= UART_LCR_STOP; 739 740 switch (ch->ch_c_cflag & CSIZE) { 741 case CS5: 742 lcr |= UART_LCR_WLEN5; 743 break; 744 case CS6: 745 lcr |= UART_LCR_WLEN6; 746 break; 747 case CS7: 748 lcr |= UART_LCR_WLEN7; 749 break; 750 case CS8: 751 default: 752 lcr |= UART_LCR_WLEN8; 753 break; 754 } 755 756 ier = readb(&ch->ch_cls_uart->ier); 757 uart_lcr = readb(&ch->ch_cls_uart->lcr); 758 759 quot = ch->ch_bd->bd_dividend / baud; 760 761 if (quot != 0) { 762 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); 763 writeb((quot & 0xff), &ch->ch_cls_uart->txrx); 764 writeb((quot >> 8), &ch->ch_cls_uart->ier); 765 writeb(lcr, &ch->ch_cls_uart->lcr); 766 } 767 768 if (uart_lcr != lcr) 769 writeb(lcr, &ch->ch_cls_uart->lcr); 770 771 if (ch->ch_c_cflag & CREAD) 772 ier |= (UART_IER_RDI | UART_IER_RLSI); 773 774 ier |= (UART_IER_THRI | UART_IER_MSI); 775 776 writeb(ier, &ch->ch_cls_uart->ier); 777 778 if (ch->ch_c_cflag & CRTSCTS) 779 cls_set_cts_flow_control(ch); 780 else if (ch->ch_c_iflag & IXON) { 781 /* 782 * If start/stop is set to disable, 783 * then we should disable flow control. 784 */ 785 if ((ch->ch_startc == __DISABLED_CHAR) || 786 (ch->ch_stopc == __DISABLED_CHAR)) 787 cls_set_no_output_flow_control(ch); 788 else 789 cls_set_ixon_flow_control(ch); 790 } else 791 cls_set_no_output_flow_control(ch); 792 793 if (ch->ch_c_cflag & CRTSCTS) 794 cls_set_rts_flow_control(ch); 795 else if (ch->ch_c_iflag & IXOFF) { 796 /* 797 * If start/stop is set to disable, 798 * then we should disable flow control. 799 */ 800 if ((ch->ch_startc == __DISABLED_CHAR) || 801 (ch->ch_stopc == __DISABLED_CHAR)) 802 cls_set_no_input_flow_control(ch); 803 else 804 cls_set_ixoff_flow_control(ch); 805 } else 806 cls_set_no_input_flow_control(ch); 807 808 cls_assert_modem_signals(ch); 809 810 /* get current status of the modem signals now */ 811 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); 812 } 813 814 /* 815 * cls_intr() 816 * 817 * Classic specific interrupt handler. 818 */ 819 static irqreturn_t cls_intr(int irq, void *voidbrd) 820 { 821 struct jsm_board *brd = voidbrd; 822 unsigned long lock_flags; 823 unsigned char uart_poll; 824 uint i = 0; 825 826 /* Lock out the slow poller from running on this board. */ 827 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); 828 829 /* 830 * Check the board's global interrupt offset to see if we 831 * acctually do have an interrupt pending on us. 832 */ 833 uart_poll = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET); 834 835 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", 836 __FILE__, __LINE__, uart_poll); 837 838 if (!uart_poll) { 839 jsm_dbg(INTR, &brd->pci_dev, 840 "Kernel interrupted to me, but no pending interrupts...\n"); 841 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 842 return IRQ_NONE; 843 } 844 845 /* At this point, we have at least SOMETHING to service, dig further. */ 846 847 /* Parse each port to find out what caused the interrupt */ 848 for (i = 0; i < brd->nasync; i++) 849 cls_parse_isr(brd, i); 850 851 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 852 853 return IRQ_HANDLED; 854 } 855 856 /* Inits UART */ 857 static void cls_uart_init(struct jsm_channel *ch) 858 { 859 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); 860 unsigned char isr_fcr = 0; 861 862 writeb(0, &ch->ch_cls_uart->ier); 863 864 /* 865 * The Enhanced Register Set may only be accessed when 866 * the Line Control Register is set to 0xBFh. 867 */ 868 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 869 870 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 871 872 /* Turn on Enhanced/Extended controls */ 873 isr_fcr |= (UART_EXAR654_EFR_ECB); 874 875 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 876 877 /* Write old LCR value back out, which turns enhanced access off */ 878 writeb(lcrb, &ch->ch_cls_uart->lcr); 879 880 /* Clear out UART and FIFO */ 881 readb(&ch->ch_cls_uart->txrx); 882 883 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), 884 &ch->ch_cls_uart->isr_fcr); 885 udelay(10); 886 887 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 888 889 readb(&ch->ch_cls_uart->lsr); 890 readb(&ch->ch_cls_uart->msr); 891 } 892 893 /* 894 * Turns off UART. 895 */ 896 static void cls_uart_off(struct jsm_channel *ch) 897 { 898 /* Stop all interrupts from accurring. */ 899 writeb(0, &ch->ch_cls_uart->ier); 900 } 901 902 /* 903 * cls_get_uarts_bytes_left. 904 * Returns 0 is nothing left in the FIFO, returns 1 otherwise. 905 * 906 * The channel lock MUST be held by the calling function. 907 */ 908 static u32 cls_get_uart_bytes_left(struct jsm_channel *ch) 909 { 910 u8 left = 0; 911 u8 lsr = readb(&ch->ch_cls_uart->lsr); 912 913 /* Determine whether the Transmitter is empty or not */ 914 if (!(lsr & UART_LSR_TEMT)) 915 left = 1; 916 else { 917 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 918 left = 0; 919 } 920 921 return left; 922 } 923 924 /* 925 * cls_send_break. 926 * Starts sending a break thru the UART. 927 * 928 * The channel lock MUST be held by the calling function. 929 */ 930 static void cls_send_break(struct jsm_channel *ch) 931 { 932 /* Tell the UART to start sending the break */ 933 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 934 u8 temp = readb(&ch->ch_cls_uart->lcr); 935 936 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); 937 ch->ch_flags |= (CH_BREAK_SENDING); 938 } 939 } 940 941 /* 942 * cls_send_immediate_char. 943 * Sends a specific character as soon as possible to the UART, 944 * jumping over any bytes that might be in the write queue. 945 * 946 * The channel lock MUST be held by the calling function. 947 */ 948 static void cls_send_immediate_char(struct jsm_channel *ch, unsigned char c) 949 { 950 writeb(c, &ch->ch_cls_uart->txrx); 951 } 952 953 struct board_ops jsm_cls_ops = { 954 .intr = cls_intr, 955 .uart_init = cls_uart_init, 956 .uart_off = cls_uart_off, 957 .param = cls_param, 958 .assert_modem_signals = cls_assert_modem_signals, 959 .flush_uart_write = cls_flush_uart_write, 960 .flush_uart_read = cls_flush_uart_read, 961 .disable_receiver = cls_disable_receiver, 962 .enable_receiver = cls_enable_receiver, 963 .send_break = cls_send_break, 964 .clear_break = cls_clear_break, 965 .send_start_character = cls_send_start_character, 966 .send_stop_character = cls_send_stop_character, 967 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart, 968 .get_uart_bytes_left = cls_get_uart_bytes_left, 969 .send_immediate_char = cls_send_immediate_char 970 }; 971 972