xref: /openbmc/linux/drivers/tty/serial/ip22zilog.c (revision f7c35abe)
1 /*
2  * Driver for Zilog serial chips found on SGI workstations and
3  * servers.  This driver could actually be made more generic.
4  *
5  * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
6  * old drivers/sgi/char/sgiserial.c code which itself is based of the original
7  * drivers/sbus/char/zs.c code.  A lot of code has been simply moved over
8  * directly from there but much has been rewritten.  Credits therefore go out
9  * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
10  * for their work there.
11  *
12  *  Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
13  *  Copyright (C) 2002 David S. Miller (davem@redhat.com)
14  */
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #include <linux/init.h>
32 
33 #include <asm/io.h>
34 #include <asm/irq.h>
35 #include <asm/sgialib.h>
36 #include <asm/sgi/ioc.h>
37 #include <asm/sgi/hpc3.h>
38 #include <asm/sgi/ip22.h>
39 
40 #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
41 #define SUPPORT_SYSRQ
42 #endif
43 
44 #include <linux/serial_core.h>
45 
46 #include "ip22zilog.h"
47 
48 /*
49  * On IP22 we need to delay after register accesses but we do not need to
50  * flush writes.
51  */
52 #define ZSDELAY()		udelay(5)
53 #define ZSDELAY_LONG()		udelay(20)
54 #define ZS_WSYNC(channel)	do { } while (0)
55 
56 #define NUM_IP22ZILOG		1
57 #define NUM_CHANNELS		(NUM_IP22ZILOG * 2)
58 
59 #define ZS_CLOCK		3672000	/* Zilog input clock rate. */
60 #define ZS_CLOCK_DIVISOR	16      /* Divisor this driver uses. */
61 
62 /*
63  * We wrap our port structure around the generic uart_port.
64  */
65 struct uart_ip22zilog_port {
66 	struct uart_port		port;
67 
68 	/* IRQ servicing chain.  */
69 	struct uart_ip22zilog_port	*next;
70 
71 	/* Current values of Zilog write registers.  */
72 	unsigned char			curregs[NUM_ZSREGS];
73 
74 	unsigned int			flags;
75 #define IP22ZILOG_FLAG_IS_CONS		0x00000004
76 #define IP22ZILOG_FLAG_IS_KGDB		0x00000008
77 #define IP22ZILOG_FLAG_MODEM_STATUS	0x00000010
78 #define IP22ZILOG_FLAG_IS_CHANNEL_A	0x00000020
79 #define IP22ZILOG_FLAG_REGS_HELD	0x00000040
80 #define IP22ZILOG_FLAG_TX_STOPPED	0x00000080
81 #define IP22ZILOG_FLAG_TX_ACTIVE	0x00000100
82 #define IP22ZILOG_FLAG_RESET_DONE	0x00000200
83 
84 	unsigned int			tty_break;
85 
86 	unsigned char			parity_mask;
87 	unsigned char			prev_status;
88 };
89 
90 #define ZILOG_CHANNEL_FROM_PORT(PORT)	((struct zilog_channel *)((PORT)->membase))
91 #define UART_ZILOG(PORT)		((struct uart_ip22zilog_port *)(PORT))
92 #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM)		\
93 	(UART_ZILOG(PORT)->curregs[REGNUM])
94 #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL)	\
95 	((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
96 #define ZS_IS_CONS(UP)	((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
97 #define ZS_IS_KGDB(UP)	((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
98 #define ZS_WANTS_MODEM_STATUS(UP)	((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
99 #define ZS_IS_CHANNEL_A(UP)	((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
100 #define ZS_REGS_HELD(UP)	((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
101 #define ZS_TX_STOPPED(UP)	((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
102 #define ZS_TX_ACTIVE(UP)	((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
103 
104 /* Reading and writing Zilog8530 registers.  The delays are to make this
105  * driver work on the IP22 which needs a settling delay after each chip
106  * register access, other machines handle this in hardware via auxiliary
107  * flip-flops which implement the settle time we do in software.
108  *
109  * The port lock must be held and local IRQs must be disabled
110  * when {read,write}_zsreg is invoked.
111  */
112 static unsigned char read_zsreg(struct zilog_channel *channel,
113 				unsigned char reg)
114 {
115 	unsigned char retval;
116 
117 	writeb(reg, &channel->control);
118 	ZSDELAY();
119 	retval = readb(&channel->control);
120 	ZSDELAY();
121 
122 	return retval;
123 }
124 
125 static void write_zsreg(struct zilog_channel *channel,
126 			unsigned char reg, unsigned char value)
127 {
128 	writeb(reg, &channel->control);
129 	ZSDELAY();
130 	writeb(value, &channel->control);
131 	ZSDELAY();
132 }
133 
134 static void ip22zilog_clear_fifo(struct zilog_channel *channel)
135 {
136 	int i;
137 
138 	for (i = 0; i < 32; i++) {
139 		unsigned char regval;
140 
141 		regval = readb(&channel->control);
142 		ZSDELAY();
143 		if (regval & Rx_CH_AV)
144 			break;
145 
146 		regval = read_zsreg(channel, R1);
147 		readb(&channel->data);
148 		ZSDELAY();
149 
150 		if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
151 			writeb(ERR_RES, &channel->control);
152 			ZSDELAY();
153 			ZS_WSYNC(channel);
154 		}
155 	}
156 }
157 
158 /* This function must only be called when the TX is not busy.  The UART
159  * port lock must be held and local interrupts disabled.
160  */
161 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
162 {
163 	int i;
164 
165 	/* Let pending transmits finish.  */
166 	for (i = 0; i < 1000; i++) {
167 		unsigned char stat = read_zsreg(channel, R1);
168 		if (stat & ALL_SNT)
169 			break;
170 		udelay(100);
171 	}
172 
173 	writeb(ERR_RES, &channel->control);
174 	ZSDELAY();
175 	ZS_WSYNC(channel);
176 
177 	ip22zilog_clear_fifo(channel);
178 
179 	/* Disable all interrupts.  */
180 	write_zsreg(channel, R1,
181 		    regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
182 
183 	/* Set parity, sync config, stop bits, and clock divisor.  */
184 	write_zsreg(channel, R4, regs[R4]);
185 
186 	/* Set misc. TX/RX control bits.  */
187 	write_zsreg(channel, R10, regs[R10]);
188 
189 	/* Set TX/RX controls sans the enable bits.  */
190 	write_zsreg(channel, R3, regs[R3] & ~RxENAB);
191 	write_zsreg(channel, R5, regs[R5] & ~TxENAB);
192 
193 	/* Synchronous mode config.  */
194 	write_zsreg(channel, R6, regs[R6]);
195 	write_zsreg(channel, R7, regs[R7]);
196 
197 	/* Don't mess with the interrupt vector (R2, unused by us) and
198 	 * master interrupt control (R9).  We make sure this is setup
199 	 * properly at probe time then never touch it again.
200 	 */
201 
202 	/* Disable baud generator.  */
203 	write_zsreg(channel, R14, regs[R14] & ~BRENAB);
204 
205 	/* Clock mode control.  */
206 	write_zsreg(channel, R11, regs[R11]);
207 
208 	/* Lower and upper byte of baud rate generator divisor.  */
209 	write_zsreg(channel, R12, regs[R12]);
210 	write_zsreg(channel, R13, regs[R13]);
211 
212 	/* Now rewrite R14, with BRENAB (if set).  */
213 	write_zsreg(channel, R14, regs[R14]);
214 
215 	/* External status interrupt control.  */
216 	write_zsreg(channel, R15, regs[R15]);
217 
218 	/* Reset external status interrupts.  */
219 	write_zsreg(channel, R0, RES_EXT_INT);
220 	write_zsreg(channel, R0, RES_EXT_INT);
221 
222 	/* Rewrite R3/R5, this time without enables masked.  */
223 	write_zsreg(channel, R3, regs[R3]);
224 	write_zsreg(channel, R5, regs[R5]);
225 
226 	/* Rewrite R1, this time without IRQ enabled masked.  */
227 	write_zsreg(channel, R1, regs[R1]);
228 }
229 
230 /* Reprogram the Zilog channel HW registers with the copies found in the
231  * software state struct.  If the transmitter is busy, we defer this update
232  * until the next TX complete interrupt.  Else, we do it right now.
233  *
234  * The UART port lock must be held and local interrupts disabled.
235  */
236 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
237 				       struct zilog_channel *channel)
238 {
239 	if (!ZS_REGS_HELD(up)) {
240 		if (ZS_TX_ACTIVE(up)) {
241 			up->flags |= IP22ZILOG_FLAG_REGS_HELD;
242 		} else {
243 			__load_zsregs(channel, up->curregs);
244 		}
245 	}
246 }
247 
248 #define Rx_BRK 0x0100                   /* BREAK event software flag.  */
249 #define Rx_SYS 0x0200                   /* SysRq event software flag.  */
250 
251 static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
252 						  struct zilog_channel *channel)
253 {
254 	unsigned char ch, flag;
255 	unsigned int r1;
256 	bool push = up->port.state != NULL;
257 
258 	for (;;) {
259 		ch = readb(&channel->control);
260 		ZSDELAY();
261 		if (!(ch & Rx_CH_AV))
262 			break;
263 
264 		r1 = read_zsreg(channel, R1);
265 		if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
266 			writeb(ERR_RES, &channel->control);
267 			ZSDELAY();
268 			ZS_WSYNC(channel);
269 		}
270 
271 		ch = readb(&channel->data);
272 		ZSDELAY();
273 
274 		ch &= up->parity_mask;
275 
276 		/* Handle the null char got when BREAK is removed.  */
277 		if (!ch)
278 			r1 |= up->tty_break;
279 
280 		/* A real serial line, record the character and status.  */
281 		flag = TTY_NORMAL;
282 		up->port.icount.rx++;
283 		if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) {
284 			up->tty_break = 0;
285 
286 			if (r1 & (Rx_SYS | Rx_BRK)) {
287 				up->port.icount.brk++;
288 				if (r1 & Rx_SYS)
289 					continue;
290 				r1 &= ~(PAR_ERR | CRC_ERR);
291 			}
292 			else if (r1 & PAR_ERR)
293 				up->port.icount.parity++;
294 			else if (r1 & CRC_ERR)
295 				up->port.icount.frame++;
296 			if (r1 & Rx_OVR)
297 				up->port.icount.overrun++;
298 			r1 &= up->port.read_status_mask;
299 			if (r1 & Rx_BRK)
300 				flag = TTY_BREAK;
301 			else if (r1 & PAR_ERR)
302 				flag = TTY_PARITY;
303 			else if (r1 & CRC_ERR)
304 				flag = TTY_FRAME;
305 		}
306 
307 		if (uart_handle_sysrq_char(&up->port, ch))
308 			continue;
309 
310 		if (push)
311 			uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);
312 	}
313 	return push;
314 }
315 
316 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
317 				   struct zilog_channel *channel)
318 {
319 	unsigned char status;
320 
321 	status = readb(&channel->control);
322 	ZSDELAY();
323 
324 	writeb(RES_EXT_INT, &channel->control);
325 	ZSDELAY();
326 	ZS_WSYNC(channel);
327 
328 	if (up->curregs[R15] & BRKIE) {
329 		if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {
330 			if (uart_handle_break(&up->port))
331 				up->tty_break = Rx_SYS;
332 			else
333 				up->tty_break = Rx_BRK;
334 		}
335 	}
336 
337 	if (ZS_WANTS_MODEM_STATUS(up)) {
338 		if (status & SYNC)
339 			up->port.icount.dsr++;
340 
341 		/* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
342 		 * But it does not tell us which bit has changed, we have to keep
343 		 * track of this ourselves.
344 		 */
345 		if ((status ^ up->prev_status) ^ DCD)
346 			uart_handle_dcd_change(&up->port,
347 					       (status & DCD));
348 		if ((status ^ up->prev_status) ^ CTS)
349 			uart_handle_cts_change(&up->port,
350 					       (status & CTS));
351 
352 		wake_up_interruptible(&up->port.state->port.delta_msr_wait);
353 	}
354 
355 	up->prev_status = status;
356 }
357 
358 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
359 				    struct zilog_channel *channel)
360 {
361 	struct circ_buf *xmit;
362 
363 	if (ZS_IS_CONS(up)) {
364 		unsigned char status = readb(&channel->control);
365 		ZSDELAY();
366 
367 		/* TX still busy?  Just wait for the next TX done interrupt.
368 		 *
369 		 * It can occur because of how we do serial console writes.  It would
370 		 * be nice to transmit console writes just like we normally would for
371 		 * a TTY line. (ie. buffered and TX interrupt driven).  That is not
372 		 * easy because console writes cannot sleep.  One solution might be
373 		 * to poll on enough port->xmit space becoming free.  -DaveM
374 		 */
375 		if (!(status & Tx_BUF_EMP))
376 			return;
377 	}
378 
379 	up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
380 
381 	if (ZS_REGS_HELD(up)) {
382 		__load_zsregs(channel, up->curregs);
383 		up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
384 	}
385 
386 	if (ZS_TX_STOPPED(up)) {
387 		up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
388 		goto ack_tx_int;
389 	}
390 
391 	if (up->port.x_char) {
392 		up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
393 		writeb(up->port.x_char, &channel->data);
394 		ZSDELAY();
395 		ZS_WSYNC(channel);
396 
397 		up->port.icount.tx++;
398 		up->port.x_char = 0;
399 		return;
400 	}
401 
402 	if (up->port.state == NULL)
403 		goto ack_tx_int;
404 	xmit = &up->port.state->xmit;
405 	if (uart_circ_empty(xmit))
406 		goto ack_tx_int;
407 	if (uart_tx_stopped(&up->port))
408 		goto ack_tx_int;
409 
410 	up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
411 	writeb(xmit->buf[xmit->tail], &channel->data);
412 	ZSDELAY();
413 	ZS_WSYNC(channel);
414 
415 	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
416 	up->port.icount.tx++;
417 
418 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
419 		uart_write_wakeup(&up->port);
420 
421 	return;
422 
423 ack_tx_int:
424 	writeb(RES_Tx_P, &channel->control);
425 	ZSDELAY();
426 	ZS_WSYNC(channel);
427 }
428 
429 static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
430 {
431 	struct uart_ip22zilog_port *up = dev_id;
432 
433 	while (up) {
434 		struct zilog_channel *channel
435 			= ZILOG_CHANNEL_FROM_PORT(&up->port);
436 		unsigned char r3;
437 		bool push = false;
438 
439 		spin_lock(&up->port.lock);
440 		r3 = read_zsreg(channel, R3);
441 
442 		/* Channel A */
443 		if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
444 			writeb(RES_H_IUS, &channel->control);
445 			ZSDELAY();
446 			ZS_WSYNC(channel);
447 
448 			if (r3 & CHARxIP)
449 				push = ip22zilog_receive_chars(up, channel);
450 			if (r3 & CHAEXT)
451 				ip22zilog_status_handle(up, channel);
452 			if (r3 & CHATxIP)
453 				ip22zilog_transmit_chars(up, channel);
454 		}
455 		spin_unlock(&up->port.lock);
456 
457 		if (push)
458 			tty_flip_buffer_push(&up->port.state->port);
459 
460 		/* Channel B */
461 		up = up->next;
462 		channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
463 		push = false;
464 
465 		spin_lock(&up->port.lock);
466 		if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
467 			writeb(RES_H_IUS, &channel->control);
468 			ZSDELAY();
469 			ZS_WSYNC(channel);
470 
471 			if (r3 & CHBRxIP)
472 				push = ip22zilog_receive_chars(up, channel);
473 			if (r3 & CHBEXT)
474 				ip22zilog_status_handle(up, channel);
475 			if (r3 & CHBTxIP)
476 				ip22zilog_transmit_chars(up, channel);
477 		}
478 		spin_unlock(&up->port.lock);
479 
480 		if (push)
481 			tty_flip_buffer_push(&up->port.state->port);
482 
483 		up = up->next;
484 	}
485 
486 	return IRQ_HANDLED;
487 }
488 
489 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
490  * port lock, it is acquired here.
491  */
492 static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
493 {
494 	struct zilog_channel *channel;
495 	unsigned char status;
496 
497 	channel = ZILOG_CHANNEL_FROM_PORT(port);
498 	status = readb(&channel->control);
499 	ZSDELAY();
500 
501 	return status;
502 }
503 
504 /* The port lock is not held.  */
505 static unsigned int ip22zilog_tx_empty(struct uart_port *port)
506 {
507 	unsigned long flags;
508 	unsigned char status;
509 	unsigned int ret;
510 
511 	spin_lock_irqsave(&port->lock, flags);
512 
513 	status = ip22zilog_read_channel_status(port);
514 
515 	spin_unlock_irqrestore(&port->lock, flags);
516 
517 	if (status & Tx_BUF_EMP)
518 		ret = TIOCSER_TEMT;
519 	else
520 		ret = 0;
521 
522 	return ret;
523 }
524 
525 /* The port lock is held and interrupts are disabled.  */
526 static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
527 {
528 	unsigned char status;
529 	unsigned int ret;
530 
531 	status = ip22zilog_read_channel_status(port);
532 
533 	ret = 0;
534 	if (status & DCD)
535 		ret |= TIOCM_CAR;
536 	if (status & SYNC)
537 		ret |= TIOCM_DSR;
538 	if (status & CTS)
539 		ret |= TIOCM_CTS;
540 
541 	return ret;
542 }
543 
544 /* The port lock is held and interrupts are disabled.  */
545 static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
546 {
547 	struct uart_ip22zilog_port *up =
548 		container_of(port, struct uart_ip22zilog_port, port);
549 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
550 	unsigned char set_bits, clear_bits;
551 
552 	set_bits = clear_bits = 0;
553 
554 	if (mctrl & TIOCM_RTS)
555 		set_bits |= RTS;
556 	else
557 		clear_bits |= RTS;
558 	if (mctrl & TIOCM_DTR)
559 		set_bits |= DTR;
560 	else
561 		clear_bits |= DTR;
562 
563 	/* NOTE: Not subject to 'transmitter active' rule.  */
564 	up->curregs[R5] |= set_bits;
565 	up->curregs[R5] &= ~clear_bits;
566 	write_zsreg(channel, R5, up->curregs[R5]);
567 }
568 
569 /* The port lock is held and interrupts are disabled.  */
570 static void ip22zilog_stop_tx(struct uart_port *port)
571 {
572 	struct uart_ip22zilog_port *up =
573 		container_of(port, struct uart_ip22zilog_port, port);
574 
575 	up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
576 }
577 
578 /* The port lock is held and interrupts are disabled.  */
579 static void ip22zilog_start_tx(struct uart_port *port)
580 {
581 	struct uart_ip22zilog_port *up =
582 		container_of(port, struct uart_ip22zilog_port, port);
583 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
584 	unsigned char status;
585 
586 	up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
587 	up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
588 
589 	status = readb(&channel->control);
590 	ZSDELAY();
591 
592 	/* TX busy?  Just wait for the TX done interrupt.  */
593 	if (!(status & Tx_BUF_EMP))
594 		return;
595 
596 	/* Send the first character to jump-start the TX done
597 	 * IRQ sending engine.
598 	 */
599 	if (port->x_char) {
600 		writeb(port->x_char, &channel->data);
601 		ZSDELAY();
602 		ZS_WSYNC(channel);
603 
604 		port->icount.tx++;
605 		port->x_char = 0;
606 	} else {
607 		struct circ_buf *xmit = &port->state->xmit;
608 
609 		if (uart_circ_empty(xmit))
610 			return;
611 		writeb(xmit->buf[xmit->tail], &channel->data);
612 		ZSDELAY();
613 		ZS_WSYNC(channel);
614 
615 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
616 		port->icount.tx++;
617 
618 		if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
619 			uart_write_wakeup(&up->port);
620 	}
621 }
622 
623 /* The port lock is held and interrupts are disabled.  */
624 static void ip22zilog_stop_rx(struct uart_port *port)
625 {
626 	struct uart_ip22zilog_port *up = UART_ZILOG(port);
627 	struct zilog_channel *channel;
628 
629 	if (ZS_IS_CONS(up))
630 		return;
631 
632 	channel = ZILOG_CHANNEL_FROM_PORT(port);
633 
634 	/* Disable all RX interrupts.  */
635 	up->curregs[R1] &= ~RxINT_MASK;
636 	ip22zilog_maybe_update_regs(up, channel);
637 }
638 
639 /* The port lock is held.  */
640 static void ip22zilog_enable_ms(struct uart_port *port)
641 {
642 	struct uart_ip22zilog_port *up =
643 		container_of(port, struct uart_ip22zilog_port, port);
644 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
645 	unsigned char new_reg;
646 
647 	new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
648 	if (new_reg != up->curregs[R15]) {
649 		up->curregs[R15] = new_reg;
650 
651 		/* NOTE: Not subject to 'transmitter active' rule.  */
652 		write_zsreg(channel, R15, up->curregs[R15]);
653 	}
654 }
655 
656 /* The port lock is not held.  */
657 static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
658 {
659 	struct uart_ip22zilog_port *up =
660 		container_of(port, struct uart_ip22zilog_port, port);
661 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
662 	unsigned char set_bits, clear_bits, new_reg;
663 	unsigned long flags;
664 
665 	set_bits = clear_bits = 0;
666 
667 	if (break_state)
668 		set_bits |= SND_BRK;
669 	else
670 		clear_bits |= SND_BRK;
671 
672 	spin_lock_irqsave(&port->lock, flags);
673 
674 	new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
675 	if (new_reg != up->curregs[R5]) {
676 		up->curregs[R5] = new_reg;
677 
678 		/* NOTE: Not subject to 'transmitter active' rule.  */
679 		write_zsreg(channel, R5, up->curregs[R5]);
680 	}
681 
682 	spin_unlock_irqrestore(&port->lock, flags);
683 }
684 
685 static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
686 {
687 	struct zilog_channel *channel;
688 	int i;
689 
690 	if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
691 		return;
692 
693 	/* Let pending transmits finish.  */
694 	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
695 	for (i = 0; i < 1000; i++) {
696 		unsigned char stat = read_zsreg(channel, R1);
697 		if (stat & ALL_SNT)
698 			break;
699 		udelay(100);
700 	}
701 
702 	if (!ZS_IS_CHANNEL_A(up)) {
703 		up++;
704 		channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
705 	}
706 	write_zsreg(channel, R9, FHWRES);
707 	ZSDELAY_LONG();
708 	(void) read_zsreg(channel, R0);
709 
710 	up->flags |= IP22ZILOG_FLAG_RESET_DONE;
711 	up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;
712 }
713 
714 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
715 {
716 	struct zilog_channel *channel;
717 
718 	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
719 
720 	__ip22zilog_reset(up);
721 
722 	__load_zsregs(channel, up->curregs);
723 	/* set master interrupt enable */
724 	write_zsreg(channel, R9, up->curregs[R9]);
725 	up->prev_status = readb(&channel->control);
726 
727 	/* Enable receiver and transmitter.  */
728 	up->curregs[R3] |= RxENAB;
729 	up->curregs[R5] |= TxENAB;
730 
731 	up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
732 	ip22zilog_maybe_update_regs(up, channel);
733 }
734 
735 static int ip22zilog_startup(struct uart_port *port)
736 {
737 	struct uart_ip22zilog_port *up = UART_ZILOG(port);
738 	unsigned long flags;
739 
740 	if (ZS_IS_CONS(up))
741 		return 0;
742 
743 	spin_lock_irqsave(&port->lock, flags);
744 	__ip22zilog_startup(up);
745 	spin_unlock_irqrestore(&port->lock, flags);
746 	return 0;
747 }
748 
749 /*
750  * The test for ZS_IS_CONS is explained by the following e-mail:
751  *****
752  * From: Russell King <rmk@arm.linux.org.uk>
753  * Date: Sun, 8 Dec 2002 10:18:38 +0000
754  *
755  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
756  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
757  * > and I noticed that something is not right with reference
758  * > counting in this case. It seems that when the console
759  * > is open by kernel initially, this is not accounted
760  * > as an open, and uart_startup is not called.
761  *
762  * That is correct.  We are unable to call uart_startup when the serial
763  * console is initialised because it may need to allocate memory (as
764  * request_irq does) and the memory allocators may not have been
765  * initialised.
766  *
767  * 1. initialise the port into a state where it can send characters in the
768  *    console write method.
769  *
770  * 2. don't do the actual hardware shutdown in your shutdown() method (but
771  *    do the normal software shutdown - ie, free irqs etc)
772  *****
773  */
774 static void ip22zilog_shutdown(struct uart_port *port)
775 {
776 	struct uart_ip22zilog_port *up = UART_ZILOG(port);
777 	struct zilog_channel *channel;
778 	unsigned long flags;
779 
780 	if (ZS_IS_CONS(up))
781 		return;
782 
783 	spin_lock_irqsave(&port->lock, flags);
784 
785 	channel = ZILOG_CHANNEL_FROM_PORT(port);
786 
787 	/* Disable receiver and transmitter.  */
788 	up->curregs[R3] &= ~RxENAB;
789 	up->curregs[R5] &= ~TxENAB;
790 
791 	/* Disable all interrupts and BRK assertion.  */
792 	up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
793 	up->curregs[R5] &= ~SND_BRK;
794 	ip22zilog_maybe_update_regs(up, channel);
795 
796 	spin_unlock_irqrestore(&port->lock, flags);
797 }
798 
799 /* Shared by TTY driver and serial console setup.  The port lock is held
800  * and local interrupts are disabled.
801  */
802 static void
803 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
804 		       unsigned int iflag, int brg)
805 {
806 
807 	up->curregs[R10] = NRZ;
808 	up->curregs[R11] = TCBR | RCBR;
809 
810 	/* Program BAUD and clock source. */
811 	up->curregs[R4] &= ~XCLK_MASK;
812 	up->curregs[R4] |= X16CLK;
813 	up->curregs[R12] = brg & 0xff;
814 	up->curregs[R13] = (brg >> 8) & 0xff;
815 	up->curregs[R14] = BRENAB;
816 
817 	/* Character size, stop bits, and parity. */
818 	up->curregs[3] &= ~RxN_MASK;
819 	up->curregs[5] &= ~TxN_MASK;
820 	switch (cflag & CSIZE) {
821 	case CS5:
822 		up->curregs[3] |= Rx5;
823 		up->curregs[5] |= Tx5;
824 		up->parity_mask = 0x1f;
825 		break;
826 	case CS6:
827 		up->curregs[3] |= Rx6;
828 		up->curregs[5] |= Tx6;
829 		up->parity_mask = 0x3f;
830 		break;
831 	case CS7:
832 		up->curregs[3] |= Rx7;
833 		up->curregs[5] |= Tx7;
834 		up->parity_mask = 0x7f;
835 		break;
836 	case CS8:
837 	default:
838 		up->curregs[3] |= Rx8;
839 		up->curregs[5] |= Tx8;
840 		up->parity_mask = 0xff;
841 		break;
842 	}
843 	up->curregs[4] &= ~0x0c;
844 	if (cflag & CSTOPB)
845 		up->curregs[4] |= SB2;
846 	else
847 		up->curregs[4] |= SB1;
848 	if (cflag & PARENB)
849 		up->curregs[4] |= PAR_ENAB;
850 	else
851 		up->curregs[4] &= ~PAR_ENAB;
852 	if (!(cflag & PARODD))
853 		up->curregs[4] |= PAR_EVEN;
854 	else
855 		up->curregs[4] &= ~PAR_EVEN;
856 
857 	up->port.read_status_mask = Rx_OVR;
858 	if (iflag & INPCK)
859 		up->port.read_status_mask |= CRC_ERR | PAR_ERR;
860 	if (iflag & (IGNBRK | BRKINT | PARMRK))
861 		up->port.read_status_mask |= BRK_ABRT;
862 
863 	up->port.ignore_status_mask = 0;
864 	if (iflag & IGNPAR)
865 		up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
866 	if (iflag & IGNBRK) {
867 		up->port.ignore_status_mask |= BRK_ABRT;
868 		if (iflag & IGNPAR)
869 			up->port.ignore_status_mask |= Rx_OVR;
870 	}
871 
872 	if ((cflag & CREAD) == 0)
873 		up->port.ignore_status_mask = 0xff;
874 }
875 
876 /* The port lock is not held.  */
877 static void
878 ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,
879 		      struct ktermios *old)
880 {
881 	struct uart_ip22zilog_port *up =
882 		container_of(port, struct uart_ip22zilog_port, port);
883 	unsigned long flags;
884 	int baud, brg;
885 
886 	baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
887 
888 	spin_lock_irqsave(&up->port.lock, flags);
889 
890 	brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
891 
892 	ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
893 
894 	if (UART_ENABLE_MS(&up->port, termios->c_cflag))
895 		up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
896 	else
897 		up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
898 
899 	ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
900 	uart_update_timeout(port, termios->c_cflag, baud);
901 
902 	spin_unlock_irqrestore(&up->port.lock, flags);
903 }
904 
905 static const char *ip22zilog_type(struct uart_port *port)
906 {
907 	return "IP22-Zilog";
908 }
909 
910 /* We do not request/release mappings of the registers here, this
911  * happens at early serial probe time.
912  */
913 static void ip22zilog_release_port(struct uart_port *port)
914 {
915 }
916 
917 static int ip22zilog_request_port(struct uart_port *port)
918 {
919 	return 0;
920 }
921 
922 /* These do not need to do anything interesting either.  */
923 static void ip22zilog_config_port(struct uart_port *port, int flags)
924 {
925 }
926 
927 /* We do not support letting the user mess with the divisor, IRQ, etc. */
928 static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
929 {
930 	return -EINVAL;
931 }
932 
933 static const struct uart_ops ip22zilog_pops = {
934 	.tx_empty	=	ip22zilog_tx_empty,
935 	.set_mctrl	=	ip22zilog_set_mctrl,
936 	.get_mctrl	=	ip22zilog_get_mctrl,
937 	.stop_tx	=	ip22zilog_stop_tx,
938 	.start_tx	=	ip22zilog_start_tx,
939 	.stop_rx	=	ip22zilog_stop_rx,
940 	.enable_ms	=	ip22zilog_enable_ms,
941 	.break_ctl	=	ip22zilog_break_ctl,
942 	.startup	=	ip22zilog_startup,
943 	.shutdown	=	ip22zilog_shutdown,
944 	.set_termios	=	ip22zilog_set_termios,
945 	.type		=	ip22zilog_type,
946 	.release_port	=	ip22zilog_release_port,
947 	.request_port	=	ip22zilog_request_port,
948 	.config_port	=	ip22zilog_config_port,
949 	.verify_port	=	ip22zilog_verify_port,
950 };
951 
952 static struct uart_ip22zilog_port *ip22zilog_port_table;
953 static struct zilog_layout **ip22zilog_chip_regs;
954 
955 static struct uart_ip22zilog_port *ip22zilog_irq_chain;
956 static int zilog_irq = -1;
957 
958 static void * __init alloc_one_table(unsigned long size)
959 {
960 	return kzalloc(size, GFP_KERNEL);
961 }
962 
963 static void __init ip22zilog_alloc_tables(void)
964 {
965 	ip22zilog_port_table = (struct uart_ip22zilog_port *)
966 		alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));
967 	ip22zilog_chip_regs = (struct zilog_layout **)
968 		alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));
969 
970 	if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {
971 		panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");
972 	}
973 }
974 
975 /* Get the address of the registers for IP22-Zilog instance CHIP.  */
976 static struct zilog_layout * __init get_zs(int chip)
977 {
978 	unsigned long base;
979 
980 	if (chip < 0 || chip >= NUM_IP22ZILOG) {
981 		panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);
982 	}
983 
984 	/* Not probe-able, hard code it. */
985 	base = (unsigned long) &sgioc->uart;
986 
987 	zilog_irq = SGI_SERIAL_IRQ;
988 	request_mem_region(base, 8, "IP22-Zilog");
989 
990 	return (struct zilog_layout *) base;
991 }
992 
993 #define ZS_PUT_CHAR_MAX_DELAY	2000	/* 10 ms */
994 
995 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
996 static void ip22zilog_put_char(struct uart_port *port, int ch)
997 {
998 	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
999 	int loops = ZS_PUT_CHAR_MAX_DELAY;
1000 
1001 	/* This is a timed polling loop so do not switch the explicit
1002 	 * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1003 	 */
1004 	do {
1005 		unsigned char val = readb(&channel->control);
1006 		if (val & Tx_BUF_EMP) {
1007 			ZSDELAY();
1008 			break;
1009 		}
1010 		udelay(5);
1011 	} while (--loops);
1012 
1013 	writeb(ch, &channel->data);
1014 	ZSDELAY();
1015 	ZS_WSYNC(channel);
1016 }
1017 
1018 static void
1019 ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
1020 {
1021 	struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1022 	unsigned long flags;
1023 
1024 	spin_lock_irqsave(&up->port.lock, flags);
1025 	uart_console_write(&up->port, s, count, ip22zilog_put_char);
1026 	udelay(2);
1027 	spin_unlock_irqrestore(&up->port.lock, flags);
1028 }
1029 
1030 static int __init ip22zilog_console_setup(struct console *con, char *options)
1031 {
1032 	struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1033 	unsigned long flags;
1034 	int baud = 9600, bits = 8;
1035 	int parity = 'n';
1036 	int flow = 'n';
1037 
1038 	up->flags |= IP22ZILOG_FLAG_IS_CONS;
1039 
1040 	printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index);
1041 
1042 	spin_lock_irqsave(&up->port.lock, flags);
1043 
1044 	up->curregs[R15] |= BRKIE;
1045 
1046 	__ip22zilog_startup(up);
1047 
1048 	spin_unlock_irqrestore(&up->port.lock, flags);
1049 
1050 	if (options)
1051 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1052 	return uart_set_options(&up->port, con, baud, parity, bits, flow);
1053 }
1054 
1055 static struct uart_driver ip22zilog_reg;
1056 
1057 static struct console ip22zilog_console = {
1058 	.name	=	"ttyS",
1059 	.write	=	ip22zilog_console_write,
1060 	.device	=	uart_console_device,
1061 	.setup	=	ip22zilog_console_setup,
1062 	.flags	=	CON_PRINTBUFFER,
1063 	.index	=	-1,
1064 	.data	=	&ip22zilog_reg,
1065 };
1066 #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */
1067 
1068 static struct uart_driver ip22zilog_reg = {
1069 	.owner		= THIS_MODULE,
1070 	.driver_name	= "serial",
1071 	.dev_name	= "ttyS",
1072 	.major		= TTY_MAJOR,
1073 	.minor		= 64,
1074 	.nr		= NUM_CHANNELS,
1075 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1076 	.cons		= &ip22zilog_console,
1077 #endif
1078 };
1079 
1080 static void __init ip22zilog_prepare(void)
1081 {
1082 	struct uart_ip22zilog_port *up;
1083 	struct zilog_layout *rp;
1084 	int channel, chip;
1085 
1086 	/*
1087 	 * Temporary fix.
1088 	 */
1089 	for (channel = 0; channel < NUM_CHANNELS; channel++)
1090 		spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1091 
1092 	ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];
1093         up = &ip22zilog_port_table[0];
1094 	for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1095 		up[channel].next = &up[channel - 1];
1096 	up[channel].next = NULL;
1097 
1098 	for (chip = 0; chip < NUM_IP22ZILOG; chip++) {
1099 		if (!ip22zilog_chip_regs[chip]) {
1100 			ip22zilog_chip_regs[chip] = rp = get_zs(chip);
1101 
1102 			up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1103 			up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1104 
1105 			/* In theory mapbase is the physical address ...  */
1106 			up[(chip * 2) + 0].port.mapbase =
1107 				(unsigned long) ioremap((unsigned long) &rp->channelB, 8);
1108 			up[(chip * 2) + 1].port.mapbase =
1109 				(unsigned long) ioremap((unsigned long) &rp->channelA, 8);
1110 		}
1111 
1112 		/* Channel A */
1113 		up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1114 		up[(chip * 2) + 0].port.irq = zilog_irq;
1115 		up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1116 		up[(chip * 2) + 0].port.fifosize = 1;
1117 		up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1118 		up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1119 		up[(chip * 2) + 0].port.flags = 0;
1120 		up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1121 		up[(chip * 2) + 0].flags = 0;
1122 
1123 		/* Channel B */
1124 		up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1125 		up[(chip * 2) + 1].port.irq = zilog_irq;
1126 		up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1127 		up[(chip * 2) + 1].port.fifosize = 1;
1128 		up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1129 		up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1130 		up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1131 		up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1132 	}
1133 
1134 	for (channel = 0; channel < NUM_CHANNELS; channel++) {
1135 		struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];
1136 		int brg;
1137 
1138 		/* Normal serial TTY. */
1139 		up->parity_mask = 0xff;
1140 		up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1141 		up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1142 		up->curregs[R3] = RxENAB | Rx8;
1143 		up->curregs[R5] = TxENAB | Tx8;
1144 		up->curregs[R9] = NV | MIE;
1145 		up->curregs[R10] = NRZ;
1146 		up->curregs[R11] = TCBR | RCBR;
1147 		brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1148 		up->curregs[R12] = (brg & 0xff);
1149 		up->curregs[R13] = (brg >> 8) & 0xff;
1150 		up->curregs[R14] = BRENAB;
1151 	}
1152 }
1153 
1154 static int __init ip22zilog_ports_init(void)
1155 {
1156 	int ret;
1157 
1158 	printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1159 
1160 	ip22zilog_prepare();
1161 
1162 	if (request_irq(zilog_irq, ip22zilog_interrupt, 0,
1163 			"IP22-Zilog", ip22zilog_irq_chain)) {
1164 		panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1165 	}
1166 
1167 	ret = uart_register_driver(&ip22zilog_reg);
1168 	if (ret == 0) {
1169 		int i;
1170 
1171 		for (i = 0; i < NUM_CHANNELS; i++) {
1172 			struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1173 
1174 			uart_add_one_port(&ip22zilog_reg, &up->port);
1175 		}
1176 	}
1177 
1178 	return ret;
1179 }
1180 
1181 static int __init ip22zilog_init(void)
1182 {
1183 	/* IP22 Zilog setup is hard coded, no probing to do.  */
1184 	ip22zilog_alloc_tables();
1185 	ip22zilog_ports_init();
1186 
1187 	return 0;
1188 }
1189 
1190 static void __exit ip22zilog_exit(void)
1191 {
1192 	int i;
1193 	struct uart_ip22zilog_port *up;
1194 
1195 	for (i = 0; i < NUM_CHANNELS; i++) {
1196 		up = &ip22zilog_port_table[i];
1197 
1198 		uart_remove_one_port(&ip22zilog_reg, &up->port);
1199 	}
1200 
1201 	/* Free IO mem */
1202 	up = &ip22zilog_port_table[0];
1203 	for (i = 0; i < NUM_IP22ZILOG; i++) {
1204 		if (up[(i * 2) + 0].port.mapbase) {
1205 		   iounmap((void*)up[(i * 2) + 0].port.mapbase);
1206 		   up[(i * 2) + 0].port.mapbase = 0;
1207 		}
1208 		if (up[(i * 2) + 1].port.mapbase) {
1209 			iounmap((void*)up[(i * 2) + 1].port.mapbase);
1210 			up[(i * 2) + 1].port.mapbase = 0;
1211 		}
1212 	}
1213 
1214 	uart_unregister_driver(&ip22zilog_reg);
1215 }
1216 
1217 module_init(ip22zilog_init);
1218 module_exit(ip22zilog_exit);
1219 
1220 /* David wrote it but I'm to blame for the bugs ...  */
1221 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1222 MODULE_DESCRIPTION("SGI Zilog serial port driver");
1223 MODULE_LICENSE("GPL");
1224