1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Motorola/Freescale IMX serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Author: Sascha Hauer <sascha@saschahauer.de> 8 * Copyright (C) 2004 Pengutronix 9 */ 10 11 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12 #define SUPPORT_SYSRQ 13 #endif 14 15 #include <linux/module.h> 16 #include <linux/ioport.h> 17 #include <linux/init.h> 18 #include <linux/console.h> 19 #include <linux/sysrq.h> 20 #include <linux/platform_device.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial_core.h> 24 #include <linux/serial.h> 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/rational.h> 28 #include <linux/slab.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/io.h> 32 #include <linux/dma-mapping.h> 33 34 #include <asm/irq.h> 35 #include <linux/platform_data/serial-imx.h> 36 #include <linux/platform_data/dma-imx.h> 37 38 #include "serial_mctrl_gpio.h" 39 40 /* Register definitions */ 41 #define URXD0 0x0 /* Receiver Register */ 42 #define URTX0 0x40 /* Transmitter Register */ 43 #define UCR1 0x80 /* Control Register 1 */ 44 #define UCR2 0x84 /* Control Register 2 */ 45 #define UCR3 0x88 /* Control Register 3 */ 46 #define UCR4 0x8c /* Control Register 4 */ 47 #define UFCR 0x90 /* FIFO Control Register */ 48 #define USR1 0x94 /* Status Register 1 */ 49 #define USR2 0x98 /* Status Register 2 */ 50 #define UESC 0x9c /* Escape Character Register */ 51 #define UTIM 0xa0 /* Escape Timer Register */ 52 #define UBIR 0xa4 /* BRM Incremental Register */ 53 #define UBMR 0xa8 /* BRM Modulator Register */ 54 #define UBRC 0xac /* Baud Rate Count Register */ 55 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 56 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 57 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 58 59 /* UART Control Register Bit Fields.*/ 60 #define URXD_DUMMY_READ (1<<16) 61 #define URXD_CHARRDY (1<<15) 62 #define URXD_ERR (1<<14) 63 #define URXD_OVRRUN (1<<13) 64 #define URXD_FRMERR (1<<12) 65 #define URXD_BRK (1<<11) 66 #define URXD_PRERR (1<<10) 67 #define URXD_RX_DATA (0xFF<<0) 68 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 69 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 70 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 71 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 72 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 73 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 74 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 75 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 76 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 77 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 78 #define UCR1_SNDBRK (1<<4) /* Send break */ 79 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 80 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 81 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 82 #define UCR1_DOZE (1<<1) /* Doze */ 83 #define UCR1_UARTEN (1<<0) /* UART enabled */ 84 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 85 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 86 #define UCR2_CTSC (1<<13) /* CTS pin control */ 87 #define UCR2_CTS (1<<12) /* Clear to send */ 88 #define UCR2_ESCEN (1<<11) /* Escape enable */ 89 #define UCR2_PREN (1<<8) /* Parity enable */ 90 #define UCR2_PROE (1<<7) /* Parity odd/even */ 91 #define UCR2_STPB (1<<6) /* Stop */ 92 #define UCR2_WS (1<<5) /* Word size */ 93 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 94 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 95 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 96 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 97 #define UCR2_SRST (1<<0) /* SW reset */ 98 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 99 #define UCR3_PARERREN (1<<12) /* Parity enable */ 100 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 101 #define UCR3_DSR (1<<10) /* Data set ready */ 102 #define UCR3_DCD (1<<9) /* Data carrier detect */ 103 #define UCR3_RI (1<<8) /* Ring indicator */ 104 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 105 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 106 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 107 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 108 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 109 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 110 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 111 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 112 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 113 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 114 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 115 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 116 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 117 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 118 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 119 #define UCR4_IRSC (1<<5) /* IR special case */ 120 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 121 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 122 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 123 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 124 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 125 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 126 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 127 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 128 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 129 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 130 #define USR1_RTSS (1<<14) /* RTS pin status */ 131 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 132 #define USR1_RTSD (1<<12) /* RTS delta */ 133 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 134 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 135 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 136 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 137 #define USR1_DTRD (1<<7) /* DTR Delta */ 138 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 139 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 140 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 141 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 142 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 143 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 144 #define USR2_IDLE (1<<12) /* Idle condition */ 145 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 146 #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 147 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 148 #define USR2_WAKE (1<<7) /* Wake */ 149 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 150 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 151 #define USR2_TXDC (1<<3) /* Transmitter complete */ 152 #define USR2_BRCD (1<<2) /* Break condition */ 153 #define USR2_ORE (1<<1) /* Overrun error */ 154 #define USR2_RDR (1<<0) /* Recv data ready */ 155 #define UTS_FRCPERR (1<<13) /* Force parity error */ 156 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 157 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 158 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 159 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 160 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 161 #define UTS_SOFTRST (1<<0) /* Software reset */ 162 163 /* We've been assigned a range on the "Low-density serial ports" major */ 164 #define SERIAL_IMX_MAJOR 207 165 #define MINOR_START 16 166 #define DEV_NAME "ttymxc" 167 168 /* 169 * This determines how often we check the modem status signals 170 * for any change. They generally aren't connected to an IRQ 171 * so we have to poll them. We also check immediately before 172 * filling the TX fifo incase CTS has been dropped. 173 */ 174 #define MCTRL_TIMEOUT (250*HZ/1000) 175 176 #define DRIVER_NAME "IMX-uart" 177 178 #define UART_NR 8 179 180 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 181 enum imx_uart_type { 182 IMX1_UART, 183 IMX21_UART, 184 IMX53_UART, 185 IMX6Q_UART, 186 }; 187 188 /* device type dependent stuff */ 189 struct imx_uart_data { 190 unsigned uts_reg; 191 enum imx_uart_type devtype; 192 }; 193 194 struct imx_port { 195 struct uart_port port; 196 struct timer_list timer; 197 unsigned int old_status; 198 unsigned int have_rtscts:1; 199 unsigned int have_rtsgpio:1; 200 unsigned int dte_mode:1; 201 struct clk *clk_ipg; 202 struct clk *clk_per; 203 const struct imx_uart_data *devdata; 204 205 struct mctrl_gpios *gpios; 206 207 /* shadow registers */ 208 unsigned int ucr1; 209 unsigned int ucr2; 210 unsigned int ucr3; 211 unsigned int ucr4; 212 unsigned int ufcr; 213 214 /* DMA fields */ 215 unsigned int dma_is_enabled:1; 216 unsigned int dma_is_rxing:1; 217 unsigned int dma_is_txing:1; 218 struct dma_chan *dma_chan_rx, *dma_chan_tx; 219 struct scatterlist rx_sgl, tx_sgl[2]; 220 void *rx_buf; 221 struct circ_buf rx_ring; 222 unsigned int rx_periods; 223 dma_cookie_t rx_cookie; 224 unsigned int tx_bytes; 225 unsigned int dma_tx_nents; 226 unsigned int saved_reg[10]; 227 bool context_saved; 228 }; 229 230 struct imx_port_ucrs { 231 unsigned int ucr1; 232 unsigned int ucr2; 233 unsigned int ucr3; 234 }; 235 236 static struct imx_uart_data imx_uart_devdata[] = { 237 [IMX1_UART] = { 238 .uts_reg = IMX1_UTS, 239 .devtype = IMX1_UART, 240 }, 241 [IMX21_UART] = { 242 .uts_reg = IMX21_UTS, 243 .devtype = IMX21_UART, 244 }, 245 [IMX53_UART] = { 246 .uts_reg = IMX21_UTS, 247 .devtype = IMX53_UART, 248 }, 249 [IMX6Q_UART] = { 250 .uts_reg = IMX21_UTS, 251 .devtype = IMX6Q_UART, 252 }, 253 }; 254 255 static const struct platform_device_id imx_uart_devtype[] = { 256 { 257 .name = "imx1-uart", 258 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 259 }, { 260 .name = "imx21-uart", 261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 262 }, { 263 .name = "imx53-uart", 264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 265 }, { 266 .name = "imx6q-uart", 267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 268 }, { 269 /* sentinel */ 270 } 271 }; 272 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 273 274 static const struct of_device_id imx_uart_dt_ids[] = { 275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 276 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 277 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 278 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 279 { /* sentinel */ } 280 }; 281 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 282 283 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 284 { 285 switch (offset) { 286 case UCR1: 287 sport->ucr1 = val; 288 break; 289 case UCR2: 290 sport->ucr2 = val; 291 break; 292 case UCR3: 293 sport->ucr3 = val; 294 break; 295 case UCR4: 296 sport->ucr4 = val; 297 break; 298 case UFCR: 299 sport->ufcr = val; 300 break; 301 default: 302 break; 303 } 304 writel(val, sport->port.membase + offset); 305 } 306 307 static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 308 { 309 switch (offset) { 310 case UCR1: 311 return sport->ucr1; 312 break; 313 case UCR2: 314 /* 315 * UCR2_SRST is the only bit in the cached registers that might 316 * differ from the value that was last written. As it only 317 * automatically becomes one after being cleared, reread 318 * conditionally. 319 */ 320 if (!(sport->ucr2 & UCR2_SRST)) 321 sport->ucr2 = readl(sport->port.membase + offset); 322 return sport->ucr2; 323 break; 324 case UCR3: 325 return sport->ucr3; 326 break; 327 case UCR4: 328 return sport->ucr4; 329 break; 330 case UFCR: 331 return sport->ufcr; 332 break; 333 default: 334 return readl(sport->port.membase + offset); 335 } 336 } 337 338 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 339 { 340 return sport->devdata->uts_reg; 341 } 342 343 static inline int imx_uart_is_imx1(struct imx_port *sport) 344 { 345 return sport->devdata->devtype == IMX1_UART; 346 } 347 348 static inline int imx_uart_is_imx21(struct imx_port *sport) 349 { 350 return sport->devdata->devtype == IMX21_UART; 351 } 352 353 static inline int imx_uart_is_imx53(struct imx_port *sport) 354 { 355 return sport->devdata->devtype == IMX53_UART; 356 } 357 358 static inline int imx_uart_is_imx6q(struct imx_port *sport) 359 { 360 return sport->devdata->devtype == IMX6Q_UART; 361 } 362 /* 363 * Save and restore functions for UCR1, UCR2 and UCR3 registers 364 */ 365 #if defined(CONFIG_SERIAL_IMX_CONSOLE) 366 static void imx_uart_ucrs_save(struct imx_port *sport, 367 struct imx_port_ucrs *ucr) 368 { 369 /* save control registers */ 370 ucr->ucr1 = imx_uart_readl(sport, UCR1); 371 ucr->ucr2 = imx_uart_readl(sport, UCR2); 372 ucr->ucr3 = imx_uart_readl(sport, UCR3); 373 } 374 375 static void imx_uart_ucrs_restore(struct imx_port *sport, 376 struct imx_port_ucrs *ucr) 377 { 378 /* restore control registers */ 379 imx_uart_writel(sport, ucr->ucr1, UCR1); 380 imx_uart_writel(sport, ucr->ucr2, UCR2); 381 imx_uart_writel(sport, ucr->ucr3, UCR3); 382 } 383 #endif 384 385 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 386 { 387 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 388 389 sport->port.mctrl |= TIOCM_RTS; 390 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 391 } 392 393 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 394 { 395 *ucr2 &= ~UCR2_CTSC; 396 *ucr2 |= UCR2_CTS; 397 398 sport->port.mctrl &= ~TIOCM_RTS; 399 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 400 } 401 402 static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2) 403 { 404 *ucr2 |= UCR2_CTSC; 405 } 406 407 /* called with port.lock taken and irqs off */ 408 static void imx_uart_start_rx(struct uart_port *port) 409 { 410 struct imx_port *sport = (struct imx_port *)port; 411 unsigned int ucr1, ucr2; 412 413 ucr1 = imx_uart_readl(sport, UCR1); 414 ucr2 = imx_uart_readl(sport, UCR2); 415 416 ucr2 |= UCR2_RXEN; 417 418 if (sport->dma_is_enabled) { 419 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 420 } else { 421 ucr1 |= UCR1_RRDYEN; 422 ucr2 |= UCR2_ATEN; 423 } 424 425 /* Write UCR2 first as it includes RXEN */ 426 imx_uart_writel(sport, ucr2, UCR2); 427 imx_uart_writel(sport, ucr1, UCR1); 428 } 429 430 /* called with port.lock taken and irqs off */ 431 static void imx_uart_stop_tx(struct uart_port *port) 432 { 433 struct imx_port *sport = (struct imx_port *)port; 434 u32 ucr1; 435 436 /* 437 * We are maybe in the SMP context, so if the DMA TX thread is running 438 * on other cpu, we have to wait for it to finish. 439 */ 440 if (sport->dma_is_txing) 441 return; 442 443 ucr1 = imx_uart_readl(sport, UCR1); 444 imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1); 445 446 /* in rs485 mode disable transmitter if shifter is empty */ 447 if (port->rs485.flags & SER_RS485_ENABLED && 448 imx_uart_readl(sport, USR2) & USR2_TXDC) { 449 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 450 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 451 imx_uart_rts_active(sport, &ucr2); 452 else 453 imx_uart_rts_inactive(sport, &ucr2); 454 imx_uart_writel(sport, ucr2, UCR2); 455 456 imx_uart_start_rx(port); 457 458 ucr4 = imx_uart_readl(sport, UCR4); 459 ucr4 &= ~UCR4_TCEN; 460 imx_uart_writel(sport, ucr4, UCR4); 461 } 462 } 463 464 /* called with port.lock taken and irqs off */ 465 static void imx_uart_stop_rx(struct uart_port *port) 466 { 467 struct imx_port *sport = (struct imx_port *)port; 468 u32 ucr1, ucr2; 469 470 ucr1 = imx_uart_readl(sport, UCR1); 471 ucr2 = imx_uart_readl(sport, UCR2); 472 473 if (sport->dma_is_enabled) { 474 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 475 } else { 476 ucr1 &= ~UCR1_RRDYEN; 477 ucr2 &= ~UCR2_ATEN; 478 } 479 imx_uart_writel(sport, ucr1, UCR1); 480 481 ucr2 &= ~UCR2_RXEN; 482 imx_uart_writel(sport, ucr2, UCR2); 483 } 484 485 /* called with port.lock taken and irqs off */ 486 static void imx_uart_enable_ms(struct uart_port *port) 487 { 488 struct imx_port *sport = (struct imx_port *)port; 489 490 mod_timer(&sport->timer, jiffies); 491 492 mctrl_gpio_enable_ms(sport->gpios); 493 } 494 495 static void imx_uart_dma_tx(struct imx_port *sport); 496 497 /* called with port.lock taken and irqs off */ 498 static inline void imx_uart_transmit_buffer(struct imx_port *sport) 499 { 500 struct circ_buf *xmit = &sport->port.state->xmit; 501 502 if (sport->port.x_char) { 503 /* Send next char */ 504 imx_uart_writel(sport, sport->port.x_char, URTX0); 505 sport->port.icount.tx++; 506 sport->port.x_char = 0; 507 return; 508 } 509 510 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 511 imx_uart_stop_tx(&sport->port); 512 return; 513 } 514 515 if (sport->dma_is_enabled) { 516 u32 ucr1; 517 /* 518 * We've just sent a X-char Ensure the TX DMA is enabled 519 * and the TX IRQ is disabled. 520 **/ 521 ucr1 = imx_uart_readl(sport, UCR1); 522 ucr1 &= ~UCR1_TXMPTYEN; 523 if (sport->dma_is_txing) { 524 ucr1 |= UCR1_TXDMAEN; 525 imx_uart_writel(sport, ucr1, UCR1); 526 } else { 527 imx_uart_writel(sport, ucr1, UCR1); 528 imx_uart_dma_tx(sport); 529 } 530 531 return; 532 } 533 534 while (!uart_circ_empty(xmit) && 535 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 536 /* send xmit->buf[xmit->tail] 537 * out the port here */ 538 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 539 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 540 sport->port.icount.tx++; 541 } 542 543 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 544 uart_write_wakeup(&sport->port); 545 546 if (uart_circ_empty(xmit)) 547 imx_uart_stop_tx(&sport->port); 548 } 549 550 static void imx_uart_dma_tx_callback(void *data) 551 { 552 struct imx_port *sport = data; 553 struct scatterlist *sgl = &sport->tx_sgl[0]; 554 struct circ_buf *xmit = &sport->port.state->xmit; 555 unsigned long flags; 556 u32 ucr1; 557 558 spin_lock_irqsave(&sport->port.lock, flags); 559 560 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 561 562 ucr1 = imx_uart_readl(sport, UCR1); 563 ucr1 &= ~UCR1_TXDMAEN; 564 imx_uart_writel(sport, ucr1, UCR1); 565 566 /* update the stat */ 567 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 568 sport->port.icount.tx += sport->tx_bytes; 569 570 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 571 572 sport->dma_is_txing = 0; 573 574 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 575 uart_write_wakeup(&sport->port); 576 577 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 578 imx_uart_dma_tx(sport); 579 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 580 u32 ucr4 = imx_uart_readl(sport, UCR4); 581 ucr4 |= UCR4_TCEN; 582 imx_uart_writel(sport, ucr4, UCR4); 583 } 584 585 spin_unlock_irqrestore(&sport->port.lock, flags); 586 } 587 588 /* called with port.lock taken and irqs off */ 589 static void imx_uart_dma_tx(struct imx_port *sport) 590 { 591 struct circ_buf *xmit = &sport->port.state->xmit; 592 struct scatterlist *sgl = sport->tx_sgl; 593 struct dma_async_tx_descriptor *desc; 594 struct dma_chan *chan = sport->dma_chan_tx; 595 struct device *dev = sport->port.dev; 596 u32 ucr1, ucr4; 597 int ret; 598 599 if (sport->dma_is_txing) 600 return; 601 602 ucr4 = imx_uart_readl(sport, UCR4); 603 ucr4 &= ~UCR4_TCEN; 604 imx_uart_writel(sport, ucr4, UCR4); 605 606 sport->tx_bytes = uart_circ_chars_pending(xmit); 607 608 if (xmit->tail < xmit->head) { 609 sport->dma_tx_nents = 1; 610 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 611 } else { 612 sport->dma_tx_nents = 2; 613 sg_init_table(sgl, 2); 614 sg_set_buf(sgl, xmit->buf + xmit->tail, 615 UART_XMIT_SIZE - xmit->tail); 616 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 617 } 618 619 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 620 if (ret == 0) { 621 dev_err(dev, "DMA mapping error for TX.\n"); 622 return; 623 } 624 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 625 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 626 if (!desc) { 627 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 628 DMA_TO_DEVICE); 629 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 630 return; 631 } 632 desc->callback = imx_uart_dma_tx_callback; 633 desc->callback_param = sport; 634 635 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 636 uart_circ_chars_pending(xmit)); 637 638 ucr1 = imx_uart_readl(sport, UCR1); 639 ucr1 |= UCR1_TXDMAEN; 640 imx_uart_writel(sport, ucr1, UCR1); 641 642 /* fire it */ 643 sport->dma_is_txing = 1; 644 dmaengine_submit(desc); 645 dma_async_issue_pending(chan); 646 return; 647 } 648 649 /* called with port.lock taken and irqs off */ 650 static void imx_uart_start_tx(struct uart_port *port) 651 { 652 struct imx_port *sport = (struct imx_port *)port; 653 u32 ucr1; 654 655 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 656 return; 657 658 if (port->rs485.flags & SER_RS485_ENABLED) { 659 u32 ucr2; 660 661 ucr2 = imx_uart_readl(sport, UCR2); 662 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 663 imx_uart_rts_active(sport, &ucr2); 664 else 665 imx_uart_rts_inactive(sport, &ucr2); 666 imx_uart_writel(sport, ucr2, UCR2); 667 668 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 669 imx_uart_stop_rx(port); 670 671 /* 672 * Enable transmitter and shifter empty irq only if DMA is off. 673 * In the DMA case this is done in the tx-callback. 674 */ 675 if (!sport->dma_is_enabled) { 676 u32 ucr4 = imx_uart_readl(sport, UCR4); 677 ucr4 |= UCR4_TCEN; 678 imx_uart_writel(sport, ucr4, UCR4); 679 } 680 } 681 682 if (!sport->dma_is_enabled) { 683 ucr1 = imx_uart_readl(sport, UCR1); 684 imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1); 685 } 686 687 if (sport->dma_is_enabled) { 688 if (sport->port.x_char) { 689 /* We have X-char to send, so enable TX IRQ and 690 * disable TX DMA to let TX interrupt to send X-char */ 691 ucr1 = imx_uart_readl(sport, UCR1); 692 ucr1 &= ~UCR1_TXDMAEN; 693 ucr1 |= UCR1_TXMPTYEN; 694 imx_uart_writel(sport, ucr1, UCR1); 695 return; 696 } 697 698 if (!uart_circ_empty(&port->state->xmit) && 699 !uart_tx_stopped(port)) 700 imx_uart_dma_tx(sport); 701 return; 702 } 703 } 704 705 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 706 { 707 struct imx_port *sport = dev_id; 708 u32 usr1; 709 unsigned long flags; 710 711 spin_lock_irqsave(&sport->port.lock, flags); 712 713 imx_uart_writel(sport, USR1_RTSD, USR1); 714 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 715 uart_handle_cts_change(&sport->port, !!usr1); 716 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 717 718 spin_unlock_irqrestore(&sport->port.lock, flags); 719 return IRQ_HANDLED; 720 } 721 722 static irqreturn_t imx_uart_txint(int irq, void *dev_id) 723 { 724 struct imx_port *sport = dev_id; 725 unsigned long flags; 726 727 spin_lock_irqsave(&sport->port.lock, flags); 728 imx_uart_transmit_buffer(sport); 729 spin_unlock_irqrestore(&sport->port.lock, flags); 730 return IRQ_HANDLED; 731 } 732 733 static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 734 { 735 struct imx_port *sport = dev_id; 736 unsigned int rx, flg, ignored = 0; 737 struct tty_port *port = &sport->port.state->port; 738 unsigned long flags; 739 740 spin_lock_irqsave(&sport->port.lock, flags); 741 742 while (imx_uart_readl(sport, USR2) & USR2_RDR) { 743 u32 usr2; 744 745 flg = TTY_NORMAL; 746 sport->port.icount.rx++; 747 748 rx = imx_uart_readl(sport, URXD0); 749 750 usr2 = imx_uart_readl(sport, USR2); 751 if (usr2 & USR2_BRCD) { 752 imx_uart_writel(sport, USR2_BRCD, USR2); 753 if (uart_handle_break(&sport->port)) 754 continue; 755 } 756 757 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 758 continue; 759 760 if (unlikely(rx & URXD_ERR)) { 761 if (rx & URXD_BRK) 762 sport->port.icount.brk++; 763 else if (rx & URXD_PRERR) 764 sport->port.icount.parity++; 765 else if (rx & URXD_FRMERR) 766 sport->port.icount.frame++; 767 if (rx & URXD_OVRRUN) 768 sport->port.icount.overrun++; 769 770 if (rx & sport->port.ignore_status_mask) { 771 if (++ignored > 100) 772 goto out; 773 continue; 774 } 775 776 rx &= (sport->port.read_status_mask | 0xFF); 777 778 if (rx & URXD_BRK) 779 flg = TTY_BREAK; 780 else if (rx & URXD_PRERR) 781 flg = TTY_PARITY; 782 else if (rx & URXD_FRMERR) 783 flg = TTY_FRAME; 784 if (rx & URXD_OVRRUN) 785 flg = TTY_OVERRUN; 786 787 #ifdef SUPPORT_SYSRQ 788 sport->port.sysrq = 0; 789 #endif 790 } 791 792 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 793 goto out; 794 795 if (tty_insert_flip_char(port, rx, flg) == 0) 796 sport->port.icount.buf_overrun++; 797 } 798 799 out: 800 spin_unlock_irqrestore(&sport->port.lock, flags); 801 tty_flip_buffer_push(port); 802 return IRQ_HANDLED; 803 } 804 805 static void imx_uart_clear_rx_errors(struct imx_port *sport); 806 807 /* 808 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 809 */ 810 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 811 { 812 unsigned int tmp = TIOCM_DSR; 813 unsigned usr1 = imx_uart_readl(sport, USR1); 814 unsigned usr2 = imx_uart_readl(sport, USR2); 815 816 if (usr1 & USR1_RTSS) 817 tmp |= TIOCM_CTS; 818 819 /* in DCE mode DCDIN is always 0 */ 820 if (!(usr2 & USR2_DCDIN)) 821 tmp |= TIOCM_CAR; 822 823 if (sport->dte_mode) 824 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 825 tmp |= TIOCM_RI; 826 827 return tmp; 828 } 829 830 /* 831 * Handle any change of modem status signal since we were last called. 832 */ 833 static void imx_uart_mctrl_check(struct imx_port *sport) 834 { 835 unsigned int status, changed; 836 837 status = imx_uart_get_hwmctrl(sport); 838 changed = status ^ sport->old_status; 839 840 if (changed == 0) 841 return; 842 843 sport->old_status = status; 844 845 if (changed & TIOCM_RI && status & TIOCM_RI) 846 sport->port.icount.rng++; 847 if (changed & TIOCM_DSR) 848 sport->port.icount.dsr++; 849 if (changed & TIOCM_CAR) 850 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 851 if (changed & TIOCM_CTS) 852 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 853 854 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 855 } 856 857 static irqreturn_t imx_uart_int(int irq, void *dev_id) 858 { 859 struct imx_port *sport = dev_id; 860 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 861 irqreturn_t ret = IRQ_NONE; 862 863 usr1 = imx_uart_readl(sport, USR1); 864 usr2 = imx_uart_readl(sport, USR2); 865 ucr1 = imx_uart_readl(sport, UCR1); 866 ucr2 = imx_uart_readl(sport, UCR2); 867 ucr3 = imx_uart_readl(sport, UCR3); 868 ucr4 = imx_uart_readl(sport, UCR4); 869 870 /* 871 * Even if a condition is true that can trigger an irq only handle it if 872 * the respective irq source is enabled. This prevents some undesired 873 * actions, for example if a character that sits in the RX FIFO and that 874 * should be fetched via DMA is tried to be fetched using PIO. Or the 875 * receiver is currently off and so reading from URXD0 results in an 876 * exception. So just mask the (raw) status bits for disabled irqs. 877 */ 878 if ((ucr1 & UCR1_RRDYEN) == 0) 879 usr1 &= ~USR1_RRDY; 880 if ((ucr2 & UCR2_ATEN) == 0) 881 usr1 &= ~USR1_AGTIM; 882 if ((ucr1 & UCR1_TXMPTYEN) == 0) 883 usr1 &= ~USR1_TRDY; 884 if ((ucr4 & UCR4_TCEN) == 0) 885 usr2 &= ~USR2_TXDC; 886 if ((ucr3 & UCR3_DTRDEN) == 0) 887 usr1 &= ~USR1_DTRD; 888 if ((ucr1 & UCR1_RTSDEN) == 0) 889 usr1 &= ~USR1_RTSD; 890 if ((ucr3 & UCR3_AWAKEN) == 0) 891 usr1 &= ~USR1_AWAKE; 892 if ((ucr4 & UCR4_OREN) == 0) 893 usr2 &= ~USR2_ORE; 894 895 if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 896 imx_uart_rxint(irq, dev_id); 897 ret = IRQ_HANDLED; 898 } 899 900 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 901 imx_uart_txint(irq, dev_id); 902 ret = IRQ_HANDLED; 903 } 904 905 if (usr1 & USR1_DTRD) { 906 unsigned long flags; 907 908 imx_uart_writel(sport, USR1_DTRD, USR1); 909 910 spin_lock_irqsave(&sport->port.lock, flags); 911 imx_uart_mctrl_check(sport); 912 spin_unlock_irqrestore(&sport->port.lock, flags); 913 914 ret = IRQ_HANDLED; 915 } 916 917 if (usr1 & USR1_RTSD) { 918 imx_uart_rtsint(irq, dev_id); 919 ret = IRQ_HANDLED; 920 } 921 922 if (usr1 & USR1_AWAKE) { 923 imx_uart_writel(sport, USR1_AWAKE, USR1); 924 ret = IRQ_HANDLED; 925 } 926 927 if (usr2 & USR2_ORE) { 928 sport->port.icount.overrun++; 929 imx_uart_writel(sport, USR2_ORE, USR2); 930 ret = IRQ_HANDLED; 931 } 932 933 return ret; 934 } 935 936 /* 937 * Return TIOCSER_TEMT when transmitter is not busy. 938 */ 939 static unsigned int imx_uart_tx_empty(struct uart_port *port) 940 { 941 struct imx_port *sport = (struct imx_port *)port; 942 unsigned int ret; 943 944 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 945 946 /* If the TX DMA is working, return 0. */ 947 if (sport->dma_is_txing) 948 ret = 0; 949 950 return ret; 951 } 952 953 /* called with port.lock taken and irqs off */ 954 static unsigned int imx_uart_get_mctrl(struct uart_port *port) 955 { 956 struct imx_port *sport = (struct imx_port *)port; 957 unsigned int ret = imx_uart_get_hwmctrl(sport); 958 959 mctrl_gpio_get(sport->gpios, &ret); 960 961 return ret; 962 } 963 964 /* called with port.lock taken and irqs off */ 965 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 966 { 967 struct imx_port *sport = (struct imx_port *)port; 968 u32 ucr3, uts; 969 970 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 971 u32 ucr2; 972 973 ucr2 = imx_uart_readl(sport, UCR2); 974 ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 975 if (mctrl & TIOCM_RTS) 976 ucr2 |= UCR2_CTS | UCR2_CTSC; 977 imx_uart_writel(sport, ucr2, UCR2); 978 } 979 980 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 981 if (!(mctrl & TIOCM_DTR)) 982 ucr3 |= UCR3_DSR; 983 imx_uart_writel(sport, ucr3, UCR3); 984 985 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 986 if (mctrl & TIOCM_LOOP) 987 uts |= UTS_LOOP; 988 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 989 990 mctrl_gpio_set(sport->gpios, mctrl); 991 } 992 993 /* 994 * Interrupts always disabled. 995 */ 996 static void imx_uart_break_ctl(struct uart_port *port, int break_state) 997 { 998 struct imx_port *sport = (struct imx_port *)port; 999 unsigned long flags; 1000 u32 ucr1; 1001 1002 spin_lock_irqsave(&sport->port.lock, flags); 1003 1004 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1005 1006 if (break_state != 0) 1007 ucr1 |= UCR1_SNDBRK; 1008 1009 imx_uart_writel(sport, ucr1, UCR1); 1010 1011 spin_unlock_irqrestore(&sport->port.lock, flags); 1012 } 1013 1014 /* 1015 * This is our per-port timeout handler, for checking the 1016 * modem status signals. 1017 */ 1018 static void imx_uart_timeout(struct timer_list *t) 1019 { 1020 struct imx_port *sport = from_timer(sport, t, timer); 1021 unsigned long flags; 1022 1023 if (sport->port.state) { 1024 spin_lock_irqsave(&sport->port.lock, flags); 1025 imx_uart_mctrl_check(sport); 1026 spin_unlock_irqrestore(&sport->port.lock, flags); 1027 1028 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1029 } 1030 } 1031 1032 #define RX_BUF_SIZE (PAGE_SIZE) 1033 1034 /* 1035 * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1036 * [1] the RX DMA buffer is full. 1037 * [2] the aging timer expires 1038 * 1039 * Condition [2] is triggered when a character has been sitting in the FIFO 1040 * for at least 8 byte durations. 1041 */ 1042 static void imx_uart_dma_rx_callback(void *data) 1043 { 1044 struct imx_port *sport = data; 1045 struct dma_chan *chan = sport->dma_chan_rx; 1046 struct scatterlist *sgl = &sport->rx_sgl; 1047 struct tty_port *port = &sport->port.state->port; 1048 struct dma_tx_state state; 1049 struct circ_buf *rx_ring = &sport->rx_ring; 1050 enum dma_status status; 1051 unsigned int w_bytes = 0; 1052 unsigned int r_bytes; 1053 unsigned int bd_size; 1054 1055 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1056 1057 if (status == DMA_ERROR) { 1058 imx_uart_clear_rx_errors(sport); 1059 return; 1060 } 1061 1062 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1063 1064 /* 1065 * The state-residue variable represents the empty space 1066 * relative to the entire buffer. Taking this in consideration 1067 * the head is always calculated base on the buffer total 1068 * length - DMA transaction residue. The UART script from the 1069 * SDMA firmware will jump to the next buffer descriptor, 1070 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 1071 * Taking this in consideration the tail is always at the 1072 * beginning of the buffer descriptor that contains the head. 1073 */ 1074 1075 /* Calculate the head */ 1076 rx_ring->head = sg_dma_len(sgl) - state.residue; 1077 1078 /* Calculate the tail. */ 1079 bd_size = sg_dma_len(sgl) / sport->rx_periods; 1080 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 1081 1082 if (rx_ring->head <= sg_dma_len(sgl) && 1083 rx_ring->head > rx_ring->tail) { 1084 1085 /* Move data from tail to head */ 1086 r_bytes = rx_ring->head - rx_ring->tail; 1087 1088 /* CPU claims ownership of RX DMA buffer */ 1089 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 1090 DMA_FROM_DEVICE); 1091 1092 w_bytes = tty_insert_flip_string(port, 1093 sport->rx_buf + rx_ring->tail, r_bytes); 1094 1095 /* UART retrieves ownership of RX DMA buffer */ 1096 dma_sync_sg_for_device(sport->port.dev, sgl, 1, 1097 DMA_FROM_DEVICE); 1098 1099 if (w_bytes != r_bytes) 1100 sport->port.icount.buf_overrun++; 1101 1102 sport->port.icount.rx += w_bytes; 1103 } else { 1104 WARN_ON(rx_ring->head > sg_dma_len(sgl)); 1105 WARN_ON(rx_ring->head <= rx_ring->tail); 1106 } 1107 } 1108 1109 if (w_bytes) { 1110 tty_flip_buffer_push(port); 1111 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 1112 } 1113 } 1114 1115 /* RX DMA buffer periods */ 1116 #define RX_DMA_PERIODS 4 1117 1118 static int imx_uart_start_rx_dma(struct imx_port *sport) 1119 { 1120 struct scatterlist *sgl = &sport->rx_sgl; 1121 struct dma_chan *chan = sport->dma_chan_rx; 1122 struct device *dev = sport->port.dev; 1123 struct dma_async_tx_descriptor *desc; 1124 int ret; 1125 1126 sport->rx_ring.head = 0; 1127 sport->rx_ring.tail = 0; 1128 sport->rx_periods = RX_DMA_PERIODS; 1129 1130 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1131 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1132 if (ret == 0) { 1133 dev_err(dev, "DMA mapping error for RX.\n"); 1134 return -EINVAL; 1135 } 1136 1137 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 1138 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 1139 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1140 1141 if (!desc) { 1142 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1143 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1144 return -EINVAL; 1145 } 1146 desc->callback = imx_uart_dma_rx_callback; 1147 desc->callback_param = sport; 1148 1149 dev_dbg(dev, "RX: prepare for the DMA.\n"); 1150 sport->dma_is_rxing = 1; 1151 sport->rx_cookie = dmaengine_submit(desc); 1152 dma_async_issue_pending(chan); 1153 return 0; 1154 } 1155 1156 static void imx_uart_clear_rx_errors(struct imx_port *sport) 1157 { 1158 struct tty_port *port = &sport->port.state->port; 1159 u32 usr1, usr2; 1160 1161 usr1 = imx_uart_readl(sport, USR1); 1162 usr2 = imx_uart_readl(sport, USR2); 1163 1164 if (usr2 & USR2_BRCD) { 1165 sport->port.icount.brk++; 1166 imx_uart_writel(sport, USR2_BRCD, USR2); 1167 uart_handle_break(&sport->port); 1168 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 1169 sport->port.icount.buf_overrun++; 1170 tty_flip_buffer_push(port); 1171 } else { 1172 dev_err(sport->port.dev, "DMA transaction error.\n"); 1173 if (usr1 & USR1_FRAMERR) { 1174 sport->port.icount.frame++; 1175 imx_uart_writel(sport, USR1_FRAMERR, USR1); 1176 } else if (usr1 & USR1_PARITYERR) { 1177 sport->port.icount.parity++; 1178 imx_uart_writel(sport, USR1_PARITYERR, USR1); 1179 } 1180 } 1181 1182 if (usr2 & USR2_ORE) { 1183 sport->port.icount.overrun++; 1184 imx_uart_writel(sport, USR2_ORE, USR2); 1185 } 1186 1187 } 1188 1189 #define TXTL_DEFAULT 2 /* reset default */ 1190 #define RXTL_DEFAULT 1 /* reset default */ 1191 #define TXTL_DMA 8 /* DMA burst setting */ 1192 #define RXTL_DMA 9 /* DMA burst setting */ 1193 1194 static void imx_uart_setup_ufcr(struct imx_port *sport, 1195 unsigned char txwl, unsigned char rxwl) 1196 { 1197 unsigned int val; 1198 1199 /* set receiver / transmitter trigger level */ 1200 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1201 val |= txwl << UFCR_TXTL_SHF | rxwl; 1202 imx_uart_writel(sport, val, UFCR); 1203 } 1204 1205 static void imx_uart_dma_exit(struct imx_port *sport) 1206 { 1207 if (sport->dma_chan_rx) { 1208 dmaengine_terminate_sync(sport->dma_chan_rx); 1209 dma_release_channel(sport->dma_chan_rx); 1210 sport->dma_chan_rx = NULL; 1211 sport->rx_cookie = -EINVAL; 1212 kfree(sport->rx_buf); 1213 sport->rx_buf = NULL; 1214 } 1215 1216 if (sport->dma_chan_tx) { 1217 dmaengine_terminate_sync(sport->dma_chan_tx); 1218 dma_release_channel(sport->dma_chan_tx); 1219 sport->dma_chan_tx = NULL; 1220 } 1221 } 1222 1223 static int imx_uart_dma_init(struct imx_port *sport) 1224 { 1225 struct dma_slave_config slave_config = {}; 1226 struct device *dev = sport->port.dev; 1227 int ret; 1228 1229 /* Prepare for RX : */ 1230 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1231 if (!sport->dma_chan_rx) { 1232 dev_dbg(dev, "cannot get the DMA channel.\n"); 1233 ret = -EINVAL; 1234 goto err; 1235 } 1236 1237 slave_config.direction = DMA_DEV_TO_MEM; 1238 slave_config.src_addr = sport->port.mapbase + URXD0; 1239 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1240 /* one byte less than the watermark level to enable the aging timer */ 1241 slave_config.src_maxburst = RXTL_DMA - 1; 1242 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1243 if (ret) { 1244 dev_err(dev, "error in RX dma configuration.\n"); 1245 goto err; 1246 } 1247 1248 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1249 if (!sport->rx_buf) { 1250 ret = -ENOMEM; 1251 goto err; 1252 } 1253 sport->rx_ring.buf = sport->rx_buf; 1254 1255 /* Prepare for TX : */ 1256 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1257 if (!sport->dma_chan_tx) { 1258 dev_err(dev, "cannot get the TX DMA channel!\n"); 1259 ret = -EINVAL; 1260 goto err; 1261 } 1262 1263 slave_config.direction = DMA_MEM_TO_DEV; 1264 slave_config.dst_addr = sport->port.mapbase + URTX0; 1265 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1266 slave_config.dst_maxburst = TXTL_DMA; 1267 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1268 if (ret) { 1269 dev_err(dev, "error in TX dma configuration."); 1270 goto err; 1271 } 1272 1273 return 0; 1274 err: 1275 imx_uart_dma_exit(sport); 1276 return ret; 1277 } 1278 1279 static void imx_uart_enable_dma(struct imx_port *sport) 1280 { 1281 u32 ucr1; 1282 1283 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1284 1285 /* set UCR1 */ 1286 ucr1 = imx_uart_readl(sport, UCR1); 1287 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 1288 imx_uart_writel(sport, ucr1, UCR1); 1289 1290 sport->dma_is_enabled = 1; 1291 } 1292 1293 static void imx_uart_disable_dma(struct imx_port *sport) 1294 { 1295 u32 ucr1; 1296 1297 /* clear UCR1 */ 1298 ucr1 = imx_uart_readl(sport, UCR1); 1299 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 1300 imx_uart_writel(sport, ucr1, UCR1); 1301 1302 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1303 1304 sport->dma_is_enabled = 0; 1305 } 1306 1307 /* half the RX buffer size */ 1308 #define CTSTL 16 1309 1310 static int imx_uart_startup(struct uart_port *port) 1311 { 1312 struct imx_port *sport = (struct imx_port *)port; 1313 int retval, i; 1314 unsigned long flags; 1315 int dma_is_inited = 0; 1316 u32 ucr1, ucr2, ucr4; 1317 1318 retval = clk_prepare_enable(sport->clk_per); 1319 if (retval) 1320 return retval; 1321 retval = clk_prepare_enable(sport->clk_ipg); 1322 if (retval) { 1323 clk_disable_unprepare(sport->clk_per); 1324 return retval; 1325 } 1326 1327 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1328 1329 /* disable the DREN bit (Data Ready interrupt enable) before 1330 * requesting IRQs 1331 */ 1332 ucr4 = imx_uart_readl(sport, UCR4); 1333 1334 /* set the trigger level for CTS */ 1335 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1336 ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1337 1338 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1339 1340 /* Can we enable the DMA support? */ 1341 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 1342 dma_is_inited = 1; 1343 1344 spin_lock_irqsave(&sport->port.lock, flags); 1345 /* Reset fifo's and state machines */ 1346 i = 100; 1347 1348 ucr2 = imx_uart_readl(sport, UCR2); 1349 ucr2 &= ~UCR2_SRST; 1350 imx_uart_writel(sport, ucr2, UCR2); 1351 1352 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1353 udelay(1); 1354 1355 /* 1356 * Finally, clear and enable interrupts 1357 */ 1358 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 1359 imx_uart_writel(sport, USR2_ORE, USR2); 1360 1361 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 1362 ucr1 |= UCR1_UARTEN; 1363 if (sport->have_rtscts) 1364 ucr1 |= UCR1_RTSDEN; 1365 1366 imx_uart_writel(sport, ucr1, UCR1); 1367 1368 ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 1369 if (!sport->dma_is_enabled) 1370 ucr4 |= UCR4_OREN; 1371 imx_uart_writel(sport, ucr4, UCR4); 1372 1373 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 1374 ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1375 if (!sport->have_rtscts) 1376 ucr2 |= UCR2_IRTS; 1377 /* 1378 * make sure the edge sensitive RTS-irq is disabled, 1379 * we're using RTSD instead. 1380 */ 1381 if (!imx_uart_is_imx1(sport)) 1382 ucr2 &= ~UCR2_RTSEN; 1383 imx_uart_writel(sport, ucr2, UCR2); 1384 1385 if (!imx_uart_is_imx1(sport)) { 1386 u32 ucr3; 1387 1388 ucr3 = imx_uart_readl(sport, UCR3); 1389 1390 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 1391 1392 if (sport->dte_mode) 1393 /* disable broken interrupts */ 1394 ucr3 &= ~(UCR3_RI | UCR3_DCD); 1395 1396 imx_uart_writel(sport, ucr3, UCR3); 1397 } 1398 1399 /* 1400 * Enable modem status interrupts 1401 */ 1402 imx_uart_enable_ms(&sport->port); 1403 1404 if (dma_is_inited) { 1405 imx_uart_enable_dma(sport); 1406 imx_uart_start_rx_dma(sport); 1407 } else { 1408 ucr1 = imx_uart_readl(sport, UCR1); 1409 ucr1 |= UCR1_RRDYEN; 1410 imx_uart_writel(sport, ucr1, UCR1); 1411 1412 ucr2 = imx_uart_readl(sport, UCR2); 1413 ucr2 |= UCR2_ATEN; 1414 imx_uart_writel(sport, ucr2, UCR2); 1415 } 1416 1417 spin_unlock_irqrestore(&sport->port.lock, flags); 1418 1419 return 0; 1420 } 1421 1422 static void imx_uart_shutdown(struct uart_port *port) 1423 { 1424 struct imx_port *sport = (struct imx_port *)port; 1425 unsigned long flags; 1426 u32 ucr1, ucr2, ucr4; 1427 1428 if (sport->dma_is_enabled) { 1429 dmaengine_terminate_sync(sport->dma_chan_tx); 1430 if (sport->dma_is_txing) { 1431 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 1432 sport->dma_tx_nents, DMA_TO_DEVICE); 1433 sport->dma_is_txing = 0; 1434 } 1435 dmaengine_terminate_sync(sport->dma_chan_rx); 1436 if (sport->dma_is_rxing) { 1437 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1438 1, DMA_FROM_DEVICE); 1439 sport->dma_is_rxing = 0; 1440 } 1441 1442 spin_lock_irqsave(&sport->port.lock, flags); 1443 imx_uart_stop_tx(port); 1444 imx_uart_stop_rx(port); 1445 imx_uart_disable_dma(sport); 1446 spin_unlock_irqrestore(&sport->port.lock, flags); 1447 imx_uart_dma_exit(sport); 1448 } 1449 1450 mctrl_gpio_disable_ms(sport->gpios); 1451 1452 spin_lock_irqsave(&sport->port.lock, flags); 1453 ucr2 = imx_uart_readl(sport, UCR2); 1454 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 1455 imx_uart_writel(sport, ucr2, UCR2); 1456 1457 ucr4 = imx_uart_readl(sport, UCR4); 1458 ucr4 &= ~UCR4_OREN; 1459 imx_uart_writel(sport, ucr4, UCR4); 1460 spin_unlock_irqrestore(&sport->port.lock, flags); 1461 1462 /* 1463 * Stop our timer. 1464 */ 1465 del_timer_sync(&sport->timer); 1466 1467 /* 1468 * Disable all interrupts, port and break condition. 1469 */ 1470 1471 spin_lock_irqsave(&sport->port.lock, flags); 1472 ucr1 = imx_uart_readl(sport, UCR1); 1473 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1474 1475 imx_uart_writel(sport, ucr1, UCR1); 1476 spin_unlock_irqrestore(&sport->port.lock, flags); 1477 1478 clk_disable_unprepare(sport->clk_per); 1479 clk_disable_unprepare(sport->clk_ipg); 1480 } 1481 1482 /* called with port.lock taken and irqs off */ 1483 static void imx_uart_flush_buffer(struct uart_port *port) 1484 { 1485 struct imx_port *sport = (struct imx_port *)port; 1486 struct scatterlist *sgl = &sport->tx_sgl[0]; 1487 u32 ucr2; 1488 int i = 100, ubir, ubmr, uts; 1489 1490 if (!sport->dma_chan_tx) 1491 return; 1492 1493 sport->tx_bytes = 0; 1494 dmaengine_terminate_all(sport->dma_chan_tx); 1495 if (sport->dma_is_txing) { 1496 u32 ucr1; 1497 1498 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1499 DMA_TO_DEVICE); 1500 ucr1 = imx_uart_readl(sport, UCR1); 1501 ucr1 &= ~UCR1_TXDMAEN; 1502 imx_uart_writel(sport, ucr1, UCR1); 1503 sport->dma_is_txing = 0; 1504 } 1505 1506 /* 1507 * According to the Reference Manual description of the UART SRST bit: 1508 * 1509 * "Reset the transmit and receive state machines, 1510 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1511 * and UTS[6-3]". 1512 * 1513 * We don't need to restore the old values from USR1, USR2, URXD and 1514 * UTXD. UBRC is read only, so only save/restore the other three 1515 * registers. 1516 */ 1517 ubir = imx_uart_readl(sport, UBIR); 1518 ubmr = imx_uart_readl(sport, UBMR); 1519 uts = imx_uart_readl(sport, IMX21_UTS); 1520 1521 ucr2 = imx_uart_readl(sport, UCR2); 1522 ucr2 &= ~UCR2_SRST; 1523 imx_uart_writel(sport, ucr2, UCR2); 1524 1525 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1526 udelay(1); 1527 1528 /* Restore the registers */ 1529 imx_uart_writel(sport, ubir, UBIR); 1530 imx_uart_writel(sport, ubmr, UBMR); 1531 imx_uart_writel(sport, uts, IMX21_UTS); 1532 } 1533 1534 static void 1535 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1536 struct ktermios *old) 1537 { 1538 struct imx_port *sport = (struct imx_port *)port; 1539 unsigned long flags; 1540 u32 ucr2, old_ucr1, old_ucr2, ufcr; 1541 unsigned int baud, quot; 1542 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1543 unsigned long div; 1544 unsigned long num, denom; 1545 uint64_t tdiv64; 1546 1547 /* 1548 * We only support CS7 and CS8. 1549 */ 1550 while ((termios->c_cflag & CSIZE) != CS7 && 1551 (termios->c_cflag & CSIZE) != CS8) { 1552 termios->c_cflag &= ~CSIZE; 1553 termios->c_cflag |= old_csize; 1554 old_csize = CS8; 1555 } 1556 1557 if ((termios->c_cflag & CSIZE) == CS8) 1558 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1559 else 1560 ucr2 = UCR2_SRST | UCR2_IRTS; 1561 1562 if (termios->c_cflag & CRTSCTS) { 1563 if (sport->have_rtscts) { 1564 ucr2 &= ~UCR2_IRTS; 1565 1566 if (port->rs485.flags & SER_RS485_ENABLED) { 1567 /* 1568 * RTS is mandatory for rs485 operation, so keep 1569 * it under manual control and keep transmitter 1570 * disabled. 1571 */ 1572 if (port->rs485.flags & 1573 SER_RS485_RTS_AFTER_SEND) 1574 imx_uart_rts_active(sport, &ucr2); 1575 else 1576 imx_uart_rts_inactive(sport, &ucr2); 1577 } else { 1578 imx_uart_rts_auto(sport, &ucr2); 1579 } 1580 } else { 1581 termios->c_cflag &= ~CRTSCTS; 1582 } 1583 } else if (port->rs485.flags & SER_RS485_ENABLED) { 1584 /* disable transmitter */ 1585 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1586 imx_uart_rts_active(sport, &ucr2); 1587 else 1588 imx_uart_rts_inactive(sport, &ucr2); 1589 } 1590 1591 1592 if (termios->c_cflag & CSTOPB) 1593 ucr2 |= UCR2_STPB; 1594 if (termios->c_cflag & PARENB) { 1595 ucr2 |= UCR2_PREN; 1596 if (termios->c_cflag & PARODD) 1597 ucr2 |= UCR2_PROE; 1598 } 1599 1600 del_timer_sync(&sport->timer); 1601 1602 /* 1603 * Ask the core to calculate the divisor for us. 1604 */ 1605 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1606 quot = uart_get_divisor(port, baud); 1607 1608 spin_lock_irqsave(&sport->port.lock, flags); 1609 1610 sport->port.read_status_mask = 0; 1611 if (termios->c_iflag & INPCK) 1612 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1613 if (termios->c_iflag & (BRKINT | PARMRK)) 1614 sport->port.read_status_mask |= URXD_BRK; 1615 1616 /* 1617 * Characters to ignore 1618 */ 1619 sport->port.ignore_status_mask = 0; 1620 if (termios->c_iflag & IGNPAR) 1621 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1622 if (termios->c_iflag & IGNBRK) { 1623 sport->port.ignore_status_mask |= URXD_BRK; 1624 /* 1625 * If we're ignoring parity and break indicators, 1626 * ignore overruns too (for real raw support). 1627 */ 1628 if (termios->c_iflag & IGNPAR) 1629 sport->port.ignore_status_mask |= URXD_OVRRUN; 1630 } 1631 1632 if ((termios->c_cflag & CREAD) == 0) 1633 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1634 1635 /* 1636 * Update the per-port timeout. 1637 */ 1638 uart_update_timeout(port, termios->c_cflag, baud); 1639 1640 /* 1641 * disable interrupts and drain transmitter 1642 */ 1643 old_ucr1 = imx_uart_readl(sport, UCR1); 1644 imx_uart_writel(sport, 1645 old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1646 UCR1); 1647 old_ucr2 = imx_uart_readl(sport, UCR2); 1648 imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2); 1649 1650 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)) 1651 barrier(); 1652 1653 /* then, disable everything */ 1654 imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2); 1655 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1656 1657 /* custom-baudrate handling */ 1658 div = sport->port.uartclk / (baud * 16); 1659 if (baud == 38400 && quot != div) 1660 baud = sport->port.uartclk / (quot * 16); 1661 1662 div = sport->port.uartclk / (baud * 16); 1663 if (div > 7) 1664 div = 7; 1665 if (!div) 1666 div = 1; 1667 1668 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1669 1 << 16, 1 << 16, &num, &denom); 1670 1671 tdiv64 = sport->port.uartclk; 1672 tdiv64 *= num; 1673 do_div(tdiv64, denom * 16 * div); 1674 tty_termios_encode_baud_rate(termios, 1675 (speed_t)tdiv64, (speed_t)tdiv64); 1676 1677 num -= 1; 1678 denom -= 1; 1679 1680 ufcr = imx_uart_readl(sport, UFCR); 1681 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1682 imx_uart_writel(sport, ufcr, UFCR); 1683 1684 imx_uart_writel(sport, num, UBIR); 1685 imx_uart_writel(sport, denom, UBMR); 1686 1687 if (!imx_uart_is_imx1(sport)) 1688 imx_uart_writel(sport, sport->port.uartclk / div / 1000, 1689 IMX21_ONEMS); 1690 1691 imx_uart_writel(sport, old_ucr1, UCR1); 1692 1693 /* set the parity, stop bits and data size */ 1694 imx_uart_writel(sport, ucr2 | old_ucr2, UCR2); 1695 1696 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1697 imx_uart_enable_ms(&sport->port); 1698 1699 spin_unlock_irqrestore(&sport->port.lock, flags); 1700 } 1701 1702 static const char *imx_uart_type(struct uart_port *port) 1703 { 1704 struct imx_port *sport = (struct imx_port *)port; 1705 1706 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1707 } 1708 1709 /* 1710 * Configure/autoconfigure the port. 1711 */ 1712 static void imx_uart_config_port(struct uart_port *port, int flags) 1713 { 1714 struct imx_port *sport = (struct imx_port *)port; 1715 1716 if (flags & UART_CONFIG_TYPE) 1717 sport->port.type = PORT_IMX; 1718 } 1719 1720 /* 1721 * Verify the new serial_struct (for TIOCSSERIAL). 1722 * The only change we allow are to the flags and type, and 1723 * even then only between PORT_IMX and PORT_UNKNOWN 1724 */ 1725 static int 1726 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1727 { 1728 struct imx_port *sport = (struct imx_port *)port; 1729 int ret = 0; 1730 1731 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1732 ret = -EINVAL; 1733 if (sport->port.irq != ser->irq) 1734 ret = -EINVAL; 1735 if (ser->io_type != UPIO_MEM) 1736 ret = -EINVAL; 1737 if (sport->port.uartclk / 16 != ser->baud_base) 1738 ret = -EINVAL; 1739 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1740 ret = -EINVAL; 1741 if (sport->port.iobase != ser->port) 1742 ret = -EINVAL; 1743 if (ser->hub6 != 0) 1744 ret = -EINVAL; 1745 return ret; 1746 } 1747 1748 #if defined(CONFIG_CONSOLE_POLL) 1749 1750 static int imx_uart_poll_init(struct uart_port *port) 1751 { 1752 struct imx_port *sport = (struct imx_port *)port; 1753 unsigned long flags; 1754 u32 ucr1, ucr2; 1755 int retval; 1756 1757 retval = clk_prepare_enable(sport->clk_ipg); 1758 if (retval) 1759 return retval; 1760 retval = clk_prepare_enable(sport->clk_per); 1761 if (retval) 1762 clk_disable_unprepare(sport->clk_ipg); 1763 1764 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1765 1766 spin_lock_irqsave(&sport->port.lock, flags); 1767 1768 /* 1769 * Be careful about the order of enabling bits here. First enable the 1770 * receiver (UARTEN + RXEN) and only then the corresponding irqs. 1771 * This prevents that a character that already sits in the RX fifo is 1772 * triggering an irq but the try to fetch it from there results in an 1773 * exception because UARTEN or RXEN is still off. 1774 */ 1775 ucr1 = imx_uart_readl(sport, UCR1); 1776 ucr2 = imx_uart_readl(sport, UCR2); 1777 1778 if (imx_uart_is_imx1(sport)) 1779 ucr1 |= IMX1_UCR1_UARTCLKEN; 1780 1781 ucr1 |= UCR1_UARTEN; 1782 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN); 1783 1784 ucr2 |= UCR2_RXEN; 1785 ucr2 &= ~UCR2_ATEN; 1786 1787 imx_uart_writel(sport, ucr1, UCR1); 1788 imx_uart_writel(sport, ucr2, UCR2); 1789 1790 /* now enable irqs */ 1791 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 1792 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 1793 1794 spin_unlock_irqrestore(&sport->port.lock, flags); 1795 1796 return 0; 1797 } 1798 1799 static int imx_uart_poll_get_char(struct uart_port *port) 1800 { 1801 struct imx_port *sport = (struct imx_port *)port; 1802 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 1803 return NO_POLL_CHAR; 1804 1805 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 1806 } 1807 1808 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 1809 { 1810 struct imx_port *sport = (struct imx_port *)port; 1811 unsigned int status; 1812 1813 /* drain */ 1814 do { 1815 status = imx_uart_readl(sport, USR1); 1816 } while (~status & USR1_TRDY); 1817 1818 /* write */ 1819 imx_uart_writel(sport, c, URTX0); 1820 1821 /* flush */ 1822 do { 1823 status = imx_uart_readl(sport, USR2); 1824 } while (~status & USR2_TXDC); 1825 } 1826 #endif 1827 1828 /* called with port.lock taken and irqs off or from .probe without locking */ 1829 static int imx_uart_rs485_config(struct uart_port *port, 1830 struct serial_rs485 *rs485conf) 1831 { 1832 struct imx_port *sport = (struct imx_port *)port; 1833 u32 ucr2; 1834 1835 /* unimplemented */ 1836 rs485conf->delay_rts_before_send = 0; 1837 rs485conf->delay_rts_after_send = 0; 1838 1839 /* RTS is required to control the transmitter */ 1840 if (!sport->have_rtscts && !sport->have_rtsgpio) 1841 rs485conf->flags &= ~SER_RS485_ENABLED; 1842 1843 if (rs485conf->flags & SER_RS485_ENABLED) { 1844 /* Enable receiver if low-active RTS signal is requested */ 1845 if (sport->have_rtscts && !sport->have_rtsgpio && 1846 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 1847 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1848 1849 /* disable transmitter */ 1850 ucr2 = imx_uart_readl(sport, UCR2); 1851 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1852 imx_uart_rts_active(sport, &ucr2); 1853 else 1854 imx_uart_rts_inactive(sport, &ucr2); 1855 imx_uart_writel(sport, ucr2, UCR2); 1856 } 1857 1858 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 1859 if (!(rs485conf->flags & SER_RS485_ENABLED) || 1860 rs485conf->flags & SER_RS485_RX_DURING_TX) 1861 imx_uart_start_rx(port); 1862 1863 port->rs485 = *rs485conf; 1864 1865 return 0; 1866 } 1867 1868 static const struct uart_ops imx_uart_pops = { 1869 .tx_empty = imx_uart_tx_empty, 1870 .set_mctrl = imx_uart_set_mctrl, 1871 .get_mctrl = imx_uart_get_mctrl, 1872 .stop_tx = imx_uart_stop_tx, 1873 .start_tx = imx_uart_start_tx, 1874 .stop_rx = imx_uart_stop_rx, 1875 .enable_ms = imx_uart_enable_ms, 1876 .break_ctl = imx_uart_break_ctl, 1877 .startup = imx_uart_startup, 1878 .shutdown = imx_uart_shutdown, 1879 .flush_buffer = imx_uart_flush_buffer, 1880 .set_termios = imx_uart_set_termios, 1881 .type = imx_uart_type, 1882 .config_port = imx_uart_config_port, 1883 .verify_port = imx_uart_verify_port, 1884 #if defined(CONFIG_CONSOLE_POLL) 1885 .poll_init = imx_uart_poll_init, 1886 .poll_get_char = imx_uart_poll_get_char, 1887 .poll_put_char = imx_uart_poll_put_char, 1888 #endif 1889 }; 1890 1891 static struct imx_port *imx_uart_ports[UART_NR]; 1892 1893 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1894 static void imx_uart_console_putchar(struct uart_port *port, int ch) 1895 { 1896 struct imx_port *sport = (struct imx_port *)port; 1897 1898 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1899 barrier(); 1900 1901 imx_uart_writel(sport, ch, URTX0); 1902 } 1903 1904 /* 1905 * Interrupts are disabled on entering 1906 */ 1907 static void 1908 imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1909 { 1910 struct imx_port *sport = imx_uart_ports[co->index]; 1911 struct imx_port_ucrs old_ucr; 1912 unsigned int ucr1; 1913 unsigned long flags = 0; 1914 int locked = 1; 1915 int retval; 1916 1917 retval = clk_enable(sport->clk_per); 1918 if (retval) 1919 return; 1920 retval = clk_enable(sport->clk_ipg); 1921 if (retval) { 1922 clk_disable(sport->clk_per); 1923 return; 1924 } 1925 1926 if (sport->port.sysrq) 1927 locked = 0; 1928 else if (oops_in_progress) 1929 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1930 else 1931 spin_lock_irqsave(&sport->port.lock, flags); 1932 1933 /* 1934 * First, save UCR1/2/3 and then disable interrupts 1935 */ 1936 imx_uart_ucrs_save(sport, &old_ucr); 1937 ucr1 = old_ucr.ucr1; 1938 1939 if (imx_uart_is_imx1(sport)) 1940 ucr1 |= IMX1_UCR1_UARTCLKEN; 1941 ucr1 |= UCR1_UARTEN; 1942 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1943 1944 imx_uart_writel(sport, ucr1, UCR1); 1945 1946 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1947 1948 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 1949 1950 /* 1951 * Finally, wait for transmitter to become empty 1952 * and restore UCR1/2/3 1953 */ 1954 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1955 1956 imx_uart_ucrs_restore(sport, &old_ucr); 1957 1958 if (locked) 1959 spin_unlock_irqrestore(&sport->port.lock, flags); 1960 1961 clk_disable(sport->clk_ipg); 1962 clk_disable(sport->clk_per); 1963 } 1964 1965 /* 1966 * If the port was already initialised (eg, by a boot loader), 1967 * try to determine the current setup. 1968 */ 1969 static void __init 1970 imx_uart_console_get_options(struct imx_port *sport, int *baud, 1971 int *parity, int *bits) 1972 { 1973 1974 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1975 /* ok, the port was enabled */ 1976 unsigned int ucr2, ubir, ubmr, uartclk; 1977 unsigned int baud_raw; 1978 unsigned int ucfr_rfdiv; 1979 1980 ucr2 = imx_uart_readl(sport, UCR2); 1981 1982 *parity = 'n'; 1983 if (ucr2 & UCR2_PREN) { 1984 if (ucr2 & UCR2_PROE) 1985 *parity = 'o'; 1986 else 1987 *parity = 'e'; 1988 } 1989 1990 if (ucr2 & UCR2_WS) 1991 *bits = 8; 1992 else 1993 *bits = 7; 1994 1995 ubir = imx_uart_readl(sport, UBIR) & 0xffff; 1996 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 1997 1998 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 1999 if (ucfr_rfdiv == 6) 2000 ucfr_rfdiv = 7; 2001 else 2002 ucfr_rfdiv = 6 - ucfr_rfdiv; 2003 2004 uartclk = clk_get_rate(sport->clk_per); 2005 uartclk /= ucfr_rfdiv; 2006 2007 { /* 2008 * The next code provides exact computation of 2009 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2010 * without need of float support or long long division, 2011 * which would be required to prevent 32bit arithmetic overflow 2012 */ 2013 unsigned int mul = ubir + 1; 2014 unsigned int div = 16 * (ubmr + 1); 2015 unsigned int rem = uartclk % div; 2016 2017 baud_raw = (uartclk / div) * mul; 2018 baud_raw += (rem * mul + div / 2) / div; 2019 *baud = (baud_raw + 50) / 100 * 100; 2020 } 2021 2022 if (*baud != baud_raw) 2023 pr_info("Console IMX rounded baud rate from %d to %d\n", 2024 baud_raw, *baud); 2025 } 2026 } 2027 2028 static int __init 2029 imx_uart_console_setup(struct console *co, char *options) 2030 { 2031 struct imx_port *sport; 2032 int baud = 9600; 2033 int bits = 8; 2034 int parity = 'n'; 2035 int flow = 'n'; 2036 int retval; 2037 2038 /* 2039 * Check whether an invalid uart number has been specified, and 2040 * if so, search for the first available port that does have 2041 * console support. 2042 */ 2043 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2044 co->index = 0; 2045 sport = imx_uart_ports[co->index]; 2046 if (sport == NULL) 2047 return -ENODEV; 2048 2049 /* For setting the registers, we only need to enable the ipg clock. */ 2050 retval = clk_prepare_enable(sport->clk_ipg); 2051 if (retval) 2052 goto error_console; 2053 2054 if (options) 2055 uart_parse_options(options, &baud, &parity, &bits, &flow); 2056 else 2057 imx_uart_console_get_options(sport, &baud, &parity, &bits); 2058 2059 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2060 2061 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 2062 2063 clk_disable(sport->clk_ipg); 2064 if (retval) { 2065 clk_unprepare(sport->clk_ipg); 2066 goto error_console; 2067 } 2068 2069 retval = clk_prepare(sport->clk_per); 2070 if (retval) 2071 clk_disable_unprepare(sport->clk_ipg); 2072 2073 error_console: 2074 return retval; 2075 } 2076 2077 static struct uart_driver imx_uart_uart_driver; 2078 static struct console imx_uart_console = { 2079 .name = DEV_NAME, 2080 .write = imx_uart_console_write, 2081 .device = uart_console_device, 2082 .setup = imx_uart_console_setup, 2083 .flags = CON_PRINTBUFFER, 2084 .index = -1, 2085 .data = &imx_uart_uart_driver, 2086 }; 2087 2088 #define IMX_CONSOLE &imx_uart_console 2089 2090 #ifdef CONFIG_OF 2091 static void imx_uart_console_early_putchar(struct uart_port *port, int ch) 2092 { 2093 struct imx_port *sport = (struct imx_port *)port; 2094 2095 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2096 cpu_relax(); 2097 2098 imx_uart_writel(sport, ch, URTX0); 2099 } 2100 2101 static void imx_uart_console_early_write(struct console *con, const char *s, 2102 unsigned count) 2103 { 2104 struct earlycon_device *dev = con->data; 2105 2106 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar); 2107 } 2108 2109 static int __init 2110 imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2111 { 2112 if (!dev->port.membase) 2113 return -ENODEV; 2114 2115 dev->con->write = imx_uart_console_early_write; 2116 2117 return 0; 2118 } 2119 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2120 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2121 #endif 2122 2123 #else 2124 #define IMX_CONSOLE NULL 2125 #endif 2126 2127 static struct uart_driver imx_uart_uart_driver = { 2128 .owner = THIS_MODULE, 2129 .driver_name = DRIVER_NAME, 2130 .dev_name = DEV_NAME, 2131 .major = SERIAL_IMX_MAJOR, 2132 .minor = MINOR_START, 2133 .nr = ARRAY_SIZE(imx_uart_ports), 2134 .cons = IMX_CONSOLE, 2135 }; 2136 2137 #ifdef CONFIG_OF 2138 /* 2139 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 2140 * could successfully get all information from dt or a negative errno. 2141 */ 2142 static int imx_uart_probe_dt(struct imx_port *sport, 2143 struct platform_device *pdev) 2144 { 2145 struct device_node *np = pdev->dev.of_node; 2146 int ret; 2147 2148 sport->devdata = of_device_get_match_data(&pdev->dev); 2149 if (!sport->devdata) 2150 /* no device tree device */ 2151 return 1; 2152 2153 ret = of_alias_get_id(np, "serial"); 2154 if (ret < 0) { 2155 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2156 return ret; 2157 } 2158 sport->port.line = ret; 2159 2160 if (of_get_property(np, "uart-has-rtscts", NULL) || 2161 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 2162 sport->have_rtscts = 1; 2163 2164 if (of_get_property(np, "fsl,dte-mode", NULL)) 2165 sport->dte_mode = 1; 2166 2167 if (of_get_property(np, "rts-gpios", NULL)) 2168 sport->have_rtsgpio = 1; 2169 2170 return 0; 2171 } 2172 #else 2173 static inline int imx_uart_probe_dt(struct imx_port *sport, 2174 struct platform_device *pdev) 2175 { 2176 return 1; 2177 } 2178 #endif 2179 2180 static void imx_uart_probe_pdata(struct imx_port *sport, 2181 struct platform_device *pdev) 2182 { 2183 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 2184 2185 sport->port.line = pdev->id; 2186 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 2187 2188 if (!pdata) 2189 return; 2190 2191 if (pdata->flags & IMXUART_HAVE_RTSCTS) 2192 sport->have_rtscts = 1; 2193 } 2194 2195 static int imx_uart_probe(struct platform_device *pdev) 2196 { 2197 struct imx_port *sport; 2198 void __iomem *base; 2199 int ret = 0; 2200 u32 ucr1; 2201 struct resource *res; 2202 int txirq, rxirq, rtsirq; 2203 2204 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2205 if (!sport) 2206 return -ENOMEM; 2207 2208 ret = imx_uart_probe_dt(sport, pdev); 2209 if (ret > 0) 2210 imx_uart_probe_pdata(sport, pdev); 2211 else if (ret < 0) 2212 return ret; 2213 2214 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 2215 dev_err(&pdev->dev, "serial%d out of range\n", 2216 sport->port.line); 2217 return -EINVAL; 2218 } 2219 2220 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2221 base = devm_ioremap_resource(&pdev->dev, res); 2222 if (IS_ERR(base)) 2223 return PTR_ERR(base); 2224 2225 rxirq = platform_get_irq(pdev, 0); 2226 txirq = platform_get_irq(pdev, 1); 2227 rtsirq = platform_get_irq(pdev, 2); 2228 2229 sport->port.dev = &pdev->dev; 2230 sport->port.mapbase = res->start; 2231 sport->port.membase = base; 2232 sport->port.type = PORT_IMX, 2233 sport->port.iotype = UPIO_MEM; 2234 sport->port.irq = rxirq; 2235 sport->port.fifosize = 32; 2236 sport->port.ops = &imx_uart_pops; 2237 sport->port.rs485_config = imx_uart_rs485_config; 2238 sport->port.flags = UPF_BOOT_AUTOCONF; 2239 timer_setup(&sport->timer, imx_uart_timeout, 0); 2240 2241 sport->gpios = mctrl_gpio_init(&sport->port, 0); 2242 if (IS_ERR(sport->gpios)) 2243 return PTR_ERR(sport->gpios); 2244 2245 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2246 if (IS_ERR(sport->clk_ipg)) { 2247 ret = PTR_ERR(sport->clk_ipg); 2248 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 2249 return ret; 2250 } 2251 2252 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 2253 if (IS_ERR(sport->clk_per)) { 2254 ret = PTR_ERR(sport->clk_per); 2255 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 2256 return ret; 2257 } 2258 2259 sport->port.uartclk = clk_get_rate(sport->clk_per); 2260 2261 /* For register access, we only need to enable the ipg clock. */ 2262 ret = clk_prepare_enable(sport->clk_ipg); 2263 if (ret) { 2264 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 2265 return ret; 2266 } 2267 2268 /* initialize shadow register values */ 2269 sport->ucr1 = readl(sport->port.membase + UCR1); 2270 sport->ucr2 = readl(sport->port.membase + UCR2); 2271 sport->ucr3 = readl(sport->port.membase + UCR3); 2272 sport->ucr4 = readl(sport->port.membase + UCR4); 2273 sport->ufcr = readl(sport->port.membase + UFCR); 2274 2275 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2276 2277 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2278 (!sport->have_rtscts && !sport->have_rtsgpio)) 2279 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2280 2281 /* 2282 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 2283 * signal cannot be set low during transmission in case the 2284 * receiver is off (limitation of the i.MX UART IP). 2285 */ 2286 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2287 sport->have_rtscts && !sport->have_rtsgpio && 2288 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 2289 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 2290 dev_err(&pdev->dev, 2291 "low-active RTS not possible when receiver is off, enabling receiver\n"); 2292 2293 imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2294 2295 /* Disable interrupts before requesting them */ 2296 ucr1 = imx_uart_readl(sport, UCR1); 2297 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 2298 UCR1_TXMPTYEN | UCR1_RTSDEN); 2299 imx_uart_writel(sport, ucr1, UCR1); 2300 2301 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2302 /* 2303 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2304 * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2305 * and DCD (when they are outputs) or enables the respective 2306 * irqs. So set this bit early, i.e. before requesting irqs. 2307 */ 2308 u32 ufcr = imx_uart_readl(sport, UFCR); 2309 if (!(ufcr & UFCR_DCEDTE)) 2310 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2311 2312 /* 2313 * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2314 * enabled later because they cannot be cleared 2315 * (confirmed on i.MX25) which makes them unusable. 2316 */ 2317 imx_uart_writel(sport, 2318 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2319 UCR3); 2320 2321 } else { 2322 u32 ucr3 = UCR3_DSR; 2323 u32 ufcr = imx_uart_readl(sport, UFCR); 2324 if (ufcr & UFCR_DCEDTE) 2325 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 2326 2327 if (!imx_uart_is_imx1(sport)) 2328 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 2329 imx_uart_writel(sport, ucr3, UCR3); 2330 } 2331 2332 clk_disable_unprepare(sport->clk_ipg); 2333 2334 /* 2335 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2336 * chips only have one interrupt. 2337 */ 2338 if (txirq > 0) { 2339 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2340 dev_name(&pdev->dev), sport); 2341 if (ret) { 2342 dev_err(&pdev->dev, "failed to request rx irq: %d\n", 2343 ret); 2344 return ret; 2345 } 2346 2347 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2348 dev_name(&pdev->dev), sport); 2349 if (ret) { 2350 dev_err(&pdev->dev, "failed to request tx irq: %d\n", 2351 ret); 2352 return ret; 2353 } 2354 } else { 2355 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2356 dev_name(&pdev->dev), sport); 2357 if (ret) { 2358 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2359 return ret; 2360 } 2361 } 2362 2363 imx_uart_ports[sport->port.line] = sport; 2364 2365 platform_set_drvdata(pdev, sport); 2366 2367 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2368 } 2369 2370 static int imx_uart_remove(struct platform_device *pdev) 2371 { 2372 struct imx_port *sport = platform_get_drvdata(pdev); 2373 2374 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2375 } 2376 2377 static void imx_uart_restore_context(struct imx_port *sport) 2378 { 2379 if (!sport->context_saved) 2380 return; 2381 2382 imx_uart_writel(sport, sport->saved_reg[4], UFCR); 2383 imx_uart_writel(sport, sport->saved_reg[5], UESC); 2384 imx_uart_writel(sport, sport->saved_reg[6], UTIM); 2385 imx_uart_writel(sport, sport->saved_reg[7], UBIR); 2386 imx_uart_writel(sport, sport->saved_reg[8], UBMR); 2387 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 2388 imx_uart_writel(sport, sport->saved_reg[0], UCR1); 2389 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 2390 imx_uart_writel(sport, sport->saved_reg[2], UCR3); 2391 imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2392 sport->context_saved = false; 2393 } 2394 2395 static void imx_uart_save_context(struct imx_port *sport) 2396 { 2397 /* Save necessary regs */ 2398 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 2399 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 2400 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 2401 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 2402 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 2403 sport->saved_reg[5] = imx_uart_readl(sport, UESC); 2404 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 2405 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 2406 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 2407 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2408 sport->context_saved = true; 2409 } 2410 2411 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2412 { 2413 u32 ucr3; 2414 2415 ucr3 = imx_uart_readl(sport, UCR3); 2416 if (on) { 2417 imx_uart_writel(sport, USR1_AWAKE, USR1); 2418 ucr3 |= UCR3_AWAKEN; 2419 } else { 2420 ucr3 &= ~UCR3_AWAKEN; 2421 } 2422 imx_uart_writel(sport, ucr3, UCR3); 2423 2424 if (sport->have_rtscts) { 2425 u32 ucr1 = imx_uart_readl(sport, UCR1); 2426 if (on) 2427 ucr1 |= UCR1_RTSDEN; 2428 else 2429 ucr1 &= ~UCR1_RTSDEN; 2430 imx_uart_writel(sport, ucr1, UCR1); 2431 } 2432 } 2433 2434 static int imx_uart_suspend_noirq(struct device *dev) 2435 { 2436 struct imx_port *sport = dev_get_drvdata(dev); 2437 2438 imx_uart_save_context(sport); 2439 2440 clk_disable(sport->clk_ipg); 2441 2442 return 0; 2443 } 2444 2445 static int imx_uart_resume_noirq(struct device *dev) 2446 { 2447 struct imx_port *sport = dev_get_drvdata(dev); 2448 int ret; 2449 2450 ret = clk_enable(sport->clk_ipg); 2451 if (ret) 2452 return ret; 2453 2454 imx_uart_restore_context(sport); 2455 2456 return 0; 2457 } 2458 2459 static int imx_uart_suspend(struct device *dev) 2460 { 2461 struct imx_port *sport = dev_get_drvdata(dev); 2462 int ret; 2463 2464 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2465 disable_irq(sport->port.irq); 2466 2467 ret = clk_prepare_enable(sport->clk_ipg); 2468 if (ret) 2469 return ret; 2470 2471 /* enable wakeup from i.MX UART */ 2472 imx_uart_enable_wakeup(sport, true); 2473 2474 return 0; 2475 } 2476 2477 static int imx_uart_resume(struct device *dev) 2478 { 2479 struct imx_port *sport = dev_get_drvdata(dev); 2480 2481 /* disable wakeup from i.MX UART */ 2482 imx_uart_enable_wakeup(sport, false); 2483 2484 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2485 enable_irq(sport->port.irq); 2486 2487 clk_disable_unprepare(sport->clk_ipg); 2488 2489 return 0; 2490 } 2491 2492 static int imx_uart_freeze(struct device *dev) 2493 { 2494 struct imx_port *sport = dev_get_drvdata(dev); 2495 2496 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2497 2498 return clk_prepare_enable(sport->clk_ipg); 2499 } 2500 2501 static int imx_uart_thaw(struct device *dev) 2502 { 2503 struct imx_port *sport = dev_get_drvdata(dev); 2504 2505 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2506 2507 clk_disable_unprepare(sport->clk_ipg); 2508 2509 return 0; 2510 } 2511 2512 static const struct dev_pm_ops imx_uart_pm_ops = { 2513 .suspend_noirq = imx_uart_suspend_noirq, 2514 .resume_noirq = imx_uart_resume_noirq, 2515 .freeze_noirq = imx_uart_suspend_noirq, 2516 .restore_noirq = imx_uart_resume_noirq, 2517 .suspend = imx_uart_suspend, 2518 .resume = imx_uart_resume, 2519 .freeze = imx_uart_freeze, 2520 .thaw = imx_uart_thaw, 2521 .restore = imx_uart_thaw, 2522 }; 2523 2524 static struct platform_driver imx_uart_platform_driver = { 2525 .probe = imx_uart_probe, 2526 .remove = imx_uart_remove, 2527 2528 .id_table = imx_uart_devtype, 2529 .driver = { 2530 .name = "imx-uart", 2531 .of_match_table = imx_uart_dt_ids, 2532 .pm = &imx_uart_pm_ops, 2533 }, 2534 }; 2535 2536 static int __init imx_uart_init(void) 2537 { 2538 int ret = uart_register_driver(&imx_uart_uart_driver); 2539 2540 if (ret) 2541 return ret; 2542 2543 ret = platform_driver_register(&imx_uart_platform_driver); 2544 if (ret != 0) 2545 uart_unregister_driver(&imx_uart_uart_driver); 2546 2547 return ret; 2548 } 2549 2550 static void __exit imx_uart_exit(void) 2551 { 2552 platform_driver_unregister(&imx_uart_platform_driver); 2553 uart_unregister_driver(&imx_uart_uart_driver); 2554 } 2555 2556 module_init(imx_uart_init); 2557 module_exit(imx_uart_exit); 2558 2559 MODULE_AUTHOR("Sascha Hauer"); 2560 MODULE_DESCRIPTION("IMX generic serial port driver"); 2561 MODULE_LICENSE("GPL"); 2562 MODULE_ALIAS("platform:imx-uart"); 2563