1 /* 2 * Driver for Motorola/Freescale IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #include <linux/module.h> 25 #include <linux/ioport.h> 26 #include <linux/init.h> 27 #include <linux/console.h> 28 #include <linux/sysrq.h> 29 #include <linux/platform_device.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial_core.h> 33 #include <linux/serial.h> 34 #include <linux/clk.h> 35 #include <linux/delay.h> 36 #include <linux/rational.h> 37 #include <linux/slab.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/io.h> 41 #include <linux/dma-mapping.h> 42 43 #include <asm/irq.h> 44 #include <linux/platform_data/serial-imx.h> 45 #include <linux/platform_data/dma-imx.h> 46 47 /* Register definitions */ 48 #define URXD0 0x0 /* Receiver Register */ 49 #define URTX0 0x40 /* Transmitter Register */ 50 #define UCR1 0x80 /* Control Register 1 */ 51 #define UCR2 0x84 /* Control Register 2 */ 52 #define UCR3 0x88 /* Control Register 3 */ 53 #define UCR4 0x8c /* Control Register 4 */ 54 #define UFCR 0x90 /* FIFO Control Register */ 55 #define USR1 0x94 /* Status Register 1 */ 56 #define USR2 0x98 /* Status Register 2 */ 57 #define UESC 0x9c /* Escape Character Register */ 58 #define UTIM 0xa0 /* Escape Timer Register */ 59 #define UBIR 0xa4 /* BRM Incremental Register */ 60 #define UBMR 0xa8 /* BRM Modulator Register */ 61 #define UBRC 0xac /* Baud Rate Count Register */ 62 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 63 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 64 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 65 66 /* UART Control Register Bit Fields.*/ 67 #define URXD_DUMMY_READ (1<<16) 68 #define URXD_CHARRDY (1<<15) 69 #define URXD_ERR (1<<14) 70 #define URXD_OVRRUN (1<<13) 71 #define URXD_FRMERR (1<<12) 72 #define URXD_BRK (1<<11) 73 #define URXD_PRERR (1<<10) 74 #define URXD_RX_DATA (0xFF<<0) 75 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 76 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 77 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 78 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 79 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 80 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 81 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 82 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 83 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 84 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 85 #define UCR1_SNDBRK (1<<4) /* Send break */ 86 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 87 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 88 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 89 #define UCR1_DOZE (1<<1) /* Doze */ 90 #define UCR1_UARTEN (1<<0) /* UART enabled */ 91 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 92 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 93 #define UCR2_CTSC (1<<13) /* CTS pin control */ 94 #define UCR2_CTS (1<<12) /* Clear to send */ 95 #define UCR2_ESCEN (1<<11) /* Escape enable */ 96 #define UCR2_PREN (1<<8) /* Parity enable */ 97 #define UCR2_PROE (1<<7) /* Parity odd/even */ 98 #define UCR2_STPB (1<<6) /* Stop */ 99 #define UCR2_WS (1<<5) /* Word size */ 100 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 101 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 102 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 103 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 104 #define UCR2_SRST (1<<0) /* SW reset */ 105 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 106 #define UCR3_PARERREN (1<<12) /* Parity enable */ 107 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 108 #define UCR3_DSR (1<<10) /* Data set ready */ 109 #define UCR3_DCD (1<<9) /* Data carrier detect */ 110 #define UCR3_RI (1<<8) /* Ring indicator */ 111 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 112 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 113 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 114 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 115 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 116 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 117 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 118 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 119 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 120 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 121 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 122 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 123 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 124 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 125 #define UCR4_IRSC (1<<5) /* IR special case */ 126 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 127 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 128 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 129 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 130 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 131 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 132 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 133 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 136 #define USR1_RTSS (1<<14) /* RTS pin status */ 137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 138 #define USR1_RTSD (1<<12) /* RTS delta */ 139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 142 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 143 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 144 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 145 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 146 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 147 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 148 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 149 #define USR2_IDLE (1<<12) /* Idle condition */ 150 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 151 #define USR2_WAKE (1<<7) /* Wake */ 152 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 153 #define USR2_TXDC (1<<3) /* Transmitter complete */ 154 #define USR2_BRCD (1<<2) /* Break condition */ 155 #define USR2_ORE (1<<1) /* Overrun error */ 156 #define USR2_RDR (1<<0) /* Recv data ready */ 157 #define UTS_FRCPERR (1<<13) /* Force parity error */ 158 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 159 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 160 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 161 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 162 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 163 #define UTS_SOFTRST (1<<0) /* Software reset */ 164 165 /* We've been assigned a range on the "Low-density serial ports" major */ 166 #define SERIAL_IMX_MAJOR 207 167 #define MINOR_START 16 168 #define DEV_NAME "ttymxc" 169 170 /* 171 * This determines how often we check the modem status signals 172 * for any change. They generally aren't connected to an IRQ 173 * so we have to poll them. We also check immediately before 174 * filling the TX fifo incase CTS has been dropped. 175 */ 176 #define MCTRL_TIMEOUT (250*HZ/1000) 177 178 #define DRIVER_NAME "IMX-uart" 179 180 #define UART_NR 8 181 182 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 183 enum imx_uart_type { 184 IMX1_UART, 185 IMX21_UART, 186 IMX6Q_UART, 187 }; 188 189 /* device type dependent stuff */ 190 struct imx_uart_data { 191 unsigned uts_reg; 192 enum imx_uart_type devtype; 193 }; 194 195 struct imx_port { 196 struct uart_port port; 197 struct timer_list timer; 198 unsigned int old_status; 199 unsigned int have_rtscts:1; 200 unsigned int dte_mode:1; 201 unsigned int irda_inv_rx:1; 202 unsigned int irda_inv_tx:1; 203 unsigned short trcv_delay; /* transceiver delay */ 204 struct clk *clk_ipg; 205 struct clk *clk_per; 206 const struct imx_uart_data *devdata; 207 208 /* DMA fields */ 209 unsigned int dma_is_inited:1; 210 unsigned int dma_is_enabled:1; 211 unsigned int dma_is_rxing:1; 212 unsigned int dma_is_txing:1; 213 struct dma_chan *dma_chan_rx, *dma_chan_tx; 214 struct scatterlist rx_sgl, tx_sgl[2]; 215 void *rx_buf; 216 unsigned int tx_bytes; 217 unsigned int dma_tx_nents; 218 wait_queue_head_t dma_wait; 219 }; 220 221 struct imx_port_ucrs { 222 unsigned int ucr1; 223 unsigned int ucr2; 224 unsigned int ucr3; 225 }; 226 227 static struct imx_uart_data imx_uart_devdata[] = { 228 [IMX1_UART] = { 229 .uts_reg = IMX1_UTS, 230 .devtype = IMX1_UART, 231 }, 232 [IMX21_UART] = { 233 .uts_reg = IMX21_UTS, 234 .devtype = IMX21_UART, 235 }, 236 [IMX6Q_UART] = { 237 .uts_reg = IMX21_UTS, 238 .devtype = IMX6Q_UART, 239 }, 240 }; 241 242 static const struct platform_device_id imx_uart_devtype[] = { 243 { 244 .name = "imx1-uart", 245 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 246 }, { 247 .name = "imx21-uart", 248 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 249 }, { 250 .name = "imx6q-uart", 251 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 252 }, { 253 /* sentinel */ 254 } 255 }; 256 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 257 258 static const struct of_device_id imx_uart_dt_ids[] = { 259 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 260 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 261 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 262 { /* sentinel */ } 263 }; 264 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 265 266 static inline unsigned uts_reg(struct imx_port *sport) 267 { 268 return sport->devdata->uts_reg; 269 } 270 271 static inline int is_imx1_uart(struct imx_port *sport) 272 { 273 return sport->devdata->devtype == IMX1_UART; 274 } 275 276 static inline int is_imx21_uart(struct imx_port *sport) 277 { 278 return sport->devdata->devtype == IMX21_UART; 279 } 280 281 static inline int is_imx6q_uart(struct imx_port *sport) 282 { 283 return sport->devdata->devtype == IMX6Q_UART; 284 } 285 /* 286 * Save and restore functions for UCR1, UCR2 and UCR3 registers 287 */ 288 #if defined(CONFIG_SERIAL_IMX_CONSOLE) 289 static void imx_port_ucrs_save(struct uart_port *port, 290 struct imx_port_ucrs *ucr) 291 { 292 /* save control registers */ 293 ucr->ucr1 = readl(port->membase + UCR1); 294 ucr->ucr2 = readl(port->membase + UCR2); 295 ucr->ucr3 = readl(port->membase + UCR3); 296 } 297 298 static void imx_port_ucrs_restore(struct uart_port *port, 299 struct imx_port_ucrs *ucr) 300 { 301 /* restore control registers */ 302 writel(ucr->ucr1, port->membase + UCR1); 303 writel(ucr->ucr2, port->membase + UCR2); 304 writel(ucr->ucr3, port->membase + UCR3); 305 } 306 #endif 307 308 /* 309 * Handle any change of modem status signal since we were last called. 310 */ 311 static void imx_mctrl_check(struct imx_port *sport) 312 { 313 unsigned int status, changed; 314 315 status = sport->port.ops->get_mctrl(&sport->port); 316 changed = status ^ sport->old_status; 317 318 if (changed == 0) 319 return; 320 321 sport->old_status = status; 322 323 if (changed & TIOCM_RI) 324 sport->port.icount.rng++; 325 if (changed & TIOCM_DSR) 326 sport->port.icount.dsr++; 327 if (changed & TIOCM_CAR) 328 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 329 if (changed & TIOCM_CTS) 330 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 331 332 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 333 } 334 335 /* 336 * This is our per-port timeout handler, for checking the 337 * modem status signals. 338 */ 339 static void imx_timeout(unsigned long data) 340 { 341 struct imx_port *sport = (struct imx_port *)data; 342 unsigned long flags; 343 344 if (sport->port.state) { 345 spin_lock_irqsave(&sport->port.lock, flags); 346 imx_mctrl_check(sport); 347 spin_unlock_irqrestore(&sport->port.lock, flags); 348 349 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 350 } 351 } 352 353 /* 354 * interrupts disabled on entry 355 */ 356 static void imx_stop_tx(struct uart_port *port) 357 { 358 struct imx_port *sport = (struct imx_port *)port; 359 unsigned long temp; 360 361 /* 362 * We are maybe in the SMP context, so if the DMA TX thread is running 363 * on other cpu, we have to wait for it to finish. 364 */ 365 if (sport->dma_is_enabled && sport->dma_is_txing) 366 return; 367 368 temp = readl(port->membase + UCR1); 369 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); 370 371 /* in rs485 mode disable transmitter if shifter is empty */ 372 if (port->rs485.flags & SER_RS485_ENABLED && 373 readl(port->membase + USR2) & USR2_TXDC) { 374 temp = readl(port->membase + UCR2); 375 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 376 temp &= ~UCR2_CTS; 377 else 378 temp |= UCR2_CTS; 379 writel(temp, port->membase + UCR2); 380 381 temp = readl(port->membase + UCR4); 382 temp &= ~UCR4_TCEN; 383 writel(temp, port->membase + UCR4); 384 } 385 } 386 387 /* 388 * interrupts disabled on entry 389 */ 390 static void imx_stop_rx(struct uart_port *port) 391 { 392 struct imx_port *sport = (struct imx_port *)port; 393 unsigned long temp; 394 395 if (sport->dma_is_enabled && sport->dma_is_rxing) { 396 if (sport->port.suspended) { 397 dmaengine_terminate_all(sport->dma_chan_rx); 398 sport->dma_is_rxing = 0; 399 } else { 400 return; 401 } 402 } 403 404 temp = readl(sport->port.membase + UCR2); 405 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 406 407 /* disable the `Receiver Ready Interrrupt` */ 408 temp = readl(sport->port.membase + UCR1); 409 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 410 } 411 412 /* 413 * Set the modem control timer to fire immediately. 414 */ 415 static void imx_enable_ms(struct uart_port *port) 416 { 417 struct imx_port *sport = (struct imx_port *)port; 418 419 mod_timer(&sport->timer, jiffies); 420 } 421 422 static void imx_dma_tx(struct imx_port *sport); 423 static inline void imx_transmit_buffer(struct imx_port *sport) 424 { 425 struct circ_buf *xmit = &sport->port.state->xmit; 426 unsigned long temp; 427 428 if (sport->port.x_char) { 429 /* Send next char */ 430 writel(sport->port.x_char, sport->port.membase + URTX0); 431 sport->port.icount.tx++; 432 sport->port.x_char = 0; 433 return; 434 } 435 436 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 437 imx_stop_tx(&sport->port); 438 return; 439 } 440 441 if (sport->dma_is_enabled) { 442 /* 443 * We've just sent a X-char Ensure the TX DMA is enabled 444 * and the TX IRQ is disabled. 445 **/ 446 temp = readl(sport->port.membase + UCR1); 447 temp &= ~UCR1_TXMPTYEN; 448 if (sport->dma_is_txing) { 449 temp |= UCR1_TDMAEN; 450 writel(temp, sport->port.membase + UCR1); 451 } else { 452 writel(temp, sport->port.membase + UCR1); 453 imx_dma_tx(sport); 454 } 455 } 456 457 while (!uart_circ_empty(xmit) && 458 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 459 /* send xmit->buf[xmit->tail] 460 * out the port here */ 461 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 462 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 463 sport->port.icount.tx++; 464 } 465 466 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 467 uart_write_wakeup(&sport->port); 468 469 if (uart_circ_empty(xmit)) 470 imx_stop_tx(&sport->port); 471 } 472 473 static void dma_tx_callback(void *data) 474 { 475 struct imx_port *sport = data; 476 struct scatterlist *sgl = &sport->tx_sgl[0]; 477 struct circ_buf *xmit = &sport->port.state->xmit; 478 unsigned long flags; 479 unsigned long temp; 480 481 spin_lock_irqsave(&sport->port.lock, flags); 482 483 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 484 485 temp = readl(sport->port.membase + UCR1); 486 temp &= ~UCR1_TDMAEN; 487 writel(temp, sport->port.membase + UCR1); 488 489 /* update the stat */ 490 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 491 sport->port.icount.tx += sport->tx_bytes; 492 493 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 494 495 sport->dma_is_txing = 0; 496 497 spin_unlock_irqrestore(&sport->port.lock, flags); 498 499 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 500 uart_write_wakeup(&sport->port); 501 502 if (waitqueue_active(&sport->dma_wait)) { 503 wake_up(&sport->dma_wait); 504 dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 505 return; 506 } 507 508 spin_lock_irqsave(&sport->port.lock, flags); 509 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 510 imx_dma_tx(sport); 511 spin_unlock_irqrestore(&sport->port.lock, flags); 512 } 513 514 static void imx_dma_tx(struct imx_port *sport) 515 { 516 struct circ_buf *xmit = &sport->port.state->xmit; 517 struct scatterlist *sgl = sport->tx_sgl; 518 struct dma_async_tx_descriptor *desc; 519 struct dma_chan *chan = sport->dma_chan_tx; 520 struct device *dev = sport->port.dev; 521 unsigned long temp; 522 int ret; 523 524 if (sport->dma_is_txing) 525 return; 526 527 sport->tx_bytes = uart_circ_chars_pending(xmit); 528 529 if (xmit->tail < xmit->head) { 530 sport->dma_tx_nents = 1; 531 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 532 } else { 533 sport->dma_tx_nents = 2; 534 sg_init_table(sgl, 2); 535 sg_set_buf(sgl, xmit->buf + xmit->tail, 536 UART_XMIT_SIZE - xmit->tail); 537 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 538 } 539 540 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 541 if (ret == 0) { 542 dev_err(dev, "DMA mapping error for TX.\n"); 543 return; 544 } 545 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 546 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 547 if (!desc) { 548 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 549 DMA_TO_DEVICE); 550 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 551 return; 552 } 553 desc->callback = dma_tx_callback; 554 desc->callback_param = sport; 555 556 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 557 uart_circ_chars_pending(xmit)); 558 559 temp = readl(sport->port.membase + UCR1); 560 temp |= UCR1_TDMAEN; 561 writel(temp, sport->port.membase + UCR1); 562 563 /* fire it */ 564 sport->dma_is_txing = 1; 565 dmaengine_submit(desc); 566 dma_async_issue_pending(chan); 567 return; 568 } 569 570 /* 571 * interrupts disabled on entry 572 */ 573 static void imx_start_tx(struct uart_port *port) 574 { 575 struct imx_port *sport = (struct imx_port *)port; 576 unsigned long temp; 577 578 if (port->rs485.flags & SER_RS485_ENABLED) { 579 /* enable transmitter and shifter empty irq */ 580 temp = readl(port->membase + UCR2); 581 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 582 temp &= ~UCR2_CTS; 583 else 584 temp |= UCR2_CTS; 585 writel(temp, port->membase + UCR2); 586 587 temp = readl(port->membase + UCR4); 588 temp |= UCR4_TCEN; 589 writel(temp, port->membase + UCR4); 590 } 591 592 if (!sport->dma_is_enabled) { 593 temp = readl(sport->port.membase + UCR1); 594 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 595 } 596 597 if (sport->dma_is_enabled) { 598 if (sport->port.x_char) { 599 /* We have X-char to send, so enable TX IRQ and 600 * disable TX DMA to let TX interrupt to send X-char */ 601 temp = readl(sport->port.membase + UCR1); 602 temp &= ~UCR1_TDMAEN; 603 temp |= UCR1_TXMPTYEN; 604 writel(temp, sport->port.membase + UCR1); 605 return; 606 } 607 608 if (!uart_circ_empty(&port->state->xmit) && 609 !uart_tx_stopped(port)) 610 imx_dma_tx(sport); 611 return; 612 } 613 } 614 615 static irqreturn_t imx_rtsint(int irq, void *dev_id) 616 { 617 struct imx_port *sport = dev_id; 618 unsigned int val; 619 unsigned long flags; 620 621 spin_lock_irqsave(&sport->port.lock, flags); 622 623 writel(USR1_RTSD, sport->port.membase + USR1); 624 val = readl(sport->port.membase + USR1) & USR1_RTSS; 625 uart_handle_cts_change(&sport->port, !!val); 626 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 627 628 spin_unlock_irqrestore(&sport->port.lock, flags); 629 return IRQ_HANDLED; 630 } 631 632 static irqreturn_t imx_txint(int irq, void *dev_id) 633 { 634 struct imx_port *sport = dev_id; 635 unsigned long flags; 636 637 spin_lock_irqsave(&sport->port.lock, flags); 638 imx_transmit_buffer(sport); 639 spin_unlock_irqrestore(&sport->port.lock, flags); 640 return IRQ_HANDLED; 641 } 642 643 static irqreturn_t imx_rxint(int irq, void *dev_id) 644 { 645 struct imx_port *sport = dev_id; 646 unsigned int rx, flg, ignored = 0; 647 struct tty_port *port = &sport->port.state->port; 648 unsigned long flags, temp; 649 650 spin_lock_irqsave(&sport->port.lock, flags); 651 652 while (readl(sport->port.membase + USR2) & USR2_RDR) { 653 flg = TTY_NORMAL; 654 sport->port.icount.rx++; 655 656 rx = readl(sport->port.membase + URXD0); 657 658 temp = readl(sport->port.membase + USR2); 659 if (temp & USR2_BRCD) { 660 writel(USR2_BRCD, sport->port.membase + USR2); 661 if (uart_handle_break(&sport->port)) 662 continue; 663 } 664 665 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 666 continue; 667 668 if (unlikely(rx & URXD_ERR)) { 669 if (rx & URXD_BRK) 670 sport->port.icount.brk++; 671 else if (rx & URXD_PRERR) 672 sport->port.icount.parity++; 673 else if (rx & URXD_FRMERR) 674 sport->port.icount.frame++; 675 if (rx & URXD_OVRRUN) 676 sport->port.icount.overrun++; 677 678 if (rx & sport->port.ignore_status_mask) { 679 if (++ignored > 100) 680 goto out; 681 continue; 682 } 683 684 rx &= (sport->port.read_status_mask | 0xFF); 685 686 if (rx & URXD_BRK) 687 flg = TTY_BREAK; 688 else if (rx & URXD_PRERR) 689 flg = TTY_PARITY; 690 else if (rx & URXD_FRMERR) 691 flg = TTY_FRAME; 692 if (rx & URXD_OVRRUN) 693 flg = TTY_OVERRUN; 694 695 #ifdef SUPPORT_SYSRQ 696 sport->port.sysrq = 0; 697 #endif 698 } 699 700 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 701 goto out; 702 703 tty_insert_flip_char(port, rx, flg); 704 } 705 706 out: 707 spin_unlock_irqrestore(&sport->port.lock, flags); 708 tty_flip_buffer_push(port); 709 return IRQ_HANDLED; 710 } 711 712 static int start_rx_dma(struct imx_port *sport); 713 /* 714 * If the RXFIFO is filled with some data, and then we 715 * arise a DMA operation to receive them. 716 */ 717 static void imx_dma_rxint(struct imx_port *sport) 718 { 719 unsigned long temp; 720 unsigned long flags; 721 722 spin_lock_irqsave(&sport->port.lock, flags); 723 724 temp = readl(sport->port.membase + USR2); 725 if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 726 sport->dma_is_rxing = 1; 727 728 /* disable the `Recerver Ready Interrrupt` */ 729 temp = readl(sport->port.membase + UCR1); 730 temp &= ~(UCR1_RRDYEN); 731 writel(temp, sport->port.membase + UCR1); 732 733 /* tell the DMA to receive the data. */ 734 start_rx_dma(sport); 735 } 736 737 spin_unlock_irqrestore(&sport->port.lock, flags); 738 } 739 740 static irqreturn_t imx_int(int irq, void *dev_id) 741 { 742 struct imx_port *sport = dev_id; 743 unsigned int sts; 744 unsigned int sts2; 745 746 sts = readl(sport->port.membase + USR1); 747 sts2 = readl(sport->port.membase + USR2); 748 749 if (sts & USR1_RRDY) { 750 if (sport->dma_is_enabled) 751 imx_dma_rxint(sport); 752 else 753 imx_rxint(irq, dev_id); 754 } 755 756 if ((sts & USR1_TRDY && 757 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || 758 (sts2 & USR2_TXDC && 759 readl(sport->port.membase + UCR4) & UCR4_TCEN)) 760 imx_txint(irq, dev_id); 761 762 if (sts & USR1_RTSD) 763 imx_rtsint(irq, dev_id); 764 765 if (sts & USR1_AWAKE) 766 writel(USR1_AWAKE, sport->port.membase + USR1); 767 768 if (sts2 & USR2_ORE) { 769 dev_err(sport->port.dev, "Rx FIFO overrun\n"); 770 sport->port.icount.overrun++; 771 writel(USR2_ORE, sport->port.membase + USR2); 772 } 773 774 return IRQ_HANDLED; 775 } 776 777 /* 778 * Return TIOCSER_TEMT when transmitter is not busy. 779 */ 780 static unsigned int imx_tx_empty(struct uart_port *port) 781 { 782 struct imx_port *sport = (struct imx_port *)port; 783 unsigned int ret; 784 785 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 786 787 /* If the TX DMA is working, return 0. */ 788 if (sport->dma_is_enabled && sport->dma_is_txing) 789 ret = 0; 790 791 return ret; 792 } 793 794 /* 795 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 796 */ 797 static unsigned int imx_get_mctrl(struct uart_port *port) 798 { 799 struct imx_port *sport = (struct imx_port *)port; 800 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 801 802 if (readl(sport->port.membase + USR1) & USR1_RTSS) 803 tmp |= TIOCM_CTS; 804 805 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 806 tmp |= TIOCM_RTS; 807 808 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 809 tmp |= TIOCM_LOOP; 810 811 return tmp; 812 } 813 814 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 815 { 816 struct imx_port *sport = (struct imx_port *)port; 817 unsigned long temp; 818 819 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 820 temp = readl(sport->port.membase + UCR2); 821 temp &= ~(UCR2_CTS | UCR2_CTSC); 822 if (mctrl & TIOCM_RTS) 823 temp |= UCR2_CTS | UCR2_CTSC; 824 writel(temp, sport->port.membase + UCR2); 825 } 826 827 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 828 if (mctrl & TIOCM_LOOP) 829 temp |= UTS_LOOP; 830 writel(temp, sport->port.membase + uts_reg(sport)); 831 } 832 833 /* 834 * Interrupts always disabled. 835 */ 836 static void imx_break_ctl(struct uart_port *port, int break_state) 837 { 838 struct imx_port *sport = (struct imx_port *)port; 839 unsigned long flags, temp; 840 841 spin_lock_irqsave(&sport->port.lock, flags); 842 843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 844 845 if (break_state != 0) 846 temp |= UCR1_SNDBRK; 847 848 writel(temp, sport->port.membase + UCR1); 849 850 spin_unlock_irqrestore(&sport->port.lock, flags); 851 } 852 853 #define TXTL 2 /* reset default */ 854 #define RXTL 1 /* reset default */ 855 856 static void imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 857 { 858 unsigned int val; 859 860 /* set receiver / transmitter trigger level */ 861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 862 val |= TXTL << UFCR_TXTL_SHF | RXTL; 863 writel(val, sport->port.membase + UFCR); 864 } 865 866 #define RX_BUF_SIZE (PAGE_SIZE) 867 static void imx_rx_dma_done(struct imx_port *sport) 868 { 869 unsigned long temp; 870 unsigned long flags; 871 872 spin_lock_irqsave(&sport->port.lock, flags); 873 874 /* Enable this interrupt when the RXFIFO is empty. */ 875 temp = readl(sport->port.membase + UCR1); 876 temp |= UCR1_RRDYEN; 877 writel(temp, sport->port.membase + UCR1); 878 879 sport->dma_is_rxing = 0; 880 881 /* Is the shutdown waiting for us? */ 882 if (waitqueue_active(&sport->dma_wait)) 883 wake_up(&sport->dma_wait); 884 885 spin_unlock_irqrestore(&sport->port.lock, flags); 886 } 887 888 /* 889 * There are three kinds of RX DMA interrupts(such as in the MX6Q): 890 * [1] the RX DMA buffer is full. 891 * [2] the Aging timer expires(wait for 8 bytes long) 892 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 893 * 894 * The [2] is trigger when a character was been sitting in the FIFO 895 * meanwhile [3] can wait for 32 bytes long when the RX line is 896 * on IDLE state and RxFIFO is empty. 897 */ 898 static void dma_rx_callback(void *data) 899 { 900 struct imx_port *sport = data; 901 struct dma_chan *chan = sport->dma_chan_rx; 902 struct scatterlist *sgl = &sport->rx_sgl; 903 struct tty_port *port = &sport->port.state->port; 904 struct dma_tx_state state; 905 enum dma_status status; 906 unsigned int count; 907 908 /* unmap it first */ 909 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 910 911 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 912 count = RX_BUF_SIZE - state.residue; 913 914 if (readl(sport->port.membase + USR2) & USR2_IDLE) { 915 /* In condition [3] the SDMA counted up too early */ 916 count--; 917 918 writel(USR2_IDLE, sport->port.membase + USR2); 919 } 920 921 dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 922 923 if (count) { 924 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) 925 tty_insert_flip_string(port, sport->rx_buf, count); 926 tty_flip_buffer_push(port); 927 928 start_rx_dma(sport); 929 } else if (readl(sport->port.membase + USR2) & USR2_RDR) { 930 /* 931 * start rx_dma directly once data in RXFIFO, more efficient 932 * than before: 933 * 1. call imx_rx_dma_done to stop dma if no data received 934 * 2. wait next RDR interrupt to start dma transfer. 935 */ 936 start_rx_dma(sport); 937 } else { 938 /* 939 * stop dma to prevent too many IDLE event trigged if no data 940 * in RXFIFO 941 */ 942 imx_rx_dma_done(sport); 943 } 944 } 945 946 static int start_rx_dma(struct imx_port *sport) 947 { 948 struct scatterlist *sgl = &sport->rx_sgl; 949 struct dma_chan *chan = sport->dma_chan_rx; 950 struct device *dev = sport->port.dev; 951 struct dma_async_tx_descriptor *desc; 952 int ret; 953 954 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 955 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 956 if (ret == 0) { 957 dev_err(dev, "DMA mapping error for RX.\n"); 958 return -EINVAL; 959 } 960 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 961 DMA_PREP_INTERRUPT); 962 if (!desc) { 963 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 964 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 965 return -EINVAL; 966 } 967 desc->callback = dma_rx_callback; 968 desc->callback_param = sport; 969 970 dev_dbg(dev, "RX: prepare for the DMA.\n"); 971 dmaengine_submit(desc); 972 dma_async_issue_pending(chan); 973 return 0; 974 } 975 976 static void imx_uart_dma_exit(struct imx_port *sport) 977 { 978 if (sport->dma_chan_rx) { 979 dma_release_channel(sport->dma_chan_rx); 980 sport->dma_chan_rx = NULL; 981 982 kfree(sport->rx_buf); 983 sport->rx_buf = NULL; 984 } 985 986 if (sport->dma_chan_tx) { 987 dma_release_channel(sport->dma_chan_tx); 988 sport->dma_chan_tx = NULL; 989 } 990 991 sport->dma_is_inited = 0; 992 } 993 994 static int imx_uart_dma_init(struct imx_port *sport) 995 { 996 struct dma_slave_config slave_config = {}; 997 struct device *dev = sport->port.dev; 998 int ret; 999 1000 /* Prepare for RX : */ 1001 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1002 if (!sport->dma_chan_rx) { 1003 dev_dbg(dev, "cannot get the DMA channel.\n"); 1004 ret = -EINVAL; 1005 goto err; 1006 } 1007 1008 slave_config.direction = DMA_DEV_TO_MEM; 1009 slave_config.src_addr = sport->port.mapbase + URXD0; 1010 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1011 slave_config.src_maxburst = RXTL; 1012 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1013 if (ret) { 1014 dev_err(dev, "error in RX dma configuration.\n"); 1015 goto err; 1016 } 1017 1018 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1019 if (!sport->rx_buf) { 1020 ret = -ENOMEM; 1021 goto err; 1022 } 1023 1024 /* Prepare for TX : */ 1025 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1026 if (!sport->dma_chan_tx) { 1027 dev_err(dev, "cannot get the TX DMA channel!\n"); 1028 ret = -EINVAL; 1029 goto err; 1030 } 1031 1032 slave_config.direction = DMA_MEM_TO_DEV; 1033 slave_config.dst_addr = sport->port.mapbase + URTX0; 1034 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1035 slave_config.dst_maxburst = TXTL; 1036 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1037 if (ret) { 1038 dev_err(dev, "error in TX dma configuration."); 1039 goto err; 1040 } 1041 1042 sport->dma_is_inited = 1; 1043 1044 return 0; 1045 err: 1046 imx_uart_dma_exit(sport); 1047 return ret; 1048 } 1049 1050 static void imx_enable_dma(struct imx_port *sport) 1051 { 1052 unsigned long temp; 1053 1054 init_waitqueue_head(&sport->dma_wait); 1055 1056 /* set UCR1 */ 1057 temp = readl(sport->port.membase + UCR1); 1058 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1059 /* wait for 32 idle frames for IDDMA interrupt */ 1060 UCR1_ICD_REG(3); 1061 writel(temp, sport->port.membase + UCR1); 1062 1063 /* set UCR4 */ 1064 temp = readl(sport->port.membase + UCR4); 1065 temp |= UCR4_IDDMAEN; 1066 writel(temp, sport->port.membase + UCR4); 1067 1068 sport->dma_is_enabled = 1; 1069 } 1070 1071 static void imx_disable_dma(struct imx_port *sport) 1072 { 1073 unsigned long temp; 1074 1075 /* clear UCR1 */ 1076 temp = readl(sport->port.membase + UCR1); 1077 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1078 writel(temp, sport->port.membase + UCR1); 1079 1080 /* clear UCR2 */ 1081 temp = readl(sport->port.membase + UCR2); 1082 temp &= ~(UCR2_CTSC | UCR2_CTS); 1083 writel(temp, sport->port.membase + UCR2); 1084 1085 /* clear UCR4 */ 1086 temp = readl(sport->port.membase + UCR4); 1087 temp &= ~UCR4_IDDMAEN; 1088 writel(temp, sport->port.membase + UCR4); 1089 1090 sport->dma_is_enabled = 0; 1091 } 1092 1093 /* half the RX buffer size */ 1094 #define CTSTL 16 1095 1096 static int imx_startup(struct uart_port *port) 1097 { 1098 struct imx_port *sport = (struct imx_port *)port; 1099 int retval, i; 1100 unsigned long flags, temp; 1101 1102 retval = clk_prepare_enable(sport->clk_per); 1103 if (retval) 1104 return retval; 1105 retval = clk_prepare_enable(sport->clk_ipg); 1106 if (retval) { 1107 clk_disable_unprepare(sport->clk_per); 1108 return retval; 1109 } 1110 1111 imx_setup_ufcr(sport, 0); 1112 1113 /* disable the DREN bit (Data Ready interrupt enable) before 1114 * requesting IRQs 1115 */ 1116 temp = readl(sport->port.membase + UCR4); 1117 1118 /* set the trigger level for CTS */ 1119 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1120 temp |= CTSTL << UCR4_CTSTL_SHF; 1121 1122 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1123 1124 spin_lock_irqsave(&sport->port.lock, flags); 1125 /* Reset fifo's and state machines */ 1126 i = 100; 1127 1128 temp = readl(sport->port.membase + UCR2); 1129 temp &= ~UCR2_SRST; 1130 writel(temp, sport->port.membase + UCR2); 1131 1132 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1133 udelay(1); 1134 1135 /* 1136 * Finally, clear and enable interrupts 1137 */ 1138 writel(USR1_RTSD, sport->port.membase + USR1); 1139 writel(USR2_ORE, sport->port.membase + USR2); 1140 1141 temp = readl(sport->port.membase + UCR1); 1142 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1143 1144 writel(temp, sport->port.membase + UCR1); 1145 1146 temp = readl(sport->port.membase + UCR4); 1147 temp |= UCR4_OREN; 1148 writel(temp, sport->port.membase + UCR4); 1149 1150 temp = readl(sport->port.membase + UCR2); 1151 temp |= (UCR2_RXEN | UCR2_TXEN); 1152 if (!sport->have_rtscts) 1153 temp |= UCR2_IRTS; 1154 writel(temp, sport->port.membase + UCR2); 1155 1156 if (!is_imx1_uart(sport)) { 1157 temp = readl(sport->port.membase + UCR3); 1158 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1159 writel(temp, sport->port.membase + UCR3); 1160 } 1161 1162 /* 1163 * Enable modem status interrupts 1164 */ 1165 imx_enable_ms(&sport->port); 1166 spin_unlock_irqrestore(&sport->port.lock, flags); 1167 1168 return 0; 1169 } 1170 1171 static void imx_shutdown(struct uart_port *port) 1172 { 1173 struct imx_port *sport = (struct imx_port *)port; 1174 unsigned long temp; 1175 unsigned long flags; 1176 1177 if (sport->dma_is_enabled) { 1178 int ret; 1179 1180 /* We have to wait for the DMA to finish. */ 1181 ret = wait_event_interruptible(sport->dma_wait, 1182 !sport->dma_is_rxing && !sport->dma_is_txing); 1183 if (ret != 0) { 1184 sport->dma_is_rxing = 0; 1185 sport->dma_is_txing = 0; 1186 dmaengine_terminate_all(sport->dma_chan_tx); 1187 dmaengine_terminate_all(sport->dma_chan_rx); 1188 } 1189 spin_lock_irqsave(&sport->port.lock, flags); 1190 imx_stop_tx(port); 1191 imx_stop_rx(port); 1192 imx_disable_dma(sport); 1193 spin_unlock_irqrestore(&sport->port.lock, flags); 1194 imx_uart_dma_exit(sport); 1195 } 1196 1197 spin_lock_irqsave(&sport->port.lock, flags); 1198 temp = readl(sport->port.membase + UCR2); 1199 temp &= ~(UCR2_TXEN); 1200 writel(temp, sport->port.membase + UCR2); 1201 spin_unlock_irqrestore(&sport->port.lock, flags); 1202 1203 /* 1204 * Stop our timer. 1205 */ 1206 del_timer_sync(&sport->timer); 1207 1208 /* 1209 * Disable all interrupts, port and break condition. 1210 */ 1211 1212 spin_lock_irqsave(&sport->port.lock, flags); 1213 temp = readl(sport->port.membase + UCR1); 1214 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1215 1216 writel(temp, sport->port.membase + UCR1); 1217 spin_unlock_irqrestore(&sport->port.lock, flags); 1218 1219 clk_disable_unprepare(sport->clk_per); 1220 clk_disable_unprepare(sport->clk_ipg); 1221 } 1222 1223 static void imx_flush_buffer(struct uart_port *port) 1224 { 1225 struct imx_port *sport = (struct imx_port *)port; 1226 struct scatterlist *sgl = &sport->tx_sgl[0]; 1227 unsigned long temp; 1228 int i = 100, ubir, ubmr, uts; 1229 1230 if (!sport->dma_chan_tx) 1231 return; 1232 1233 sport->tx_bytes = 0; 1234 dmaengine_terminate_all(sport->dma_chan_tx); 1235 if (sport->dma_is_txing) { 1236 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1237 DMA_TO_DEVICE); 1238 temp = readl(sport->port.membase + UCR1); 1239 temp &= ~UCR1_TDMAEN; 1240 writel(temp, sport->port.membase + UCR1); 1241 sport->dma_is_txing = false; 1242 } 1243 1244 /* 1245 * According to the Reference Manual description of the UART SRST bit: 1246 * "Reset the transmit and receive state machines, 1247 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1248 * and UTS[6-3]". As we don't need to restore the old values from 1249 * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1250 */ 1251 ubir = readl(sport->port.membase + UBIR); 1252 ubmr = readl(sport->port.membase + UBMR); 1253 uts = readl(sport->port.membase + IMX21_UTS); 1254 1255 temp = readl(sport->port.membase + UCR2); 1256 temp &= ~UCR2_SRST; 1257 writel(temp, sport->port.membase + UCR2); 1258 1259 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1260 udelay(1); 1261 1262 /* Restore the registers */ 1263 writel(ubir, sport->port.membase + UBIR); 1264 writel(ubmr, sport->port.membase + UBMR); 1265 writel(uts, sport->port.membase + IMX21_UTS); 1266 } 1267 1268 static void 1269 imx_set_termios(struct uart_port *port, struct ktermios *termios, 1270 struct ktermios *old) 1271 { 1272 struct imx_port *sport = (struct imx_port *)port; 1273 unsigned long flags; 1274 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1275 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1276 unsigned int div, ufcr; 1277 unsigned long num, denom; 1278 uint64_t tdiv64; 1279 1280 /* 1281 * We only support CS7 and CS8. 1282 */ 1283 while ((termios->c_cflag & CSIZE) != CS7 && 1284 (termios->c_cflag & CSIZE) != CS8) { 1285 termios->c_cflag &= ~CSIZE; 1286 termios->c_cflag |= old_csize; 1287 old_csize = CS8; 1288 } 1289 1290 if ((termios->c_cflag & CSIZE) == CS8) 1291 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1292 else 1293 ucr2 = UCR2_SRST | UCR2_IRTS; 1294 1295 if (termios->c_cflag & CRTSCTS) { 1296 if (sport->have_rtscts) { 1297 ucr2 &= ~UCR2_IRTS; 1298 1299 if (port->rs485.flags & SER_RS485_ENABLED) { 1300 /* 1301 * RTS is mandatory for rs485 operation, so keep 1302 * it under manual control and keep transmitter 1303 * disabled. 1304 */ 1305 if (!(port->rs485.flags & 1306 SER_RS485_RTS_AFTER_SEND)) 1307 ucr2 |= UCR2_CTS; 1308 } else { 1309 ucr2 |= UCR2_CTSC; 1310 } 1311 1312 /* Can we enable the DMA support? */ 1313 if (is_imx6q_uart(sport) && !uart_console(port) 1314 && !sport->dma_is_inited) 1315 imx_uart_dma_init(sport); 1316 } else { 1317 termios->c_cflag &= ~CRTSCTS; 1318 } 1319 } else if (port->rs485.flags & SER_RS485_ENABLED) 1320 /* disable transmitter */ 1321 if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND)) 1322 ucr2 |= UCR2_CTS; 1323 1324 if (termios->c_cflag & CSTOPB) 1325 ucr2 |= UCR2_STPB; 1326 if (termios->c_cflag & PARENB) { 1327 ucr2 |= UCR2_PREN; 1328 if (termios->c_cflag & PARODD) 1329 ucr2 |= UCR2_PROE; 1330 } 1331 1332 del_timer_sync(&sport->timer); 1333 1334 /* 1335 * Ask the core to calculate the divisor for us. 1336 */ 1337 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1338 quot = uart_get_divisor(port, baud); 1339 1340 spin_lock_irqsave(&sport->port.lock, flags); 1341 1342 sport->port.read_status_mask = 0; 1343 if (termios->c_iflag & INPCK) 1344 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1345 if (termios->c_iflag & (BRKINT | PARMRK)) 1346 sport->port.read_status_mask |= URXD_BRK; 1347 1348 /* 1349 * Characters to ignore 1350 */ 1351 sport->port.ignore_status_mask = 0; 1352 if (termios->c_iflag & IGNPAR) 1353 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1354 if (termios->c_iflag & IGNBRK) { 1355 sport->port.ignore_status_mask |= URXD_BRK; 1356 /* 1357 * If we're ignoring parity and break indicators, 1358 * ignore overruns too (for real raw support). 1359 */ 1360 if (termios->c_iflag & IGNPAR) 1361 sport->port.ignore_status_mask |= URXD_OVRRUN; 1362 } 1363 1364 if ((termios->c_cflag & CREAD) == 0) 1365 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1366 1367 /* 1368 * Update the per-port timeout. 1369 */ 1370 uart_update_timeout(port, termios->c_cflag, baud); 1371 1372 /* 1373 * disable interrupts and drain transmitter 1374 */ 1375 old_ucr1 = readl(sport->port.membase + UCR1); 1376 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1377 sport->port.membase + UCR1); 1378 1379 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1380 barrier(); 1381 1382 /* then, disable everything */ 1383 old_txrxen = readl(sport->port.membase + UCR2); 1384 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1385 sport->port.membase + UCR2); 1386 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1387 1388 /* custom-baudrate handling */ 1389 div = sport->port.uartclk / (baud * 16); 1390 if (baud == 38400 && quot != div) 1391 baud = sport->port.uartclk / (quot * 16); 1392 1393 div = sport->port.uartclk / (baud * 16); 1394 if (div > 7) 1395 div = 7; 1396 if (!div) 1397 div = 1; 1398 1399 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1400 1 << 16, 1 << 16, &num, &denom); 1401 1402 tdiv64 = sport->port.uartclk; 1403 tdiv64 *= num; 1404 do_div(tdiv64, denom * 16 * div); 1405 tty_termios_encode_baud_rate(termios, 1406 (speed_t)tdiv64, (speed_t)tdiv64); 1407 1408 num -= 1; 1409 denom -= 1; 1410 1411 ufcr = readl(sport->port.membase + UFCR); 1412 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1413 if (sport->dte_mode) 1414 ufcr |= UFCR_DCEDTE; 1415 writel(ufcr, sport->port.membase + UFCR); 1416 1417 writel(num, sport->port.membase + UBIR); 1418 writel(denom, sport->port.membase + UBMR); 1419 1420 if (!is_imx1_uart(sport)) 1421 writel(sport->port.uartclk / div / 1000, 1422 sport->port.membase + IMX21_ONEMS); 1423 1424 writel(old_ucr1, sport->port.membase + UCR1); 1425 1426 /* set the parity, stop bits and data size */ 1427 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1428 1429 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1430 imx_enable_ms(&sport->port); 1431 1432 if (sport->dma_is_inited && !sport->dma_is_enabled) 1433 imx_enable_dma(sport); 1434 spin_unlock_irqrestore(&sport->port.lock, flags); 1435 } 1436 1437 static const char *imx_type(struct uart_port *port) 1438 { 1439 struct imx_port *sport = (struct imx_port *)port; 1440 1441 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1442 } 1443 1444 /* 1445 * Configure/autoconfigure the port. 1446 */ 1447 static void imx_config_port(struct uart_port *port, int flags) 1448 { 1449 struct imx_port *sport = (struct imx_port *)port; 1450 1451 if (flags & UART_CONFIG_TYPE) 1452 sport->port.type = PORT_IMX; 1453 } 1454 1455 /* 1456 * Verify the new serial_struct (for TIOCSSERIAL). 1457 * The only change we allow are to the flags and type, and 1458 * even then only between PORT_IMX and PORT_UNKNOWN 1459 */ 1460 static int 1461 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1462 { 1463 struct imx_port *sport = (struct imx_port *)port; 1464 int ret = 0; 1465 1466 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1467 ret = -EINVAL; 1468 if (sport->port.irq != ser->irq) 1469 ret = -EINVAL; 1470 if (ser->io_type != UPIO_MEM) 1471 ret = -EINVAL; 1472 if (sport->port.uartclk / 16 != ser->baud_base) 1473 ret = -EINVAL; 1474 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1475 ret = -EINVAL; 1476 if (sport->port.iobase != ser->port) 1477 ret = -EINVAL; 1478 if (ser->hub6 != 0) 1479 ret = -EINVAL; 1480 return ret; 1481 } 1482 1483 #if defined(CONFIG_CONSOLE_POLL) 1484 1485 static int imx_poll_init(struct uart_port *port) 1486 { 1487 struct imx_port *sport = (struct imx_port *)port; 1488 unsigned long flags; 1489 unsigned long temp; 1490 int retval; 1491 1492 retval = clk_prepare_enable(sport->clk_ipg); 1493 if (retval) 1494 return retval; 1495 retval = clk_prepare_enable(sport->clk_per); 1496 if (retval) 1497 clk_disable_unprepare(sport->clk_ipg); 1498 1499 imx_setup_ufcr(sport, 0); 1500 1501 spin_lock_irqsave(&sport->port.lock, flags); 1502 1503 temp = readl(sport->port.membase + UCR1); 1504 if (is_imx1_uart(sport)) 1505 temp |= IMX1_UCR1_UARTCLKEN; 1506 temp |= UCR1_UARTEN | UCR1_RRDYEN; 1507 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 1508 writel(temp, sport->port.membase + UCR1); 1509 1510 temp = readl(sport->port.membase + UCR2); 1511 temp |= UCR2_RXEN; 1512 writel(temp, sport->port.membase + UCR2); 1513 1514 spin_unlock_irqrestore(&sport->port.lock, flags); 1515 1516 return 0; 1517 } 1518 1519 static int imx_poll_get_char(struct uart_port *port) 1520 { 1521 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 1522 return NO_POLL_CHAR; 1523 1524 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 1525 } 1526 1527 static void imx_poll_put_char(struct uart_port *port, unsigned char c) 1528 { 1529 unsigned int status; 1530 1531 /* drain */ 1532 do { 1533 status = readl_relaxed(port->membase + USR1); 1534 } while (~status & USR1_TRDY); 1535 1536 /* write */ 1537 writel_relaxed(c, port->membase + URTX0); 1538 1539 /* flush */ 1540 do { 1541 status = readl_relaxed(port->membase + USR2); 1542 } while (~status & USR2_TXDC); 1543 } 1544 #endif 1545 1546 static int imx_rs485_config(struct uart_port *port, 1547 struct serial_rs485 *rs485conf) 1548 { 1549 struct imx_port *sport = (struct imx_port *)port; 1550 1551 /* unimplemented */ 1552 rs485conf->delay_rts_before_send = 0; 1553 rs485conf->delay_rts_after_send = 0; 1554 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1555 1556 /* RTS is required to control the transmitter */ 1557 if (!sport->have_rtscts) 1558 rs485conf->flags &= ~SER_RS485_ENABLED; 1559 1560 if (rs485conf->flags & SER_RS485_ENABLED) { 1561 unsigned long temp; 1562 1563 /* disable transmitter */ 1564 temp = readl(sport->port.membase + UCR2); 1565 temp &= ~UCR2_CTSC; 1566 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1567 temp &= ~UCR2_CTS; 1568 else 1569 temp |= UCR2_CTS; 1570 writel(temp, sport->port.membase + UCR2); 1571 } 1572 1573 port->rs485 = *rs485conf; 1574 1575 return 0; 1576 } 1577 1578 static struct uart_ops imx_pops = { 1579 .tx_empty = imx_tx_empty, 1580 .set_mctrl = imx_set_mctrl, 1581 .get_mctrl = imx_get_mctrl, 1582 .stop_tx = imx_stop_tx, 1583 .start_tx = imx_start_tx, 1584 .stop_rx = imx_stop_rx, 1585 .enable_ms = imx_enable_ms, 1586 .break_ctl = imx_break_ctl, 1587 .startup = imx_startup, 1588 .shutdown = imx_shutdown, 1589 .flush_buffer = imx_flush_buffer, 1590 .set_termios = imx_set_termios, 1591 .type = imx_type, 1592 .config_port = imx_config_port, 1593 .verify_port = imx_verify_port, 1594 #if defined(CONFIG_CONSOLE_POLL) 1595 .poll_init = imx_poll_init, 1596 .poll_get_char = imx_poll_get_char, 1597 .poll_put_char = imx_poll_put_char, 1598 #endif 1599 }; 1600 1601 static struct imx_port *imx_ports[UART_NR]; 1602 1603 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1604 static void imx_console_putchar(struct uart_port *port, int ch) 1605 { 1606 struct imx_port *sport = (struct imx_port *)port; 1607 1608 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1609 barrier(); 1610 1611 writel(ch, sport->port.membase + URTX0); 1612 } 1613 1614 /* 1615 * Interrupts are disabled on entering 1616 */ 1617 static void 1618 imx_console_write(struct console *co, const char *s, unsigned int count) 1619 { 1620 struct imx_port *sport = imx_ports[co->index]; 1621 struct imx_port_ucrs old_ucr; 1622 unsigned int ucr1; 1623 unsigned long flags = 0; 1624 int locked = 1; 1625 int retval; 1626 1627 retval = clk_enable(sport->clk_per); 1628 if (retval) 1629 return; 1630 retval = clk_enable(sport->clk_ipg); 1631 if (retval) { 1632 clk_disable(sport->clk_per); 1633 return; 1634 } 1635 1636 if (sport->port.sysrq) 1637 locked = 0; 1638 else if (oops_in_progress) 1639 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1640 else 1641 spin_lock_irqsave(&sport->port.lock, flags); 1642 1643 /* 1644 * First, save UCR1/2/3 and then disable interrupts 1645 */ 1646 imx_port_ucrs_save(&sport->port, &old_ucr); 1647 ucr1 = old_ucr.ucr1; 1648 1649 if (is_imx1_uart(sport)) 1650 ucr1 |= IMX1_UCR1_UARTCLKEN; 1651 ucr1 |= UCR1_UARTEN; 1652 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1653 1654 writel(ucr1, sport->port.membase + UCR1); 1655 1656 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1657 1658 uart_console_write(&sport->port, s, count, imx_console_putchar); 1659 1660 /* 1661 * Finally, wait for transmitter to become empty 1662 * and restore UCR1/2/3 1663 */ 1664 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1665 1666 imx_port_ucrs_restore(&sport->port, &old_ucr); 1667 1668 if (locked) 1669 spin_unlock_irqrestore(&sport->port.lock, flags); 1670 1671 clk_disable(sport->clk_ipg); 1672 clk_disable(sport->clk_per); 1673 } 1674 1675 /* 1676 * If the port was already initialised (eg, by a boot loader), 1677 * try to determine the current setup. 1678 */ 1679 static void __init 1680 imx_console_get_options(struct imx_port *sport, int *baud, 1681 int *parity, int *bits) 1682 { 1683 1684 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1685 /* ok, the port was enabled */ 1686 unsigned int ucr2, ubir, ubmr, uartclk; 1687 unsigned int baud_raw; 1688 unsigned int ucfr_rfdiv; 1689 1690 ucr2 = readl(sport->port.membase + UCR2); 1691 1692 *parity = 'n'; 1693 if (ucr2 & UCR2_PREN) { 1694 if (ucr2 & UCR2_PROE) 1695 *parity = 'o'; 1696 else 1697 *parity = 'e'; 1698 } 1699 1700 if (ucr2 & UCR2_WS) 1701 *bits = 8; 1702 else 1703 *bits = 7; 1704 1705 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1706 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1707 1708 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1709 if (ucfr_rfdiv == 6) 1710 ucfr_rfdiv = 7; 1711 else 1712 ucfr_rfdiv = 6 - ucfr_rfdiv; 1713 1714 uartclk = clk_get_rate(sport->clk_per); 1715 uartclk /= ucfr_rfdiv; 1716 1717 { /* 1718 * The next code provides exact computation of 1719 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1720 * without need of float support or long long division, 1721 * which would be required to prevent 32bit arithmetic overflow 1722 */ 1723 unsigned int mul = ubir + 1; 1724 unsigned int div = 16 * (ubmr + 1); 1725 unsigned int rem = uartclk % div; 1726 1727 baud_raw = (uartclk / div) * mul; 1728 baud_raw += (rem * mul + div / 2) / div; 1729 *baud = (baud_raw + 50) / 100 * 100; 1730 } 1731 1732 if (*baud != baud_raw) 1733 pr_info("Console IMX rounded baud rate from %d to %d\n", 1734 baud_raw, *baud); 1735 } 1736 } 1737 1738 static int __init 1739 imx_console_setup(struct console *co, char *options) 1740 { 1741 struct imx_port *sport; 1742 int baud = 9600; 1743 int bits = 8; 1744 int parity = 'n'; 1745 int flow = 'n'; 1746 int retval; 1747 1748 /* 1749 * Check whether an invalid uart number has been specified, and 1750 * if so, search for the first available port that does have 1751 * console support. 1752 */ 1753 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1754 co->index = 0; 1755 sport = imx_ports[co->index]; 1756 if (sport == NULL) 1757 return -ENODEV; 1758 1759 /* For setting the registers, we only need to enable the ipg clock. */ 1760 retval = clk_prepare_enable(sport->clk_ipg); 1761 if (retval) 1762 goto error_console; 1763 1764 if (options) 1765 uart_parse_options(options, &baud, &parity, &bits, &flow); 1766 else 1767 imx_console_get_options(sport, &baud, &parity, &bits); 1768 1769 imx_setup_ufcr(sport, 0); 1770 1771 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 1772 1773 clk_disable(sport->clk_ipg); 1774 if (retval) { 1775 clk_unprepare(sport->clk_ipg); 1776 goto error_console; 1777 } 1778 1779 retval = clk_prepare(sport->clk_per); 1780 if (retval) 1781 clk_disable_unprepare(sport->clk_ipg); 1782 1783 error_console: 1784 return retval; 1785 } 1786 1787 static struct uart_driver imx_reg; 1788 static struct console imx_console = { 1789 .name = DEV_NAME, 1790 .write = imx_console_write, 1791 .device = uart_console_device, 1792 .setup = imx_console_setup, 1793 .flags = CON_PRINTBUFFER, 1794 .index = -1, 1795 .data = &imx_reg, 1796 }; 1797 1798 #define IMX_CONSOLE &imx_console 1799 #else 1800 #define IMX_CONSOLE NULL 1801 #endif 1802 1803 static struct uart_driver imx_reg = { 1804 .owner = THIS_MODULE, 1805 .driver_name = DRIVER_NAME, 1806 .dev_name = DEV_NAME, 1807 .major = SERIAL_IMX_MAJOR, 1808 .minor = MINOR_START, 1809 .nr = ARRAY_SIZE(imx_ports), 1810 .cons = IMX_CONSOLE, 1811 }; 1812 1813 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1814 { 1815 struct imx_port *sport = platform_get_drvdata(dev); 1816 unsigned int val; 1817 1818 /* enable wakeup from i.MX UART */ 1819 val = readl(sport->port.membase + UCR3); 1820 val |= UCR3_AWAKEN; 1821 writel(val, sport->port.membase + UCR3); 1822 1823 uart_suspend_port(&imx_reg, &sport->port); 1824 1825 return 0; 1826 } 1827 1828 static int serial_imx_resume(struct platform_device *dev) 1829 { 1830 struct imx_port *sport = platform_get_drvdata(dev); 1831 unsigned int val; 1832 1833 /* disable wakeup from i.MX UART */ 1834 val = readl(sport->port.membase + UCR3); 1835 val &= ~UCR3_AWAKEN; 1836 writel(val, sport->port.membase + UCR3); 1837 1838 uart_resume_port(&imx_reg, &sport->port); 1839 1840 return 0; 1841 } 1842 1843 #ifdef CONFIG_OF 1844 /* 1845 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 1846 * could successfully get all information from dt or a negative errno. 1847 */ 1848 static int serial_imx_probe_dt(struct imx_port *sport, 1849 struct platform_device *pdev) 1850 { 1851 struct device_node *np = pdev->dev.of_node; 1852 const struct of_device_id *of_id = 1853 of_match_device(imx_uart_dt_ids, &pdev->dev); 1854 int ret; 1855 1856 if (!np) 1857 /* no device tree device */ 1858 return 1; 1859 1860 ret = of_alias_get_id(np, "serial"); 1861 if (ret < 0) { 1862 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1863 return ret; 1864 } 1865 sport->port.line = ret; 1866 1867 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1868 sport->have_rtscts = 1; 1869 1870 if (of_get_property(np, "fsl,dte-mode", NULL)) 1871 sport->dte_mode = 1; 1872 1873 sport->devdata = of_id->data; 1874 1875 return 0; 1876 } 1877 #else 1878 static inline int serial_imx_probe_dt(struct imx_port *sport, 1879 struct platform_device *pdev) 1880 { 1881 return 1; 1882 } 1883 #endif 1884 1885 static void serial_imx_probe_pdata(struct imx_port *sport, 1886 struct platform_device *pdev) 1887 { 1888 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 1889 1890 sport->port.line = pdev->id; 1891 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 1892 1893 if (!pdata) 1894 return; 1895 1896 if (pdata->flags & IMXUART_HAVE_RTSCTS) 1897 sport->have_rtscts = 1; 1898 } 1899 1900 static int serial_imx_probe(struct platform_device *pdev) 1901 { 1902 struct imx_port *sport; 1903 void __iomem *base; 1904 int ret = 0; 1905 struct resource *res; 1906 int txirq, rxirq, rtsirq; 1907 1908 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1909 if (!sport) 1910 return -ENOMEM; 1911 1912 ret = serial_imx_probe_dt(sport, pdev); 1913 if (ret > 0) 1914 serial_imx_probe_pdata(sport, pdev); 1915 else if (ret < 0) 1916 return ret; 1917 1918 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1919 base = devm_ioremap_resource(&pdev->dev, res); 1920 if (IS_ERR(base)) 1921 return PTR_ERR(base); 1922 1923 rxirq = platform_get_irq(pdev, 0); 1924 txirq = platform_get_irq(pdev, 1); 1925 rtsirq = platform_get_irq(pdev, 2); 1926 1927 sport->port.dev = &pdev->dev; 1928 sport->port.mapbase = res->start; 1929 sport->port.membase = base; 1930 sport->port.type = PORT_IMX, 1931 sport->port.iotype = UPIO_MEM; 1932 sport->port.irq = rxirq; 1933 sport->port.fifosize = 32; 1934 sport->port.ops = &imx_pops; 1935 sport->port.rs485_config = imx_rs485_config; 1936 sport->port.rs485.flags = 1937 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX; 1938 sport->port.flags = UPF_BOOT_AUTOCONF; 1939 init_timer(&sport->timer); 1940 sport->timer.function = imx_timeout; 1941 sport->timer.data = (unsigned long)sport; 1942 1943 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1944 if (IS_ERR(sport->clk_ipg)) { 1945 ret = PTR_ERR(sport->clk_ipg); 1946 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 1947 return ret; 1948 } 1949 1950 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 1951 if (IS_ERR(sport->clk_per)) { 1952 ret = PTR_ERR(sport->clk_per); 1953 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 1954 return ret; 1955 } 1956 1957 sport->port.uartclk = clk_get_rate(sport->clk_per); 1958 1959 /* 1960 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 1961 * chips only have one interrupt. 1962 */ 1963 if (txirq > 0) { 1964 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 1965 dev_name(&pdev->dev), sport); 1966 if (ret) 1967 return ret; 1968 1969 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 1970 dev_name(&pdev->dev), sport); 1971 if (ret) 1972 return ret; 1973 } else { 1974 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 1975 dev_name(&pdev->dev), sport); 1976 if (ret) 1977 return ret; 1978 } 1979 1980 imx_ports[sport->port.line] = sport; 1981 1982 platform_set_drvdata(pdev, sport); 1983 1984 return uart_add_one_port(&imx_reg, &sport->port); 1985 } 1986 1987 static int serial_imx_remove(struct platform_device *pdev) 1988 { 1989 struct imx_port *sport = platform_get_drvdata(pdev); 1990 1991 return uart_remove_one_port(&imx_reg, &sport->port); 1992 } 1993 1994 static struct platform_driver serial_imx_driver = { 1995 .probe = serial_imx_probe, 1996 .remove = serial_imx_remove, 1997 1998 .suspend = serial_imx_suspend, 1999 .resume = serial_imx_resume, 2000 .id_table = imx_uart_devtype, 2001 .driver = { 2002 .name = "imx-uart", 2003 .of_match_table = imx_uart_dt_ids, 2004 }, 2005 }; 2006 2007 static int __init imx_serial_init(void) 2008 { 2009 int ret = uart_register_driver(&imx_reg); 2010 2011 if (ret) 2012 return ret; 2013 2014 ret = platform_driver_register(&serial_imx_driver); 2015 if (ret != 0) 2016 uart_unregister_driver(&imx_reg); 2017 2018 return ret; 2019 } 2020 2021 static void __exit imx_serial_exit(void) 2022 { 2023 platform_driver_unregister(&serial_imx_driver); 2024 uart_unregister_driver(&imx_reg); 2025 } 2026 2027 module_init(imx_serial_init); 2028 module_exit(imx_serial_exit); 2029 2030 MODULE_AUTHOR("Sascha Hauer"); 2031 MODULE_DESCRIPTION("IMX generic serial port driver"); 2032 MODULE_LICENSE("GPL"); 2033 MODULE_ALIAS("platform:imx-uart"); 2034