1 /* 2 * Driver for Motorola/Freescale IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #include <linux/module.h> 25 #include <linux/ioport.h> 26 #include <linux/init.h> 27 #include <linux/console.h> 28 #include <linux/sysrq.h> 29 #include <linux/platform_device.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial_core.h> 33 #include <linux/serial.h> 34 #include <linux/clk.h> 35 #include <linux/delay.h> 36 #include <linux/rational.h> 37 #include <linux/slab.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/io.h> 41 #include <linux/dma-mapping.h> 42 43 #include <asm/irq.h> 44 #include <linux/platform_data/serial-imx.h> 45 #include <linux/platform_data/dma-imx.h> 46 47 #include "serial_mctrl_gpio.h" 48 49 /* Register definitions */ 50 #define URXD0 0x0 /* Receiver Register */ 51 #define URTX0 0x40 /* Transmitter Register */ 52 #define UCR1 0x80 /* Control Register 1 */ 53 #define UCR2 0x84 /* Control Register 2 */ 54 #define UCR3 0x88 /* Control Register 3 */ 55 #define UCR4 0x8c /* Control Register 4 */ 56 #define UFCR 0x90 /* FIFO Control Register */ 57 #define USR1 0x94 /* Status Register 1 */ 58 #define USR2 0x98 /* Status Register 2 */ 59 #define UESC 0x9c /* Escape Character Register */ 60 #define UTIM 0xa0 /* Escape Timer Register */ 61 #define UBIR 0xa4 /* BRM Incremental Register */ 62 #define UBMR 0xa8 /* BRM Modulator Register */ 63 #define UBRC 0xac /* Baud Rate Count Register */ 64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 67 68 /* UART Control Register Bit Fields.*/ 69 #define URXD_DUMMY_READ (1<<16) 70 #define URXD_CHARRDY (1<<15) 71 #define URXD_ERR (1<<14) 72 #define URXD_OVRRUN (1<<13) 73 #define URXD_FRMERR (1<<12) 74 #define URXD_BRK (1<<11) 75 #define URXD_PRERR (1<<10) 76 #define URXD_RX_DATA (0xFF<<0) 77 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 78 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 79 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 80 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 82 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 83 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 84 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 85 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 86 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 87 #define UCR1_SNDBRK (1<<4) /* Send break */ 88 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 90 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 91 #define UCR1_DOZE (1<<1) /* Doze */ 92 #define UCR1_UARTEN (1<<0) /* UART enabled */ 93 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 94 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 95 #define UCR2_CTSC (1<<13) /* CTS pin control */ 96 #define UCR2_CTS (1<<12) /* Clear to send */ 97 #define UCR2_ESCEN (1<<11) /* Escape enable */ 98 #define UCR2_PREN (1<<8) /* Parity enable */ 99 #define UCR2_PROE (1<<7) /* Parity odd/even */ 100 #define UCR2_STPB (1<<6) /* Stop */ 101 #define UCR2_WS (1<<5) /* Word size */ 102 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 103 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 104 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 105 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 106 #define UCR2_SRST (1<<0) /* SW reset */ 107 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 108 #define UCR3_PARERREN (1<<12) /* Parity enable */ 109 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 110 #define UCR3_DSR (1<<10) /* Data set ready */ 111 #define UCR3_DCD (1<<9) /* Data carrier detect */ 112 #define UCR3_RI (1<<8) /* Ring indicator */ 113 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 114 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 115 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 116 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 117 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 118 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 120 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 127 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 128 #define UCR4_IRSC (1<<5) /* IR special case */ 129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 134 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 135 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 136 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 137 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 138 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 139 #define USR1_RTSS (1<<14) /* RTS pin status */ 140 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 141 #define USR1_RTSD (1<<12) /* RTS delta */ 142 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 143 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 144 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 145 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 146 #define USR1_DTRD (1<<7) /* DTR Delta */ 147 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 148 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 149 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 150 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 151 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 152 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 153 #define USR2_IDLE (1<<12) /* Idle condition */ 154 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 155 #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 156 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 157 #define USR2_WAKE (1<<7) /* Wake */ 158 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 159 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 160 #define USR2_TXDC (1<<3) /* Transmitter complete */ 161 #define USR2_BRCD (1<<2) /* Break condition */ 162 #define USR2_ORE (1<<1) /* Overrun error */ 163 #define USR2_RDR (1<<0) /* Recv data ready */ 164 #define UTS_FRCPERR (1<<13) /* Force parity error */ 165 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 166 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 167 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 168 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 169 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 170 #define UTS_SOFTRST (1<<0) /* Software reset */ 171 172 /* We've been assigned a range on the "Low-density serial ports" major */ 173 #define SERIAL_IMX_MAJOR 207 174 #define MINOR_START 16 175 #define DEV_NAME "ttymxc" 176 177 /* 178 * This determines how often we check the modem status signals 179 * for any change. They generally aren't connected to an IRQ 180 * so we have to poll them. We also check immediately before 181 * filling the TX fifo incase CTS has been dropped. 182 */ 183 #define MCTRL_TIMEOUT (250*HZ/1000) 184 185 #define DRIVER_NAME "IMX-uart" 186 187 #define UART_NR 8 188 189 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 190 enum imx_uart_type { 191 IMX1_UART, 192 IMX21_UART, 193 IMX53_UART, 194 IMX6Q_UART, 195 }; 196 197 /* device type dependent stuff */ 198 struct imx_uart_data { 199 unsigned uts_reg; 200 enum imx_uart_type devtype; 201 }; 202 203 struct imx_port { 204 struct uart_port port; 205 struct timer_list timer; 206 unsigned int old_status; 207 unsigned int have_rtscts:1; 208 unsigned int dte_mode:1; 209 unsigned int irda_inv_rx:1; 210 unsigned int irda_inv_tx:1; 211 unsigned short trcv_delay; /* transceiver delay */ 212 struct clk *clk_ipg; 213 struct clk *clk_per; 214 const struct imx_uart_data *devdata; 215 216 struct mctrl_gpios *gpios; 217 218 /* DMA fields */ 219 unsigned int dma_is_inited:1; 220 unsigned int dma_is_enabled:1; 221 unsigned int dma_is_rxing:1; 222 unsigned int dma_is_txing:1; 223 struct dma_chan *dma_chan_rx, *dma_chan_tx; 224 struct scatterlist rx_sgl, tx_sgl[2]; 225 void *rx_buf; 226 struct circ_buf rx_ring; 227 unsigned int rx_periods; 228 dma_cookie_t rx_cookie; 229 unsigned int tx_bytes; 230 unsigned int dma_tx_nents; 231 wait_queue_head_t dma_wait; 232 unsigned int saved_reg[10]; 233 bool context_saved; 234 }; 235 236 struct imx_port_ucrs { 237 unsigned int ucr1; 238 unsigned int ucr2; 239 unsigned int ucr3; 240 }; 241 242 static struct imx_uart_data imx_uart_devdata[] = { 243 [IMX1_UART] = { 244 .uts_reg = IMX1_UTS, 245 .devtype = IMX1_UART, 246 }, 247 [IMX21_UART] = { 248 .uts_reg = IMX21_UTS, 249 .devtype = IMX21_UART, 250 }, 251 [IMX53_UART] = { 252 .uts_reg = IMX21_UTS, 253 .devtype = IMX53_UART, 254 }, 255 [IMX6Q_UART] = { 256 .uts_reg = IMX21_UTS, 257 .devtype = IMX6Q_UART, 258 }, 259 }; 260 261 static const struct platform_device_id imx_uart_devtype[] = { 262 { 263 .name = "imx1-uart", 264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 265 }, { 266 .name = "imx21-uart", 267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 268 }, { 269 .name = "imx53-uart", 270 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 271 }, { 272 .name = "imx6q-uart", 273 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 274 }, { 275 /* sentinel */ 276 } 277 }; 278 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 279 280 static const struct of_device_id imx_uart_dt_ids[] = { 281 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 282 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 283 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 284 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 285 { /* sentinel */ } 286 }; 287 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 288 289 static inline unsigned uts_reg(struct imx_port *sport) 290 { 291 return sport->devdata->uts_reg; 292 } 293 294 static inline int is_imx1_uart(struct imx_port *sport) 295 { 296 return sport->devdata->devtype == IMX1_UART; 297 } 298 299 static inline int is_imx21_uart(struct imx_port *sport) 300 { 301 return sport->devdata->devtype == IMX21_UART; 302 } 303 304 static inline int is_imx53_uart(struct imx_port *sport) 305 { 306 return sport->devdata->devtype == IMX53_UART; 307 } 308 309 static inline int is_imx6q_uart(struct imx_port *sport) 310 { 311 return sport->devdata->devtype == IMX6Q_UART; 312 } 313 /* 314 * Save and restore functions for UCR1, UCR2 and UCR3 registers 315 */ 316 #if defined(CONFIG_SERIAL_IMX_CONSOLE) 317 static void imx_port_ucrs_save(struct uart_port *port, 318 struct imx_port_ucrs *ucr) 319 { 320 /* save control registers */ 321 ucr->ucr1 = readl(port->membase + UCR1); 322 ucr->ucr2 = readl(port->membase + UCR2); 323 ucr->ucr3 = readl(port->membase + UCR3); 324 } 325 326 static void imx_port_ucrs_restore(struct uart_port *port, 327 struct imx_port_ucrs *ucr) 328 { 329 /* restore control registers */ 330 writel(ucr->ucr1, port->membase + UCR1); 331 writel(ucr->ucr2, port->membase + UCR2); 332 writel(ucr->ucr3, port->membase + UCR3); 333 } 334 #endif 335 336 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2) 337 { 338 *ucr2 &= ~UCR2_CTSC; 339 *ucr2 |= UCR2_CTS; 340 341 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); 342 } 343 344 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2) 345 { 346 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 347 348 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); 349 } 350 351 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2) 352 { 353 *ucr2 |= UCR2_CTSC; 354 } 355 356 /* 357 * interrupts disabled on entry 358 */ 359 static void imx_stop_tx(struct uart_port *port) 360 { 361 struct imx_port *sport = (struct imx_port *)port; 362 unsigned long temp; 363 364 /* 365 * We are maybe in the SMP context, so if the DMA TX thread is running 366 * on other cpu, we have to wait for it to finish. 367 */ 368 if (sport->dma_is_enabled && sport->dma_is_txing) 369 return; 370 371 temp = readl(port->membase + UCR1); 372 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); 373 374 /* in rs485 mode disable transmitter if shifter is empty */ 375 if (port->rs485.flags & SER_RS485_ENABLED && 376 readl(port->membase + USR2) & USR2_TXDC) { 377 temp = readl(port->membase + UCR2); 378 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 379 imx_port_rts_inactive(sport, &temp); 380 else 381 imx_port_rts_active(sport, &temp); 382 temp |= UCR2_RXEN; 383 writel(temp, port->membase + UCR2); 384 385 temp = readl(port->membase + UCR4); 386 temp &= ~UCR4_TCEN; 387 writel(temp, port->membase + UCR4); 388 } 389 } 390 391 /* 392 * interrupts disabled on entry 393 */ 394 static void imx_stop_rx(struct uart_port *port) 395 { 396 struct imx_port *sport = (struct imx_port *)port; 397 unsigned long temp; 398 399 if (sport->dma_is_enabled && sport->dma_is_rxing) { 400 if (sport->port.suspended) { 401 dmaengine_terminate_all(sport->dma_chan_rx); 402 sport->dma_is_rxing = 0; 403 } else { 404 return; 405 } 406 } 407 408 temp = readl(sport->port.membase + UCR2); 409 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 410 411 /* disable the `Receiver Ready Interrrupt` */ 412 temp = readl(sport->port.membase + UCR1); 413 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 414 } 415 416 /* 417 * Set the modem control timer to fire immediately. 418 */ 419 static void imx_enable_ms(struct uart_port *port) 420 { 421 struct imx_port *sport = (struct imx_port *)port; 422 423 mod_timer(&sport->timer, jiffies); 424 425 mctrl_gpio_enable_ms(sport->gpios); 426 } 427 428 static void imx_dma_tx(struct imx_port *sport); 429 static inline void imx_transmit_buffer(struct imx_port *sport) 430 { 431 struct circ_buf *xmit = &sport->port.state->xmit; 432 unsigned long temp; 433 434 if (sport->port.x_char) { 435 /* Send next char */ 436 writel(sport->port.x_char, sport->port.membase + URTX0); 437 sport->port.icount.tx++; 438 sport->port.x_char = 0; 439 return; 440 } 441 442 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 443 imx_stop_tx(&sport->port); 444 return; 445 } 446 447 if (sport->dma_is_enabled) { 448 /* 449 * We've just sent a X-char Ensure the TX DMA is enabled 450 * and the TX IRQ is disabled. 451 **/ 452 temp = readl(sport->port.membase + UCR1); 453 temp &= ~UCR1_TXMPTYEN; 454 if (sport->dma_is_txing) { 455 temp |= UCR1_TDMAEN; 456 writel(temp, sport->port.membase + UCR1); 457 } else { 458 writel(temp, sport->port.membase + UCR1); 459 imx_dma_tx(sport); 460 } 461 } 462 463 while (!uart_circ_empty(xmit) && 464 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 465 /* send xmit->buf[xmit->tail] 466 * out the port here */ 467 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 468 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 469 sport->port.icount.tx++; 470 } 471 472 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 473 uart_write_wakeup(&sport->port); 474 475 if (uart_circ_empty(xmit)) 476 imx_stop_tx(&sport->port); 477 } 478 479 static void dma_tx_callback(void *data) 480 { 481 struct imx_port *sport = data; 482 struct scatterlist *sgl = &sport->tx_sgl[0]; 483 struct circ_buf *xmit = &sport->port.state->xmit; 484 unsigned long flags; 485 unsigned long temp; 486 487 spin_lock_irqsave(&sport->port.lock, flags); 488 489 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 490 491 temp = readl(sport->port.membase + UCR1); 492 temp &= ~UCR1_TDMAEN; 493 writel(temp, sport->port.membase + UCR1); 494 495 /* update the stat */ 496 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 497 sport->port.icount.tx += sport->tx_bytes; 498 499 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 500 501 sport->dma_is_txing = 0; 502 503 spin_unlock_irqrestore(&sport->port.lock, flags); 504 505 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 506 uart_write_wakeup(&sport->port); 507 508 if (waitqueue_active(&sport->dma_wait)) { 509 wake_up(&sport->dma_wait); 510 dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 511 return; 512 } 513 514 spin_lock_irqsave(&sport->port.lock, flags); 515 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 516 imx_dma_tx(sport); 517 spin_unlock_irqrestore(&sport->port.lock, flags); 518 } 519 520 static void imx_dma_tx(struct imx_port *sport) 521 { 522 struct circ_buf *xmit = &sport->port.state->xmit; 523 struct scatterlist *sgl = sport->tx_sgl; 524 struct dma_async_tx_descriptor *desc; 525 struct dma_chan *chan = sport->dma_chan_tx; 526 struct device *dev = sport->port.dev; 527 unsigned long temp; 528 int ret; 529 530 if (sport->dma_is_txing) 531 return; 532 533 sport->tx_bytes = uart_circ_chars_pending(xmit); 534 535 if (xmit->tail < xmit->head) { 536 sport->dma_tx_nents = 1; 537 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 538 } else { 539 sport->dma_tx_nents = 2; 540 sg_init_table(sgl, 2); 541 sg_set_buf(sgl, xmit->buf + xmit->tail, 542 UART_XMIT_SIZE - xmit->tail); 543 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 544 } 545 546 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 547 if (ret == 0) { 548 dev_err(dev, "DMA mapping error for TX.\n"); 549 return; 550 } 551 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 552 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 553 if (!desc) { 554 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 555 DMA_TO_DEVICE); 556 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 557 return; 558 } 559 desc->callback = dma_tx_callback; 560 desc->callback_param = sport; 561 562 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 563 uart_circ_chars_pending(xmit)); 564 565 temp = readl(sport->port.membase + UCR1); 566 temp |= UCR1_TDMAEN; 567 writel(temp, sport->port.membase + UCR1); 568 569 /* fire it */ 570 sport->dma_is_txing = 1; 571 dmaengine_submit(desc); 572 dma_async_issue_pending(chan); 573 return; 574 } 575 576 /* 577 * interrupts disabled on entry 578 */ 579 static void imx_start_tx(struct uart_port *port) 580 { 581 struct imx_port *sport = (struct imx_port *)port; 582 unsigned long temp; 583 584 if (port->rs485.flags & SER_RS485_ENABLED) { 585 temp = readl(port->membase + UCR2); 586 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 587 imx_port_rts_inactive(sport, &temp); 588 else 589 imx_port_rts_active(sport, &temp); 590 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 591 temp &= ~UCR2_RXEN; 592 writel(temp, port->membase + UCR2); 593 594 /* enable transmitter and shifter empty irq */ 595 temp = readl(port->membase + UCR4); 596 temp |= UCR4_TCEN; 597 writel(temp, port->membase + UCR4); 598 } 599 600 if (!sport->dma_is_enabled) { 601 temp = readl(sport->port.membase + UCR1); 602 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 603 } 604 605 if (sport->dma_is_enabled) { 606 if (sport->port.x_char) { 607 /* We have X-char to send, so enable TX IRQ and 608 * disable TX DMA to let TX interrupt to send X-char */ 609 temp = readl(sport->port.membase + UCR1); 610 temp &= ~UCR1_TDMAEN; 611 temp |= UCR1_TXMPTYEN; 612 writel(temp, sport->port.membase + UCR1); 613 return; 614 } 615 616 if (!uart_circ_empty(&port->state->xmit) && 617 !uart_tx_stopped(port)) 618 imx_dma_tx(sport); 619 return; 620 } 621 } 622 623 static irqreturn_t imx_rtsint(int irq, void *dev_id) 624 { 625 struct imx_port *sport = dev_id; 626 unsigned int val; 627 unsigned long flags; 628 629 spin_lock_irqsave(&sport->port.lock, flags); 630 631 writel(USR1_RTSD, sport->port.membase + USR1); 632 val = readl(sport->port.membase + USR1) & USR1_RTSS; 633 uart_handle_cts_change(&sport->port, !!val); 634 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 635 636 spin_unlock_irqrestore(&sport->port.lock, flags); 637 return IRQ_HANDLED; 638 } 639 640 static irqreturn_t imx_txint(int irq, void *dev_id) 641 { 642 struct imx_port *sport = dev_id; 643 unsigned long flags; 644 645 spin_lock_irqsave(&sport->port.lock, flags); 646 imx_transmit_buffer(sport); 647 spin_unlock_irqrestore(&sport->port.lock, flags); 648 return IRQ_HANDLED; 649 } 650 651 static irqreturn_t imx_rxint(int irq, void *dev_id) 652 { 653 struct imx_port *sport = dev_id; 654 unsigned int rx, flg, ignored = 0; 655 struct tty_port *port = &sport->port.state->port; 656 unsigned long flags, temp; 657 658 spin_lock_irqsave(&sport->port.lock, flags); 659 660 while (readl(sport->port.membase + USR2) & USR2_RDR) { 661 flg = TTY_NORMAL; 662 sport->port.icount.rx++; 663 664 rx = readl(sport->port.membase + URXD0); 665 666 temp = readl(sport->port.membase + USR2); 667 if (temp & USR2_BRCD) { 668 writel(USR2_BRCD, sport->port.membase + USR2); 669 if (uart_handle_break(&sport->port)) 670 continue; 671 } 672 673 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 674 continue; 675 676 if (unlikely(rx & URXD_ERR)) { 677 if (rx & URXD_BRK) 678 sport->port.icount.brk++; 679 else if (rx & URXD_PRERR) 680 sport->port.icount.parity++; 681 else if (rx & URXD_FRMERR) 682 sport->port.icount.frame++; 683 if (rx & URXD_OVRRUN) 684 sport->port.icount.overrun++; 685 686 if (rx & sport->port.ignore_status_mask) { 687 if (++ignored > 100) 688 goto out; 689 continue; 690 } 691 692 rx &= (sport->port.read_status_mask | 0xFF); 693 694 if (rx & URXD_BRK) 695 flg = TTY_BREAK; 696 else if (rx & URXD_PRERR) 697 flg = TTY_PARITY; 698 else if (rx & URXD_FRMERR) 699 flg = TTY_FRAME; 700 if (rx & URXD_OVRRUN) 701 flg = TTY_OVERRUN; 702 703 #ifdef SUPPORT_SYSRQ 704 sport->port.sysrq = 0; 705 #endif 706 } 707 708 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 709 goto out; 710 711 if (tty_insert_flip_char(port, rx, flg) == 0) 712 sport->port.icount.buf_overrun++; 713 } 714 715 out: 716 spin_unlock_irqrestore(&sport->port.lock, flags); 717 tty_flip_buffer_push(port); 718 return IRQ_HANDLED; 719 } 720 721 static void clear_rx_errors(struct imx_port *sport); 722 static int start_rx_dma(struct imx_port *sport); 723 /* 724 * If the RXFIFO is filled with some data, and then we 725 * arise a DMA operation to receive them. 726 */ 727 static void imx_dma_rxint(struct imx_port *sport) 728 { 729 unsigned long temp; 730 unsigned long flags; 731 732 spin_lock_irqsave(&sport->port.lock, flags); 733 734 temp = readl(sport->port.membase + USR2); 735 if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 736 sport->dma_is_rxing = 1; 737 738 /* disable the receiver ready and aging timer interrupts */ 739 temp = readl(sport->port.membase + UCR1); 740 temp &= ~(UCR1_RRDYEN); 741 writel(temp, sport->port.membase + UCR1); 742 743 temp = readl(sport->port.membase + UCR2); 744 temp &= ~(UCR2_ATEN); 745 writel(temp, sport->port.membase + UCR2); 746 747 /* disable the rx errors interrupts */ 748 temp = readl(sport->port.membase + UCR4); 749 temp &= ~UCR4_OREN; 750 writel(temp, sport->port.membase + UCR4); 751 752 /* tell the DMA to receive the data. */ 753 start_rx_dma(sport); 754 } 755 756 spin_unlock_irqrestore(&sport->port.lock, flags); 757 } 758 759 /* 760 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 761 */ 762 static unsigned int imx_get_hwmctrl(struct imx_port *sport) 763 { 764 unsigned int tmp = TIOCM_DSR; 765 unsigned usr1 = readl(sport->port.membase + USR1); 766 unsigned usr2 = readl(sport->port.membase + USR2); 767 768 if (usr1 & USR1_RTSS) 769 tmp |= TIOCM_CTS; 770 771 /* in DCE mode DCDIN is always 0 */ 772 if (!(usr2 & USR2_DCDIN)) 773 tmp |= TIOCM_CAR; 774 775 if (sport->dte_mode) 776 if (!(readl(sport->port.membase + USR2) & USR2_RIIN)) 777 tmp |= TIOCM_RI; 778 779 return tmp; 780 } 781 782 /* 783 * Handle any change of modem status signal since we were last called. 784 */ 785 static void imx_mctrl_check(struct imx_port *sport) 786 { 787 unsigned int status, changed; 788 789 status = imx_get_hwmctrl(sport); 790 changed = status ^ sport->old_status; 791 792 if (changed == 0) 793 return; 794 795 sport->old_status = status; 796 797 if (changed & TIOCM_RI && status & TIOCM_RI) 798 sport->port.icount.rng++; 799 if (changed & TIOCM_DSR) 800 sport->port.icount.dsr++; 801 if (changed & TIOCM_CAR) 802 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 803 if (changed & TIOCM_CTS) 804 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 805 806 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 807 } 808 809 static irqreturn_t imx_int(int irq, void *dev_id) 810 { 811 struct imx_port *sport = dev_id; 812 unsigned int sts; 813 unsigned int sts2; 814 irqreturn_t ret = IRQ_NONE; 815 816 sts = readl(sport->port.membase + USR1); 817 sts2 = readl(sport->port.membase + USR2); 818 819 if (sts & (USR1_RRDY | USR1_AGTIM)) { 820 if (sport->dma_is_enabled) 821 imx_dma_rxint(sport); 822 else 823 imx_rxint(irq, dev_id); 824 ret = IRQ_HANDLED; 825 } 826 827 if ((sts & USR1_TRDY && 828 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || 829 (sts2 & USR2_TXDC && 830 readl(sport->port.membase + UCR4) & UCR4_TCEN)) { 831 imx_txint(irq, dev_id); 832 ret = IRQ_HANDLED; 833 } 834 835 if (sts & USR1_DTRD) { 836 unsigned long flags; 837 838 if (sts & USR1_DTRD) 839 writel(USR1_DTRD, sport->port.membase + USR1); 840 841 spin_lock_irqsave(&sport->port.lock, flags); 842 imx_mctrl_check(sport); 843 spin_unlock_irqrestore(&sport->port.lock, flags); 844 845 ret = IRQ_HANDLED; 846 } 847 848 if (sts & USR1_RTSD) { 849 imx_rtsint(irq, dev_id); 850 ret = IRQ_HANDLED; 851 } 852 853 if (sts & USR1_AWAKE) { 854 writel(USR1_AWAKE, sport->port.membase + USR1); 855 ret = IRQ_HANDLED; 856 } 857 858 if (sts2 & USR2_ORE) { 859 sport->port.icount.overrun++; 860 writel(USR2_ORE, sport->port.membase + USR2); 861 ret = IRQ_HANDLED; 862 } 863 864 return ret; 865 } 866 867 /* 868 * Return TIOCSER_TEMT when transmitter is not busy. 869 */ 870 static unsigned int imx_tx_empty(struct uart_port *port) 871 { 872 struct imx_port *sport = (struct imx_port *)port; 873 unsigned int ret; 874 875 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 876 877 /* If the TX DMA is working, return 0. */ 878 if (sport->dma_is_enabled && sport->dma_is_txing) 879 ret = 0; 880 881 return ret; 882 } 883 884 static unsigned int imx_get_mctrl(struct uart_port *port) 885 { 886 struct imx_port *sport = (struct imx_port *)port; 887 unsigned int ret = imx_get_hwmctrl(sport); 888 889 mctrl_gpio_get(sport->gpios, &ret); 890 891 return ret; 892 } 893 894 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 895 { 896 struct imx_port *sport = (struct imx_port *)port; 897 unsigned long temp; 898 899 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 900 temp = readl(sport->port.membase + UCR2); 901 temp &= ~(UCR2_CTS | UCR2_CTSC); 902 if (mctrl & TIOCM_RTS) 903 temp |= UCR2_CTS | UCR2_CTSC; 904 writel(temp, sport->port.membase + UCR2); 905 } 906 907 temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR; 908 if (!(mctrl & TIOCM_DTR)) 909 temp |= UCR3_DSR; 910 writel(temp, sport->port.membase + UCR3); 911 912 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 913 if (mctrl & TIOCM_LOOP) 914 temp |= UTS_LOOP; 915 writel(temp, sport->port.membase + uts_reg(sport)); 916 917 mctrl_gpio_set(sport->gpios, mctrl); 918 } 919 920 /* 921 * Interrupts always disabled. 922 */ 923 static void imx_break_ctl(struct uart_port *port, int break_state) 924 { 925 struct imx_port *sport = (struct imx_port *)port; 926 unsigned long flags, temp; 927 928 spin_lock_irqsave(&sport->port.lock, flags); 929 930 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 931 932 if (break_state != 0) 933 temp |= UCR1_SNDBRK; 934 935 writel(temp, sport->port.membase + UCR1); 936 937 spin_unlock_irqrestore(&sport->port.lock, flags); 938 } 939 940 /* 941 * This is our per-port timeout handler, for checking the 942 * modem status signals. 943 */ 944 static void imx_timeout(unsigned long data) 945 { 946 struct imx_port *sport = (struct imx_port *)data; 947 unsigned long flags; 948 949 if (sport->port.state) { 950 spin_lock_irqsave(&sport->port.lock, flags); 951 imx_mctrl_check(sport); 952 spin_unlock_irqrestore(&sport->port.lock, flags); 953 954 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 955 } 956 } 957 958 #define RX_BUF_SIZE (PAGE_SIZE) 959 960 /* 961 * There are two kinds of RX DMA interrupts(such as in the MX6Q): 962 * [1] the RX DMA buffer is full. 963 * [2] the aging timer expires 964 * 965 * Condition [2] is triggered when a character has been sitting in the FIFO 966 * for at least 8 byte durations. 967 */ 968 static void dma_rx_callback(void *data) 969 { 970 struct imx_port *sport = data; 971 struct dma_chan *chan = sport->dma_chan_rx; 972 struct scatterlist *sgl = &sport->rx_sgl; 973 struct tty_port *port = &sport->port.state->port; 974 struct dma_tx_state state; 975 struct circ_buf *rx_ring = &sport->rx_ring; 976 enum dma_status status; 977 unsigned int w_bytes = 0; 978 unsigned int r_bytes; 979 unsigned int bd_size; 980 981 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 982 983 if (status == DMA_ERROR) { 984 dev_err(sport->port.dev, "DMA transaction error.\n"); 985 clear_rx_errors(sport); 986 return; 987 } 988 989 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 990 991 /* 992 * The state-residue variable represents the empty space 993 * relative to the entire buffer. Taking this in consideration 994 * the head is always calculated base on the buffer total 995 * length - DMA transaction residue. The UART script from the 996 * SDMA firmware will jump to the next buffer descriptor, 997 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 998 * Taking this in consideration the tail is always at the 999 * beginning of the buffer descriptor that contains the head. 1000 */ 1001 1002 /* Calculate the head */ 1003 rx_ring->head = sg_dma_len(sgl) - state.residue; 1004 1005 /* Calculate the tail. */ 1006 bd_size = sg_dma_len(sgl) / sport->rx_periods; 1007 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 1008 1009 if (rx_ring->head <= sg_dma_len(sgl) && 1010 rx_ring->head > rx_ring->tail) { 1011 1012 /* Move data from tail to head */ 1013 r_bytes = rx_ring->head - rx_ring->tail; 1014 1015 /* CPU claims ownership of RX DMA buffer */ 1016 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 1017 DMA_FROM_DEVICE); 1018 1019 w_bytes = tty_insert_flip_string(port, 1020 sport->rx_buf + rx_ring->tail, r_bytes); 1021 1022 /* UART retrieves ownership of RX DMA buffer */ 1023 dma_sync_sg_for_device(sport->port.dev, sgl, 1, 1024 DMA_FROM_DEVICE); 1025 1026 if (w_bytes != r_bytes) 1027 sport->port.icount.buf_overrun++; 1028 1029 sport->port.icount.rx += w_bytes; 1030 } else { 1031 WARN_ON(rx_ring->head > sg_dma_len(sgl)); 1032 WARN_ON(rx_ring->head <= rx_ring->tail); 1033 } 1034 } 1035 1036 if (w_bytes) { 1037 tty_flip_buffer_push(port); 1038 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 1039 } 1040 } 1041 1042 /* RX DMA buffer periods */ 1043 #define RX_DMA_PERIODS 4 1044 1045 static int start_rx_dma(struct imx_port *sport) 1046 { 1047 struct scatterlist *sgl = &sport->rx_sgl; 1048 struct dma_chan *chan = sport->dma_chan_rx; 1049 struct device *dev = sport->port.dev; 1050 struct dma_async_tx_descriptor *desc; 1051 int ret; 1052 1053 sport->rx_ring.head = 0; 1054 sport->rx_ring.tail = 0; 1055 sport->rx_periods = RX_DMA_PERIODS; 1056 1057 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1058 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1059 if (ret == 0) { 1060 dev_err(dev, "DMA mapping error for RX.\n"); 1061 return -EINVAL; 1062 } 1063 1064 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 1065 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 1066 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1067 1068 if (!desc) { 1069 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1070 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1071 return -EINVAL; 1072 } 1073 desc->callback = dma_rx_callback; 1074 desc->callback_param = sport; 1075 1076 dev_dbg(dev, "RX: prepare for the DMA.\n"); 1077 sport->rx_cookie = dmaengine_submit(desc); 1078 dma_async_issue_pending(chan); 1079 return 0; 1080 } 1081 1082 static void clear_rx_errors(struct imx_port *sport) 1083 { 1084 unsigned int status_usr1, status_usr2; 1085 1086 status_usr1 = readl(sport->port.membase + USR1); 1087 status_usr2 = readl(sport->port.membase + USR2); 1088 1089 if (status_usr2 & USR2_BRCD) { 1090 sport->port.icount.brk++; 1091 writel(USR2_BRCD, sport->port.membase + USR2); 1092 } else if (status_usr1 & USR1_FRAMERR) { 1093 sport->port.icount.frame++; 1094 writel(USR1_FRAMERR, sport->port.membase + USR1); 1095 } else if (status_usr1 & USR1_PARITYERR) { 1096 sport->port.icount.parity++; 1097 writel(USR1_PARITYERR, sport->port.membase + USR1); 1098 } 1099 1100 if (status_usr2 & USR2_ORE) { 1101 sport->port.icount.overrun++; 1102 writel(USR2_ORE, sport->port.membase + USR2); 1103 } 1104 1105 } 1106 1107 #define TXTL_DEFAULT 2 /* reset default */ 1108 #define RXTL_DEFAULT 1 /* reset default */ 1109 #define TXTL_DMA 8 /* DMA burst setting */ 1110 #define RXTL_DMA 9 /* DMA burst setting */ 1111 1112 static void imx_setup_ufcr(struct imx_port *sport, 1113 unsigned char txwl, unsigned char rxwl) 1114 { 1115 unsigned int val; 1116 1117 /* set receiver / transmitter trigger level */ 1118 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1119 val |= txwl << UFCR_TXTL_SHF | rxwl; 1120 writel(val, sport->port.membase + UFCR); 1121 } 1122 1123 static void imx_uart_dma_exit(struct imx_port *sport) 1124 { 1125 if (sport->dma_chan_rx) { 1126 dmaengine_terminate_sync(sport->dma_chan_rx); 1127 dma_release_channel(sport->dma_chan_rx); 1128 sport->dma_chan_rx = NULL; 1129 sport->rx_cookie = -EINVAL; 1130 kfree(sport->rx_buf); 1131 sport->rx_buf = NULL; 1132 } 1133 1134 if (sport->dma_chan_tx) { 1135 dmaengine_terminate_sync(sport->dma_chan_tx); 1136 dma_release_channel(sport->dma_chan_tx); 1137 sport->dma_chan_tx = NULL; 1138 } 1139 1140 sport->dma_is_inited = 0; 1141 } 1142 1143 static int imx_uart_dma_init(struct imx_port *sport) 1144 { 1145 struct dma_slave_config slave_config = {}; 1146 struct device *dev = sport->port.dev; 1147 int ret; 1148 1149 /* Prepare for RX : */ 1150 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1151 if (!sport->dma_chan_rx) { 1152 dev_dbg(dev, "cannot get the DMA channel.\n"); 1153 ret = -EINVAL; 1154 goto err; 1155 } 1156 1157 slave_config.direction = DMA_DEV_TO_MEM; 1158 slave_config.src_addr = sport->port.mapbase + URXD0; 1159 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1160 /* one byte less than the watermark level to enable the aging timer */ 1161 slave_config.src_maxburst = RXTL_DMA - 1; 1162 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1163 if (ret) { 1164 dev_err(dev, "error in RX dma configuration.\n"); 1165 goto err; 1166 } 1167 1168 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1169 if (!sport->rx_buf) { 1170 ret = -ENOMEM; 1171 goto err; 1172 } 1173 sport->rx_ring.buf = sport->rx_buf; 1174 1175 /* Prepare for TX : */ 1176 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1177 if (!sport->dma_chan_tx) { 1178 dev_err(dev, "cannot get the TX DMA channel!\n"); 1179 ret = -EINVAL; 1180 goto err; 1181 } 1182 1183 slave_config.direction = DMA_MEM_TO_DEV; 1184 slave_config.dst_addr = sport->port.mapbase + URTX0; 1185 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1186 slave_config.dst_maxburst = TXTL_DMA; 1187 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1188 if (ret) { 1189 dev_err(dev, "error in TX dma configuration."); 1190 goto err; 1191 } 1192 1193 sport->dma_is_inited = 1; 1194 1195 return 0; 1196 err: 1197 imx_uart_dma_exit(sport); 1198 return ret; 1199 } 1200 1201 static void imx_enable_dma(struct imx_port *sport) 1202 { 1203 unsigned long temp; 1204 1205 init_waitqueue_head(&sport->dma_wait); 1206 1207 /* set UCR1 */ 1208 temp = readl(sport->port.membase + UCR1); 1209 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN; 1210 writel(temp, sport->port.membase + UCR1); 1211 1212 temp = readl(sport->port.membase + UCR2); 1213 temp |= UCR2_ATEN; 1214 writel(temp, sport->port.membase + UCR2); 1215 1216 imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1217 1218 sport->dma_is_enabled = 1; 1219 } 1220 1221 static void imx_disable_dma(struct imx_port *sport) 1222 { 1223 unsigned long temp; 1224 1225 /* clear UCR1 */ 1226 temp = readl(sport->port.membase + UCR1); 1227 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1228 writel(temp, sport->port.membase + UCR1); 1229 1230 /* clear UCR2 */ 1231 temp = readl(sport->port.membase + UCR2); 1232 temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN); 1233 writel(temp, sport->port.membase + UCR2); 1234 1235 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1236 1237 sport->dma_is_enabled = 0; 1238 } 1239 1240 /* half the RX buffer size */ 1241 #define CTSTL 16 1242 1243 static int imx_startup(struct uart_port *port) 1244 { 1245 struct imx_port *sport = (struct imx_port *)port; 1246 int retval, i; 1247 unsigned long flags, temp; 1248 1249 retval = clk_prepare_enable(sport->clk_per); 1250 if (retval) 1251 return retval; 1252 retval = clk_prepare_enable(sport->clk_ipg); 1253 if (retval) { 1254 clk_disable_unprepare(sport->clk_per); 1255 return retval; 1256 } 1257 1258 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1259 1260 /* disable the DREN bit (Data Ready interrupt enable) before 1261 * requesting IRQs 1262 */ 1263 temp = readl(sport->port.membase + UCR4); 1264 1265 /* set the trigger level for CTS */ 1266 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1267 temp |= CTSTL << UCR4_CTSTL_SHF; 1268 1269 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1270 1271 /* Can we enable the DMA support? */ 1272 if (!uart_console(port) && !sport->dma_is_inited) 1273 imx_uart_dma_init(sport); 1274 1275 spin_lock_irqsave(&sport->port.lock, flags); 1276 /* Reset fifo's and state machines */ 1277 i = 100; 1278 1279 temp = readl(sport->port.membase + UCR2); 1280 temp &= ~UCR2_SRST; 1281 writel(temp, sport->port.membase + UCR2); 1282 1283 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1284 udelay(1); 1285 1286 /* 1287 * Finally, clear and enable interrupts 1288 */ 1289 writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1); 1290 writel(USR2_ORE, sport->port.membase + USR2); 1291 1292 if (sport->dma_is_inited && !sport->dma_is_enabled) 1293 imx_enable_dma(sport); 1294 1295 temp = readl(sport->port.membase + UCR1); 1296 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1297 1298 writel(temp, sport->port.membase + UCR1); 1299 1300 temp = readl(sport->port.membase + UCR4); 1301 temp |= UCR4_OREN; 1302 writel(temp, sport->port.membase + UCR4); 1303 1304 temp = readl(sport->port.membase + UCR2); 1305 temp |= (UCR2_RXEN | UCR2_TXEN); 1306 if (!sport->have_rtscts) 1307 temp |= UCR2_IRTS; 1308 /* 1309 * make sure the edge sensitive RTS-irq is disabled, 1310 * we're using RTSD instead. 1311 */ 1312 if (!is_imx1_uart(sport)) 1313 temp &= ~UCR2_RTSEN; 1314 writel(temp, sport->port.membase + UCR2); 1315 1316 if (!is_imx1_uart(sport)) { 1317 temp = readl(sport->port.membase + UCR3); 1318 1319 /* 1320 * The effect of RI and DCD differs depending on the UFCR_DCEDTE 1321 * bit. In DCE mode they control the outputs, in DTE mode they 1322 * enable the respective irqs. At least the DCD irq cannot be 1323 * cleared on i.MX25 at least, so it's not usable and must be 1324 * disabled. I don't have test hardware to check if RI has the 1325 * same problem but I consider this likely so it's disabled for 1326 * now, too. 1327 */ 1328 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | 1329 UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 1330 1331 if (sport->dte_mode) 1332 temp &= ~(UCR3_RI | UCR3_DCD); 1333 1334 writel(temp, sport->port.membase + UCR3); 1335 } 1336 1337 /* 1338 * Enable modem status interrupts 1339 */ 1340 imx_enable_ms(&sport->port); 1341 spin_unlock_irqrestore(&sport->port.lock, flags); 1342 1343 return 0; 1344 } 1345 1346 static void imx_shutdown(struct uart_port *port) 1347 { 1348 struct imx_port *sport = (struct imx_port *)port; 1349 unsigned long temp; 1350 unsigned long flags; 1351 1352 if (sport->dma_is_enabled) { 1353 sport->dma_is_rxing = 0; 1354 sport->dma_is_txing = 0; 1355 dmaengine_terminate_sync(sport->dma_chan_tx); 1356 dmaengine_terminate_sync(sport->dma_chan_rx); 1357 1358 spin_lock_irqsave(&sport->port.lock, flags); 1359 imx_stop_tx(port); 1360 imx_stop_rx(port); 1361 imx_disable_dma(sport); 1362 spin_unlock_irqrestore(&sport->port.lock, flags); 1363 imx_uart_dma_exit(sport); 1364 } 1365 1366 mctrl_gpio_disable_ms(sport->gpios); 1367 1368 spin_lock_irqsave(&sport->port.lock, flags); 1369 temp = readl(sport->port.membase + UCR2); 1370 temp &= ~(UCR2_TXEN); 1371 writel(temp, sport->port.membase + UCR2); 1372 spin_unlock_irqrestore(&sport->port.lock, flags); 1373 1374 /* 1375 * Stop our timer. 1376 */ 1377 del_timer_sync(&sport->timer); 1378 1379 /* 1380 * Disable all interrupts, port and break condition. 1381 */ 1382 1383 spin_lock_irqsave(&sport->port.lock, flags); 1384 temp = readl(sport->port.membase + UCR1); 1385 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1386 1387 writel(temp, sport->port.membase + UCR1); 1388 spin_unlock_irqrestore(&sport->port.lock, flags); 1389 1390 clk_disable_unprepare(sport->clk_per); 1391 clk_disable_unprepare(sport->clk_ipg); 1392 } 1393 1394 static void imx_flush_buffer(struct uart_port *port) 1395 { 1396 struct imx_port *sport = (struct imx_port *)port; 1397 struct scatterlist *sgl = &sport->tx_sgl[0]; 1398 unsigned long temp; 1399 int i = 100, ubir, ubmr, uts; 1400 1401 if (!sport->dma_chan_tx) 1402 return; 1403 1404 sport->tx_bytes = 0; 1405 dmaengine_terminate_all(sport->dma_chan_tx); 1406 if (sport->dma_is_txing) { 1407 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1408 DMA_TO_DEVICE); 1409 temp = readl(sport->port.membase + UCR1); 1410 temp &= ~UCR1_TDMAEN; 1411 writel(temp, sport->port.membase + UCR1); 1412 sport->dma_is_txing = false; 1413 } 1414 1415 /* 1416 * According to the Reference Manual description of the UART SRST bit: 1417 * "Reset the transmit and receive state machines, 1418 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1419 * and UTS[6-3]". As we don't need to restore the old values from 1420 * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1421 */ 1422 ubir = readl(sport->port.membase + UBIR); 1423 ubmr = readl(sport->port.membase + UBMR); 1424 uts = readl(sport->port.membase + IMX21_UTS); 1425 1426 temp = readl(sport->port.membase + UCR2); 1427 temp &= ~UCR2_SRST; 1428 writel(temp, sport->port.membase + UCR2); 1429 1430 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1431 udelay(1); 1432 1433 /* Restore the registers */ 1434 writel(ubir, sport->port.membase + UBIR); 1435 writel(ubmr, sport->port.membase + UBMR); 1436 writel(uts, sport->port.membase + IMX21_UTS); 1437 } 1438 1439 static void 1440 imx_set_termios(struct uart_port *port, struct ktermios *termios, 1441 struct ktermios *old) 1442 { 1443 struct imx_port *sport = (struct imx_port *)port; 1444 unsigned long flags; 1445 unsigned long ucr2, old_ucr1, old_ucr2; 1446 unsigned int baud, quot; 1447 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1448 unsigned long div, ufcr; 1449 unsigned long num, denom; 1450 uint64_t tdiv64; 1451 1452 /* 1453 * We only support CS7 and CS8. 1454 */ 1455 while ((termios->c_cflag & CSIZE) != CS7 && 1456 (termios->c_cflag & CSIZE) != CS8) { 1457 termios->c_cflag &= ~CSIZE; 1458 termios->c_cflag |= old_csize; 1459 old_csize = CS8; 1460 } 1461 1462 if ((termios->c_cflag & CSIZE) == CS8) 1463 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1464 else 1465 ucr2 = UCR2_SRST | UCR2_IRTS; 1466 1467 if (termios->c_cflag & CRTSCTS) { 1468 if (sport->have_rtscts) { 1469 ucr2 &= ~UCR2_IRTS; 1470 1471 if (port->rs485.flags & SER_RS485_ENABLED) { 1472 /* 1473 * RTS is mandatory for rs485 operation, so keep 1474 * it under manual control and keep transmitter 1475 * disabled. 1476 */ 1477 if (port->rs485.flags & 1478 SER_RS485_RTS_AFTER_SEND) 1479 imx_port_rts_inactive(sport, &ucr2); 1480 else 1481 imx_port_rts_active(sport, &ucr2); 1482 } else { 1483 imx_port_rts_auto(sport, &ucr2); 1484 } 1485 } else { 1486 termios->c_cflag &= ~CRTSCTS; 1487 } 1488 } else if (port->rs485.flags & SER_RS485_ENABLED) { 1489 /* disable transmitter */ 1490 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1491 imx_port_rts_inactive(sport, &ucr2); 1492 else 1493 imx_port_rts_active(sport, &ucr2); 1494 } 1495 1496 1497 if (termios->c_cflag & CSTOPB) 1498 ucr2 |= UCR2_STPB; 1499 if (termios->c_cflag & PARENB) { 1500 ucr2 |= UCR2_PREN; 1501 if (termios->c_cflag & PARODD) 1502 ucr2 |= UCR2_PROE; 1503 } 1504 1505 del_timer_sync(&sport->timer); 1506 1507 /* 1508 * Ask the core to calculate the divisor for us. 1509 */ 1510 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1511 quot = uart_get_divisor(port, baud); 1512 1513 spin_lock_irqsave(&sport->port.lock, flags); 1514 1515 sport->port.read_status_mask = 0; 1516 if (termios->c_iflag & INPCK) 1517 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1518 if (termios->c_iflag & (BRKINT | PARMRK)) 1519 sport->port.read_status_mask |= URXD_BRK; 1520 1521 /* 1522 * Characters to ignore 1523 */ 1524 sport->port.ignore_status_mask = 0; 1525 if (termios->c_iflag & IGNPAR) 1526 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1527 if (termios->c_iflag & IGNBRK) { 1528 sport->port.ignore_status_mask |= URXD_BRK; 1529 /* 1530 * If we're ignoring parity and break indicators, 1531 * ignore overruns too (for real raw support). 1532 */ 1533 if (termios->c_iflag & IGNPAR) 1534 sport->port.ignore_status_mask |= URXD_OVRRUN; 1535 } 1536 1537 if ((termios->c_cflag & CREAD) == 0) 1538 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1539 1540 /* 1541 * Update the per-port timeout. 1542 */ 1543 uart_update_timeout(port, termios->c_cflag, baud); 1544 1545 /* 1546 * disable interrupts and drain transmitter 1547 */ 1548 old_ucr1 = readl(sport->port.membase + UCR1); 1549 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1550 sport->port.membase + UCR1); 1551 1552 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1553 barrier(); 1554 1555 /* then, disable everything */ 1556 old_ucr2 = readl(sport->port.membase + UCR2); 1557 writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN), 1558 sport->port.membase + UCR2); 1559 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1560 1561 /* custom-baudrate handling */ 1562 div = sport->port.uartclk / (baud * 16); 1563 if (baud == 38400 && quot != div) 1564 baud = sport->port.uartclk / (quot * 16); 1565 1566 div = sport->port.uartclk / (baud * 16); 1567 if (div > 7) 1568 div = 7; 1569 if (!div) 1570 div = 1; 1571 1572 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1573 1 << 16, 1 << 16, &num, &denom); 1574 1575 tdiv64 = sport->port.uartclk; 1576 tdiv64 *= num; 1577 do_div(tdiv64, denom * 16 * div); 1578 tty_termios_encode_baud_rate(termios, 1579 (speed_t)tdiv64, (speed_t)tdiv64); 1580 1581 num -= 1; 1582 denom -= 1; 1583 1584 ufcr = readl(sport->port.membase + UFCR); 1585 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1586 if (sport->dte_mode) 1587 ufcr |= UFCR_DCEDTE; 1588 writel(ufcr, sport->port.membase + UFCR); 1589 1590 writel(num, sport->port.membase + UBIR); 1591 writel(denom, sport->port.membase + UBMR); 1592 1593 if (!is_imx1_uart(sport)) 1594 writel(sport->port.uartclk / div / 1000, 1595 sport->port.membase + IMX21_ONEMS); 1596 1597 writel(old_ucr1, sport->port.membase + UCR1); 1598 1599 /* set the parity, stop bits and data size */ 1600 writel(ucr2 | old_ucr2, sport->port.membase + UCR2); 1601 1602 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1603 imx_enable_ms(&sport->port); 1604 1605 spin_unlock_irqrestore(&sport->port.lock, flags); 1606 } 1607 1608 static const char *imx_type(struct uart_port *port) 1609 { 1610 struct imx_port *sport = (struct imx_port *)port; 1611 1612 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1613 } 1614 1615 /* 1616 * Configure/autoconfigure the port. 1617 */ 1618 static void imx_config_port(struct uart_port *port, int flags) 1619 { 1620 struct imx_port *sport = (struct imx_port *)port; 1621 1622 if (flags & UART_CONFIG_TYPE) 1623 sport->port.type = PORT_IMX; 1624 } 1625 1626 /* 1627 * Verify the new serial_struct (for TIOCSSERIAL). 1628 * The only change we allow are to the flags and type, and 1629 * even then only between PORT_IMX and PORT_UNKNOWN 1630 */ 1631 static int 1632 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1633 { 1634 struct imx_port *sport = (struct imx_port *)port; 1635 int ret = 0; 1636 1637 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1638 ret = -EINVAL; 1639 if (sport->port.irq != ser->irq) 1640 ret = -EINVAL; 1641 if (ser->io_type != UPIO_MEM) 1642 ret = -EINVAL; 1643 if (sport->port.uartclk / 16 != ser->baud_base) 1644 ret = -EINVAL; 1645 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1646 ret = -EINVAL; 1647 if (sport->port.iobase != ser->port) 1648 ret = -EINVAL; 1649 if (ser->hub6 != 0) 1650 ret = -EINVAL; 1651 return ret; 1652 } 1653 1654 #if defined(CONFIG_CONSOLE_POLL) 1655 1656 static int imx_poll_init(struct uart_port *port) 1657 { 1658 struct imx_port *sport = (struct imx_port *)port; 1659 unsigned long flags; 1660 unsigned long temp; 1661 int retval; 1662 1663 retval = clk_prepare_enable(sport->clk_ipg); 1664 if (retval) 1665 return retval; 1666 retval = clk_prepare_enable(sport->clk_per); 1667 if (retval) 1668 clk_disable_unprepare(sport->clk_ipg); 1669 1670 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1671 1672 spin_lock_irqsave(&sport->port.lock, flags); 1673 1674 temp = readl(sport->port.membase + UCR1); 1675 if (is_imx1_uart(sport)) 1676 temp |= IMX1_UCR1_UARTCLKEN; 1677 temp |= UCR1_UARTEN | UCR1_RRDYEN; 1678 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 1679 writel(temp, sport->port.membase + UCR1); 1680 1681 temp = readl(sport->port.membase + UCR2); 1682 temp |= UCR2_RXEN; 1683 writel(temp, sport->port.membase + UCR2); 1684 1685 spin_unlock_irqrestore(&sport->port.lock, flags); 1686 1687 return 0; 1688 } 1689 1690 static int imx_poll_get_char(struct uart_port *port) 1691 { 1692 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 1693 return NO_POLL_CHAR; 1694 1695 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 1696 } 1697 1698 static void imx_poll_put_char(struct uart_port *port, unsigned char c) 1699 { 1700 unsigned int status; 1701 1702 /* drain */ 1703 do { 1704 status = readl_relaxed(port->membase + USR1); 1705 } while (~status & USR1_TRDY); 1706 1707 /* write */ 1708 writel_relaxed(c, port->membase + URTX0); 1709 1710 /* flush */ 1711 do { 1712 status = readl_relaxed(port->membase + USR2); 1713 } while (~status & USR2_TXDC); 1714 } 1715 #endif 1716 1717 static int imx_rs485_config(struct uart_port *port, 1718 struct serial_rs485 *rs485conf) 1719 { 1720 struct imx_port *sport = (struct imx_port *)port; 1721 unsigned long temp; 1722 1723 /* unimplemented */ 1724 rs485conf->delay_rts_before_send = 0; 1725 rs485conf->delay_rts_after_send = 0; 1726 1727 /* RTS is required to control the transmitter */ 1728 if (!sport->have_rtscts) 1729 rs485conf->flags &= ~SER_RS485_ENABLED; 1730 1731 if (rs485conf->flags & SER_RS485_ENABLED) { 1732 /* disable transmitter */ 1733 temp = readl(sport->port.membase + UCR2); 1734 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1735 imx_port_rts_inactive(sport, &temp); 1736 else 1737 imx_port_rts_active(sport, &temp); 1738 writel(temp, sport->port.membase + UCR2); 1739 } 1740 1741 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 1742 if (!(rs485conf->flags & SER_RS485_ENABLED) || 1743 rs485conf->flags & SER_RS485_RX_DURING_TX) { 1744 temp = readl(sport->port.membase + UCR2); 1745 temp |= UCR2_RXEN; 1746 writel(temp, sport->port.membase + UCR2); 1747 } 1748 1749 port->rs485 = *rs485conf; 1750 1751 return 0; 1752 } 1753 1754 static const struct uart_ops imx_pops = { 1755 .tx_empty = imx_tx_empty, 1756 .set_mctrl = imx_set_mctrl, 1757 .get_mctrl = imx_get_mctrl, 1758 .stop_tx = imx_stop_tx, 1759 .start_tx = imx_start_tx, 1760 .stop_rx = imx_stop_rx, 1761 .enable_ms = imx_enable_ms, 1762 .break_ctl = imx_break_ctl, 1763 .startup = imx_startup, 1764 .shutdown = imx_shutdown, 1765 .flush_buffer = imx_flush_buffer, 1766 .set_termios = imx_set_termios, 1767 .type = imx_type, 1768 .config_port = imx_config_port, 1769 .verify_port = imx_verify_port, 1770 #if defined(CONFIG_CONSOLE_POLL) 1771 .poll_init = imx_poll_init, 1772 .poll_get_char = imx_poll_get_char, 1773 .poll_put_char = imx_poll_put_char, 1774 #endif 1775 }; 1776 1777 static struct imx_port *imx_ports[UART_NR]; 1778 1779 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1780 static void imx_console_putchar(struct uart_port *port, int ch) 1781 { 1782 struct imx_port *sport = (struct imx_port *)port; 1783 1784 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1785 barrier(); 1786 1787 writel(ch, sport->port.membase + URTX0); 1788 } 1789 1790 /* 1791 * Interrupts are disabled on entering 1792 */ 1793 static void 1794 imx_console_write(struct console *co, const char *s, unsigned int count) 1795 { 1796 struct imx_port *sport = imx_ports[co->index]; 1797 struct imx_port_ucrs old_ucr; 1798 unsigned int ucr1; 1799 unsigned long flags = 0; 1800 int locked = 1; 1801 int retval; 1802 1803 retval = clk_enable(sport->clk_per); 1804 if (retval) 1805 return; 1806 retval = clk_enable(sport->clk_ipg); 1807 if (retval) { 1808 clk_disable(sport->clk_per); 1809 return; 1810 } 1811 1812 if (sport->port.sysrq) 1813 locked = 0; 1814 else if (oops_in_progress) 1815 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1816 else 1817 spin_lock_irqsave(&sport->port.lock, flags); 1818 1819 /* 1820 * First, save UCR1/2/3 and then disable interrupts 1821 */ 1822 imx_port_ucrs_save(&sport->port, &old_ucr); 1823 ucr1 = old_ucr.ucr1; 1824 1825 if (is_imx1_uart(sport)) 1826 ucr1 |= IMX1_UCR1_UARTCLKEN; 1827 ucr1 |= UCR1_UARTEN; 1828 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1829 1830 writel(ucr1, sport->port.membase + UCR1); 1831 1832 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1833 1834 uart_console_write(&sport->port, s, count, imx_console_putchar); 1835 1836 /* 1837 * Finally, wait for transmitter to become empty 1838 * and restore UCR1/2/3 1839 */ 1840 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1841 1842 imx_port_ucrs_restore(&sport->port, &old_ucr); 1843 1844 if (locked) 1845 spin_unlock_irqrestore(&sport->port.lock, flags); 1846 1847 clk_disable(sport->clk_ipg); 1848 clk_disable(sport->clk_per); 1849 } 1850 1851 /* 1852 * If the port was already initialised (eg, by a boot loader), 1853 * try to determine the current setup. 1854 */ 1855 static void __init 1856 imx_console_get_options(struct imx_port *sport, int *baud, 1857 int *parity, int *bits) 1858 { 1859 1860 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1861 /* ok, the port was enabled */ 1862 unsigned int ucr2, ubir, ubmr, uartclk; 1863 unsigned int baud_raw; 1864 unsigned int ucfr_rfdiv; 1865 1866 ucr2 = readl(sport->port.membase + UCR2); 1867 1868 *parity = 'n'; 1869 if (ucr2 & UCR2_PREN) { 1870 if (ucr2 & UCR2_PROE) 1871 *parity = 'o'; 1872 else 1873 *parity = 'e'; 1874 } 1875 1876 if (ucr2 & UCR2_WS) 1877 *bits = 8; 1878 else 1879 *bits = 7; 1880 1881 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1882 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1883 1884 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1885 if (ucfr_rfdiv == 6) 1886 ucfr_rfdiv = 7; 1887 else 1888 ucfr_rfdiv = 6 - ucfr_rfdiv; 1889 1890 uartclk = clk_get_rate(sport->clk_per); 1891 uartclk /= ucfr_rfdiv; 1892 1893 { /* 1894 * The next code provides exact computation of 1895 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1896 * without need of float support or long long division, 1897 * which would be required to prevent 32bit arithmetic overflow 1898 */ 1899 unsigned int mul = ubir + 1; 1900 unsigned int div = 16 * (ubmr + 1); 1901 unsigned int rem = uartclk % div; 1902 1903 baud_raw = (uartclk / div) * mul; 1904 baud_raw += (rem * mul + div / 2) / div; 1905 *baud = (baud_raw + 50) / 100 * 100; 1906 } 1907 1908 if (*baud != baud_raw) 1909 pr_info("Console IMX rounded baud rate from %d to %d\n", 1910 baud_raw, *baud); 1911 } 1912 } 1913 1914 static int __init 1915 imx_console_setup(struct console *co, char *options) 1916 { 1917 struct imx_port *sport; 1918 int baud = 9600; 1919 int bits = 8; 1920 int parity = 'n'; 1921 int flow = 'n'; 1922 int retval; 1923 1924 /* 1925 * Check whether an invalid uart number has been specified, and 1926 * if so, search for the first available port that does have 1927 * console support. 1928 */ 1929 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1930 co->index = 0; 1931 sport = imx_ports[co->index]; 1932 if (sport == NULL) 1933 return -ENODEV; 1934 1935 /* For setting the registers, we only need to enable the ipg clock. */ 1936 retval = clk_prepare_enable(sport->clk_ipg); 1937 if (retval) 1938 goto error_console; 1939 1940 if (options) 1941 uart_parse_options(options, &baud, &parity, &bits, &flow); 1942 else 1943 imx_console_get_options(sport, &baud, &parity, &bits); 1944 1945 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1946 1947 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 1948 1949 clk_disable(sport->clk_ipg); 1950 if (retval) { 1951 clk_unprepare(sport->clk_ipg); 1952 goto error_console; 1953 } 1954 1955 retval = clk_prepare(sport->clk_per); 1956 if (retval) 1957 clk_disable_unprepare(sport->clk_ipg); 1958 1959 error_console: 1960 return retval; 1961 } 1962 1963 static struct uart_driver imx_reg; 1964 static struct console imx_console = { 1965 .name = DEV_NAME, 1966 .write = imx_console_write, 1967 .device = uart_console_device, 1968 .setup = imx_console_setup, 1969 .flags = CON_PRINTBUFFER, 1970 .index = -1, 1971 .data = &imx_reg, 1972 }; 1973 1974 #define IMX_CONSOLE &imx_console 1975 1976 #ifdef CONFIG_OF 1977 static void imx_console_early_putchar(struct uart_port *port, int ch) 1978 { 1979 while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL) 1980 cpu_relax(); 1981 1982 writel_relaxed(ch, port->membase + URTX0); 1983 } 1984 1985 static void imx_console_early_write(struct console *con, const char *s, 1986 unsigned count) 1987 { 1988 struct earlycon_device *dev = con->data; 1989 1990 uart_console_write(&dev->port, s, count, imx_console_early_putchar); 1991 } 1992 1993 static int __init 1994 imx_console_early_setup(struct earlycon_device *dev, const char *opt) 1995 { 1996 if (!dev->port.membase) 1997 return -ENODEV; 1998 1999 dev->con->write = imx_console_early_write; 2000 2001 return 0; 2002 } 2003 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2004 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2005 #endif 2006 2007 #else 2008 #define IMX_CONSOLE NULL 2009 #endif 2010 2011 static struct uart_driver imx_reg = { 2012 .owner = THIS_MODULE, 2013 .driver_name = DRIVER_NAME, 2014 .dev_name = DEV_NAME, 2015 .major = SERIAL_IMX_MAJOR, 2016 .minor = MINOR_START, 2017 .nr = ARRAY_SIZE(imx_ports), 2018 .cons = IMX_CONSOLE, 2019 }; 2020 2021 #ifdef CONFIG_OF 2022 /* 2023 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 2024 * could successfully get all information from dt or a negative errno. 2025 */ 2026 static int serial_imx_probe_dt(struct imx_port *sport, 2027 struct platform_device *pdev) 2028 { 2029 struct device_node *np = pdev->dev.of_node; 2030 int ret; 2031 2032 sport->devdata = of_device_get_match_data(&pdev->dev); 2033 if (!sport->devdata) 2034 /* no device tree device */ 2035 return 1; 2036 2037 ret = of_alias_get_id(np, "serial"); 2038 if (ret < 0) { 2039 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2040 return ret; 2041 } 2042 sport->port.line = ret; 2043 2044 if (of_get_property(np, "uart-has-rtscts", NULL) || 2045 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 2046 sport->have_rtscts = 1; 2047 2048 if (of_get_property(np, "fsl,dte-mode", NULL)) 2049 sport->dte_mode = 1; 2050 2051 return 0; 2052 } 2053 #else 2054 static inline int serial_imx_probe_dt(struct imx_port *sport, 2055 struct platform_device *pdev) 2056 { 2057 return 1; 2058 } 2059 #endif 2060 2061 static void serial_imx_probe_pdata(struct imx_port *sport, 2062 struct platform_device *pdev) 2063 { 2064 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 2065 2066 sport->port.line = pdev->id; 2067 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 2068 2069 if (!pdata) 2070 return; 2071 2072 if (pdata->flags & IMXUART_HAVE_RTSCTS) 2073 sport->have_rtscts = 1; 2074 } 2075 2076 static int serial_imx_probe(struct platform_device *pdev) 2077 { 2078 struct imx_port *sport; 2079 void __iomem *base; 2080 int ret = 0, reg; 2081 struct resource *res; 2082 int txirq, rxirq, rtsirq; 2083 2084 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2085 if (!sport) 2086 return -ENOMEM; 2087 2088 ret = serial_imx_probe_dt(sport, pdev); 2089 if (ret > 0) 2090 serial_imx_probe_pdata(sport, pdev); 2091 else if (ret < 0) 2092 return ret; 2093 2094 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2095 base = devm_ioremap_resource(&pdev->dev, res); 2096 if (IS_ERR(base)) 2097 return PTR_ERR(base); 2098 2099 rxirq = platform_get_irq(pdev, 0); 2100 txirq = platform_get_irq(pdev, 1); 2101 rtsirq = platform_get_irq(pdev, 2); 2102 2103 sport->port.dev = &pdev->dev; 2104 sport->port.mapbase = res->start; 2105 sport->port.membase = base; 2106 sport->port.type = PORT_IMX, 2107 sport->port.iotype = UPIO_MEM; 2108 sport->port.irq = rxirq; 2109 sport->port.fifosize = 32; 2110 sport->port.ops = &imx_pops; 2111 sport->port.rs485_config = imx_rs485_config; 2112 sport->port.rs485.flags = 2113 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX; 2114 sport->port.flags = UPF_BOOT_AUTOCONF; 2115 init_timer(&sport->timer); 2116 sport->timer.function = imx_timeout; 2117 sport->timer.data = (unsigned long)sport; 2118 2119 sport->gpios = mctrl_gpio_init(&sport->port, 0); 2120 if (IS_ERR(sport->gpios)) 2121 return PTR_ERR(sport->gpios); 2122 2123 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2124 if (IS_ERR(sport->clk_ipg)) { 2125 ret = PTR_ERR(sport->clk_ipg); 2126 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 2127 return ret; 2128 } 2129 2130 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 2131 if (IS_ERR(sport->clk_per)) { 2132 ret = PTR_ERR(sport->clk_per); 2133 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 2134 return ret; 2135 } 2136 2137 sport->port.uartclk = clk_get_rate(sport->clk_per); 2138 2139 /* For register access, we only need to enable the ipg clock. */ 2140 ret = clk_prepare_enable(sport->clk_ipg); 2141 if (ret) { 2142 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 2143 return ret; 2144 } 2145 2146 /* Disable interrupts before requesting them */ 2147 reg = readl_relaxed(sport->port.membase + UCR1); 2148 reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 2149 UCR1_TXMPTYEN | UCR1_RTSDEN); 2150 writel_relaxed(reg, sport->port.membase + UCR1); 2151 2152 clk_disable_unprepare(sport->clk_ipg); 2153 2154 /* 2155 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2156 * chips only have one interrupt. 2157 */ 2158 if (txirq > 0) { 2159 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2160 dev_name(&pdev->dev), sport); 2161 if (ret) { 2162 dev_err(&pdev->dev, "failed to request rx irq: %d\n", 2163 ret); 2164 return ret; 2165 } 2166 2167 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2168 dev_name(&pdev->dev), sport); 2169 if (ret) { 2170 dev_err(&pdev->dev, "failed to request tx irq: %d\n", 2171 ret); 2172 return ret; 2173 } 2174 } else { 2175 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2176 dev_name(&pdev->dev), sport); 2177 if (ret) { 2178 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2179 return ret; 2180 } 2181 } 2182 2183 imx_ports[sport->port.line] = sport; 2184 2185 platform_set_drvdata(pdev, sport); 2186 2187 return uart_add_one_port(&imx_reg, &sport->port); 2188 } 2189 2190 static int serial_imx_remove(struct platform_device *pdev) 2191 { 2192 struct imx_port *sport = platform_get_drvdata(pdev); 2193 2194 return uart_remove_one_port(&imx_reg, &sport->port); 2195 } 2196 2197 static void serial_imx_restore_context(struct imx_port *sport) 2198 { 2199 if (!sport->context_saved) 2200 return; 2201 2202 writel(sport->saved_reg[4], sport->port.membase + UFCR); 2203 writel(sport->saved_reg[5], sport->port.membase + UESC); 2204 writel(sport->saved_reg[6], sport->port.membase + UTIM); 2205 writel(sport->saved_reg[7], sport->port.membase + UBIR); 2206 writel(sport->saved_reg[8], sport->port.membase + UBMR); 2207 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS); 2208 writel(sport->saved_reg[0], sport->port.membase + UCR1); 2209 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2); 2210 writel(sport->saved_reg[2], sport->port.membase + UCR3); 2211 writel(sport->saved_reg[3], sport->port.membase + UCR4); 2212 sport->context_saved = false; 2213 } 2214 2215 static void serial_imx_save_context(struct imx_port *sport) 2216 { 2217 /* Save necessary regs */ 2218 sport->saved_reg[0] = readl(sport->port.membase + UCR1); 2219 sport->saved_reg[1] = readl(sport->port.membase + UCR2); 2220 sport->saved_reg[2] = readl(sport->port.membase + UCR3); 2221 sport->saved_reg[3] = readl(sport->port.membase + UCR4); 2222 sport->saved_reg[4] = readl(sport->port.membase + UFCR); 2223 sport->saved_reg[5] = readl(sport->port.membase + UESC); 2224 sport->saved_reg[6] = readl(sport->port.membase + UTIM); 2225 sport->saved_reg[7] = readl(sport->port.membase + UBIR); 2226 sport->saved_reg[8] = readl(sport->port.membase + UBMR); 2227 sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS); 2228 sport->context_saved = true; 2229 } 2230 2231 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on) 2232 { 2233 unsigned int val; 2234 2235 val = readl(sport->port.membase + UCR3); 2236 if (on) 2237 val |= UCR3_AWAKEN; 2238 else 2239 val &= ~UCR3_AWAKEN; 2240 writel(val, sport->port.membase + UCR3); 2241 2242 val = readl(sport->port.membase + UCR1); 2243 if (on) 2244 val |= UCR1_RTSDEN; 2245 else 2246 val &= ~UCR1_RTSDEN; 2247 writel(val, sport->port.membase + UCR1); 2248 } 2249 2250 static int imx_serial_port_suspend_noirq(struct device *dev) 2251 { 2252 struct platform_device *pdev = to_platform_device(dev); 2253 struct imx_port *sport = platform_get_drvdata(pdev); 2254 int ret; 2255 2256 ret = clk_enable(sport->clk_ipg); 2257 if (ret) 2258 return ret; 2259 2260 serial_imx_save_context(sport); 2261 2262 clk_disable(sport->clk_ipg); 2263 2264 return 0; 2265 } 2266 2267 static int imx_serial_port_resume_noirq(struct device *dev) 2268 { 2269 struct platform_device *pdev = to_platform_device(dev); 2270 struct imx_port *sport = platform_get_drvdata(pdev); 2271 int ret; 2272 2273 ret = clk_enable(sport->clk_ipg); 2274 if (ret) 2275 return ret; 2276 2277 serial_imx_restore_context(sport); 2278 2279 clk_disable(sport->clk_ipg); 2280 2281 return 0; 2282 } 2283 2284 static int imx_serial_port_suspend(struct device *dev) 2285 { 2286 struct platform_device *pdev = to_platform_device(dev); 2287 struct imx_port *sport = platform_get_drvdata(pdev); 2288 2289 /* enable wakeup from i.MX UART */ 2290 serial_imx_enable_wakeup(sport, true); 2291 2292 uart_suspend_port(&imx_reg, &sport->port); 2293 2294 /* Needed to enable clock in suspend_noirq */ 2295 return clk_prepare(sport->clk_ipg); 2296 } 2297 2298 static int imx_serial_port_resume(struct device *dev) 2299 { 2300 struct platform_device *pdev = to_platform_device(dev); 2301 struct imx_port *sport = platform_get_drvdata(pdev); 2302 2303 /* disable wakeup from i.MX UART */ 2304 serial_imx_enable_wakeup(sport, false); 2305 2306 uart_resume_port(&imx_reg, &sport->port); 2307 2308 clk_unprepare(sport->clk_ipg); 2309 2310 return 0; 2311 } 2312 2313 static const struct dev_pm_ops imx_serial_port_pm_ops = { 2314 .suspend_noirq = imx_serial_port_suspend_noirq, 2315 .resume_noirq = imx_serial_port_resume_noirq, 2316 .suspend = imx_serial_port_suspend, 2317 .resume = imx_serial_port_resume, 2318 }; 2319 2320 static struct platform_driver serial_imx_driver = { 2321 .probe = serial_imx_probe, 2322 .remove = serial_imx_remove, 2323 2324 .id_table = imx_uart_devtype, 2325 .driver = { 2326 .name = "imx-uart", 2327 .of_match_table = imx_uart_dt_ids, 2328 .pm = &imx_serial_port_pm_ops, 2329 }, 2330 }; 2331 2332 static int __init imx_serial_init(void) 2333 { 2334 int ret = uart_register_driver(&imx_reg); 2335 2336 if (ret) 2337 return ret; 2338 2339 ret = platform_driver_register(&serial_imx_driver); 2340 if (ret != 0) 2341 uart_unregister_driver(&imx_reg); 2342 2343 return ret; 2344 } 2345 2346 static void __exit imx_serial_exit(void) 2347 { 2348 platform_driver_unregister(&serial_imx_driver); 2349 uart_unregister_driver(&imx_reg); 2350 } 2351 2352 module_init(imx_serial_init); 2353 module_exit(imx_serial_exit); 2354 2355 MODULE_AUTHOR("Sascha Hauer"); 2356 MODULE_DESCRIPTION("IMX generic serial port driver"); 2357 MODULE_LICENSE("GPL"); 2358 MODULE_ALIAS("platform:imx-uart"); 2359