1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Motorola/Freescale IMX serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Author: Sascha Hauer <sascha@saschahauer.de> 8 * Copyright (C) 2004 Pengutronix 9 */ 10 11 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12 #define SUPPORT_SYSRQ 13 #endif 14 15 #include <linux/module.h> 16 #include <linux/ioport.h> 17 #include <linux/init.h> 18 #include <linux/console.h> 19 #include <linux/sysrq.h> 20 #include <linux/platform_device.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial_core.h> 24 #include <linux/serial.h> 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/rational.h> 28 #include <linux/slab.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/io.h> 32 #include <linux/dma-mapping.h> 33 34 #include <asm/irq.h> 35 #include <linux/platform_data/serial-imx.h> 36 #include <linux/platform_data/dma-imx.h> 37 38 #include "serial_mctrl_gpio.h" 39 40 /* Register definitions */ 41 #define URXD0 0x0 /* Receiver Register */ 42 #define URTX0 0x40 /* Transmitter Register */ 43 #define UCR1 0x80 /* Control Register 1 */ 44 #define UCR2 0x84 /* Control Register 2 */ 45 #define UCR3 0x88 /* Control Register 3 */ 46 #define UCR4 0x8c /* Control Register 4 */ 47 #define UFCR 0x90 /* FIFO Control Register */ 48 #define USR1 0x94 /* Status Register 1 */ 49 #define USR2 0x98 /* Status Register 2 */ 50 #define UESC 0x9c /* Escape Character Register */ 51 #define UTIM 0xa0 /* Escape Timer Register */ 52 #define UBIR 0xa4 /* BRM Incremental Register */ 53 #define UBMR 0xa8 /* BRM Modulator Register */ 54 #define UBRC 0xac /* Baud Rate Count Register */ 55 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 56 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 57 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 58 59 /* UART Control Register Bit Fields.*/ 60 #define URXD_DUMMY_READ (1<<16) 61 #define URXD_CHARRDY (1<<15) 62 #define URXD_ERR (1<<14) 63 #define URXD_OVRRUN (1<<13) 64 #define URXD_FRMERR (1<<12) 65 #define URXD_BRK (1<<11) 66 #define URXD_PRERR (1<<10) 67 #define URXD_RX_DATA (0xFF<<0) 68 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 69 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 70 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 71 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 72 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 73 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 74 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 75 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 76 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 77 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 78 #define UCR1_SNDBRK (1<<4) /* Send break */ 79 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 80 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 81 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 82 #define UCR1_DOZE (1<<1) /* Doze */ 83 #define UCR1_UARTEN (1<<0) /* UART enabled */ 84 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 85 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 86 #define UCR2_CTSC (1<<13) /* CTS pin control */ 87 #define UCR2_CTS (1<<12) /* Clear to send */ 88 #define UCR2_ESCEN (1<<11) /* Escape enable */ 89 #define UCR2_PREN (1<<8) /* Parity enable */ 90 #define UCR2_PROE (1<<7) /* Parity odd/even */ 91 #define UCR2_STPB (1<<6) /* Stop */ 92 #define UCR2_WS (1<<5) /* Word size */ 93 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 94 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 95 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 96 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 97 #define UCR2_SRST (1<<0) /* SW reset */ 98 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 99 #define UCR3_PARERREN (1<<12) /* Parity enable */ 100 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 101 #define UCR3_DSR (1<<10) /* Data set ready */ 102 #define UCR3_DCD (1<<9) /* Data carrier detect */ 103 #define UCR3_RI (1<<8) /* Ring indicator */ 104 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 105 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 106 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 107 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 108 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 109 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 110 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 111 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 112 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 113 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 114 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 115 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 116 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 117 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 118 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 119 #define UCR4_IRSC (1<<5) /* IR special case */ 120 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 121 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 122 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 123 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 124 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 125 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 126 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 127 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 128 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 129 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 130 #define USR1_RTSS (1<<14) /* RTS pin status */ 131 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 132 #define USR1_RTSD (1<<12) /* RTS delta */ 133 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 134 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 135 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 136 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 137 #define USR1_DTRD (1<<7) /* DTR Delta */ 138 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 139 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 140 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 141 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 142 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 143 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 144 #define USR2_IDLE (1<<12) /* Idle condition */ 145 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 146 #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 147 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 148 #define USR2_WAKE (1<<7) /* Wake */ 149 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 150 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 151 #define USR2_TXDC (1<<3) /* Transmitter complete */ 152 #define USR2_BRCD (1<<2) /* Break condition */ 153 #define USR2_ORE (1<<1) /* Overrun error */ 154 #define USR2_RDR (1<<0) /* Recv data ready */ 155 #define UTS_FRCPERR (1<<13) /* Force parity error */ 156 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 157 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 158 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 159 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 160 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 161 #define UTS_SOFTRST (1<<0) /* Software reset */ 162 163 /* We've been assigned a range on the "Low-density serial ports" major */ 164 #define SERIAL_IMX_MAJOR 207 165 #define MINOR_START 16 166 #define DEV_NAME "ttymxc" 167 168 /* 169 * This determines how often we check the modem status signals 170 * for any change. They generally aren't connected to an IRQ 171 * so we have to poll them. We also check immediately before 172 * filling the TX fifo incase CTS has been dropped. 173 */ 174 #define MCTRL_TIMEOUT (250*HZ/1000) 175 176 #define DRIVER_NAME "IMX-uart" 177 178 #define UART_NR 8 179 180 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 181 enum imx_uart_type { 182 IMX1_UART, 183 IMX21_UART, 184 IMX53_UART, 185 IMX6Q_UART, 186 }; 187 188 /* device type dependent stuff */ 189 struct imx_uart_data { 190 unsigned uts_reg; 191 enum imx_uart_type devtype; 192 }; 193 194 struct imx_port { 195 struct uart_port port; 196 struct timer_list timer; 197 unsigned int old_status; 198 unsigned int have_rtscts:1; 199 unsigned int have_rtsgpio:1; 200 unsigned int dte_mode:1; 201 struct clk *clk_ipg; 202 struct clk *clk_per; 203 const struct imx_uart_data *devdata; 204 205 struct mctrl_gpios *gpios; 206 207 /* shadow registers */ 208 unsigned int ucr1; 209 unsigned int ucr2; 210 unsigned int ucr3; 211 unsigned int ucr4; 212 unsigned int ufcr; 213 214 /* DMA fields */ 215 unsigned int dma_is_enabled:1; 216 unsigned int dma_is_rxing:1; 217 unsigned int dma_is_txing:1; 218 struct dma_chan *dma_chan_rx, *dma_chan_tx; 219 struct scatterlist rx_sgl, tx_sgl[2]; 220 void *rx_buf; 221 struct circ_buf rx_ring; 222 unsigned int rx_periods; 223 dma_cookie_t rx_cookie; 224 unsigned int tx_bytes; 225 unsigned int dma_tx_nents; 226 unsigned int saved_reg[10]; 227 bool context_saved; 228 }; 229 230 struct imx_port_ucrs { 231 unsigned int ucr1; 232 unsigned int ucr2; 233 unsigned int ucr3; 234 }; 235 236 static struct imx_uart_data imx_uart_devdata[] = { 237 [IMX1_UART] = { 238 .uts_reg = IMX1_UTS, 239 .devtype = IMX1_UART, 240 }, 241 [IMX21_UART] = { 242 .uts_reg = IMX21_UTS, 243 .devtype = IMX21_UART, 244 }, 245 [IMX53_UART] = { 246 .uts_reg = IMX21_UTS, 247 .devtype = IMX53_UART, 248 }, 249 [IMX6Q_UART] = { 250 .uts_reg = IMX21_UTS, 251 .devtype = IMX6Q_UART, 252 }, 253 }; 254 255 static const struct platform_device_id imx_uart_devtype[] = { 256 { 257 .name = "imx1-uart", 258 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 259 }, { 260 .name = "imx21-uart", 261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 262 }, { 263 .name = "imx53-uart", 264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 265 }, { 266 .name = "imx6q-uart", 267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 268 }, { 269 /* sentinel */ 270 } 271 }; 272 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 273 274 static const struct of_device_id imx_uart_dt_ids[] = { 275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 276 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 277 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 278 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 279 { /* sentinel */ } 280 }; 281 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 282 283 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 284 { 285 switch (offset) { 286 case UCR1: 287 sport->ucr1 = val; 288 break; 289 case UCR2: 290 sport->ucr2 = val; 291 break; 292 case UCR3: 293 sport->ucr3 = val; 294 break; 295 case UCR4: 296 sport->ucr4 = val; 297 break; 298 case UFCR: 299 sport->ufcr = val; 300 break; 301 default: 302 break; 303 } 304 writel(val, sport->port.membase + offset); 305 } 306 307 static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 308 { 309 switch (offset) { 310 case UCR1: 311 return sport->ucr1; 312 break; 313 case UCR2: 314 /* 315 * UCR2_SRST is the only bit in the cached registers that might 316 * differ from the value that was last written. As it only 317 * clears after being set, reread conditionally. 318 */ 319 if (!(sport->ucr2 & UCR2_SRST)) 320 sport->ucr2 = readl(sport->port.membase + offset); 321 return sport->ucr2; 322 break; 323 case UCR3: 324 return sport->ucr3; 325 break; 326 case UCR4: 327 return sport->ucr4; 328 break; 329 case UFCR: 330 return sport->ufcr; 331 break; 332 default: 333 return readl(sport->port.membase + offset); 334 } 335 } 336 337 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 338 { 339 return sport->devdata->uts_reg; 340 } 341 342 static inline int imx_uart_is_imx1(struct imx_port *sport) 343 { 344 return sport->devdata->devtype == IMX1_UART; 345 } 346 347 static inline int imx_uart_is_imx21(struct imx_port *sport) 348 { 349 return sport->devdata->devtype == IMX21_UART; 350 } 351 352 static inline int imx_uart_is_imx53(struct imx_port *sport) 353 { 354 return sport->devdata->devtype == IMX53_UART; 355 } 356 357 static inline int imx_uart_is_imx6q(struct imx_port *sport) 358 { 359 return sport->devdata->devtype == IMX6Q_UART; 360 } 361 /* 362 * Save and restore functions for UCR1, UCR2 and UCR3 registers 363 */ 364 #if defined(CONFIG_SERIAL_IMX_CONSOLE) 365 static void imx_uart_ucrs_save(struct imx_port *sport, 366 struct imx_port_ucrs *ucr) 367 { 368 /* save control registers */ 369 ucr->ucr1 = imx_uart_readl(sport, UCR1); 370 ucr->ucr2 = imx_uart_readl(sport, UCR2); 371 ucr->ucr3 = imx_uart_readl(sport, UCR3); 372 } 373 374 static void imx_uart_ucrs_restore(struct imx_port *sport, 375 struct imx_port_ucrs *ucr) 376 { 377 /* restore control registers */ 378 imx_uart_writel(sport, ucr->ucr1, UCR1); 379 imx_uart_writel(sport, ucr->ucr2, UCR2); 380 imx_uart_writel(sport, ucr->ucr3, UCR3); 381 } 382 #endif 383 384 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 385 { 386 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 387 388 sport->port.mctrl |= TIOCM_RTS; 389 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 390 } 391 392 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 393 { 394 *ucr2 &= ~UCR2_CTSC; 395 *ucr2 |= UCR2_CTS; 396 397 sport->port.mctrl &= ~TIOCM_RTS; 398 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 399 } 400 401 static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2) 402 { 403 *ucr2 |= UCR2_CTSC; 404 } 405 406 /* called with port.lock taken and irqs off */ 407 static void imx_uart_start_rx(struct uart_port *port) 408 { 409 struct imx_port *sport = (struct imx_port *)port; 410 unsigned int ucr1, ucr2; 411 412 ucr1 = imx_uart_readl(sport, UCR1); 413 ucr2 = imx_uart_readl(sport, UCR2); 414 415 ucr2 |= UCR2_RXEN; 416 417 if (sport->dma_is_enabled) { 418 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 419 } else { 420 ucr1 |= UCR1_RRDYEN; 421 ucr2 |= UCR2_ATEN; 422 } 423 424 /* Write UCR2 first as it includes RXEN */ 425 imx_uart_writel(sport, ucr2, UCR2); 426 imx_uart_writel(sport, ucr1, UCR1); 427 } 428 429 /* called with port.lock taken and irqs off */ 430 static void imx_uart_stop_tx(struct uart_port *port) 431 { 432 struct imx_port *sport = (struct imx_port *)port; 433 u32 ucr1; 434 435 /* 436 * We are maybe in the SMP context, so if the DMA TX thread is running 437 * on other cpu, we have to wait for it to finish. 438 */ 439 if (sport->dma_is_txing) 440 return; 441 442 ucr1 = imx_uart_readl(sport, UCR1); 443 imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1); 444 445 /* in rs485 mode disable transmitter if shifter is empty */ 446 if (port->rs485.flags & SER_RS485_ENABLED && 447 imx_uart_readl(sport, USR2) & USR2_TXDC) { 448 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 449 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 450 imx_uart_rts_active(sport, &ucr2); 451 else 452 imx_uart_rts_inactive(sport, &ucr2); 453 imx_uart_writel(sport, ucr2, UCR2); 454 455 imx_uart_start_rx(port); 456 457 ucr4 = imx_uart_readl(sport, UCR4); 458 ucr4 &= ~UCR4_TCEN; 459 imx_uart_writel(sport, ucr4, UCR4); 460 } 461 } 462 463 /* called with port.lock taken and irqs off */ 464 static void imx_uart_stop_rx(struct uart_port *port) 465 { 466 struct imx_port *sport = (struct imx_port *)port; 467 u32 ucr1, ucr2; 468 469 ucr1 = imx_uart_readl(sport, UCR1); 470 ucr2 = imx_uart_readl(sport, UCR2); 471 472 if (sport->dma_is_enabled) { 473 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 474 } else { 475 ucr1 &= ~UCR1_RRDYEN; 476 ucr2 &= ~UCR2_ATEN; 477 } 478 imx_uart_writel(sport, ucr1, UCR1); 479 480 ucr2 &= ~UCR2_RXEN; 481 imx_uart_writel(sport, ucr2, UCR2); 482 } 483 484 /* called with port.lock taken and irqs off */ 485 static void imx_uart_enable_ms(struct uart_port *port) 486 { 487 struct imx_port *sport = (struct imx_port *)port; 488 489 mod_timer(&sport->timer, jiffies); 490 491 mctrl_gpio_enable_ms(sport->gpios); 492 } 493 494 static void imx_uart_dma_tx(struct imx_port *sport); 495 496 /* called with port.lock taken and irqs off */ 497 static inline void imx_uart_transmit_buffer(struct imx_port *sport) 498 { 499 struct circ_buf *xmit = &sport->port.state->xmit; 500 501 if (sport->port.x_char) { 502 /* Send next char */ 503 imx_uart_writel(sport, sport->port.x_char, URTX0); 504 sport->port.icount.tx++; 505 sport->port.x_char = 0; 506 return; 507 } 508 509 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 510 imx_uart_stop_tx(&sport->port); 511 return; 512 } 513 514 if (sport->dma_is_enabled) { 515 u32 ucr1; 516 /* 517 * We've just sent a X-char Ensure the TX DMA is enabled 518 * and the TX IRQ is disabled. 519 **/ 520 ucr1 = imx_uart_readl(sport, UCR1); 521 ucr1 &= ~UCR1_TXMPTYEN; 522 if (sport->dma_is_txing) { 523 ucr1 |= UCR1_TXDMAEN; 524 imx_uart_writel(sport, ucr1, UCR1); 525 } else { 526 imx_uart_writel(sport, ucr1, UCR1); 527 imx_uart_dma_tx(sport); 528 } 529 530 return; 531 } 532 533 while (!uart_circ_empty(xmit) && 534 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 535 /* send xmit->buf[xmit->tail] 536 * out the port here */ 537 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 538 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 539 sport->port.icount.tx++; 540 } 541 542 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 543 uart_write_wakeup(&sport->port); 544 545 if (uart_circ_empty(xmit)) 546 imx_uart_stop_tx(&sport->port); 547 } 548 549 static void imx_uart_dma_tx_callback(void *data) 550 { 551 struct imx_port *sport = data; 552 struct scatterlist *sgl = &sport->tx_sgl[0]; 553 struct circ_buf *xmit = &sport->port.state->xmit; 554 unsigned long flags; 555 u32 ucr1; 556 557 spin_lock_irqsave(&sport->port.lock, flags); 558 559 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 560 561 ucr1 = imx_uart_readl(sport, UCR1); 562 ucr1 &= ~UCR1_TXDMAEN; 563 imx_uart_writel(sport, ucr1, UCR1); 564 565 /* update the stat */ 566 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 567 sport->port.icount.tx += sport->tx_bytes; 568 569 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 570 571 sport->dma_is_txing = 0; 572 573 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 574 uart_write_wakeup(&sport->port); 575 576 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 577 imx_uart_dma_tx(sport); 578 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 579 u32 ucr4 = imx_uart_readl(sport, UCR4); 580 ucr4 |= UCR4_TCEN; 581 imx_uart_writel(sport, ucr4, UCR4); 582 } 583 584 spin_unlock_irqrestore(&sport->port.lock, flags); 585 } 586 587 /* called with port.lock taken and irqs off */ 588 static void imx_uart_dma_tx(struct imx_port *sport) 589 { 590 struct circ_buf *xmit = &sport->port.state->xmit; 591 struct scatterlist *sgl = sport->tx_sgl; 592 struct dma_async_tx_descriptor *desc; 593 struct dma_chan *chan = sport->dma_chan_tx; 594 struct device *dev = sport->port.dev; 595 u32 ucr1, ucr4; 596 int ret; 597 598 if (sport->dma_is_txing) 599 return; 600 601 ucr4 = imx_uart_readl(sport, UCR4); 602 ucr4 &= ~UCR4_TCEN; 603 imx_uart_writel(sport, ucr4, UCR4); 604 605 sport->tx_bytes = uart_circ_chars_pending(xmit); 606 607 if (xmit->tail < xmit->head) { 608 sport->dma_tx_nents = 1; 609 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 610 } else { 611 sport->dma_tx_nents = 2; 612 sg_init_table(sgl, 2); 613 sg_set_buf(sgl, xmit->buf + xmit->tail, 614 UART_XMIT_SIZE - xmit->tail); 615 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 616 } 617 618 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 619 if (ret == 0) { 620 dev_err(dev, "DMA mapping error for TX.\n"); 621 return; 622 } 623 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 624 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 625 if (!desc) { 626 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 627 DMA_TO_DEVICE); 628 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 629 return; 630 } 631 desc->callback = imx_uart_dma_tx_callback; 632 desc->callback_param = sport; 633 634 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 635 uart_circ_chars_pending(xmit)); 636 637 ucr1 = imx_uart_readl(sport, UCR1); 638 ucr1 |= UCR1_TXDMAEN; 639 imx_uart_writel(sport, ucr1, UCR1); 640 641 /* fire it */ 642 sport->dma_is_txing = 1; 643 dmaengine_submit(desc); 644 dma_async_issue_pending(chan); 645 return; 646 } 647 648 /* called with port.lock taken and irqs off */ 649 static void imx_uart_start_tx(struct uart_port *port) 650 { 651 struct imx_port *sport = (struct imx_port *)port; 652 u32 ucr1; 653 654 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 655 return; 656 657 if (port->rs485.flags & SER_RS485_ENABLED) { 658 u32 ucr2; 659 660 ucr2 = imx_uart_readl(sport, UCR2); 661 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 662 imx_uart_rts_active(sport, &ucr2); 663 else 664 imx_uart_rts_inactive(sport, &ucr2); 665 imx_uart_writel(sport, ucr2, UCR2); 666 667 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 668 imx_uart_stop_rx(port); 669 670 /* 671 * Enable transmitter and shifter empty irq only if DMA is off. 672 * In the DMA case this is done in the tx-callback. 673 */ 674 if (!sport->dma_is_enabled) { 675 u32 ucr4 = imx_uart_readl(sport, UCR4); 676 ucr4 |= UCR4_TCEN; 677 imx_uart_writel(sport, ucr4, UCR4); 678 } 679 } 680 681 if (!sport->dma_is_enabled) { 682 ucr1 = imx_uart_readl(sport, UCR1); 683 imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1); 684 } 685 686 if (sport->dma_is_enabled) { 687 if (sport->port.x_char) { 688 /* We have X-char to send, so enable TX IRQ and 689 * disable TX DMA to let TX interrupt to send X-char */ 690 ucr1 = imx_uart_readl(sport, UCR1); 691 ucr1 &= ~UCR1_TXDMAEN; 692 ucr1 |= UCR1_TXMPTYEN; 693 imx_uart_writel(sport, ucr1, UCR1); 694 return; 695 } 696 697 if (!uart_circ_empty(&port->state->xmit) && 698 !uart_tx_stopped(port)) 699 imx_uart_dma_tx(sport); 700 return; 701 } 702 } 703 704 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 705 { 706 struct imx_port *sport = dev_id; 707 u32 usr1; 708 unsigned long flags; 709 710 spin_lock_irqsave(&sport->port.lock, flags); 711 712 imx_uart_writel(sport, USR1_RTSD, USR1); 713 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 714 uart_handle_cts_change(&sport->port, !!usr1); 715 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 716 717 spin_unlock_irqrestore(&sport->port.lock, flags); 718 return IRQ_HANDLED; 719 } 720 721 static irqreturn_t imx_uart_txint(int irq, void *dev_id) 722 { 723 struct imx_port *sport = dev_id; 724 unsigned long flags; 725 726 spin_lock_irqsave(&sport->port.lock, flags); 727 imx_uart_transmit_buffer(sport); 728 spin_unlock_irqrestore(&sport->port.lock, flags); 729 return IRQ_HANDLED; 730 } 731 732 static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 733 { 734 struct imx_port *sport = dev_id; 735 unsigned int rx, flg, ignored = 0; 736 struct tty_port *port = &sport->port.state->port; 737 unsigned long flags; 738 739 spin_lock_irqsave(&sport->port.lock, flags); 740 741 while (imx_uart_readl(sport, USR2) & USR2_RDR) { 742 u32 usr2; 743 744 flg = TTY_NORMAL; 745 sport->port.icount.rx++; 746 747 rx = imx_uart_readl(sport, URXD0); 748 749 usr2 = imx_uart_readl(sport, USR2); 750 if (usr2 & USR2_BRCD) { 751 imx_uart_writel(sport, USR2_BRCD, USR2); 752 if (uart_handle_break(&sport->port)) 753 continue; 754 } 755 756 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 757 continue; 758 759 if (unlikely(rx & URXD_ERR)) { 760 if (rx & URXD_BRK) 761 sport->port.icount.brk++; 762 else if (rx & URXD_PRERR) 763 sport->port.icount.parity++; 764 else if (rx & URXD_FRMERR) 765 sport->port.icount.frame++; 766 if (rx & URXD_OVRRUN) 767 sport->port.icount.overrun++; 768 769 if (rx & sport->port.ignore_status_mask) { 770 if (++ignored > 100) 771 goto out; 772 continue; 773 } 774 775 rx &= (sport->port.read_status_mask | 0xFF); 776 777 if (rx & URXD_BRK) 778 flg = TTY_BREAK; 779 else if (rx & URXD_PRERR) 780 flg = TTY_PARITY; 781 else if (rx & URXD_FRMERR) 782 flg = TTY_FRAME; 783 if (rx & URXD_OVRRUN) 784 flg = TTY_OVERRUN; 785 786 #ifdef SUPPORT_SYSRQ 787 sport->port.sysrq = 0; 788 #endif 789 } 790 791 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 792 goto out; 793 794 if (tty_insert_flip_char(port, rx, flg) == 0) 795 sport->port.icount.buf_overrun++; 796 } 797 798 out: 799 spin_unlock_irqrestore(&sport->port.lock, flags); 800 tty_flip_buffer_push(port); 801 return IRQ_HANDLED; 802 } 803 804 static void imx_uart_clear_rx_errors(struct imx_port *sport); 805 806 /* 807 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 808 */ 809 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 810 { 811 unsigned int tmp = TIOCM_DSR; 812 unsigned usr1 = imx_uart_readl(sport, USR1); 813 unsigned usr2 = imx_uart_readl(sport, USR2); 814 815 if (usr1 & USR1_RTSS) 816 tmp |= TIOCM_CTS; 817 818 /* in DCE mode DCDIN is always 0 */ 819 if (!(usr2 & USR2_DCDIN)) 820 tmp |= TIOCM_CAR; 821 822 if (sport->dte_mode) 823 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 824 tmp |= TIOCM_RI; 825 826 return tmp; 827 } 828 829 /* 830 * Handle any change of modem status signal since we were last called. 831 */ 832 static void imx_uart_mctrl_check(struct imx_port *sport) 833 { 834 unsigned int status, changed; 835 836 status = imx_uart_get_hwmctrl(sport); 837 changed = status ^ sport->old_status; 838 839 if (changed == 0) 840 return; 841 842 sport->old_status = status; 843 844 if (changed & TIOCM_RI && status & TIOCM_RI) 845 sport->port.icount.rng++; 846 if (changed & TIOCM_DSR) 847 sport->port.icount.dsr++; 848 if (changed & TIOCM_CAR) 849 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 850 if (changed & TIOCM_CTS) 851 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 852 853 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 854 } 855 856 static irqreturn_t imx_uart_int(int irq, void *dev_id) 857 { 858 struct imx_port *sport = dev_id; 859 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 860 irqreturn_t ret = IRQ_NONE; 861 862 usr1 = imx_uart_readl(sport, USR1); 863 usr2 = imx_uart_readl(sport, USR2); 864 ucr1 = imx_uart_readl(sport, UCR1); 865 ucr2 = imx_uart_readl(sport, UCR2); 866 ucr3 = imx_uart_readl(sport, UCR3); 867 ucr4 = imx_uart_readl(sport, UCR4); 868 869 /* 870 * Even if a condition is true that can trigger an irq only handle it if 871 * the respective irq source is enabled. This prevents some undesired 872 * actions, for example if a character that sits in the RX FIFO and that 873 * should be fetched via DMA is tried to be fetched using PIO. Or the 874 * receiver is currently off and so reading from URXD0 results in an 875 * exception. So just mask the (raw) status bits for disabled irqs. 876 */ 877 if ((ucr1 & UCR1_RRDYEN) == 0) 878 usr1 &= ~USR1_RRDY; 879 if ((ucr2 & UCR2_ATEN) == 0) 880 usr1 &= ~USR1_AGTIM; 881 if ((ucr1 & UCR1_TXMPTYEN) == 0) 882 usr1 &= ~USR1_TRDY; 883 if ((ucr4 & UCR4_TCEN) == 0) 884 usr2 &= ~USR2_TXDC; 885 if ((ucr3 & UCR3_DTRDEN) == 0) 886 usr1 &= ~USR1_DTRD; 887 if ((ucr1 & UCR1_RTSDEN) == 0) 888 usr1 &= ~USR1_RTSD; 889 if ((ucr3 & UCR3_AWAKEN) == 0) 890 usr1 &= ~USR1_AWAKE; 891 if ((ucr4 & UCR4_OREN) == 0) 892 usr2 &= ~USR2_ORE; 893 894 if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 895 imx_uart_rxint(irq, dev_id); 896 ret = IRQ_HANDLED; 897 } 898 899 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 900 imx_uart_txint(irq, dev_id); 901 ret = IRQ_HANDLED; 902 } 903 904 if (usr1 & USR1_DTRD) { 905 unsigned long flags; 906 907 imx_uart_writel(sport, USR1_DTRD, USR1); 908 909 spin_lock_irqsave(&sport->port.lock, flags); 910 imx_uart_mctrl_check(sport); 911 spin_unlock_irqrestore(&sport->port.lock, flags); 912 913 ret = IRQ_HANDLED; 914 } 915 916 if (usr1 & USR1_RTSD) { 917 imx_uart_rtsint(irq, dev_id); 918 ret = IRQ_HANDLED; 919 } 920 921 if (usr1 & USR1_AWAKE) { 922 imx_uart_writel(sport, USR1_AWAKE, USR1); 923 ret = IRQ_HANDLED; 924 } 925 926 if (usr2 & USR2_ORE) { 927 sport->port.icount.overrun++; 928 imx_uart_writel(sport, USR2_ORE, USR2); 929 ret = IRQ_HANDLED; 930 } 931 932 return ret; 933 } 934 935 /* 936 * Return TIOCSER_TEMT when transmitter is not busy. 937 */ 938 static unsigned int imx_uart_tx_empty(struct uart_port *port) 939 { 940 struct imx_port *sport = (struct imx_port *)port; 941 unsigned int ret; 942 943 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 944 945 /* If the TX DMA is working, return 0. */ 946 if (sport->dma_is_txing) 947 ret = 0; 948 949 return ret; 950 } 951 952 /* called with port.lock taken and irqs off */ 953 static unsigned int imx_uart_get_mctrl(struct uart_port *port) 954 { 955 struct imx_port *sport = (struct imx_port *)port; 956 unsigned int ret = imx_uart_get_hwmctrl(sport); 957 958 mctrl_gpio_get(sport->gpios, &ret); 959 960 return ret; 961 } 962 963 /* called with port.lock taken and irqs off */ 964 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 965 { 966 struct imx_port *sport = (struct imx_port *)port; 967 u32 ucr3, uts; 968 969 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 970 u32 ucr2; 971 972 ucr2 = imx_uart_readl(sport, UCR2); 973 ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 974 if (mctrl & TIOCM_RTS) 975 ucr2 |= UCR2_CTS | UCR2_CTSC; 976 imx_uart_writel(sport, ucr2, UCR2); 977 } 978 979 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 980 if (!(mctrl & TIOCM_DTR)) 981 ucr3 |= UCR3_DSR; 982 imx_uart_writel(sport, ucr3, UCR3); 983 984 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 985 if (mctrl & TIOCM_LOOP) 986 uts |= UTS_LOOP; 987 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 988 989 mctrl_gpio_set(sport->gpios, mctrl); 990 } 991 992 /* 993 * Interrupts always disabled. 994 */ 995 static void imx_uart_break_ctl(struct uart_port *port, int break_state) 996 { 997 struct imx_port *sport = (struct imx_port *)port; 998 unsigned long flags; 999 u32 ucr1; 1000 1001 spin_lock_irqsave(&sport->port.lock, flags); 1002 1003 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1004 1005 if (break_state != 0) 1006 ucr1 |= UCR1_SNDBRK; 1007 1008 imx_uart_writel(sport, ucr1, UCR1); 1009 1010 spin_unlock_irqrestore(&sport->port.lock, flags); 1011 } 1012 1013 /* 1014 * This is our per-port timeout handler, for checking the 1015 * modem status signals. 1016 */ 1017 static void imx_uart_timeout(struct timer_list *t) 1018 { 1019 struct imx_port *sport = from_timer(sport, t, timer); 1020 unsigned long flags; 1021 1022 if (sport->port.state) { 1023 spin_lock_irqsave(&sport->port.lock, flags); 1024 imx_uart_mctrl_check(sport); 1025 spin_unlock_irqrestore(&sport->port.lock, flags); 1026 1027 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1028 } 1029 } 1030 1031 #define RX_BUF_SIZE (PAGE_SIZE) 1032 1033 /* 1034 * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1035 * [1] the RX DMA buffer is full. 1036 * [2] the aging timer expires 1037 * 1038 * Condition [2] is triggered when a character has been sitting in the FIFO 1039 * for at least 8 byte durations. 1040 */ 1041 static void imx_uart_dma_rx_callback(void *data) 1042 { 1043 struct imx_port *sport = data; 1044 struct dma_chan *chan = sport->dma_chan_rx; 1045 struct scatterlist *sgl = &sport->rx_sgl; 1046 struct tty_port *port = &sport->port.state->port; 1047 struct dma_tx_state state; 1048 struct circ_buf *rx_ring = &sport->rx_ring; 1049 enum dma_status status; 1050 unsigned int w_bytes = 0; 1051 unsigned int r_bytes; 1052 unsigned int bd_size; 1053 1054 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 1055 1056 if (status == DMA_ERROR) { 1057 imx_uart_clear_rx_errors(sport); 1058 return; 1059 } 1060 1061 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1062 1063 /* 1064 * The state-residue variable represents the empty space 1065 * relative to the entire buffer. Taking this in consideration 1066 * the head is always calculated base on the buffer total 1067 * length - DMA transaction residue. The UART script from the 1068 * SDMA firmware will jump to the next buffer descriptor, 1069 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 1070 * Taking this in consideration the tail is always at the 1071 * beginning of the buffer descriptor that contains the head. 1072 */ 1073 1074 /* Calculate the head */ 1075 rx_ring->head = sg_dma_len(sgl) - state.residue; 1076 1077 /* Calculate the tail. */ 1078 bd_size = sg_dma_len(sgl) / sport->rx_periods; 1079 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 1080 1081 if (rx_ring->head <= sg_dma_len(sgl) && 1082 rx_ring->head > rx_ring->tail) { 1083 1084 /* Move data from tail to head */ 1085 r_bytes = rx_ring->head - rx_ring->tail; 1086 1087 /* CPU claims ownership of RX DMA buffer */ 1088 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 1089 DMA_FROM_DEVICE); 1090 1091 w_bytes = tty_insert_flip_string(port, 1092 sport->rx_buf + rx_ring->tail, r_bytes); 1093 1094 /* UART retrieves ownership of RX DMA buffer */ 1095 dma_sync_sg_for_device(sport->port.dev, sgl, 1, 1096 DMA_FROM_DEVICE); 1097 1098 if (w_bytes != r_bytes) 1099 sport->port.icount.buf_overrun++; 1100 1101 sport->port.icount.rx += w_bytes; 1102 } else { 1103 WARN_ON(rx_ring->head > sg_dma_len(sgl)); 1104 WARN_ON(rx_ring->head <= rx_ring->tail); 1105 } 1106 } 1107 1108 if (w_bytes) { 1109 tty_flip_buffer_push(port); 1110 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 1111 } 1112 } 1113 1114 /* RX DMA buffer periods */ 1115 #define RX_DMA_PERIODS 4 1116 1117 static int imx_uart_start_rx_dma(struct imx_port *sport) 1118 { 1119 struct scatterlist *sgl = &sport->rx_sgl; 1120 struct dma_chan *chan = sport->dma_chan_rx; 1121 struct device *dev = sport->port.dev; 1122 struct dma_async_tx_descriptor *desc; 1123 int ret; 1124 1125 sport->rx_ring.head = 0; 1126 sport->rx_ring.tail = 0; 1127 sport->rx_periods = RX_DMA_PERIODS; 1128 1129 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1130 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1131 if (ret == 0) { 1132 dev_err(dev, "DMA mapping error for RX.\n"); 1133 return -EINVAL; 1134 } 1135 1136 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 1137 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 1138 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1139 1140 if (!desc) { 1141 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1142 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1143 return -EINVAL; 1144 } 1145 desc->callback = imx_uart_dma_rx_callback; 1146 desc->callback_param = sport; 1147 1148 dev_dbg(dev, "RX: prepare for the DMA.\n"); 1149 sport->dma_is_rxing = 1; 1150 sport->rx_cookie = dmaengine_submit(desc); 1151 dma_async_issue_pending(chan); 1152 return 0; 1153 } 1154 1155 static void imx_uart_clear_rx_errors(struct imx_port *sport) 1156 { 1157 struct tty_port *port = &sport->port.state->port; 1158 u32 usr1, usr2; 1159 1160 usr1 = imx_uart_readl(sport, USR1); 1161 usr2 = imx_uart_readl(sport, USR2); 1162 1163 if (usr2 & USR2_BRCD) { 1164 sport->port.icount.brk++; 1165 imx_uart_writel(sport, USR2_BRCD, USR2); 1166 uart_handle_break(&sport->port); 1167 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 1168 sport->port.icount.buf_overrun++; 1169 tty_flip_buffer_push(port); 1170 } else { 1171 dev_err(sport->port.dev, "DMA transaction error.\n"); 1172 if (usr1 & USR1_FRAMERR) { 1173 sport->port.icount.frame++; 1174 imx_uart_writel(sport, USR1_FRAMERR, USR1); 1175 } else if (usr1 & USR1_PARITYERR) { 1176 sport->port.icount.parity++; 1177 imx_uart_writel(sport, USR1_PARITYERR, USR1); 1178 } 1179 } 1180 1181 if (usr2 & USR2_ORE) { 1182 sport->port.icount.overrun++; 1183 imx_uart_writel(sport, USR2_ORE, USR2); 1184 } 1185 1186 } 1187 1188 #define TXTL_DEFAULT 2 /* reset default */ 1189 #define RXTL_DEFAULT 1 /* reset default */ 1190 #define TXTL_DMA 8 /* DMA burst setting */ 1191 #define RXTL_DMA 9 /* DMA burst setting */ 1192 1193 static void imx_uart_setup_ufcr(struct imx_port *sport, 1194 unsigned char txwl, unsigned char rxwl) 1195 { 1196 unsigned int val; 1197 1198 /* set receiver / transmitter trigger level */ 1199 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1200 val |= txwl << UFCR_TXTL_SHF | rxwl; 1201 imx_uart_writel(sport, val, UFCR); 1202 } 1203 1204 static void imx_uart_dma_exit(struct imx_port *sport) 1205 { 1206 if (sport->dma_chan_rx) { 1207 dmaengine_terminate_sync(sport->dma_chan_rx); 1208 dma_release_channel(sport->dma_chan_rx); 1209 sport->dma_chan_rx = NULL; 1210 sport->rx_cookie = -EINVAL; 1211 kfree(sport->rx_buf); 1212 sport->rx_buf = NULL; 1213 } 1214 1215 if (sport->dma_chan_tx) { 1216 dmaengine_terminate_sync(sport->dma_chan_tx); 1217 dma_release_channel(sport->dma_chan_tx); 1218 sport->dma_chan_tx = NULL; 1219 } 1220 } 1221 1222 static int imx_uart_dma_init(struct imx_port *sport) 1223 { 1224 struct dma_slave_config slave_config = {}; 1225 struct device *dev = sport->port.dev; 1226 int ret; 1227 1228 /* Prepare for RX : */ 1229 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1230 if (!sport->dma_chan_rx) { 1231 dev_dbg(dev, "cannot get the DMA channel.\n"); 1232 ret = -EINVAL; 1233 goto err; 1234 } 1235 1236 slave_config.direction = DMA_DEV_TO_MEM; 1237 slave_config.src_addr = sport->port.mapbase + URXD0; 1238 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1239 /* one byte less than the watermark level to enable the aging timer */ 1240 slave_config.src_maxburst = RXTL_DMA - 1; 1241 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1242 if (ret) { 1243 dev_err(dev, "error in RX dma configuration.\n"); 1244 goto err; 1245 } 1246 1247 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1248 if (!sport->rx_buf) { 1249 ret = -ENOMEM; 1250 goto err; 1251 } 1252 sport->rx_ring.buf = sport->rx_buf; 1253 1254 /* Prepare for TX : */ 1255 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1256 if (!sport->dma_chan_tx) { 1257 dev_err(dev, "cannot get the TX DMA channel!\n"); 1258 ret = -EINVAL; 1259 goto err; 1260 } 1261 1262 slave_config.direction = DMA_MEM_TO_DEV; 1263 slave_config.dst_addr = sport->port.mapbase + URTX0; 1264 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1265 slave_config.dst_maxburst = TXTL_DMA; 1266 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1267 if (ret) { 1268 dev_err(dev, "error in TX dma configuration."); 1269 goto err; 1270 } 1271 1272 return 0; 1273 err: 1274 imx_uart_dma_exit(sport); 1275 return ret; 1276 } 1277 1278 static void imx_uart_enable_dma(struct imx_port *sport) 1279 { 1280 u32 ucr1; 1281 1282 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1283 1284 /* set UCR1 */ 1285 ucr1 = imx_uart_readl(sport, UCR1); 1286 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 1287 imx_uart_writel(sport, ucr1, UCR1); 1288 1289 sport->dma_is_enabled = 1; 1290 } 1291 1292 static void imx_uart_disable_dma(struct imx_port *sport) 1293 { 1294 u32 ucr1; 1295 1296 /* clear UCR1 */ 1297 ucr1 = imx_uart_readl(sport, UCR1); 1298 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 1299 imx_uart_writel(sport, ucr1, UCR1); 1300 1301 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1302 1303 sport->dma_is_enabled = 0; 1304 } 1305 1306 /* half the RX buffer size */ 1307 #define CTSTL 16 1308 1309 static int imx_uart_startup(struct uart_port *port) 1310 { 1311 struct imx_port *sport = (struct imx_port *)port; 1312 int retval, i; 1313 unsigned long flags; 1314 int dma_is_inited = 0; 1315 u32 ucr1, ucr2, ucr4; 1316 1317 retval = clk_prepare_enable(sport->clk_per); 1318 if (retval) 1319 return retval; 1320 retval = clk_prepare_enable(sport->clk_ipg); 1321 if (retval) { 1322 clk_disable_unprepare(sport->clk_per); 1323 return retval; 1324 } 1325 1326 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1327 1328 /* disable the DREN bit (Data Ready interrupt enable) before 1329 * requesting IRQs 1330 */ 1331 ucr4 = imx_uart_readl(sport, UCR4); 1332 1333 /* set the trigger level for CTS */ 1334 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1335 ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1336 1337 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1338 1339 /* Can we enable the DMA support? */ 1340 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 1341 dma_is_inited = 1; 1342 1343 spin_lock_irqsave(&sport->port.lock, flags); 1344 /* Reset fifo's and state machines */ 1345 i = 100; 1346 1347 ucr2 = imx_uart_readl(sport, UCR2); 1348 ucr2 &= ~UCR2_SRST; 1349 imx_uart_writel(sport, ucr2, UCR2); 1350 1351 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1352 udelay(1); 1353 1354 /* 1355 * Finally, clear and enable interrupts 1356 */ 1357 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 1358 imx_uart_writel(sport, USR2_ORE, USR2); 1359 1360 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 1361 ucr1 |= UCR1_UARTEN; 1362 if (sport->have_rtscts) 1363 ucr1 |= UCR1_RTSDEN; 1364 1365 imx_uart_writel(sport, ucr1, UCR1); 1366 1367 ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 1368 if (!sport->dma_is_enabled) 1369 ucr4 |= UCR4_OREN; 1370 imx_uart_writel(sport, ucr4, UCR4); 1371 1372 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 1373 ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1374 if (!sport->have_rtscts) 1375 ucr2 |= UCR2_IRTS; 1376 /* 1377 * make sure the edge sensitive RTS-irq is disabled, 1378 * we're using RTSD instead. 1379 */ 1380 if (!imx_uart_is_imx1(sport)) 1381 ucr2 &= ~UCR2_RTSEN; 1382 imx_uart_writel(sport, ucr2, UCR2); 1383 1384 if (!imx_uart_is_imx1(sport)) { 1385 u32 ucr3; 1386 1387 ucr3 = imx_uart_readl(sport, UCR3); 1388 1389 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 1390 1391 if (sport->dte_mode) 1392 /* disable broken interrupts */ 1393 ucr3 &= ~(UCR3_RI | UCR3_DCD); 1394 1395 imx_uart_writel(sport, ucr3, UCR3); 1396 } 1397 1398 /* 1399 * Enable modem status interrupts 1400 */ 1401 imx_uart_enable_ms(&sport->port); 1402 1403 if (dma_is_inited) { 1404 imx_uart_enable_dma(sport); 1405 imx_uart_start_rx_dma(sport); 1406 } else { 1407 ucr1 = imx_uart_readl(sport, UCR1); 1408 ucr1 |= UCR1_RRDYEN; 1409 imx_uart_writel(sport, ucr1, UCR1); 1410 1411 ucr2 = imx_uart_readl(sport, UCR2); 1412 ucr2 |= UCR2_ATEN; 1413 imx_uart_writel(sport, ucr2, UCR2); 1414 } 1415 1416 spin_unlock_irqrestore(&sport->port.lock, flags); 1417 1418 return 0; 1419 } 1420 1421 static void imx_uart_shutdown(struct uart_port *port) 1422 { 1423 struct imx_port *sport = (struct imx_port *)port; 1424 unsigned long flags; 1425 u32 ucr1, ucr2, ucr4; 1426 1427 if (sport->dma_is_enabled) { 1428 dmaengine_terminate_sync(sport->dma_chan_tx); 1429 if (sport->dma_is_txing) { 1430 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 1431 sport->dma_tx_nents, DMA_TO_DEVICE); 1432 sport->dma_is_txing = 0; 1433 } 1434 dmaengine_terminate_sync(sport->dma_chan_rx); 1435 if (sport->dma_is_rxing) { 1436 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1437 1, DMA_FROM_DEVICE); 1438 sport->dma_is_rxing = 0; 1439 } 1440 1441 spin_lock_irqsave(&sport->port.lock, flags); 1442 imx_uart_stop_tx(port); 1443 imx_uart_stop_rx(port); 1444 imx_uart_disable_dma(sport); 1445 spin_unlock_irqrestore(&sport->port.lock, flags); 1446 imx_uart_dma_exit(sport); 1447 } 1448 1449 mctrl_gpio_disable_ms(sport->gpios); 1450 1451 spin_lock_irqsave(&sport->port.lock, flags); 1452 ucr2 = imx_uart_readl(sport, UCR2); 1453 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 1454 imx_uart_writel(sport, ucr2, UCR2); 1455 1456 ucr4 = imx_uart_readl(sport, UCR4); 1457 ucr4 &= ~UCR4_OREN; 1458 imx_uart_writel(sport, ucr4, UCR4); 1459 spin_unlock_irqrestore(&sport->port.lock, flags); 1460 1461 /* 1462 * Stop our timer. 1463 */ 1464 del_timer_sync(&sport->timer); 1465 1466 /* 1467 * Disable all interrupts, port and break condition. 1468 */ 1469 1470 spin_lock_irqsave(&sport->port.lock, flags); 1471 ucr1 = imx_uart_readl(sport, UCR1); 1472 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1473 1474 imx_uart_writel(sport, ucr1, UCR1); 1475 spin_unlock_irqrestore(&sport->port.lock, flags); 1476 1477 clk_disable_unprepare(sport->clk_per); 1478 clk_disable_unprepare(sport->clk_ipg); 1479 } 1480 1481 /* called with port.lock taken and irqs off */ 1482 static void imx_uart_flush_buffer(struct uart_port *port) 1483 { 1484 struct imx_port *sport = (struct imx_port *)port; 1485 struct scatterlist *sgl = &sport->tx_sgl[0]; 1486 u32 ucr2; 1487 int i = 100, ubir, ubmr, uts; 1488 1489 if (!sport->dma_chan_tx) 1490 return; 1491 1492 sport->tx_bytes = 0; 1493 dmaengine_terminate_all(sport->dma_chan_tx); 1494 if (sport->dma_is_txing) { 1495 u32 ucr1; 1496 1497 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1498 DMA_TO_DEVICE); 1499 ucr1 = imx_uart_readl(sport, UCR1); 1500 ucr1 &= ~UCR1_TXDMAEN; 1501 imx_uart_writel(sport, ucr1, UCR1); 1502 sport->dma_is_txing = 0; 1503 } 1504 1505 /* 1506 * According to the Reference Manual description of the UART SRST bit: 1507 * 1508 * "Reset the transmit and receive state machines, 1509 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1510 * and UTS[6-3]". 1511 * 1512 * We don't need to restore the old values from USR1, USR2, URXD and 1513 * UTXD. UBRC is read only, so only save/restore the other three 1514 * registers. 1515 */ 1516 ubir = imx_uart_readl(sport, UBIR); 1517 ubmr = imx_uart_readl(sport, UBMR); 1518 uts = imx_uart_readl(sport, IMX21_UTS); 1519 1520 ucr2 = imx_uart_readl(sport, UCR2); 1521 ucr2 &= ~UCR2_SRST; 1522 imx_uart_writel(sport, ucr2, UCR2); 1523 1524 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1525 udelay(1); 1526 1527 /* Restore the registers */ 1528 imx_uart_writel(sport, ubir, UBIR); 1529 imx_uart_writel(sport, ubmr, UBMR); 1530 imx_uart_writel(sport, uts, IMX21_UTS); 1531 } 1532 1533 static void 1534 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1535 struct ktermios *old) 1536 { 1537 struct imx_port *sport = (struct imx_port *)port; 1538 unsigned long flags; 1539 u32 ucr2, old_ucr1, old_ucr2, ufcr; 1540 unsigned int baud, quot; 1541 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1542 unsigned long div; 1543 unsigned long num, denom; 1544 uint64_t tdiv64; 1545 1546 /* 1547 * We only support CS7 and CS8. 1548 */ 1549 while ((termios->c_cflag & CSIZE) != CS7 && 1550 (termios->c_cflag & CSIZE) != CS8) { 1551 termios->c_cflag &= ~CSIZE; 1552 termios->c_cflag |= old_csize; 1553 old_csize = CS8; 1554 } 1555 1556 if ((termios->c_cflag & CSIZE) == CS8) 1557 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1558 else 1559 ucr2 = UCR2_SRST | UCR2_IRTS; 1560 1561 if (termios->c_cflag & CRTSCTS) { 1562 if (sport->have_rtscts) { 1563 ucr2 &= ~UCR2_IRTS; 1564 1565 if (port->rs485.flags & SER_RS485_ENABLED) { 1566 /* 1567 * RTS is mandatory for rs485 operation, so keep 1568 * it under manual control and keep transmitter 1569 * disabled. 1570 */ 1571 if (port->rs485.flags & 1572 SER_RS485_RTS_AFTER_SEND) 1573 imx_uart_rts_active(sport, &ucr2); 1574 else 1575 imx_uart_rts_inactive(sport, &ucr2); 1576 } else { 1577 imx_uart_rts_auto(sport, &ucr2); 1578 } 1579 } else { 1580 termios->c_cflag &= ~CRTSCTS; 1581 } 1582 } else if (port->rs485.flags & SER_RS485_ENABLED) { 1583 /* disable transmitter */ 1584 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1585 imx_uart_rts_active(sport, &ucr2); 1586 else 1587 imx_uart_rts_inactive(sport, &ucr2); 1588 } 1589 1590 1591 if (termios->c_cflag & CSTOPB) 1592 ucr2 |= UCR2_STPB; 1593 if (termios->c_cflag & PARENB) { 1594 ucr2 |= UCR2_PREN; 1595 if (termios->c_cflag & PARODD) 1596 ucr2 |= UCR2_PROE; 1597 } 1598 1599 del_timer_sync(&sport->timer); 1600 1601 /* 1602 * Ask the core to calculate the divisor for us. 1603 */ 1604 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1605 quot = uart_get_divisor(port, baud); 1606 1607 spin_lock_irqsave(&sport->port.lock, flags); 1608 1609 sport->port.read_status_mask = 0; 1610 if (termios->c_iflag & INPCK) 1611 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1612 if (termios->c_iflag & (BRKINT | PARMRK)) 1613 sport->port.read_status_mask |= URXD_BRK; 1614 1615 /* 1616 * Characters to ignore 1617 */ 1618 sport->port.ignore_status_mask = 0; 1619 if (termios->c_iflag & IGNPAR) 1620 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1621 if (termios->c_iflag & IGNBRK) { 1622 sport->port.ignore_status_mask |= URXD_BRK; 1623 /* 1624 * If we're ignoring parity and break indicators, 1625 * ignore overruns too (for real raw support). 1626 */ 1627 if (termios->c_iflag & IGNPAR) 1628 sport->port.ignore_status_mask |= URXD_OVRRUN; 1629 } 1630 1631 if ((termios->c_cflag & CREAD) == 0) 1632 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1633 1634 /* 1635 * Update the per-port timeout. 1636 */ 1637 uart_update_timeout(port, termios->c_cflag, baud); 1638 1639 /* 1640 * disable interrupts and drain transmitter 1641 */ 1642 old_ucr1 = imx_uart_readl(sport, UCR1); 1643 imx_uart_writel(sport, 1644 old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1645 UCR1); 1646 old_ucr2 = imx_uart_readl(sport, UCR2); 1647 imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2); 1648 1649 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)) 1650 barrier(); 1651 1652 /* then, disable everything */ 1653 imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2); 1654 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1655 1656 /* custom-baudrate handling */ 1657 div = sport->port.uartclk / (baud * 16); 1658 if (baud == 38400 && quot != div) 1659 baud = sport->port.uartclk / (quot * 16); 1660 1661 div = sport->port.uartclk / (baud * 16); 1662 if (div > 7) 1663 div = 7; 1664 if (!div) 1665 div = 1; 1666 1667 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1668 1 << 16, 1 << 16, &num, &denom); 1669 1670 tdiv64 = sport->port.uartclk; 1671 tdiv64 *= num; 1672 do_div(tdiv64, denom * 16 * div); 1673 tty_termios_encode_baud_rate(termios, 1674 (speed_t)tdiv64, (speed_t)tdiv64); 1675 1676 num -= 1; 1677 denom -= 1; 1678 1679 ufcr = imx_uart_readl(sport, UFCR); 1680 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1681 imx_uart_writel(sport, ufcr, UFCR); 1682 1683 imx_uart_writel(sport, num, UBIR); 1684 imx_uart_writel(sport, denom, UBMR); 1685 1686 if (!imx_uart_is_imx1(sport)) 1687 imx_uart_writel(sport, sport->port.uartclk / div / 1000, 1688 IMX21_ONEMS); 1689 1690 imx_uart_writel(sport, old_ucr1, UCR1); 1691 1692 /* set the parity, stop bits and data size */ 1693 imx_uart_writel(sport, ucr2 | old_ucr2, UCR2); 1694 1695 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1696 imx_uart_enable_ms(&sport->port); 1697 1698 spin_unlock_irqrestore(&sport->port.lock, flags); 1699 } 1700 1701 static const char *imx_uart_type(struct uart_port *port) 1702 { 1703 struct imx_port *sport = (struct imx_port *)port; 1704 1705 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1706 } 1707 1708 /* 1709 * Configure/autoconfigure the port. 1710 */ 1711 static void imx_uart_config_port(struct uart_port *port, int flags) 1712 { 1713 struct imx_port *sport = (struct imx_port *)port; 1714 1715 if (flags & UART_CONFIG_TYPE) 1716 sport->port.type = PORT_IMX; 1717 } 1718 1719 /* 1720 * Verify the new serial_struct (for TIOCSSERIAL). 1721 * The only change we allow are to the flags and type, and 1722 * even then only between PORT_IMX and PORT_UNKNOWN 1723 */ 1724 static int 1725 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1726 { 1727 struct imx_port *sport = (struct imx_port *)port; 1728 int ret = 0; 1729 1730 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1731 ret = -EINVAL; 1732 if (sport->port.irq != ser->irq) 1733 ret = -EINVAL; 1734 if (ser->io_type != UPIO_MEM) 1735 ret = -EINVAL; 1736 if (sport->port.uartclk / 16 != ser->baud_base) 1737 ret = -EINVAL; 1738 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1739 ret = -EINVAL; 1740 if (sport->port.iobase != ser->port) 1741 ret = -EINVAL; 1742 if (ser->hub6 != 0) 1743 ret = -EINVAL; 1744 return ret; 1745 } 1746 1747 #if defined(CONFIG_CONSOLE_POLL) 1748 1749 static int imx_uart_poll_init(struct uart_port *port) 1750 { 1751 struct imx_port *sport = (struct imx_port *)port; 1752 unsigned long flags; 1753 u32 ucr1, ucr2; 1754 int retval; 1755 1756 retval = clk_prepare_enable(sport->clk_ipg); 1757 if (retval) 1758 return retval; 1759 retval = clk_prepare_enable(sport->clk_per); 1760 if (retval) 1761 clk_disable_unprepare(sport->clk_ipg); 1762 1763 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1764 1765 spin_lock_irqsave(&sport->port.lock, flags); 1766 1767 /* 1768 * Be careful about the order of enabling bits here. First enable the 1769 * receiver (UARTEN + RXEN) and only then the corresponding irqs. 1770 * This prevents that a character that already sits in the RX fifo is 1771 * triggering an irq but the try to fetch it from there results in an 1772 * exception because UARTEN or RXEN is still off. 1773 */ 1774 ucr1 = imx_uart_readl(sport, UCR1); 1775 ucr2 = imx_uart_readl(sport, UCR2); 1776 1777 if (imx_uart_is_imx1(sport)) 1778 ucr1 |= IMX1_UCR1_UARTCLKEN; 1779 1780 ucr1 |= UCR1_UARTEN; 1781 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN); 1782 1783 ucr2 |= UCR2_RXEN; 1784 ucr2 &= ~UCR2_ATEN; 1785 1786 imx_uart_writel(sport, ucr1, UCR1); 1787 imx_uart_writel(sport, ucr2, UCR2); 1788 1789 /* now enable irqs */ 1790 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 1791 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 1792 1793 spin_unlock_irqrestore(&sport->port.lock, flags); 1794 1795 return 0; 1796 } 1797 1798 static int imx_uart_poll_get_char(struct uart_port *port) 1799 { 1800 struct imx_port *sport = (struct imx_port *)port; 1801 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 1802 return NO_POLL_CHAR; 1803 1804 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 1805 } 1806 1807 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 1808 { 1809 struct imx_port *sport = (struct imx_port *)port; 1810 unsigned int status; 1811 1812 /* drain */ 1813 do { 1814 status = imx_uart_readl(sport, USR1); 1815 } while (~status & USR1_TRDY); 1816 1817 /* write */ 1818 imx_uart_writel(sport, c, URTX0); 1819 1820 /* flush */ 1821 do { 1822 status = imx_uart_readl(sport, USR2); 1823 } while (~status & USR2_TXDC); 1824 } 1825 #endif 1826 1827 /* called with port.lock taken and irqs off or from .probe without locking */ 1828 static int imx_uart_rs485_config(struct uart_port *port, 1829 struct serial_rs485 *rs485conf) 1830 { 1831 struct imx_port *sport = (struct imx_port *)port; 1832 u32 ucr2; 1833 1834 /* unimplemented */ 1835 rs485conf->delay_rts_before_send = 0; 1836 rs485conf->delay_rts_after_send = 0; 1837 1838 /* RTS is required to control the transmitter */ 1839 if (!sport->have_rtscts && !sport->have_rtsgpio) 1840 rs485conf->flags &= ~SER_RS485_ENABLED; 1841 1842 if (rs485conf->flags & SER_RS485_ENABLED) { 1843 /* Enable receiver if low-active RTS signal is requested */ 1844 if (sport->have_rtscts && !sport->have_rtsgpio && 1845 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 1846 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1847 1848 /* disable transmitter */ 1849 ucr2 = imx_uart_readl(sport, UCR2); 1850 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1851 imx_uart_rts_active(sport, &ucr2); 1852 else 1853 imx_uart_rts_inactive(sport, &ucr2); 1854 imx_uart_writel(sport, ucr2, UCR2); 1855 } 1856 1857 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 1858 if (!(rs485conf->flags & SER_RS485_ENABLED) || 1859 rs485conf->flags & SER_RS485_RX_DURING_TX) 1860 imx_uart_start_rx(port); 1861 1862 port->rs485 = *rs485conf; 1863 1864 return 0; 1865 } 1866 1867 static const struct uart_ops imx_uart_pops = { 1868 .tx_empty = imx_uart_tx_empty, 1869 .set_mctrl = imx_uart_set_mctrl, 1870 .get_mctrl = imx_uart_get_mctrl, 1871 .stop_tx = imx_uart_stop_tx, 1872 .start_tx = imx_uart_start_tx, 1873 .stop_rx = imx_uart_stop_rx, 1874 .enable_ms = imx_uart_enable_ms, 1875 .break_ctl = imx_uart_break_ctl, 1876 .startup = imx_uart_startup, 1877 .shutdown = imx_uart_shutdown, 1878 .flush_buffer = imx_uart_flush_buffer, 1879 .set_termios = imx_uart_set_termios, 1880 .type = imx_uart_type, 1881 .config_port = imx_uart_config_port, 1882 .verify_port = imx_uart_verify_port, 1883 #if defined(CONFIG_CONSOLE_POLL) 1884 .poll_init = imx_uart_poll_init, 1885 .poll_get_char = imx_uart_poll_get_char, 1886 .poll_put_char = imx_uart_poll_put_char, 1887 #endif 1888 }; 1889 1890 static struct imx_port *imx_uart_ports[UART_NR]; 1891 1892 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1893 static void imx_uart_console_putchar(struct uart_port *port, int ch) 1894 { 1895 struct imx_port *sport = (struct imx_port *)port; 1896 1897 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1898 barrier(); 1899 1900 imx_uart_writel(sport, ch, URTX0); 1901 } 1902 1903 /* 1904 * Interrupts are disabled on entering 1905 */ 1906 static void 1907 imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1908 { 1909 struct imx_port *sport = imx_uart_ports[co->index]; 1910 struct imx_port_ucrs old_ucr; 1911 unsigned int ucr1; 1912 unsigned long flags = 0; 1913 int locked = 1; 1914 int retval; 1915 1916 retval = clk_enable(sport->clk_per); 1917 if (retval) 1918 return; 1919 retval = clk_enable(sport->clk_ipg); 1920 if (retval) { 1921 clk_disable(sport->clk_per); 1922 return; 1923 } 1924 1925 if (sport->port.sysrq) 1926 locked = 0; 1927 else if (oops_in_progress) 1928 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1929 else 1930 spin_lock_irqsave(&sport->port.lock, flags); 1931 1932 /* 1933 * First, save UCR1/2/3 and then disable interrupts 1934 */ 1935 imx_uart_ucrs_save(sport, &old_ucr); 1936 ucr1 = old_ucr.ucr1; 1937 1938 if (imx_uart_is_imx1(sport)) 1939 ucr1 |= IMX1_UCR1_UARTCLKEN; 1940 ucr1 |= UCR1_UARTEN; 1941 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1942 1943 imx_uart_writel(sport, ucr1, UCR1); 1944 1945 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1946 1947 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 1948 1949 /* 1950 * Finally, wait for transmitter to become empty 1951 * and restore UCR1/2/3 1952 */ 1953 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1954 1955 imx_uart_ucrs_restore(sport, &old_ucr); 1956 1957 if (locked) 1958 spin_unlock_irqrestore(&sport->port.lock, flags); 1959 1960 clk_disable(sport->clk_ipg); 1961 clk_disable(sport->clk_per); 1962 } 1963 1964 /* 1965 * If the port was already initialised (eg, by a boot loader), 1966 * try to determine the current setup. 1967 */ 1968 static void __init 1969 imx_uart_console_get_options(struct imx_port *sport, int *baud, 1970 int *parity, int *bits) 1971 { 1972 1973 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1974 /* ok, the port was enabled */ 1975 unsigned int ucr2, ubir, ubmr, uartclk; 1976 unsigned int baud_raw; 1977 unsigned int ucfr_rfdiv; 1978 1979 ucr2 = imx_uart_readl(sport, UCR2); 1980 1981 *parity = 'n'; 1982 if (ucr2 & UCR2_PREN) { 1983 if (ucr2 & UCR2_PROE) 1984 *parity = 'o'; 1985 else 1986 *parity = 'e'; 1987 } 1988 1989 if (ucr2 & UCR2_WS) 1990 *bits = 8; 1991 else 1992 *bits = 7; 1993 1994 ubir = imx_uart_readl(sport, UBIR) & 0xffff; 1995 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 1996 1997 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 1998 if (ucfr_rfdiv == 6) 1999 ucfr_rfdiv = 7; 2000 else 2001 ucfr_rfdiv = 6 - ucfr_rfdiv; 2002 2003 uartclk = clk_get_rate(sport->clk_per); 2004 uartclk /= ucfr_rfdiv; 2005 2006 { /* 2007 * The next code provides exact computation of 2008 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2009 * without need of float support or long long division, 2010 * which would be required to prevent 32bit arithmetic overflow 2011 */ 2012 unsigned int mul = ubir + 1; 2013 unsigned int div = 16 * (ubmr + 1); 2014 unsigned int rem = uartclk % div; 2015 2016 baud_raw = (uartclk / div) * mul; 2017 baud_raw += (rem * mul + div / 2) / div; 2018 *baud = (baud_raw + 50) / 100 * 100; 2019 } 2020 2021 if (*baud != baud_raw) 2022 pr_info("Console IMX rounded baud rate from %d to %d\n", 2023 baud_raw, *baud); 2024 } 2025 } 2026 2027 static int __init 2028 imx_uart_console_setup(struct console *co, char *options) 2029 { 2030 struct imx_port *sport; 2031 int baud = 9600; 2032 int bits = 8; 2033 int parity = 'n'; 2034 int flow = 'n'; 2035 int retval; 2036 2037 /* 2038 * Check whether an invalid uart number has been specified, and 2039 * if so, search for the first available port that does have 2040 * console support. 2041 */ 2042 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2043 co->index = 0; 2044 sport = imx_uart_ports[co->index]; 2045 if (sport == NULL) 2046 return -ENODEV; 2047 2048 /* For setting the registers, we only need to enable the ipg clock. */ 2049 retval = clk_prepare_enable(sport->clk_ipg); 2050 if (retval) 2051 goto error_console; 2052 2053 if (options) 2054 uart_parse_options(options, &baud, &parity, &bits, &flow); 2055 else 2056 imx_uart_console_get_options(sport, &baud, &parity, &bits); 2057 2058 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2059 2060 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 2061 2062 clk_disable(sport->clk_ipg); 2063 if (retval) { 2064 clk_unprepare(sport->clk_ipg); 2065 goto error_console; 2066 } 2067 2068 retval = clk_prepare(sport->clk_per); 2069 if (retval) 2070 clk_disable_unprepare(sport->clk_ipg); 2071 2072 error_console: 2073 return retval; 2074 } 2075 2076 static struct uart_driver imx_uart_uart_driver; 2077 static struct console imx_uart_console = { 2078 .name = DEV_NAME, 2079 .write = imx_uart_console_write, 2080 .device = uart_console_device, 2081 .setup = imx_uart_console_setup, 2082 .flags = CON_PRINTBUFFER, 2083 .index = -1, 2084 .data = &imx_uart_uart_driver, 2085 }; 2086 2087 #define IMX_CONSOLE &imx_uart_console 2088 2089 #ifdef CONFIG_OF 2090 static void imx_uart_console_early_putchar(struct uart_port *port, int ch) 2091 { 2092 struct imx_port *sport = (struct imx_port *)port; 2093 2094 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2095 cpu_relax(); 2096 2097 imx_uart_writel(sport, ch, URTX0); 2098 } 2099 2100 static void imx_uart_console_early_write(struct console *con, const char *s, 2101 unsigned count) 2102 { 2103 struct earlycon_device *dev = con->data; 2104 2105 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar); 2106 } 2107 2108 static int __init 2109 imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2110 { 2111 if (!dev->port.membase) 2112 return -ENODEV; 2113 2114 dev->con->write = imx_uart_console_early_write; 2115 2116 return 0; 2117 } 2118 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2119 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2120 #endif 2121 2122 #else 2123 #define IMX_CONSOLE NULL 2124 #endif 2125 2126 static struct uart_driver imx_uart_uart_driver = { 2127 .owner = THIS_MODULE, 2128 .driver_name = DRIVER_NAME, 2129 .dev_name = DEV_NAME, 2130 .major = SERIAL_IMX_MAJOR, 2131 .minor = MINOR_START, 2132 .nr = ARRAY_SIZE(imx_uart_ports), 2133 .cons = IMX_CONSOLE, 2134 }; 2135 2136 #ifdef CONFIG_OF 2137 /* 2138 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 2139 * could successfully get all information from dt or a negative errno. 2140 */ 2141 static int imx_uart_probe_dt(struct imx_port *sport, 2142 struct platform_device *pdev) 2143 { 2144 struct device_node *np = pdev->dev.of_node; 2145 int ret; 2146 2147 sport->devdata = of_device_get_match_data(&pdev->dev); 2148 if (!sport->devdata) 2149 /* no device tree device */ 2150 return 1; 2151 2152 ret = of_alias_get_id(np, "serial"); 2153 if (ret < 0) { 2154 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2155 return ret; 2156 } 2157 sport->port.line = ret; 2158 2159 if (of_get_property(np, "uart-has-rtscts", NULL) || 2160 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 2161 sport->have_rtscts = 1; 2162 2163 if (of_get_property(np, "fsl,dte-mode", NULL)) 2164 sport->dte_mode = 1; 2165 2166 if (of_get_property(np, "rts-gpios", NULL)) 2167 sport->have_rtsgpio = 1; 2168 2169 return 0; 2170 } 2171 #else 2172 static inline int imx_uart_probe_dt(struct imx_port *sport, 2173 struct platform_device *pdev) 2174 { 2175 return 1; 2176 } 2177 #endif 2178 2179 static void imx_uart_probe_pdata(struct imx_port *sport, 2180 struct platform_device *pdev) 2181 { 2182 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 2183 2184 sport->port.line = pdev->id; 2185 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 2186 2187 if (!pdata) 2188 return; 2189 2190 if (pdata->flags & IMXUART_HAVE_RTSCTS) 2191 sport->have_rtscts = 1; 2192 } 2193 2194 static int imx_uart_probe(struct platform_device *pdev) 2195 { 2196 struct imx_port *sport; 2197 void __iomem *base; 2198 int ret = 0; 2199 u32 ucr1; 2200 struct resource *res; 2201 int txirq, rxirq, rtsirq; 2202 2203 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2204 if (!sport) 2205 return -ENOMEM; 2206 2207 ret = imx_uart_probe_dt(sport, pdev); 2208 if (ret > 0) 2209 imx_uart_probe_pdata(sport, pdev); 2210 else if (ret < 0) 2211 return ret; 2212 2213 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 2214 dev_err(&pdev->dev, "serial%d out of range\n", 2215 sport->port.line); 2216 return -EINVAL; 2217 } 2218 2219 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2220 base = devm_ioremap_resource(&pdev->dev, res); 2221 if (IS_ERR(base)) 2222 return PTR_ERR(base); 2223 2224 rxirq = platform_get_irq(pdev, 0); 2225 txirq = platform_get_irq(pdev, 1); 2226 rtsirq = platform_get_irq(pdev, 2); 2227 2228 sport->port.dev = &pdev->dev; 2229 sport->port.mapbase = res->start; 2230 sport->port.membase = base; 2231 sport->port.type = PORT_IMX, 2232 sport->port.iotype = UPIO_MEM; 2233 sport->port.irq = rxirq; 2234 sport->port.fifosize = 32; 2235 sport->port.ops = &imx_uart_pops; 2236 sport->port.rs485_config = imx_uart_rs485_config; 2237 sport->port.flags = UPF_BOOT_AUTOCONF; 2238 timer_setup(&sport->timer, imx_uart_timeout, 0); 2239 2240 sport->gpios = mctrl_gpio_init(&sport->port, 0); 2241 if (IS_ERR(sport->gpios)) 2242 return PTR_ERR(sport->gpios); 2243 2244 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2245 if (IS_ERR(sport->clk_ipg)) { 2246 ret = PTR_ERR(sport->clk_ipg); 2247 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 2248 return ret; 2249 } 2250 2251 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 2252 if (IS_ERR(sport->clk_per)) { 2253 ret = PTR_ERR(sport->clk_per); 2254 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 2255 return ret; 2256 } 2257 2258 sport->port.uartclk = clk_get_rate(sport->clk_per); 2259 2260 /* For register access, we only need to enable the ipg clock. */ 2261 ret = clk_prepare_enable(sport->clk_ipg); 2262 if (ret) { 2263 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 2264 return ret; 2265 } 2266 2267 /* initialize shadow register values */ 2268 sport->ucr1 = readl(sport->port.membase + UCR1); 2269 sport->ucr2 = readl(sport->port.membase + UCR2); 2270 sport->ucr3 = readl(sport->port.membase + UCR3); 2271 sport->ucr4 = readl(sport->port.membase + UCR4); 2272 sport->ufcr = readl(sport->port.membase + UFCR); 2273 2274 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2275 2276 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2277 (!sport->have_rtscts && !sport->have_rtsgpio)) 2278 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2279 2280 /* 2281 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 2282 * signal cannot be set low during transmission in case the 2283 * receiver is off (limitation of the i.MX UART IP). 2284 */ 2285 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2286 sport->have_rtscts && !sport->have_rtsgpio && 2287 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 2288 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 2289 dev_err(&pdev->dev, 2290 "low-active RTS not possible when receiver is off, enabling receiver\n"); 2291 2292 imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2293 2294 /* Disable interrupts before requesting them */ 2295 ucr1 = imx_uart_readl(sport, UCR1); 2296 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 2297 UCR1_TXMPTYEN | UCR1_RTSDEN); 2298 imx_uart_writel(sport, ucr1, UCR1); 2299 2300 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2301 /* 2302 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2303 * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2304 * and DCD (when they are outputs) or enables the respective 2305 * irqs. So set this bit early, i.e. before requesting irqs. 2306 */ 2307 u32 ufcr = imx_uart_readl(sport, UFCR); 2308 if (!(ufcr & UFCR_DCEDTE)) 2309 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2310 2311 /* 2312 * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2313 * enabled later because they cannot be cleared 2314 * (confirmed on i.MX25) which makes them unusable. 2315 */ 2316 imx_uart_writel(sport, 2317 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2318 UCR3); 2319 2320 } else { 2321 u32 ucr3 = UCR3_DSR; 2322 u32 ufcr = imx_uart_readl(sport, UFCR); 2323 if (ufcr & UFCR_DCEDTE) 2324 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 2325 2326 if (!imx_uart_is_imx1(sport)) 2327 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 2328 imx_uart_writel(sport, ucr3, UCR3); 2329 } 2330 2331 clk_disable_unprepare(sport->clk_ipg); 2332 2333 /* 2334 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2335 * chips only have one interrupt. 2336 */ 2337 if (txirq > 0) { 2338 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2339 dev_name(&pdev->dev), sport); 2340 if (ret) { 2341 dev_err(&pdev->dev, "failed to request rx irq: %d\n", 2342 ret); 2343 return ret; 2344 } 2345 2346 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2347 dev_name(&pdev->dev), sport); 2348 if (ret) { 2349 dev_err(&pdev->dev, "failed to request tx irq: %d\n", 2350 ret); 2351 return ret; 2352 } 2353 } else { 2354 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2355 dev_name(&pdev->dev), sport); 2356 if (ret) { 2357 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2358 return ret; 2359 } 2360 } 2361 2362 imx_uart_ports[sport->port.line] = sport; 2363 2364 platform_set_drvdata(pdev, sport); 2365 2366 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2367 } 2368 2369 static int imx_uart_remove(struct platform_device *pdev) 2370 { 2371 struct imx_port *sport = platform_get_drvdata(pdev); 2372 2373 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2374 } 2375 2376 static void imx_uart_restore_context(struct imx_port *sport) 2377 { 2378 if (!sport->context_saved) 2379 return; 2380 2381 imx_uart_writel(sport, sport->saved_reg[4], UFCR); 2382 imx_uart_writel(sport, sport->saved_reg[5], UESC); 2383 imx_uart_writel(sport, sport->saved_reg[6], UTIM); 2384 imx_uart_writel(sport, sport->saved_reg[7], UBIR); 2385 imx_uart_writel(sport, sport->saved_reg[8], UBMR); 2386 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 2387 imx_uart_writel(sport, sport->saved_reg[0], UCR1); 2388 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 2389 imx_uart_writel(sport, sport->saved_reg[2], UCR3); 2390 imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2391 sport->context_saved = false; 2392 } 2393 2394 static void imx_uart_save_context(struct imx_port *sport) 2395 { 2396 /* Save necessary regs */ 2397 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 2398 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 2399 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 2400 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 2401 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 2402 sport->saved_reg[5] = imx_uart_readl(sport, UESC); 2403 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 2404 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 2405 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 2406 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2407 sport->context_saved = true; 2408 } 2409 2410 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2411 { 2412 u32 ucr3; 2413 2414 ucr3 = imx_uart_readl(sport, UCR3); 2415 if (on) { 2416 imx_uart_writel(sport, USR1_AWAKE, USR1); 2417 ucr3 |= UCR3_AWAKEN; 2418 } else { 2419 ucr3 &= ~UCR3_AWAKEN; 2420 } 2421 imx_uart_writel(sport, ucr3, UCR3); 2422 2423 if (sport->have_rtscts) { 2424 u32 ucr1 = imx_uart_readl(sport, UCR1); 2425 if (on) 2426 ucr1 |= UCR1_RTSDEN; 2427 else 2428 ucr1 &= ~UCR1_RTSDEN; 2429 imx_uart_writel(sport, ucr1, UCR1); 2430 } 2431 } 2432 2433 static int imx_uart_suspend_noirq(struct device *dev) 2434 { 2435 struct imx_port *sport = dev_get_drvdata(dev); 2436 2437 imx_uart_save_context(sport); 2438 2439 clk_disable(sport->clk_ipg); 2440 2441 return 0; 2442 } 2443 2444 static int imx_uart_resume_noirq(struct device *dev) 2445 { 2446 struct imx_port *sport = dev_get_drvdata(dev); 2447 int ret; 2448 2449 ret = clk_enable(sport->clk_ipg); 2450 if (ret) 2451 return ret; 2452 2453 imx_uart_restore_context(sport); 2454 2455 return 0; 2456 } 2457 2458 static int imx_uart_suspend(struct device *dev) 2459 { 2460 struct imx_port *sport = dev_get_drvdata(dev); 2461 int ret; 2462 2463 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2464 disable_irq(sport->port.irq); 2465 2466 ret = clk_prepare_enable(sport->clk_ipg); 2467 if (ret) 2468 return ret; 2469 2470 /* enable wakeup from i.MX UART */ 2471 imx_uart_enable_wakeup(sport, true); 2472 2473 return 0; 2474 } 2475 2476 static int imx_uart_resume(struct device *dev) 2477 { 2478 struct imx_port *sport = dev_get_drvdata(dev); 2479 2480 /* disable wakeup from i.MX UART */ 2481 imx_uart_enable_wakeup(sport, false); 2482 2483 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2484 enable_irq(sport->port.irq); 2485 2486 clk_disable_unprepare(sport->clk_ipg); 2487 2488 return 0; 2489 } 2490 2491 static int imx_uart_freeze(struct device *dev) 2492 { 2493 struct imx_port *sport = dev_get_drvdata(dev); 2494 2495 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2496 2497 return clk_prepare_enable(sport->clk_ipg); 2498 } 2499 2500 static int imx_uart_thaw(struct device *dev) 2501 { 2502 struct imx_port *sport = dev_get_drvdata(dev); 2503 2504 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2505 2506 clk_disable_unprepare(sport->clk_ipg); 2507 2508 return 0; 2509 } 2510 2511 static const struct dev_pm_ops imx_uart_pm_ops = { 2512 .suspend_noirq = imx_uart_suspend_noirq, 2513 .resume_noirq = imx_uart_resume_noirq, 2514 .freeze_noirq = imx_uart_suspend_noirq, 2515 .restore_noirq = imx_uart_resume_noirq, 2516 .suspend = imx_uart_suspend, 2517 .resume = imx_uart_resume, 2518 .freeze = imx_uart_freeze, 2519 .thaw = imx_uart_thaw, 2520 .restore = imx_uart_thaw, 2521 }; 2522 2523 static struct platform_driver imx_uart_platform_driver = { 2524 .probe = imx_uart_probe, 2525 .remove = imx_uart_remove, 2526 2527 .id_table = imx_uart_devtype, 2528 .driver = { 2529 .name = "imx-uart", 2530 .of_match_table = imx_uart_dt_ids, 2531 .pm = &imx_uart_pm_ops, 2532 }, 2533 }; 2534 2535 static int __init imx_uart_init(void) 2536 { 2537 int ret = uart_register_driver(&imx_uart_uart_driver); 2538 2539 if (ret) 2540 return ret; 2541 2542 ret = platform_driver_register(&imx_uart_platform_driver); 2543 if (ret != 0) 2544 uart_unregister_driver(&imx_uart_uart_driver); 2545 2546 return ret; 2547 } 2548 2549 static void __exit imx_uart_exit(void) 2550 { 2551 platform_driver_unregister(&imx_uart_platform_driver); 2552 uart_unregister_driver(&imx_uart_uart_driver); 2553 } 2554 2555 module_init(imx_uart_init); 2556 module_exit(imx_uart_exit); 2557 2558 MODULE_AUTHOR("Sascha Hauer"); 2559 MODULE_DESCRIPTION("IMX generic serial port driver"); 2560 MODULE_LICENSE("GPL"); 2561 MODULE_ALIAS("platform:imx-uart"); 2562