1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Motorola/Freescale IMX serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Author: Sascha Hauer <sascha@saschahauer.de> 8 * Copyright (C) 2004 Pengutronix 9 */ 10 11 #include <linux/module.h> 12 #include <linux/ioport.h> 13 #include <linux/init.h> 14 #include <linux/console.h> 15 #include <linux/sysrq.h> 16 #include <linux/platform_device.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/ktime.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/rational.h> 26 #include <linux/slab.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 #include <linux/io.h> 30 #include <linux/dma-mapping.h> 31 32 #include <asm/irq.h> 33 #include <linux/platform_data/dma-imx.h> 34 35 #include "serial_mctrl_gpio.h" 36 37 /* Register definitions */ 38 #define URXD0 0x0 /* Receiver Register */ 39 #define URTX0 0x40 /* Transmitter Register */ 40 #define UCR1 0x80 /* Control Register 1 */ 41 #define UCR2 0x84 /* Control Register 2 */ 42 #define UCR3 0x88 /* Control Register 3 */ 43 #define UCR4 0x8c /* Control Register 4 */ 44 #define UFCR 0x90 /* FIFO Control Register */ 45 #define USR1 0x94 /* Status Register 1 */ 46 #define USR2 0x98 /* Status Register 2 */ 47 #define UESC 0x9c /* Escape Character Register */ 48 #define UTIM 0xa0 /* Escape Timer Register */ 49 #define UBIR 0xa4 /* BRM Incremental Register */ 50 #define UBMR 0xa8 /* BRM Modulator Register */ 51 #define UBRC 0xac /* Baud Rate Count Register */ 52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 55 56 /* UART Control Register Bit Fields.*/ 57 #define URXD_DUMMY_READ (1<<16) 58 #define URXD_CHARRDY (1<<15) 59 #define URXD_ERR (1<<14) 60 #define URXD_OVRRUN (1<<13) 61 #define URXD_FRMERR (1<<12) 62 #define URXD_BRK (1<<11) 63 #define URXD_PRERR (1<<10) 64 #define URXD_RX_DATA (0xFF<<0) 65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 72 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 75 #define UCR1_SNDBRK (1<<4) /* Send break */ 76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 79 #define UCR1_DOZE (1<<1) /* Doze */ 80 #define UCR1_UARTEN (1<<0) /* UART enabled */ 81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 83 #define UCR2_CTSC (1<<13) /* CTS pin control */ 84 #define UCR2_CTS (1<<12) /* Clear to send */ 85 #define UCR2_ESCEN (1<<11) /* Escape enable */ 86 #define UCR2_PREN (1<<8) /* Parity enable */ 87 #define UCR2_PROE (1<<7) /* Parity odd/even */ 88 #define UCR2_STPB (1<<6) /* Stop */ 89 #define UCR2_WS (1<<5) /* Word size */ 90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 93 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 94 #define UCR2_SRST (1<<0) /* SW reset */ 95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 96 #define UCR3_PARERREN (1<<12) /* Parity enable */ 97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 98 #define UCR3_DSR (1<<10) /* Data set ready */ 99 #define UCR3_DCD (1<<9) /* Data carrier detect */ 100 #define UCR3_RI (1<<8) /* Ring indicator */ 101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 108 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 116 #define UCR4_IRSC (1<<5) /* IR special case */ 117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 122 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 123 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 125 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 126 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 127 #define USR1_RTSS (1<<14) /* RTS pin status */ 128 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 129 #define USR1_RTSD (1<<12) /* RTS delta */ 130 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 131 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 132 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 133 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 134 #define USR1_DTRD (1<<7) /* DTR Delta */ 135 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 136 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 137 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 138 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 139 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 140 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 141 #define USR2_IDLE (1<<12) /* Idle condition */ 142 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 143 #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 144 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 145 #define USR2_WAKE (1<<7) /* Wake */ 146 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 148 #define USR2_TXDC (1<<3) /* Transmitter complete */ 149 #define USR2_BRCD (1<<2) /* Break condition */ 150 #define USR2_ORE (1<<1) /* Overrun error */ 151 #define USR2_RDR (1<<0) /* Recv data ready */ 152 #define UTS_FRCPERR (1<<13) /* Force parity error */ 153 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 154 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 155 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 156 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 157 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 158 #define UTS_SOFTRST (1<<0) /* Software reset */ 159 160 /* We've been assigned a range on the "Low-density serial ports" major */ 161 #define SERIAL_IMX_MAJOR 207 162 #define MINOR_START 16 163 #define DEV_NAME "ttymxc" 164 165 /* 166 * This determines how often we check the modem status signals 167 * for any change. They generally aren't connected to an IRQ 168 * so we have to poll them. We also check immediately before 169 * filling the TX fifo incase CTS has been dropped. 170 */ 171 #define MCTRL_TIMEOUT (250*HZ/1000) 172 173 #define DRIVER_NAME "IMX-uart" 174 175 #define UART_NR 8 176 177 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 178 enum imx_uart_type { 179 IMX1_UART, 180 IMX21_UART, 181 IMX53_UART, 182 IMX6Q_UART, 183 }; 184 185 /* device type dependent stuff */ 186 struct imx_uart_data { 187 unsigned uts_reg; 188 enum imx_uart_type devtype; 189 }; 190 191 enum imx_tx_state { 192 OFF, 193 WAIT_AFTER_RTS, 194 SEND, 195 WAIT_AFTER_SEND, 196 }; 197 198 struct imx_port { 199 struct uart_port port; 200 struct timer_list timer; 201 unsigned int old_status; 202 unsigned int have_rtscts:1; 203 unsigned int have_rtsgpio:1; 204 unsigned int dte_mode:1; 205 unsigned int inverted_tx:1; 206 unsigned int inverted_rx:1; 207 struct clk *clk_ipg; 208 struct clk *clk_per; 209 const struct imx_uart_data *devdata; 210 211 struct mctrl_gpios *gpios; 212 213 /* shadow registers */ 214 unsigned int ucr1; 215 unsigned int ucr2; 216 unsigned int ucr3; 217 unsigned int ucr4; 218 unsigned int ufcr; 219 220 /* DMA fields */ 221 unsigned int dma_is_enabled:1; 222 unsigned int dma_is_rxing:1; 223 unsigned int dma_is_txing:1; 224 struct dma_chan *dma_chan_rx, *dma_chan_tx; 225 struct scatterlist rx_sgl, tx_sgl[2]; 226 void *rx_buf; 227 struct circ_buf rx_ring; 228 unsigned int rx_buf_size; 229 unsigned int rx_period_length; 230 unsigned int rx_periods; 231 dma_cookie_t rx_cookie; 232 unsigned int tx_bytes; 233 unsigned int dma_tx_nents; 234 unsigned int saved_reg[10]; 235 bool context_saved; 236 237 enum imx_tx_state tx_state; 238 struct hrtimer trigger_start_tx; 239 struct hrtimer trigger_stop_tx; 240 }; 241 242 struct imx_port_ucrs { 243 unsigned int ucr1; 244 unsigned int ucr2; 245 unsigned int ucr3; 246 }; 247 248 static struct imx_uart_data imx_uart_devdata[] = { 249 [IMX1_UART] = { 250 .uts_reg = IMX1_UTS, 251 .devtype = IMX1_UART, 252 }, 253 [IMX21_UART] = { 254 .uts_reg = IMX21_UTS, 255 .devtype = IMX21_UART, 256 }, 257 [IMX53_UART] = { 258 .uts_reg = IMX21_UTS, 259 .devtype = IMX53_UART, 260 }, 261 [IMX6Q_UART] = { 262 .uts_reg = IMX21_UTS, 263 .devtype = IMX6Q_UART, 264 }, 265 }; 266 267 static const struct of_device_id imx_uart_dt_ids[] = { 268 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 269 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 272 { /* sentinel */ } 273 }; 274 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 275 276 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 277 { 278 switch (offset) { 279 case UCR1: 280 sport->ucr1 = val; 281 break; 282 case UCR2: 283 sport->ucr2 = val; 284 break; 285 case UCR3: 286 sport->ucr3 = val; 287 break; 288 case UCR4: 289 sport->ucr4 = val; 290 break; 291 case UFCR: 292 sport->ufcr = val; 293 break; 294 default: 295 break; 296 } 297 writel(val, sport->port.membase + offset); 298 } 299 300 static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 301 { 302 switch (offset) { 303 case UCR1: 304 return sport->ucr1; 305 break; 306 case UCR2: 307 /* 308 * UCR2_SRST is the only bit in the cached registers that might 309 * differ from the value that was last written. As it only 310 * automatically becomes one after being cleared, reread 311 * conditionally. 312 */ 313 if (!(sport->ucr2 & UCR2_SRST)) 314 sport->ucr2 = readl(sport->port.membase + offset); 315 return sport->ucr2; 316 break; 317 case UCR3: 318 return sport->ucr3; 319 break; 320 case UCR4: 321 return sport->ucr4; 322 break; 323 case UFCR: 324 return sport->ufcr; 325 break; 326 default: 327 return readl(sport->port.membase + offset); 328 } 329 } 330 331 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 332 { 333 return sport->devdata->uts_reg; 334 } 335 336 static inline int imx_uart_is_imx1(struct imx_port *sport) 337 { 338 return sport->devdata->devtype == IMX1_UART; 339 } 340 341 static inline int imx_uart_is_imx21(struct imx_port *sport) 342 { 343 return sport->devdata->devtype == IMX21_UART; 344 } 345 346 static inline int imx_uart_is_imx53(struct imx_port *sport) 347 { 348 return sport->devdata->devtype == IMX53_UART; 349 } 350 351 static inline int imx_uart_is_imx6q(struct imx_port *sport) 352 { 353 return sport->devdata->devtype == IMX6Q_UART; 354 } 355 /* 356 * Save and restore functions for UCR1, UCR2 and UCR3 registers 357 */ 358 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 359 static void imx_uart_ucrs_save(struct imx_port *sport, 360 struct imx_port_ucrs *ucr) 361 { 362 /* save control registers */ 363 ucr->ucr1 = imx_uart_readl(sport, UCR1); 364 ucr->ucr2 = imx_uart_readl(sport, UCR2); 365 ucr->ucr3 = imx_uart_readl(sport, UCR3); 366 } 367 368 static void imx_uart_ucrs_restore(struct imx_port *sport, 369 struct imx_port_ucrs *ucr) 370 { 371 /* restore control registers */ 372 imx_uart_writel(sport, ucr->ucr1, UCR1); 373 imx_uart_writel(sport, ucr->ucr2, UCR2); 374 imx_uart_writel(sport, ucr->ucr3, UCR3); 375 } 376 #endif 377 378 /* called with port.lock taken and irqs caller dependent */ 379 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 380 { 381 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 382 383 sport->port.mctrl |= TIOCM_RTS; 384 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 385 } 386 387 /* called with port.lock taken and irqs caller dependent */ 388 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 389 { 390 *ucr2 &= ~UCR2_CTSC; 391 *ucr2 |= UCR2_CTS; 392 393 sport->port.mctrl &= ~TIOCM_RTS; 394 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 395 } 396 397 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 398 { 399 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 400 } 401 402 /* called with port.lock taken and irqs off */ 403 static void imx_uart_start_rx(struct uart_port *port) 404 { 405 struct imx_port *sport = (struct imx_port *)port; 406 unsigned int ucr1, ucr2; 407 408 ucr1 = imx_uart_readl(sport, UCR1); 409 ucr2 = imx_uart_readl(sport, UCR2); 410 411 ucr2 |= UCR2_RXEN; 412 413 if (sport->dma_is_enabled) { 414 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 415 } else { 416 ucr1 |= UCR1_RRDYEN; 417 ucr2 |= UCR2_ATEN; 418 } 419 420 /* Write UCR2 first as it includes RXEN */ 421 imx_uart_writel(sport, ucr2, UCR2); 422 imx_uart_writel(sport, ucr1, UCR1); 423 } 424 425 /* called with port.lock taken and irqs off */ 426 static void imx_uart_stop_tx(struct uart_port *port) 427 { 428 struct imx_port *sport = (struct imx_port *)port; 429 u32 ucr1, ucr4, usr2; 430 431 if (sport->tx_state == OFF) 432 return; 433 434 /* 435 * We are maybe in the SMP context, so if the DMA TX thread is running 436 * on other cpu, we have to wait for it to finish. 437 */ 438 if (sport->dma_is_txing) 439 return; 440 441 ucr1 = imx_uart_readl(sport, UCR1); 442 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 443 444 usr2 = imx_uart_readl(sport, USR2); 445 if (!(usr2 & USR2_TXDC)) { 446 /* The shifter is still busy, so retry once TC triggers */ 447 return; 448 } 449 450 ucr4 = imx_uart_readl(sport, UCR4); 451 ucr4 &= ~UCR4_TCEN; 452 imx_uart_writel(sport, ucr4, UCR4); 453 454 /* in rs485 mode disable transmitter */ 455 if (port->rs485.flags & SER_RS485_ENABLED) { 456 if (sport->tx_state == SEND) { 457 sport->tx_state = WAIT_AFTER_SEND; 458 start_hrtimer_ms(&sport->trigger_stop_tx, 459 port->rs485.delay_rts_after_send); 460 return; 461 } 462 463 if (sport->tx_state == WAIT_AFTER_RTS || 464 sport->tx_state == WAIT_AFTER_SEND) { 465 u32 ucr2; 466 467 hrtimer_try_to_cancel(&sport->trigger_start_tx); 468 469 ucr2 = imx_uart_readl(sport, UCR2); 470 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 471 imx_uart_rts_active(sport, &ucr2); 472 else 473 imx_uart_rts_inactive(sport, &ucr2); 474 imx_uart_writel(sport, ucr2, UCR2); 475 476 imx_uart_start_rx(port); 477 478 sport->tx_state = OFF; 479 } 480 } else { 481 sport->tx_state = OFF; 482 } 483 } 484 485 /* called with port.lock taken and irqs off */ 486 static void imx_uart_stop_rx(struct uart_port *port) 487 { 488 struct imx_port *sport = (struct imx_port *)port; 489 u32 ucr1, ucr2; 490 491 ucr1 = imx_uart_readl(sport, UCR1); 492 ucr2 = imx_uart_readl(sport, UCR2); 493 494 if (sport->dma_is_enabled) { 495 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 496 } else { 497 ucr1 &= ~UCR1_RRDYEN; 498 ucr2 &= ~UCR2_ATEN; 499 } 500 imx_uart_writel(sport, ucr1, UCR1); 501 502 ucr2 &= ~UCR2_RXEN; 503 imx_uart_writel(sport, ucr2, UCR2); 504 } 505 506 /* called with port.lock taken and irqs off */ 507 static void imx_uart_enable_ms(struct uart_port *port) 508 { 509 struct imx_port *sport = (struct imx_port *)port; 510 511 mod_timer(&sport->timer, jiffies); 512 513 mctrl_gpio_enable_ms(sport->gpios); 514 } 515 516 static void imx_uart_dma_tx(struct imx_port *sport); 517 518 /* called with port.lock taken and irqs off */ 519 static inline void imx_uart_transmit_buffer(struct imx_port *sport) 520 { 521 struct circ_buf *xmit = &sport->port.state->xmit; 522 523 if (sport->port.x_char) { 524 /* Send next char */ 525 imx_uart_writel(sport, sport->port.x_char, URTX0); 526 sport->port.icount.tx++; 527 sport->port.x_char = 0; 528 return; 529 } 530 531 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 532 imx_uart_stop_tx(&sport->port); 533 return; 534 } 535 536 if (sport->dma_is_enabled) { 537 u32 ucr1; 538 /* 539 * We've just sent a X-char Ensure the TX DMA is enabled 540 * and the TX IRQ is disabled. 541 **/ 542 ucr1 = imx_uart_readl(sport, UCR1); 543 ucr1 &= ~UCR1_TRDYEN; 544 if (sport->dma_is_txing) { 545 ucr1 |= UCR1_TXDMAEN; 546 imx_uart_writel(sport, ucr1, UCR1); 547 } else { 548 imx_uart_writel(sport, ucr1, UCR1); 549 imx_uart_dma_tx(sport); 550 } 551 552 return; 553 } 554 555 while (!uart_circ_empty(xmit) && 556 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 557 /* send xmit->buf[xmit->tail] 558 * out the port here */ 559 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 560 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 561 sport->port.icount.tx++; 562 } 563 564 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 565 uart_write_wakeup(&sport->port); 566 567 if (uart_circ_empty(xmit)) 568 imx_uart_stop_tx(&sport->port); 569 } 570 571 static void imx_uart_dma_tx_callback(void *data) 572 { 573 struct imx_port *sport = data; 574 struct scatterlist *sgl = &sport->tx_sgl[0]; 575 struct circ_buf *xmit = &sport->port.state->xmit; 576 unsigned long flags; 577 u32 ucr1; 578 579 spin_lock_irqsave(&sport->port.lock, flags); 580 581 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 582 583 ucr1 = imx_uart_readl(sport, UCR1); 584 ucr1 &= ~UCR1_TXDMAEN; 585 imx_uart_writel(sport, ucr1, UCR1); 586 587 /* update the stat */ 588 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 589 sport->port.icount.tx += sport->tx_bytes; 590 591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 592 593 sport->dma_is_txing = 0; 594 595 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 596 uart_write_wakeup(&sport->port); 597 598 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 599 imx_uart_dma_tx(sport); 600 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 601 u32 ucr4 = imx_uart_readl(sport, UCR4); 602 ucr4 |= UCR4_TCEN; 603 imx_uart_writel(sport, ucr4, UCR4); 604 } 605 606 spin_unlock_irqrestore(&sport->port.lock, flags); 607 } 608 609 /* called with port.lock taken and irqs off */ 610 static void imx_uart_dma_tx(struct imx_port *sport) 611 { 612 struct circ_buf *xmit = &sport->port.state->xmit; 613 struct scatterlist *sgl = sport->tx_sgl; 614 struct dma_async_tx_descriptor *desc; 615 struct dma_chan *chan = sport->dma_chan_tx; 616 struct device *dev = sport->port.dev; 617 u32 ucr1, ucr4; 618 int ret; 619 620 if (sport->dma_is_txing) 621 return; 622 623 ucr4 = imx_uart_readl(sport, UCR4); 624 ucr4 &= ~UCR4_TCEN; 625 imx_uart_writel(sport, ucr4, UCR4); 626 627 sport->tx_bytes = uart_circ_chars_pending(xmit); 628 629 if (xmit->tail < xmit->head || xmit->head == 0) { 630 sport->dma_tx_nents = 1; 631 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 632 } else { 633 sport->dma_tx_nents = 2; 634 sg_init_table(sgl, 2); 635 sg_set_buf(sgl, xmit->buf + xmit->tail, 636 UART_XMIT_SIZE - xmit->tail); 637 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 638 } 639 640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 641 if (ret == 0) { 642 dev_err(dev, "DMA mapping error for TX.\n"); 643 return; 644 } 645 desc = dmaengine_prep_slave_sg(chan, sgl, ret, 646 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 647 if (!desc) { 648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 649 DMA_TO_DEVICE); 650 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 651 return; 652 } 653 desc->callback = imx_uart_dma_tx_callback; 654 desc->callback_param = sport; 655 656 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 657 uart_circ_chars_pending(xmit)); 658 659 ucr1 = imx_uart_readl(sport, UCR1); 660 ucr1 |= UCR1_TXDMAEN; 661 imx_uart_writel(sport, ucr1, UCR1); 662 663 /* fire it */ 664 sport->dma_is_txing = 1; 665 dmaengine_submit(desc); 666 dma_async_issue_pending(chan); 667 return; 668 } 669 670 /* called with port.lock taken and irqs off */ 671 static void imx_uart_start_tx(struct uart_port *port) 672 { 673 struct imx_port *sport = (struct imx_port *)port; 674 u32 ucr1; 675 676 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 677 return; 678 679 /* 680 * We cannot simply do nothing here if sport->tx_state == SEND already 681 * because UCR1_TXMPTYEN might already have been cleared in 682 * imx_uart_stop_tx(), but tx_state is still SEND. 683 */ 684 685 if (port->rs485.flags & SER_RS485_ENABLED) { 686 if (sport->tx_state == OFF) { 687 u32 ucr2 = imx_uart_readl(sport, UCR2); 688 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 689 imx_uart_rts_active(sport, &ucr2); 690 else 691 imx_uart_rts_inactive(sport, &ucr2); 692 imx_uart_writel(sport, ucr2, UCR2); 693 694 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 695 imx_uart_stop_rx(port); 696 697 sport->tx_state = WAIT_AFTER_RTS; 698 start_hrtimer_ms(&sport->trigger_start_tx, 699 port->rs485.delay_rts_before_send); 700 return; 701 } 702 703 if (sport->tx_state == WAIT_AFTER_SEND 704 || sport->tx_state == WAIT_AFTER_RTS) { 705 706 hrtimer_try_to_cancel(&sport->trigger_stop_tx); 707 708 /* 709 * Enable transmitter and shifter empty irq only if DMA 710 * is off. In the DMA case this is done in the 711 * tx-callback. 712 */ 713 if (!sport->dma_is_enabled) { 714 u32 ucr4 = imx_uart_readl(sport, UCR4); 715 ucr4 |= UCR4_TCEN; 716 imx_uart_writel(sport, ucr4, UCR4); 717 } 718 719 sport->tx_state = SEND; 720 } 721 } else { 722 sport->tx_state = SEND; 723 } 724 725 if (!sport->dma_is_enabled) { 726 ucr1 = imx_uart_readl(sport, UCR1); 727 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 728 } 729 730 if (sport->dma_is_enabled) { 731 if (sport->port.x_char) { 732 /* We have X-char to send, so enable TX IRQ and 733 * disable TX DMA to let TX interrupt to send X-char */ 734 ucr1 = imx_uart_readl(sport, UCR1); 735 ucr1 &= ~UCR1_TXDMAEN; 736 ucr1 |= UCR1_TRDYEN; 737 imx_uart_writel(sport, ucr1, UCR1); 738 return; 739 } 740 741 if (!uart_circ_empty(&port->state->xmit) && 742 !uart_tx_stopped(port)) 743 imx_uart_dma_tx(sport); 744 return; 745 } 746 } 747 748 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 749 { 750 struct imx_port *sport = dev_id; 751 u32 usr1; 752 753 imx_uart_writel(sport, USR1_RTSD, USR1); 754 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 755 uart_handle_cts_change(&sport->port, !!usr1); 756 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 757 758 return IRQ_HANDLED; 759 } 760 761 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 762 { 763 struct imx_port *sport = dev_id; 764 irqreturn_t ret; 765 766 spin_lock(&sport->port.lock); 767 768 ret = __imx_uart_rtsint(irq, dev_id); 769 770 spin_unlock(&sport->port.lock); 771 772 return ret; 773 } 774 775 static irqreturn_t imx_uart_txint(int irq, void *dev_id) 776 { 777 struct imx_port *sport = dev_id; 778 779 spin_lock(&sport->port.lock); 780 imx_uart_transmit_buffer(sport); 781 spin_unlock(&sport->port.lock); 782 return IRQ_HANDLED; 783 } 784 785 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 786 { 787 struct imx_port *sport = dev_id; 788 unsigned int rx, flg, ignored = 0; 789 struct tty_port *port = &sport->port.state->port; 790 791 while (imx_uart_readl(sport, USR2) & USR2_RDR) { 792 u32 usr2; 793 794 flg = TTY_NORMAL; 795 sport->port.icount.rx++; 796 797 rx = imx_uart_readl(sport, URXD0); 798 799 usr2 = imx_uart_readl(sport, USR2); 800 if (usr2 & USR2_BRCD) { 801 imx_uart_writel(sport, USR2_BRCD, USR2); 802 if (uart_handle_break(&sport->port)) 803 continue; 804 } 805 806 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 807 continue; 808 809 if (unlikely(rx & URXD_ERR)) { 810 if (rx & URXD_BRK) 811 sport->port.icount.brk++; 812 else if (rx & URXD_PRERR) 813 sport->port.icount.parity++; 814 else if (rx & URXD_FRMERR) 815 sport->port.icount.frame++; 816 if (rx & URXD_OVRRUN) 817 sport->port.icount.overrun++; 818 819 if (rx & sport->port.ignore_status_mask) { 820 if (++ignored > 100) 821 goto out; 822 continue; 823 } 824 825 rx &= (sport->port.read_status_mask | 0xFF); 826 827 if (rx & URXD_BRK) 828 flg = TTY_BREAK; 829 else if (rx & URXD_PRERR) 830 flg = TTY_PARITY; 831 else if (rx & URXD_FRMERR) 832 flg = TTY_FRAME; 833 if (rx & URXD_OVRRUN) 834 flg = TTY_OVERRUN; 835 836 sport->port.sysrq = 0; 837 } 838 839 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 840 goto out; 841 842 if (tty_insert_flip_char(port, rx, flg) == 0) 843 sport->port.icount.buf_overrun++; 844 } 845 846 out: 847 tty_flip_buffer_push(port); 848 849 return IRQ_HANDLED; 850 } 851 852 static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 853 { 854 struct imx_port *sport = dev_id; 855 irqreturn_t ret; 856 857 spin_lock(&sport->port.lock); 858 859 ret = __imx_uart_rxint(irq, dev_id); 860 861 spin_unlock(&sport->port.lock); 862 863 return ret; 864 } 865 866 static void imx_uart_clear_rx_errors(struct imx_port *sport); 867 868 /* 869 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 870 */ 871 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 872 { 873 unsigned int tmp = TIOCM_DSR; 874 unsigned usr1 = imx_uart_readl(sport, USR1); 875 unsigned usr2 = imx_uart_readl(sport, USR2); 876 877 if (usr1 & USR1_RTSS) 878 tmp |= TIOCM_CTS; 879 880 /* in DCE mode DCDIN is always 0 */ 881 if (!(usr2 & USR2_DCDIN)) 882 tmp |= TIOCM_CAR; 883 884 if (sport->dte_mode) 885 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 886 tmp |= TIOCM_RI; 887 888 return tmp; 889 } 890 891 /* 892 * Handle any change of modem status signal since we were last called. 893 */ 894 static void imx_uart_mctrl_check(struct imx_port *sport) 895 { 896 unsigned int status, changed; 897 898 status = imx_uart_get_hwmctrl(sport); 899 changed = status ^ sport->old_status; 900 901 if (changed == 0) 902 return; 903 904 sport->old_status = status; 905 906 if (changed & TIOCM_RI && status & TIOCM_RI) 907 sport->port.icount.rng++; 908 if (changed & TIOCM_DSR) 909 sport->port.icount.dsr++; 910 if (changed & TIOCM_CAR) 911 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 912 if (changed & TIOCM_CTS) 913 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 914 915 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 916 } 917 918 static irqreturn_t imx_uart_int(int irq, void *dev_id) 919 { 920 struct imx_port *sport = dev_id; 921 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 922 irqreturn_t ret = IRQ_NONE; 923 924 spin_lock(&sport->port.lock); 925 926 usr1 = imx_uart_readl(sport, USR1); 927 usr2 = imx_uart_readl(sport, USR2); 928 ucr1 = imx_uart_readl(sport, UCR1); 929 ucr2 = imx_uart_readl(sport, UCR2); 930 ucr3 = imx_uart_readl(sport, UCR3); 931 ucr4 = imx_uart_readl(sport, UCR4); 932 933 /* 934 * Even if a condition is true that can trigger an irq only handle it if 935 * the respective irq source is enabled. This prevents some undesired 936 * actions, for example if a character that sits in the RX FIFO and that 937 * should be fetched via DMA is tried to be fetched using PIO. Or the 938 * receiver is currently off and so reading from URXD0 results in an 939 * exception. So just mask the (raw) status bits for disabled irqs. 940 */ 941 if ((ucr1 & UCR1_RRDYEN) == 0) 942 usr1 &= ~USR1_RRDY; 943 if ((ucr2 & UCR2_ATEN) == 0) 944 usr1 &= ~USR1_AGTIM; 945 if ((ucr1 & UCR1_TRDYEN) == 0) 946 usr1 &= ~USR1_TRDY; 947 if ((ucr4 & UCR4_TCEN) == 0) 948 usr2 &= ~USR2_TXDC; 949 if ((ucr3 & UCR3_DTRDEN) == 0) 950 usr1 &= ~USR1_DTRD; 951 if ((ucr1 & UCR1_RTSDEN) == 0) 952 usr1 &= ~USR1_RTSD; 953 if ((ucr3 & UCR3_AWAKEN) == 0) 954 usr1 &= ~USR1_AWAKE; 955 if ((ucr4 & UCR4_OREN) == 0) 956 usr2 &= ~USR2_ORE; 957 958 if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 959 imx_uart_writel(sport, USR1_AGTIM, USR1); 960 961 __imx_uart_rxint(irq, dev_id); 962 ret = IRQ_HANDLED; 963 } 964 965 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 966 imx_uart_transmit_buffer(sport); 967 ret = IRQ_HANDLED; 968 } 969 970 if (usr1 & USR1_DTRD) { 971 imx_uart_writel(sport, USR1_DTRD, USR1); 972 973 imx_uart_mctrl_check(sport); 974 975 ret = IRQ_HANDLED; 976 } 977 978 if (usr1 & USR1_RTSD) { 979 __imx_uart_rtsint(irq, dev_id); 980 ret = IRQ_HANDLED; 981 } 982 983 if (usr1 & USR1_AWAKE) { 984 imx_uart_writel(sport, USR1_AWAKE, USR1); 985 ret = IRQ_HANDLED; 986 } 987 988 if (usr2 & USR2_ORE) { 989 sport->port.icount.overrun++; 990 imx_uart_writel(sport, USR2_ORE, USR2); 991 ret = IRQ_HANDLED; 992 } 993 994 spin_unlock(&sport->port.lock); 995 996 return ret; 997 } 998 999 /* 1000 * Return TIOCSER_TEMT when transmitter is not busy. 1001 */ 1002 static unsigned int imx_uart_tx_empty(struct uart_port *port) 1003 { 1004 struct imx_port *sport = (struct imx_port *)port; 1005 unsigned int ret; 1006 1007 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 1008 1009 /* If the TX DMA is working, return 0. */ 1010 if (sport->dma_is_txing) 1011 ret = 0; 1012 1013 return ret; 1014 } 1015 1016 /* called with port.lock taken and irqs off */ 1017 static unsigned int imx_uart_get_mctrl(struct uart_port *port) 1018 { 1019 struct imx_port *sport = (struct imx_port *)port; 1020 unsigned int ret = imx_uart_get_hwmctrl(sport); 1021 1022 mctrl_gpio_get(sport->gpios, &ret); 1023 1024 return ret; 1025 } 1026 1027 /* called with port.lock taken and irqs off */ 1028 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1029 { 1030 struct imx_port *sport = (struct imx_port *)port; 1031 u32 ucr3, uts; 1032 1033 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 1034 u32 ucr2; 1035 1036 /* 1037 * Turn off autoRTS if RTS is lowered and restore autoRTS 1038 * setting if RTS is raised. 1039 */ 1040 ucr2 = imx_uart_readl(sport, UCR2); 1041 ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1042 if (mctrl & TIOCM_RTS) { 1043 ucr2 |= UCR2_CTS; 1044 /* 1045 * UCR2_IRTS is unset if and only if the port is 1046 * configured for CRTSCTS, so we use inverted UCR2_IRTS 1047 * to get the state to restore to. 1048 */ 1049 if (!(ucr2 & UCR2_IRTS)) 1050 ucr2 |= UCR2_CTSC; 1051 } 1052 imx_uart_writel(sport, ucr2, UCR2); 1053 } 1054 1055 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 1056 if (!(mctrl & TIOCM_DTR)) 1057 ucr3 |= UCR3_DSR; 1058 imx_uart_writel(sport, ucr3, UCR3); 1059 1060 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 1061 if (mctrl & TIOCM_LOOP) 1062 uts |= UTS_LOOP; 1063 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 1064 1065 mctrl_gpio_set(sport->gpios, mctrl); 1066 } 1067 1068 /* 1069 * Interrupts always disabled. 1070 */ 1071 static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1072 { 1073 struct imx_port *sport = (struct imx_port *)port; 1074 unsigned long flags; 1075 u32 ucr1; 1076 1077 spin_lock_irqsave(&sport->port.lock, flags); 1078 1079 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1080 1081 if (break_state != 0) 1082 ucr1 |= UCR1_SNDBRK; 1083 1084 imx_uart_writel(sport, ucr1, UCR1); 1085 1086 spin_unlock_irqrestore(&sport->port.lock, flags); 1087 } 1088 1089 /* 1090 * This is our per-port timeout handler, for checking the 1091 * modem status signals. 1092 */ 1093 static void imx_uart_timeout(struct timer_list *t) 1094 { 1095 struct imx_port *sport = from_timer(sport, t, timer); 1096 unsigned long flags; 1097 1098 if (sport->port.state) { 1099 spin_lock_irqsave(&sport->port.lock, flags); 1100 imx_uart_mctrl_check(sport); 1101 spin_unlock_irqrestore(&sport->port.lock, flags); 1102 1103 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1104 } 1105 } 1106 1107 /* 1108 * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1109 * [1] the RX DMA buffer is full. 1110 * [2] the aging timer expires 1111 * 1112 * Condition [2] is triggered when a character has been sitting in the FIFO 1113 * for at least 8 byte durations. 1114 */ 1115 static void imx_uart_dma_rx_callback(void *data) 1116 { 1117 struct imx_port *sport = data; 1118 struct dma_chan *chan = sport->dma_chan_rx; 1119 struct scatterlist *sgl = &sport->rx_sgl; 1120 struct tty_port *port = &sport->port.state->port; 1121 struct dma_tx_state state; 1122 struct circ_buf *rx_ring = &sport->rx_ring; 1123 enum dma_status status; 1124 unsigned int w_bytes = 0; 1125 unsigned int r_bytes; 1126 unsigned int bd_size; 1127 1128 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1129 1130 if (status == DMA_ERROR) { 1131 imx_uart_clear_rx_errors(sport); 1132 return; 1133 } 1134 1135 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1136 1137 /* 1138 * The state-residue variable represents the empty space 1139 * relative to the entire buffer. Taking this in consideration 1140 * the head is always calculated base on the buffer total 1141 * length - DMA transaction residue. The UART script from the 1142 * SDMA firmware will jump to the next buffer descriptor, 1143 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 1144 * Taking this in consideration the tail is always at the 1145 * beginning of the buffer descriptor that contains the head. 1146 */ 1147 1148 /* Calculate the head */ 1149 rx_ring->head = sg_dma_len(sgl) - state.residue; 1150 1151 /* Calculate the tail. */ 1152 bd_size = sg_dma_len(sgl) / sport->rx_periods; 1153 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 1154 1155 if (rx_ring->head <= sg_dma_len(sgl) && 1156 rx_ring->head > rx_ring->tail) { 1157 1158 /* Move data from tail to head */ 1159 r_bytes = rx_ring->head - rx_ring->tail; 1160 1161 /* CPU claims ownership of RX DMA buffer */ 1162 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 1163 DMA_FROM_DEVICE); 1164 1165 w_bytes = tty_insert_flip_string(port, 1166 sport->rx_buf + rx_ring->tail, r_bytes); 1167 1168 /* UART retrieves ownership of RX DMA buffer */ 1169 dma_sync_sg_for_device(sport->port.dev, sgl, 1, 1170 DMA_FROM_DEVICE); 1171 1172 if (w_bytes != r_bytes) 1173 sport->port.icount.buf_overrun++; 1174 1175 sport->port.icount.rx += w_bytes; 1176 } else { 1177 WARN_ON(rx_ring->head > sg_dma_len(sgl)); 1178 WARN_ON(rx_ring->head <= rx_ring->tail); 1179 } 1180 } 1181 1182 if (w_bytes) { 1183 tty_flip_buffer_push(port); 1184 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 1185 } 1186 } 1187 1188 static int imx_uart_start_rx_dma(struct imx_port *sport) 1189 { 1190 struct scatterlist *sgl = &sport->rx_sgl; 1191 struct dma_chan *chan = sport->dma_chan_rx; 1192 struct device *dev = sport->port.dev; 1193 struct dma_async_tx_descriptor *desc; 1194 int ret; 1195 1196 sport->rx_ring.head = 0; 1197 sport->rx_ring.tail = 0; 1198 1199 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); 1200 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1201 if (ret == 0) { 1202 dev_err(dev, "DMA mapping error for RX.\n"); 1203 return -EINVAL; 1204 } 1205 1206 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 1207 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 1208 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1209 1210 if (!desc) { 1211 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1212 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1213 return -EINVAL; 1214 } 1215 desc->callback = imx_uart_dma_rx_callback; 1216 desc->callback_param = sport; 1217 1218 dev_dbg(dev, "RX: prepare for the DMA.\n"); 1219 sport->dma_is_rxing = 1; 1220 sport->rx_cookie = dmaengine_submit(desc); 1221 dma_async_issue_pending(chan); 1222 return 0; 1223 } 1224 1225 static void imx_uart_clear_rx_errors(struct imx_port *sport) 1226 { 1227 struct tty_port *port = &sport->port.state->port; 1228 u32 usr1, usr2; 1229 1230 usr1 = imx_uart_readl(sport, USR1); 1231 usr2 = imx_uart_readl(sport, USR2); 1232 1233 if (usr2 & USR2_BRCD) { 1234 sport->port.icount.brk++; 1235 imx_uart_writel(sport, USR2_BRCD, USR2); 1236 uart_handle_break(&sport->port); 1237 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 1238 sport->port.icount.buf_overrun++; 1239 tty_flip_buffer_push(port); 1240 } else { 1241 if (usr1 & USR1_FRAMERR) { 1242 sport->port.icount.frame++; 1243 imx_uart_writel(sport, USR1_FRAMERR, USR1); 1244 } else if (usr1 & USR1_PARITYERR) { 1245 sport->port.icount.parity++; 1246 imx_uart_writel(sport, USR1_PARITYERR, USR1); 1247 } 1248 } 1249 1250 if (usr2 & USR2_ORE) { 1251 sport->port.icount.overrun++; 1252 imx_uart_writel(sport, USR2_ORE, USR2); 1253 } 1254 1255 } 1256 1257 #define TXTL_DEFAULT 2 /* reset default */ 1258 #define RXTL_DEFAULT 1 /* reset default */ 1259 #define TXTL_DMA 8 /* DMA burst setting */ 1260 #define RXTL_DMA 9 /* DMA burst setting */ 1261 1262 static void imx_uart_setup_ufcr(struct imx_port *sport, 1263 unsigned char txwl, unsigned char rxwl) 1264 { 1265 unsigned int val; 1266 1267 /* set receiver / transmitter trigger level */ 1268 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1269 val |= txwl << UFCR_TXTL_SHF | rxwl; 1270 imx_uart_writel(sport, val, UFCR); 1271 } 1272 1273 static void imx_uart_dma_exit(struct imx_port *sport) 1274 { 1275 if (sport->dma_chan_rx) { 1276 dmaengine_terminate_sync(sport->dma_chan_rx); 1277 dma_release_channel(sport->dma_chan_rx); 1278 sport->dma_chan_rx = NULL; 1279 sport->rx_cookie = -EINVAL; 1280 kfree(sport->rx_buf); 1281 sport->rx_buf = NULL; 1282 } 1283 1284 if (sport->dma_chan_tx) { 1285 dmaengine_terminate_sync(sport->dma_chan_tx); 1286 dma_release_channel(sport->dma_chan_tx); 1287 sport->dma_chan_tx = NULL; 1288 } 1289 } 1290 1291 static int imx_uart_dma_init(struct imx_port *sport) 1292 { 1293 struct dma_slave_config slave_config = {}; 1294 struct device *dev = sport->port.dev; 1295 int ret; 1296 1297 /* Prepare for RX : */ 1298 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1299 if (!sport->dma_chan_rx) { 1300 dev_dbg(dev, "cannot get the DMA channel.\n"); 1301 ret = -EINVAL; 1302 goto err; 1303 } 1304 1305 slave_config.direction = DMA_DEV_TO_MEM; 1306 slave_config.src_addr = sport->port.mapbase + URXD0; 1307 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1308 /* one byte less than the watermark level to enable the aging timer */ 1309 slave_config.src_maxburst = RXTL_DMA - 1; 1310 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1311 if (ret) { 1312 dev_err(dev, "error in RX dma configuration.\n"); 1313 goto err; 1314 } 1315 1316 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; 1317 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); 1318 if (!sport->rx_buf) { 1319 ret = -ENOMEM; 1320 goto err; 1321 } 1322 sport->rx_ring.buf = sport->rx_buf; 1323 1324 /* Prepare for TX : */ 1325 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1326 if (!sport->dma_chan_tx) { 1327 dev_err(dev, "cannot get the TX DMA channel!\n"); 1328 ret = -EINVAL; 1329 goto err; 1330 } 1331 1332 slave_config.direction = DMA_MEM_TO_DEV; 1333 slave_config.dst_addr = sport->port.mapbase + URTX0; 1334 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1335 slave_config.dst_maxburst = TXTL_DMA; 1336 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1337 if (ret) { 1338 dev_err(dev, "error in TX dma configuration."); 1339 goto err; 1340 } 1341 1342 return 0; 1343 err: 1344 imx_uart_dma_exit(sport); 1345 return ret; 1346 } 1347 1348 static void imx_uart_enable_dma(struct imx_port *sport) 1349 { 1350 u32 ucr1; 1351 1352 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1353 1354 /* set UCR1 */ 1355 ucr1 = imx_uart_readl(sport, UCR1); 1356 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 1357 imx_uart_writel(sport, ucr1, UCR1); 1358 1359 sport->dma_is_enabled = 1; 1360 } 1361 1362 static void imx_uart_disable_dma(struct imx_port *sport) 1363 { 1364 u32 ucr1; 1365 1366 /* clear UCR1 */ 1367 ucr1 = imx_uart_readl(sport, UCR1); 1368 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 1369 imx_uart_writel(sport, ucr1, UCR1); 1370 1371 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1372 1373 sport->dma_is_enabled = 0; 1374 } 1375 1376 /* half the RX buffer size */ 1377 #define CTSTL 16 1378 1379 static int imx_uart_startup(struct uart_port *port) 1380 { 1381 struct imx_port *sport = (struct imx_port *)port; 1382 int retval, i; 1383 unsigned long flags; 1384 int dma_is_inited = 0; 1385 u32 ucr1, ucr2, ucr3, ucr4; 1386 1387 retval = clk_prepare_enable(sport->clk_per); 1388 if (retval) 1389 return retval; 1390 retval = clk_prepare_enable(sport->clk_ipg); 1391 if (retval) { 1392 clk_disable_unprepare(sport->clk_per); 1393 return retval; 1394 } 1395 1396 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1397 1398 /* disable the DREN bit (Data Ready interrupt enable) before 1399 * requesting IRQs 1400 */ 1401 ucr4 = imx_uart_readl(sport, UCR4); 1402 1403 /* set the trigger level for CTS */ 1404 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1405 ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1406 1407 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1408 1409 /* Can we enable the DMA support? */ 1410 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 1411 dma_is_inited = 1; 1412 1413 spin_lock_irqsave(&sport->port.lock, flags); 1414 /* Reset fifo's and state machines */ 1415 i = 100; 1416 1417 ucr2 = imx_uart_readl(sport, UCR2); 1418 ucr2 &= ~UCR2_SRST; 1419 imx_uart_writel(sport, ucr2, UCR2); 1420 1421 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1422 udelay(1); 1423 1424 /* 1425 * Finally, clear and enable interrupts 1426 */ 1427 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 1428 imx_uart_writel(sport, USR2_ORE, USR2); 1429 1430 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 1431 ucr1 |= UCR1_UARTEN; 1432 if (sport->have_rtscts) 1433 ucr1 |= UCR1_RTSDEN; 1434 1435 imx_uart_writel(sport, ucr1, UCR1); 1436 1437 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 1438 if (!sport->dma_is_enabled) 1439 ucr4 |= UCR4_OREN; 1440 if (sport->inverted_rx) 1441 ucr4 |= UCR4_INVR; 1442 imx_uart_writel(sport, ucr4, UCR4); 1443 1444 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 1445 /* 1446 * configure tx polarity before enabling tx 1447 */ 1448 if (sport->inverted_tx) 1449 ucr3 |= UCR3_INVT; 1450 1451 if (!imx_uart_is_imx1(sport)) { 1452 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 1453 1454 if (sport->dte_mode) 1455 /* disable broken interrupts */ 1456 ucr3 &= ~(UCR3_RI | UCR3_DCD); 1457 } 1458 imx_uart_writel(sport, ucr3, UCR3); 1459 1460 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 1461 ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1462 if (!sport->have_rtscts) 1463 ucr2 |= UCR2_IRTS; 1464 /* 1465 * make sure the edge sensitive RTS-irq is disabled, 1466 * we're using RTSD instead. 1467 */ 1468 if (!imx_uart_is_imx1(sport)) 1469 ucr2 &= ~UCR2_RTSEN; 1470 imx_uart_writel(sport, ucr2, UCR2); 1471 1472 /* 1473 * Enable modem status interrupts 1474 */ 1475 imx_uart_enable_ms(&sport->port); 1476 1477 if (dma_is_inited) { 1478 imx_uart_enable_dma(sport); 1479 imx_uart_start_rx_dma(sport); 1480 } else { 1481 ucr1 = imx_uart_readl(sport, UCR1); 1482 ucr1 |= UCR1_RRDYEN; 1483 imx_uart_writel(sport, ucr1, UCR1); 1484 1485 ucr2 = imx_uart_readl(sport, UCR2); 1486 ucr2 |= UCR2_ATEN; 1487 imx_uart_writel(sport, ucr2, UCR2); 1488 } 1489 1490 spin_unlock_irqrestore(&sport->port.lock, flags); 1491 1492 return 0; 1493 } 1494 1495 static void imx_uart_shutdown(struct uart_port *port) 1496 { 1497 struct imx_port *sport = (struct imx_port *)port; 1498 unsigned long flags; 1499 u32 ucr1, ucr2, ucr4; 1500 1501 if (sport->dma_is_enabled) { 1502 dmaengine_terminate_sync(sport->dma_chan_tx); 1503 if (sport->dma_is_txing) { 1504 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 1505 sport->dma_tx_nents, DMA_TO_DEVICE); 1506 sport->dma_is_txing = 0; 1507 } 1508 dmaengine_terminate_sync(sport->dma_chan_rx); 1509 if (sport->dma_is_rxing) { 1510 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1511 1, DMA_FROM_DEVICE); 1512 sport->dma_is_rxing = 0; 1513 } 1514 1515 spin_lock_irqsave(&sport->port.lock, flags); 1516 imx_uart_stop_tx(port); 1517 imx_uart_stop_rx(port); 1518 imx_uart_disable_dma(sport); 1519 spin_unlock_irqrestore(&sport->port.lock, flags); 1520 imx_uart_dma_exit(sport); 1521 } 1522 1523 mctrl_gpio_disable_ms(sport->gpios); 1524 1525 spin_lock_irqsave(&sport->port.lock, flags); 1526 ucr2 = imx_uart_readl(sport, UCR2); 1527 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 1528 imx_uart_writel(sport, ucr2, UCR2); 1529 spin_unlock_irqrestore(&sport->port.lock, flags); 1530 1531 /* 1532 * Stop our timer. 1533 */ 1534 del_timer_sync(&sport->timer); 1535 1536 /* 1537 * Disable all interrupts, port and break condition. 1538 */ 1539 1540 spin_lock_irqsave(&sport->port.lock, flags); 1541 1542 ucr1 = imx_uart_readl(sport, UCR1); 1543 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1544 imx_uart_writel(sport, ucr1, UCR1); 1545 1546 ucr4 = imx_uart_readl(sport, UCR4); 1547 ucr4 &= ~(UCR4_OREN | UCR4_TCEN); 1548 imx_uart_writel(sport, ucr4, UCR4); 1549 1550 spin_unlock_irqrestore(&sport->port.lock, flags); 1551 1552 clk_disable_unprepare(sport->clk_per); 1553 clk_disable_unprepare(sport->clk_ipg); 1554 } 1555 1556 /* called with port.lock taken and irqs off */ 1557 static void imx_uart_flush_buffer(struct uart_port *port) 1558 { 1559 struct imx_port *sport = (struct imx_port *)port; 1560 struct scatterlist *sgl = &sport->tx_sgl[0]; 1561 u32 ucr2; 1562 int i = 100, ubir, ubmr, uts; 1563 1564 if (!sport->dma_chan_tx) 1565 return; 1566 1567 sport->tx_bytes = 0; 1568 dmaengine_terminate_all(sport->dma_chan_tx); 1569 if (sport->dma_is_txing) { 1570 u32 ucr1; 1571 1572 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1573 DMA_TO_DEVICE); 1574 ucr1 = imx_uart_readl(sport, UCR1); 1575 ucr1 &= ~UCR1_TXDMAEN; 1576 imx_uart_writel(sport, ucr1, UCR1); 1577 sport->dma_is_txing = 0; 1578 } 1579 1580 /* 1581 * According to the Reference Manual description of the UART SRST bit: 1582 * 1583 * "Reset the transmit and receive state machines, 1584 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1585 * and UTS[6-3]". 1586 * 1587 * We don't need to restore the old values from USR1, USR2, URXD and 1588 * UTXD. UBRC is read only, so only save/restore the other three 1589 * registers. 1590 */ 1591 ubir = imx_uart_readl(sport, UBIR); 1592 ubmr = imx_uart_readl(sport, UBMR); 1593 uts = imx_uart_readl(sport, IMX21_UTS); 1594 1595 ucr2 = imx_uart_readl(sport, UCR2); 1596 ucr2 &= ~UCR2_SRST; 1597 imx_uart_writel(sport, ucr2, UCR2); 1598 1599 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1600 udelay(1); 1601 1602 /* Restore the registers */ 1603 imx_uart_writel(sport, ubir, UBIR); 1604 imx_uart_writel(sport, ubmr, UBMR); 1605 imx_uart_writel(sport, uts, IMX21_UTS); 1606 } 1607 1608 static void 1609 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1610 struct ktermios *old) 1611 { 1612 struct imx_port *sport = (struct imx_port *)port; 1613 unsigned long flags; 1614 u32 ucr2, old_ucr2, ufcr; 1615 unsigned int baud, quot; 1616 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1617 unsigned long div; 1618 unsigned long num, denom, old_ubir, old_ubmr; 1619 uint64_t tdiv64; 1620 1621 /* 1622 * We only support CS7 and CS8. 1623 */ 1624 while ((termios->c_cflag & CSIZE) != CS7 && 1625 (termios->c_cflag & CSIZE) != CS8) { 1626 termios->c_cflag &= ~CSIZE; 1627 termios->c_cflag |= old_csize; 1628 old_csize = CS8; 1629 } 1630 1631 del_timer_sync(&sport->timer); 1632 1633 /* 1634 * Ask the core to calculate the divisor for us. 1635 */ 1636 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1637 quot = uart_get_divisor(port, baud); 1638 1639 spin_lock_irqsave(&sport->port.lock, flags); 1640 1641 /* 1642 * Read current UCR2 and save it for future use, then clear all the bits 1643 * except those we will or may need to preserve. 1644 */ 1645 old_ucr2 = imx_uart_readl(sport, UCR2); 1646 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1647 1648 ucr2 |= UCR2_SRST | UCR2_IRTS; 1649 if ((termios->c_cflag & CSIZE) == CS8) 1650 ucr2 |= UCR2_WS; 1651 1652 if (!sport->have_rtscts) 1653 termios->c_cflag &= ~CRTSCTS; 1654 1655 if (port->rs485.flags & SER_RS485_ENABLED) { 1656 /* 1657 * RTS is mandatory for rs485 operation, so keep 1658 * it under manual control and keep transmitter 1659 * disabled. 1660 */ 1661 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1662 imx_uart_rts_active(sport, &ucr2); 1663 else 1664 imx_uart_rts_inactive(sport, &ucr2); 1665 1666 } else if (termios->c_cflag & CRTSCTS) { 1667 /* 1668 * Only let receiver control RTS output if we were not requested 1669 * to have RTS inactive (which then should take precedence). 1670 */ 1671 if (ucr2 & UCR2_CTS) 1672 ucr2 |= UCR2_CTSC; 1673 } 1674 1675 if (termios->c_cflag & CRTSCTS) 1676 ucr2 &= ~UCR2_IRTS; 1677 if (termios->c_cflag & CSTOPB) 1678 ucr2 |= UCR2_STPB; 1679 if (termios->c_cflag & PARENB) { 1680 ucr2 |= UCR2_PREN; 1681 if (termios->c_cflag & PARODD) 1682 ucr2 |= UCR2_PROE; 1683 } 1684 1685 sport->port.read_status_mask = 0; 1686 if (termios->c_iflag & INPCK) 1687 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1688 if (termios->c_iflag & (BRKINT | PARMRK)) 1689 sport->port.read_status_mask |= URXD_BRK; 1690 1691 /* 1692 * Characters to ignore 1693 */ 1694 sport->port.ignore_status_mask = 0; 1695 if (termios->c_iflag & IGNPAR) 1696 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1697 if (termios->c_iflag & IGNBRK) { 1698 sport->port.ignore_status_mask |= URXD_BRK; 1699 /* 1700 * If we're ignoring parity and break indicators, 1701 * ignore overruns too (for real raw support). 1702 */ 1703 if (termios->c_iflag & IGNPAR) 1704 sport->port.ignore_status_mask |= URXD_OVRRUN; 1705 } 1706 1707 if ((termios->c_cflag & CREAD) == 0) 1708 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1709 1710 /* 1711 * Update the per-port timeout. 1712 */ 1713 uart_update_timeout(port, termios->c_cflag, baud); 1714 1715 /* custom-baudrate handling */ 1716 div = sport->port.uartclk / (baud * 16); 1717 if (baud == 38400 && quot != div) 1718 baud = sport->port.uartclk / (quot * 16); 1719 1720 div = sport->port.uartclk / (baud * 16); 1721 if (div > 7) 1722 div = 7; 1723 if (!div) 1724 div = 1; 1725 1726 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1727 1 << 16, 1 << 16, &num, &denom); 1728 1729 tdiv64 = sport->port.uartclk; 1730 tdiv64 *= num; 1731 do_div(tdiv64, denom * 16 * div); 1732 tty_termios_encode_baud_rate(termios, 1733 (speed_t)tdiv64, (speed_t)tdiv64); 1734 1735 num -= 1; 1736 denom -= 1; 1737 1738 ufcr = imx_uart_readl(sport, UFCR); 1739 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1740 imx_uart_writel(sport, ufcr, UFCR); 1741 1742 /* 1743 * Two registers below should always be written both and in this 1744 * particular order. One consequence is that we need to check if any of 1745 * them changes and then update both. We do need the check for change 1746 * as even writing the same values seem to "restart" 1747 * transmission/receiving logic in the hardware, that leads to data 1748 * breakage even when rate doesn't in fact change. E.g., user switches 1749 * RTS/CTS handshake and suddenly gets broken bytes. 1750 */ 1751 old_ubir = imx_uart_readl(sport, UBIR); 1752 old_ubmr = imx_uart_readl(sport, UBMR); 1753 if (old_ubir != num || old_ubmr != denom) { 1754 imx_uart_writel(sport, num, UBIR); 1755 imx_uart_writel(sport, denom, UBMR); 1756 } 1757 1758 if (!imx_uart_is_imx1(sport)) 1759 imx_uart_writel(sport, sport->port.uartclk / div / 1000, 1760 IMX21_ONEMS); 1761 1762 imx_uart_writel(sport, ucr2, UCR2); 1763 1764 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1765 imx_uart_enable_ms(&sport->port); 1766 1767 spin_unlock_irqrestore(&sport->port.lock, flags); 1768 } 1769 1770 static const char *imx_uart_type(struct uart_port *port) 1771 { 1772 struct imx_port *sport = (struct imx_port *)port; 1773 1774 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1775 } 1776 1777 /* 1778 * Configure/autoconfigure the port. 1779 */ 1780 static void imx_uart_config_port(struct uart_port *port, int flags) 1781 { 1782 struct imx_port *sport = (struct imx_port *)port; 1783 1784 if (flags & UART_CONFIG_TYPE) 1785 sport->port.type = PORT_IMX; 1786 } 1787 1788 /* 1789 * Verify the new serial_struct (for TIOCSSERIAL). 1790 * The only change we allow are to the flags and type, and 1791 * even then only between PORT_IMX and PORT_UNKNOWN 1792 */ 1793 static int 1794 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1795 { 1796 struct imx_port *sport = (struct imx_port *)port; 1797 int ret = 0; 1798 1799 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1800 ret = -EINVAL; 1801 if (sport->port.irq != ser->irq) 1802 ret = -EINVAL; 1803 if (ser->io_type != UPIO_MEM) 1804 ret = -EINVAL; 1805 if (sport->port.uartclk / 16 != ser->baud_base) 1806 ret = -EINVAL; 1807 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1808 ret = -EINVAL; 1809 if (sport->port.iobase != ser->port) 1810 ret = -EINVAL; 1811 if (ser->hub6 != 0) 1812 ret = -EINVAL; 1813 return ret; 1814 } 1815 1816 #if defined(CONFIG_CONSOLE_POLL) 1817 1818 static int imx_uart_poll_init(struct uart_port *port) 1819 { 1820 struct imx_port *sport = (struct imx_port *)port; 1821 unsigned long flags; 1822 u32 ucr1, ucr2; 1823 int retval; 1824 1825 retval = clk_prepare_enable(sport->clk_ipg); 1826 if (retval) 1827 return retval; 1828 retval = clk_prepare_enable(sport->clk_per); 1829 if (retval) 1830 clk_disable_unprepare(sport->clk_ipg); 1831 1832 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1833 1834 spin_lock_irqsave(&sport->port.lock, flags); 1835 1836 /* 1837 * Be careful about the order of enabling bits here. First enable the 1838 * receiver (UARTEN + RXEN) and only then the corresponding irqs. 1839 * This prevents that a character that already sits in the RX fifo is 1840 * triggering an irq but the try to fetch it from there results in an 1841 * exception because UARTEN or RXEN is still off. 1842 */ 1843 ucr1 = imx_uart_readl(sport, UCR1); 1844 ucr2 = imx_uart_readl(sport, UCR2); 1845 1846 if (imx_uart_is_imx1(sport)) 1847 ucr1 |= IMX1_UCR1_UARTCLKEN; 1848 1849 ucr1 |= UCR1_UARTEN; 1850 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 1851 1852 ucr2 |= UCR2_RXEN | UCR2_TXEN; 1853 ucr2 &= ~UCR2_ATEN; 1854 1855 imx_uart_writel(sport, ucr1, UCR1); 1856 imx_uart_writel(sport, ucr2, UCR2); 1857 1858 /* now enable irqs */ 1859 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 1860 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 1861 1862 spin_unlock_irqrestore(&sport->port.lock, flags); 1863 1864 return 0; 1865 } 1866 1867 static int imx_uart_poll_get_char(struct uart_port *port) 1868 { 1869 struct imx_port *sport = (struct imx_port *)port; 1870 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 1871 return NO_POLL_CHAR; 1872 1873 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 1874 } 1875 1876 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 1877 { 1878 struct imx_port *sport = (struct imx_port *)port; 1879 unsigned int status; 1880 1881 /* drain */ 1882 do { 1883 status = imx_uart_readl(sport, USR1); 1884 } while (~status & USR1_TRDY); 1885 1886 /* write */ 1887 imx_uart_writel(sport, c, URTX0); 1888 1889 /* flush */ 1890 do { 1891 status = imx_uart_readl(sport, USR2); 1892 } while (~status & USR2_TXDC); 1893 } 1894 #endif 1895 1896 /* called with port.lock taken and irqs off or from .probe without locking */ 1897 static int imx_uart_rs485_config(struct uart_port *port, 1898 struct serial_rs485 *rs485conf) 1899 { 1900 struct imx_port *sport = (struct imx_port *)port; 1901 u32 ucr2; 1902 1903 /* RTS is required to control the transmitter */ 1904 if (!sport->have_rtscts && !sport->have_rtsgpio) 1905 rs485conf->flags &= ~SER_RS485_ENABLED; 1906 1907 if (rs485conf->flags & SER_RS485_ENABLED) { 1908 /* Enable receiver if low-active RTS signal is requested */ 1909 if (sport->have_rtscts && !sport->have_rtsgpio && 1910 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 1911 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1912 1913 /* disable transmitter */ 1914 ucr2 = imx_uart_readl(sport, UCR2); 1915 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1916 imx_uart_rts_active(sport, &ucr2); 1917 else 1918 imx_uart_rts_inactive(sport, &ucr2); 1919 imx_uart_writel(sport, ucr2, UCR2); 1920 } 1921 1922 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 1923 if (!(rs485conf->flags & SER_RS485_ENABLED) || 1924 rs485conf->flags & SER_RS485_RX_DURING_TX) 1925 imx_uart_start_rx(port); 1926 1927 port->rs485 = *rs485conf; 1928 1929 return 0; 1930 } 1931 1932 static const struct uart_ops imx_uart_pops = { 1933 .tx_empty = imx_uart_tx_empty, 1934 .set_mctrl = imx_uart_set_mctrl, 1935 .get_mctrl = imx_uart_get_mctrl, 1936 .stop_tx = imx_uart_stop_tx, 1937 .start_tx = imx_uart_start_tx, 1938 .stop_rx = imx_uart_stop_rx, 1939 .enable_ms = imx_uart_enable_ms, 1940 .break_ctl = imx_uart_break_ctl, 1941 .startup = imx_uart_startup, 1942 .shutdown = imx_uart_shutdown, 1943 .flush_buffer = imx_uart_flush_buffer, 1944 .set_termios = imx_uart_set_termios, 1945 .type = imx_uart_type, 1946 .config_port = imx_uart_config_port, 1947 .verify_port = imx_uart_verify_port, 1948 #if defined(CONFIG_CONSOLE_POLL) 1949 .poll_init = imx_uart_poll_init, 1950 .poll_get_char = imx_uart_poll_get_char, 1951 .poll_put_char = imx_uart_poll_put_char, 1952 #endif 1953 }; 1954 1955 static struct imx_port *imx_uart_ports[UART_NR]; 1956 1957 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 1958 static void imx_uart_console_putchar(struct uart_port *port, int ch) 1959 { 1960 struct imx_port *sport = (struct imx_port *)port; 1961 1962 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1963 barrier(); 1964 1965 imx_uart_writel(sport, ch, URTX0); 1966 } 1967 1968 /* 1969 * Interrupts are disabled on entering 1970 */ 1971 static void 1972 imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1973 { 1974 struct imx_port *sport = imx_uart_ports[co->index]; 1975 struct imx_port_ucrs old_ucr; 1976 unsigned long flags; 1977 unsigned int ucr1; 1978 int locked = 1; 1979 1980 if (sport->port.sysrq) 1981 locked = 0; 1982 else if (oops_in_progress) 1983 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1984 else 1985 spin_lock_irqsave(&sport->port.lock, flags); 1986 1987 /* 1988 * First, save UCR1/2/3 and then disable interrupts 1989 */ 1990 imx_uart_ucrs_save(sport, &old_ucr); 1991 ucr1 = old_ucr.ucr1; 1992 1993 if (imx_uart_is_imx1(sport)) 1994 ucr1 |= IMX1_UCR1_UARTCLKEN; 1995 ucr1 |= UCR1_UARTEN; 1996 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1997 1998 imx_uart_writel(sport, ucr1, UCR1); 1999 2000 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2001 2002 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2003 2004 /* 2005 * Finally, wait for transmitter to become empty 2006 * and restore UCR1/2/3 2007 */ 2008 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2009 2010 imx_uart_ucrs_restore(sport, &old_ucr); 2011 2012 if (locked) 2013 spin_unlock_irqrestore(&sport->port.lock, flags); 2014 } 2015 2016 /* 2017 * If the port was already initialised (eg, by a boot loader), 2018 * try to determine the current setup. 2019 */ 2020 static void 2021 imx_uart_console_get_options(struct imx_port *sport, int *baud, 2022 int *parity, int *bits) 2023 { 2024 2025 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2026 /* ok, the port was enabled */ 2027 unsigned int ucr2, ubir, ubmr, uartclk; 2028 unsigned int baud_raw; 2029 unsigned int ucfr_rfdiv; 2030 2031 ucr2 = imx_uart_readl(sport, UCR2); 2032 2033 *parity = 'n'; 2034 if (ucr2 & UCR2_PREN) { 2035 if (ucr2 & UCR2_PROE) 2036 *parity = 'o'; 2037 else 2038 *parity = 'e'; 2039 } 2040 2041 if (ucr2 & UCR2_WS) 2042 *bits = 8; 2043 else 2044 *bits = 7; 2045 2046 ubir = imx_uart_readl(sport, UBIR) & 0xffff; 2047 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2048 2049 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2050 if (ucfr_rfdiv == 6) 2051 ucfr_rfdiv = 7; 2052 else 2053 ucfr_rfdiv = 6 - ucfr_rfdiv; 2054 2055 uartclk = clk_get_rate(sport->clk_per); 2056 uartclk /= ucfr_rfdiv; 2057 2058 { /* 2059 * The next code provides exact computation of 2060 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2061 * without need of float support or long long division, 2062 * which would be required to prevent 32bit arithmetic overflow 2063 */ 2064 unsigned int mul = ubir + 1; 2065 unsigned int div = 16 * (ubmr + 1); 2066 unsigned int rem = uartclk % div; 2067 2068 baud_raw = (uartclk / div) * mul; 2069 baud_raw += (rem * mul + div / 2) / div; 2070 *baud = (baud_raw + 50) / 100 * 100; 2071 } 2072 2073 if (*baud != baud_raw) 2074 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2075 baud_raw, *baud); 2076 } 2077 } 2078 2079 static int 2080 imx_uart_console_setup(struct console *co, char *options) 2081 { 2082 struct imx_port *sport; 2083 int baud = 9600; 2084 int bits = 8; 2085 int parity = 'n'; 2086 int flow = 'n'; 2087 int retval; 2088 2089 /* 2090 * Check whether an invalid uart number has been specified, and 2091 * if so, search for the first available port that does have 2092 * console support. 2093 */ 2094 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2095 co->index = 0; 2096 sport = imx_uart_ports[co->index]; 2097 if (sport == NULL) 2098 return -ENODEV; 2099 2100 /* For setting the registers, we only need to enable the ipg clock. */ 2101 retval = clk_prepare_enable(sport->clk_ipg); 2102 if (retval) 2103 goto error_console; 2104 2105 if (options) 2106 uart_parse_options(options, &baud, &parity, &bits, &flow); 2107 else 2108 imx_uart_console_get_options(sport, &baud, &parity, &bits); 2109 2110 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2111 2112 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 2113 2114 if (retval) { 2115 clk_disable_unprepare(sport->clk_ipg); 2116 goto error_console; 2117 } 2118 2119 retval = clk_prepare_enable(sport->clk_per); 2120 if (retval) 2121 clk_disable_unprepare(sport->clk_ipg); 2122 2123 error_console: 2124 return retval; 2125 } 2126 2127 static int 2128 imx_uart_console_exit(struct console *co) 2129 { 2130 struct imx_port *sport = imx_uart_ports[co->index]; 2131 2132 clk_disable_unprepare(sport->clk_per); 2133 clk_disable_unprepare(sport->clk_ipg); 2134 2135 return 0; 2136 } 2137 2138 static struct uart_driver imx_uart_uart_driver; 2139 static struct console imx_uart_console = { 2140 .name = DEV_NAME, 2141 .write = imx_uart_console_write, 2142 .device = uart_console_device, 2143 .setup = imx_uart_console_setup, 2144 .exit = imx_uart_console_exit, 2145 .flags = CON_PRINTBUFFER, 2146 .index = -1, 2147 .data = &imx_uart_uart_driver, 2148 }; 2149 2150 #define IMX_CONSOLE &imx_uart_console 2151 2152 #else 2153 #define IMX_CONSOLE NULL 2154 #endif 2155 2156 static struct uart_driver imx_uart_uart_driver = { 2157 .owner = THIS_MODULE, 2158 .driver_name = DRIVER_NAME, 2159 .dev_name = DEV_NAME, 2160 .major = SERIAL_IMX_MAJOR, 2161 .minor = MINOR_START, 2162 .nr = ARRAY_SIZE(imx_uart_ports), 2163 .cons = IMX_CONSOLE, 2164 }; 2165 2166 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2167 { 2168 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2169 unsigned long flags; 2170 2171 spin_lock_irqsave(&sport->port.lock, flags); 2172 if (sport->tx_state == WAIT_AFTER_RTS) 2173 imx_uart_start_tx(&sport->port); 2174 spin_unlock_irqrestore(&sport->port.lock, flags); 2175 2176 return HRTIMER_NORESTART; 2177 } 2178 2179 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2180 { 2181 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2182 unsigned long flags; 2183 2184 spin_lock_irqsave(&sport->port.lock, flags); 2185 if (sport->tx_state == WAIT_AFTER_SEND) 2186 imx_uart_stop_tx(&sport->port); 2187 spin_unlock_irqrestore(&sport->port.lock, flags); 2188 2189 return HRTIMER_NORESTART; 2190 } 2191 2192 /* Default RX DMA buffer configuration */ 2193 #define RX_DMA_PERIODS 16 2194 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4) 2195 2196 static int imx_uart_probe(struct platform_device *pdev) 2197 { 2198 struct device_node *np = pdev->dev.of_node; 2199 struct imx_port *sport; 2200 void __iomem *base; 2201 u32 dma_buf_conf[2]; 2202 int ret = 0; 2203 u32 ucr1; 2204 struct resource *res; 2205 int txirq, rxirq, rtsirq; 2206 2207 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2208 if (!sport) 2209 return -ENOMEM; 2210 2211 sport->devdata = of_device_get_match_data(&pdev->dev); 2212 2213 ret = of_alias_get_id(np, "serial"); 2214 if (ret < 0) { 2215 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2216 return ret; 2217 } 2218 sport->port.line = ret; 2219 2220 if (of_get_property(np, "uart-has-rtscts", NULL) || 2221 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 2222 sport->have_rtscts = 1; 2223 2224 if (of_get_property(np, "fsl,dte-mode", NULL)) 2225 sport->dte_mode = 1; 2226 2227 if (of_get_property(np, "rts-gpios", NULL)) 2228 sport->have_rtsgpio = 1; 2229 2230 if (of_get_property(np, "fsl,inverted-tx", NULL)) 2231 sport->inverted_tx = 1; 2232 2233 if (of_get_property(np, "fsl,inverted-rx", NULL)) 2234 sport->inverted_rx = 1; 2235 2236 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { 2237 sport->rx_period_length = dma_buf_conf[0]; 2238 sport->rx_periods = dma_buf_conf[1]; 2239 } else { 2240 sport->rx_period_length = RX_DMA_PERIOD_LEN; 2241 sport->rx_periods = RX_DMA_PERIODS; 2242 } 2243 2244 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 2245 dev_err(&pdev->dev, "serial%d out of range\n", 2246 sport->port.line); 2247 return -EINVAL; 2248 } 2249 2250 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2251 base = devm_ioremap_resource(&pdev->dev, res); 2252 if (IS_ERR(base)) 2253 return PTR_ERR(base); 2254 2255 rxirq = platform_get_irq(pdev, 0); 2256 if (rxirq < 0) 2257 return rxirq; 2258 txirq = platform_get_irq_optional(pdev, 1); 2259 rtsirq = platform_get_irq_optional(pdev, 2); 2260 2261 sport->port.dev = &pdev->dev; 2262 sport->port.mapbase = res->start; 2263 sport->port.membase = base; 2264 sport->port.type = PORT_IMX; 2265 sport->port.iotype = UPIO_MEM; 2266 sport->port.irq = rxirq; 2267 sport->port.fifosize = 32; 2268 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 2269 sport->port.ops = &imx_uart_pops; 2270 sport->port.rs485_config = imx_uart_rs485_config; 2271 sport->port.flags = UPF_BOOT_AUTOCONF; 2272 timer_setup(&sport->timer, imx_uart_timeout, 0); 2273 2274 sport->gpios = mctrl_gpio_init(&sport->port, 0); 2275 if (IS_ERR(sport->gpios)) 2276 return PTR_ERR(sport->gpios); 2277 2278 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2279 if (IS_ERR(sport->clk_ipg)) { 2280 ret = PTR_ERR(sport->clk_ipg); 2281 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 2282 return ret; 2283 } 2284 2285 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 2286 if (IS_ERR(sport->clk_per)) { 2287 ret = PTR_ERR(sport->clk_per); 2288 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 2289 return ret; 2290 } 2291 2292 sport->port.uartclk = clk_get_rate(sport->clk_per); 2293 2294 /* For register access, we only need to enable the ipg clock. */ 2295 ret = clk_prepare_enable(sport->clk_ipg); 2296 if (ret) { 2297 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 2298 return ret; 2299 } 2300 2301 /* initialize shadow register values */ 2302 sport->ucr1 = readl(sport->port.membase + UCR1); 2303 sport->ucr2 = readl(sport->port.membase + UCR2); 2304 sport->ucr3 = readl(sport->port.membase + UCR3); 2305 sport->ucr4 = readl(sport->port.membase + UCR4); 2306 sport->ufcr = readl(sport->port.membase + UFCR); 2307 2308 ret = uart_get_rs485_mode(&sport->port); 2309 if (ret) { 2310 clk_disable_unprepare(sport->clk_ipg); 2311 return ret; 2312 } 2313 2314 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2315 (!sport->have_rtscts && !sport->have_rtsgpio)) 2316 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2317 2318 /* 2319 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 2320 * signal cannot be set low during transmission in case the 2321 * receiver is off (limitation of the i.MX UART IP). 2322 */ 2323 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2324 sport->have_rtscts && !sport->have_rtsgpio && 2325 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 2326 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 2327 dev_err(&pdev->dev, 2328 "low-active RTS not possible when receiver is off, enabling receiver\n"); 2329 2330 imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2331 2332 /* Disable interrupts before requesting them */ 2333 ucr1 = imx_uart_readl(sport, UCR1); 2334 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 2335 imx_uart_writel(sport, ucr1, UCR1); 2336 2337 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2338 /* 2339 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2340 * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2341 * and DCD (when they are outputs) or enables the respective 2342 * irqs. So set this bit early, i.e. before requesting irqs. 2343 */ 2344 u32 ufcr = imx_uart_readl(sport, UFCR); 2345 if (!(ufcr & UFCR_DCEDTE)) 2346 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2347 2348 /* 2349 * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2350 * enabled later because they cannot be cleared 2351 * (confirmed on i.MX25) which makes them unusable. 2352 */ 2353 imx_uart_writel(sport, 2354 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2355 UCR3); 2356 2357 } else { 2358 u32 ucr3 = UCR3_DSR; 2359 u32 ufcr = imx_uart_readl(sport, UFCR); 2360 if (ufcr & UFCR_DCEDTE) 2361 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 2362 2363 if (!imx_uart_is_imx1(sport)) 2364 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 2365 imx_uart_writel(sport, ucr3, UCR3); 2366 } 2367 2368 clk_disable_unprepare(sport->clk_ipg); 2369 2370 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2371 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2372 sport->trigger_start_tx.function = imx_trigger_start_tx; 2373 sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2374 2375 /* 2376 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2377 * chips only have one interrupt. 2378 */ 2379 if (txirq > 0) { 2380 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2381 dev_name(&pdev->dev), sport); 2382 if (ret) { 2383 dev_err(&pdev->dev, "failed to request rx irq: %d\n", 2384 ret); 2385 return ret; 2386 } 2387 2388 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2389 dev_name(&pdev->dev), sport); 2390 if (ret) { 2391 dev_err(&pdev->dev, "failed to request tx irq: %d\n", 2392 ret); 2393 return ret; 2394 } 2395 2396 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 2397 dev_name(&pdev->dev), sport); 2398 if (ret) { 2399 dev_err(&pdev->dev, "failed to request rts irq: %d\n", 2400 ret); 2401 return ret; 2402 } 2403 } else { 2404 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2405 dev_name(&pdev->dev), sport); 2406 if (ret) { 2407 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2408 return ret; 2409 } 2410 } 2411 2412 imx_uart_ports[sport->port.line] = sport; 2413 2414 platform_set_drvdata(pdev, sport); 2415 2416 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2417 } 2418 2419 static int imx_uart_remove(struct platform_device *pdev) 2420 { 2421 struct imx_port *sport = platform_get_drvdata(pdev); 2422 2423 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2424 } 2425 2426 static void imx_uart_restore_context(struct imx_port *sport) 2427 { 2428 unsigned long flags; 2429 2430 spin_lock_irqsave(&sport->port.lock, flags); 2431 if (!sport->context_saved) { 2432 spin_unlock_irqrestore(&sport->port.lock, flags); 2433 return; 2434 } 2435 2436 imx_uart_writel(sport, sport->saved_reg[4], UFCR); 2437 imx_uart_writel(sport, sport->saved_reg[5], UESC); 2438 imx_uart_writel(sport, sport->saved_reg[6], UTIM); 2439 imx_uart_writel(sport, sport->saved_reg[7], UBIR); 2440 imx_uart_writel(sport, sport->saved_reg[8], UBMR); 2441 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 2442 imx_uart_writel(sport, sport->saved_reg[0], UCR1); 2443 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 2444 imx_uart_writel(sport, sport->saved_reg[2], UCR3); 2445 imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2446 sport->context_saved = false; 2447 spin_unlock_irqrestore(&sport->port.lock, flags); 2448 } 2449 2450 static void imx_uart_save_context(struct imx_port *sport) 2451 { 2452 unsigned long flags; 2453 2454 /* Save necessary regs */ 2455 spin_lock_irqsave(&sport->port.lock, flags); 2456 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 2457 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 2458 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 2459 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 2460 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 2461 sport->saved_reg[5] = imx_uart_readl(sport, UESC); 2462 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 2463 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 2464 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 2465 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2466 sport->context_saved = true; 2467 spin_unlock_irqrestore(&sport->port.lock, flags); 2468 } 2469 2470 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2471 { 2472 u32 ucr3; 2473 2474 ucr3 = imx_uart_readl(sport, UCR3); 2475 if (on) { 2476 imx_uart_writel(sport, USR1_AWAKE, USR1); 2477 ucr3 |= UCR3_AWAKEN; 2478 } else { 2479 ucr3 &= ~UCR3_AWAKEN; 2480 } 2481 imx_uart_writel(sport, ucr3, UCR3); 2482 2483 if (sport->have_rtscts) { 2484 u32 ucr1 = imx_uart_readl(sport, UCR1); 2485 if (on) 2486 ucr1 |= UCR1_RTSDEN; 2487 else 2488 ucr1 &= ~UCR1_RTSDEN; 2489 imx_uart_writel(sport, ucr1, UCR1); 2490 } 2491 } 2492 2493 static int imx_uart_suspend_noirq(struct device *dev) 2494 { 2495 struct imx_port *sport = dev_get_drvdata(dev); 2496 2497 imx_uart_save_context(sport); 2498 2499 clk_disable(sport->clk_ipg); 2500 2501 pinctrl_pm_select_sleep_state(dev); 2502 2503 return 0; 2504 } 2505 2506 static int imx_uart_resume_noirq(struct device *dev) 2507 { 2508 struct imx_port *sport = dev_get_drvdata(dev); 2509 int ret; 2510 2511 pinctrl_pm_select_default_state(dev); 2512 2513 ret = clk_enable(sport->clk_ipg); 2514 if (ret) 2515 return ret; 2516 2517 imx_uart_restore_context(sport); 2518 2519 return 0; 2520 } 2521 2522 static int imx_uart_suspend(struct device *dev) 2523 { 2524 struct imx_port *sport = dev_get_drvdata(dev); 2525 int ret; 2526 2527 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2528 disable_irq(sport->port.irq); 2529 2530 ret = clk_prepare_enable(sport->clk_ipg); 2531 if (ret) 2532 return ret; 2533 2534 /* enable wakeup from i.MX UART */ 2535 imx_uart_enable_wakeup(sport, true); 2536 2537 return 0; 2538 } 2539 2540 static int imx_uart_resume(struct device *dev) 2541 { 2542 struct imx_port *sport = dev_get_drvdata(dev); 2543 2544 /* disable wakeup from i.MX UART */ 2545 imx_uart_enable_wakeup(sport, false); 2546 2547 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2548 enable_irq(sport->port.irq); 2549 2550 clk_disable_unprepare(sport->clk_ipg); 2551 2552 return 0; 2553 } 2554 2555 static int imx_uart_freeze(struct device *dev) 2556 { 2557 struct imx_port *sport = dev_get_drvdata(dev); 2558 2559 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2560 2561 return clk_prepare_enable(sport->clk_ipg); 2562 } 2563 2564 static int imx_uart_thaw(struct device *dev) 2565 { 2566 struct imx_port *sport = dev_get_drvdata(dev); 2567 2568 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2569 2570 clk_disable_unprepare(sport->clk_ipg); 2571 2572 return 0; 2573 } 2574 2575 static const struct dev_pm_ops imx_uart_pm_ops = { 2576 .suspend_noirq = imx_uart_suspend_noirq, 2577 .resume_noirq = imx_uart_resume_noirq, 2578 .freeze_noirq = imx_uart_suspend_noirq, 2579 .restore_noirq = imx_uart_resume_noirq, 2580 .suspend = imx_uart_suspend, 2581 .resume = imx_uart_resume, 2582 .freeze = imx_uart_freeze, 2583 .thaw = imx_uart_thaw, 2584 .restore = imx_uart_thaw, 2585 }; 2586 2587 static struct platform_driver imx_uart_platform_driver = { 2588 .probe = imx_uart_probe, 2589 .remove = imx_uart_remove, 2590 2591 .driver = { 2592 .name = "imx-uart", 2593 .of_match_table = imx_uart_dt_ids, 2594 .pm = &imx_uart_pm_ops, 2595 }, 2596 }; 2597 2598 static int __init imx_uart_init(void) 2599 { 2600 int ret = uart_register_driver(&imx_uart_uart_driver); 2601 2602 if (ret) 2603 return ret; 2604 2605 ret = platform_driver_register(&imx_uart_platform_driver); 2606 if (ret != 0) 2607 uart_unregister_driver(&imx_uart_uart_driver); 2608 2609 return ret; 2610 } 2611 2612 static void __exit imx_uart_exit(void) 2613 { 2614 platform_driver_unregister(&imx_uart_platform_driver); 2615 uart_unregister_driver(&imx_uart_uart_driver); 2616 } 2617 2618 module_init(imx_uart_init); 2619 module_exit(imx_uart_exit); 2620 2621 MODULE_AUTHOR("Sascha Hauer"); 2622 MODULE_DESCRIPTION("IMX generic serial port driver"); 2623 MODULE_LICENSE("GPL"); 2624 MODULE_ALIAS("platform:imx-uart"); 2625