1 /* 2 * Driver for Motorola IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * Copyright (C) 2009 emlix GmbH 10 * Author: Fabian Godehardt (added IrDA support for iMX) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 * [29-Mar-2005] Mike Lee 27 * Added hardware handshake 28 */ 29 30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31 #define SUPPORT_SYSRQ 32 #endif 33 34 #include <linux/module.h> 35 #include <linux/ioport.h> 36 #include <linux/init.h> 37 #include <linux/console.h> 38 #include <linux/sysrq.h> 39 #include <linux/platform_device.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/serial_core.h> 43 #include <linux/serial.h> 44 #include <linux/clk.h> 45 #include <linux/delay.h> 46 #include <linux/rational.h> 47 #include <linux/slab.h> 48 #include <linux/of.h> 49 #include <linux/of_device.h> 50 #include <linux/pinctrl/consumer.h> 51 #include <linux/io.h> 52 53 #include <asm/irq.h> 54 #include <linux/platform_data/serial-imx.h> 55 56 /* Register definitions */ 57 #define URXD0 0x0 /* Receiver Register */ 58 #define URTX0 0x40 /* Transmitter Register */ 59 #define UCR1 0x80 /* Control Register 1 */ 60 #define UCR2 0x84 /* Control Register 2 */ 61 #define UCR3 0x88 /* Control Register 3 */ 62 #define UCR4 0x8c /* Control Register 4 */ 63 #define UFCR 0x90 /* FIFO Control Register */ 64 #define USR1 0x94 /* Status Register 1 */ 65 #define USR2 0x98 /* Status Register 2 */ 66 #define UESC 0x9c /* Escape Character Register */ 67 #define UTIM 0xa0 /* Escape Timer Register */ 68 #define UBIR 0xa4 /* BRM Incremental Register */ 69 #define UBMR 0xa8 /* BRM Modulator Register */ 70 #define UBRC 0xac /* Baud Rate Count Register */ 71 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 72 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 73 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 74 75 /* UART Control Register Bit Fields.*/ 76 #define URXD_CHARRDY (1<<15) 77 #define URXD_ERR (1<<14) 78 #define URXD_OVRRUN (1<<13) 79 #define URXD_FRMERR (1<<12) 80 #define URXD_BRK (1<<11) 81 #define URXD_PRERR (1<<10) 82 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 83 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 84 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 85 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 86 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 87 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 88 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 89 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 90 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 91 #define UCR1_SNDBRK (1<<4) /* Send break */ 92 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 93 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 94 #define UCR1_DOZE (1<<1) /* Doze */ 95 #define UCR1_UARTEN (1<<0) /* UART enabled */ 96 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 97 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 98 #define UCR2_CTSC (1<<13) /* CTS pin control */ 99 #define UCR2_CTS (1<<12) /* Clear to send */ 100 #define UCR2_ESCEN (1<<11) /* Escape enable */ 101 #define UCR2_PREN (1<<8) /* Parity enable */ 102 #define UCR2_PROE (1<<7) /* Parity odd/even */ 103 #define UCR2_STPB (1<<6) /* Stop */ 104 #define UCR2_WS (1<<5) /* Word size */ 105 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 106 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 107 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 108 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 109 #define UCR2_SRST (1<<0) /* SW reset */ 110 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 111 #define UCR3_PARERREN (1<<12) /* Parity enable */ 112 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 113 #define UCR3_DSR (1<<10) /* Data set ready */ 114 #define UCR3_DCD (1<<9) /* Data carrier detect */ 115 #define UCR3_RI (1<<8) /* Ring indicator */ 116 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 117 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 118 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 119 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 120 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 121 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 122 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 123 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 124 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 125 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 126 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 127 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 128 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 129 #define UCR4_IRSC (1<<5) /* IR special case */ 130 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 131 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 132 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 133 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 134 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 135 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 136 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 137 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 138 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 139 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 140 #define USR1_RTSS (1<<14) /* RTS pin status */ 141 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 142 #define USR1_RTSD (1<<12) /* RTS delta */ 143 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 144 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 145 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 146 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 147 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 148 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 149 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 150 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 151 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 152 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 153 #define USR2_IDLE (1<<12) /* Idle condition */ 154 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 155 #define USR2_WAKE (1<<7) /* Wake */ 156 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 157 #define USR2_TXDC (1<<3) /* Transmitter complete */ 158 #define USR2_BRCD (1<<2) /* Break condition */ 159 #define USR2_ORE (1<<1) /* Overrun error */ 160 #define USR2_RDR (1<<0) /* Recv data ready */ 161 #define UTS_FRCPERR (1<<13) /* Force parity error */ 162 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 163 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 164 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 165 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 166 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 167 #define UTS_SOFTRST (1<<0) /* Software reset */ 168 169 /* We've been assigned a range on the "Low-density serial ports" major */ 170 #define SERIAL_IMX_MAJOR 207 171 #define MINOR_START 16 172 #define DEV_NAME "ttymxc" 173 174 /* 175 * This determines how often we check the modem status signals 176 * for any change. They generally aren't connected to an IRQ 177 * so we have to poll them. We also check immediately before 178 * filling the TX fifo incase CTS has been dropped. 179 */ 180 #define MCTRL_TIMEOUT (250*HZ/1000) 181 182 #define DRIVER_NAME "IMX-uart" 183 184 #define UART_NR 8 185 186 /* i.mx21 type uart runs on all i.mx except i.mx1 */ 187 enum imx_uart_type { 188 IMX1_UART, 189 IMX21_UART, 190 }; 191 192 /* device type dependent stuff */ 193 struct imx_uart_data { 194 unsigned uts_reg; 195 enum imx_uart_type devtype; 196 }; 197 198 struct imx_port { 199 struct uart_port port; 200 struct timer_list timer; 201 unsigned int old_status; 202 int txirq, rxirq, rtsirq; 203 unsigned int have_rtscts:1; 204 unsigned int use_irda:1; 205 unsigned int irda_inv_rx:1; 206 unsigned int irda_inv_tx:1; 207 unsigned short trcv_delay; /* transceiver delay */ 208 struct clk *clk_ipg; 209 struct clk *clk_per; 210 const struct imx_uart_data *devdata; 211 }; 212 213 struct imx_port_ucrs { 214 unsigned int ucr1; 215 unsigned int ucr2; 216 unsigned int ucr3; 217 }; 218 219 #ifdef CONFIG_IRDA 220 #define USE_IRDA(sport) ((sport)->use_irda) 221 #else 222 #define USE_IRDA(sport) (0) 223 #endif 224 225 static struct imx_uart_data imx_uart_devdata[] = { 226 [IMX1_UART] = { 227 .uts_reg = IMX1_UTS, 228 .devtype = IMX1_UART, 229 }, 230 [IMX21_UART] = { 231 .uts_reg = IMX21_UTS, 232 .devtype = IMX21_UART, 233 }, 234 }; 235 236 static struct platform_device_id imx_uart_devtype[] = { 237 { 238 .name = "imx1-uart", 239 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 240 }, { 241 .name = "imx21-uart", 242 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 243 }, { 244 /* sentinel */ 245 } 246 }; 247 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 248 249 static struct of_device_id imx_uart_dt_ids[] = { 250 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 251 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 252 { /* sentinel */ } 253 }; 254 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 255 256 static inline unsigned uts_reg(struct imx_port *sport) 257 { 258 return sport->devdata->uts_reg; 259 } 260 261 static inline int is_imx1_uart(struct imx_port *sport) 262 { 263 return sport->devdata->devtype == IMX1_UART; 264 } 265 266 static inline int is_imx21_uart(struct imx_port *sport) 267 { 268 return sport->devdata->devtype == IMX21_UART; 269 } 270 271 /* 272 * Save and restore functions for UCR1, UCR2 and UCR3 registers 273 */ 274 static void imx_port_ucrs_save(struct uart_port *port, 275 struct imx_port_ucrs *ucr) 276 { 277 /* save control registers */ 278 ucr->ucr1 = readl(port->membase + UCR1); 279 ucr->ucr2 = readl(port->membase + UCR2); 280 ucr->ucr3 = readl(port->membase + UCR3); 281 } 282 283 static void imx_port_ucrs_restore(struct uart_port *port, 284 struct imx_port_ucrs *ucr) 285 { 286 /* restore control registers */ 287 writel(ucr->ucr1, port->membase + UCR1); 288 writel(ucr->ucr2, port->membase + UCR2); 289 writel(ucr->ucr3, port->membase + UCR3); 290 } 291 292 /* 293 * Handle any change of modem status signal since we were last called. 294 */ 295 static void imx_mctrl_check(struct imx_port *sport) 296 { 297 unsigned int status, changed; 298 299 status = sport->port.ops->get_mctrl(&sport->port); 300 changed = status ^ sport->old_status; 301 302 if (changed == 0) 303 return; 304 305 sport->old_status = status; 306 307 if (changed & TIOCM_RI) 308 sport->port.icount.rng++; 309 if (changed & TIOCM_DSR) 310 sport->port.icount.dsr++; 311 if (changed & TIOCM_CAR) 312 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 313 if (changed & TIOCM_CTS) 314 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 315 316 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 317 } 318 319 /* 320 * This is our per-port timeout handler, for checking the 321 * modem status signals. 322 */ 323 static void imx_timeout(unsigned long data) 324 { 325 struct imx_port *sport = (struct imx_port *)data; 326 unsigned long flags; 327 328 if (sport->port.state) { 329 spin_lock_irqsave(&sport->port.lock, flags); 330 imx_mctrl_check(sport); 331 spin_unlock_irqrestore(&sport->port.lock, flags); 332 333 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 334 } 335 } 336 337 /* 338 * interrupts disabled on entry 339 */ 340 static void imx_stop_tx(struct uart_port *port) 341 { 342 struct imx_port *sport = (struct imx_port *)port; 343 unsigned long temp; 344 345 if (USE_IRDA(sport)) { 346 /* half duplex - wait for end of transmission */ 347 int n = 256; 348 while ((--n > 0) && 349 !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 350 udelay(5); 351 barrier(); 352 } 353 /* 354 * irda transceiver - wait a bit more to avoid 355 * cutoff, hardware dependent 356 */ 357 udelay(sport->trcv_delay); 358 359 /* 360 * half duplex - reactivate receive mode, 361 * flush receive pipe echo crap 362 */ 363 if (readl(sport->port.membase + USR2) & USR2_TXDC) { 364 temp = readl(sport->port.membase + UCR1); 365 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 366 writel(temp, sport->port.membase + UCR1); 367 368 temp = readl(sport->port.membase + UCR4); 369 temp &= ~(UCR4_TCEN); 370 writel(temp, sport->port.membase + UCR4); 371 372 while (readl(sport->port.membase + URXD0) & 373 URXD_CHARRDY) 374 barrier(); 375 376 temp = readl(sport->port.membase + UCR1); 377 temp |= UCR1_RRDYEN; 378 writel(temp, sport->port.membase + UCR1); 379 380 temp = readl(sport->port.membase + UCR4); 381 temp |= UCR4_DREN; 382 writel(temp, sport->port.membase + UCR4); 383 } 384 return; 385 } 386 387 temp = readl(sport->port.membase + UCR1); 388 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 389 } 390 391 /* 392 * interrupts disabled on entry 393 */ 394 static void imx_stop_rx(struct uart_port *port) 395 { 396 struct imx_port *sport = (struct imx_port *)port; 397 unsigned long temp; 398 399 temp = readl(sport->port.membase + UCR2); 400 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 401 } 402 403 /* 404 * Set the modem control timer to fire immediately. 405 */ 406 static void imx_enable_ms(struct uart_port *port) 407 { 408 struct imx_port *sport = (struct imx_port *)port; 409 410 mod_timer(&sport->timer, jiffies); 411 } 412 413 static inline void imx_transmit_buffer(struct imx_port *sport) 414 { 415 struct circ_buf *xmit = &sport->port.state->xmit; 416 417 while (!uart_circ_empty(xmit) && 418 !(readl(sport->port.membase + uts_reg(sport)) 419 & UTS_TXFULL)) { 420 /* send xmit->buf[xmit->tail] 421 * out the port here */ 422 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 423 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 424 sport->port.icount.tx++; 425 } 426 427 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 428 uart_write_wakeup(&sport->port); 429 430 if (uart_circ_empty(xmit)) 431 imx_stop_tx(&sport->port); 432 } 433 434 /* 435 * interrupts disabled on entry 436 */ 437 static void imx_start_tx(struct uart_port *port) 438 { 439 struct imx_port *sport = (struct imx_port *)port; 440 unsigned long temp; 441 442 if (USE_IRDA(sport)) { 443 /* half duplex in IrDA mode; have to disable receive mode */ 444 temp = readl(sport->port.membase + UCR4); 445 temp &= ~(UCR4_DREN); 446 writel(temp, sport->port.membase + UCR4); 447 448 temp = readl(sport->port.membase + UCR1); 449 temp &= ~(UCR1_RRDYEN); 450 writel(temp, sport->port.membase + UCR1); 451 } 452 453 temp = readl(sport->port.membase + UCR1); 454 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 455 456 if (USE_IRDA(sport)) { 457 temp = readl(sport->port.membase + UCR1); 458 temp |= UCR1_TRDYEN; 459 writel(temp, sport->port.membase + UCR1); 460 461 temp = readl(sport->port.membase + UCR4); 462 temp |= UCR4_TCEN; 463 writel(temp, sport->port.membase + UCR4); 464 } 465 466 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) 467 imx_transmit_buffer(sport); 468 } 469 470 static irqreturn_t imx_rtsint(int irq, void *dev_id) 471 { 472 struct imx_port *sport = dev_id; 473 unsigned int val; 474 unsigned long flags; 475 476 spin_lock_irqsave(&sport->port.lock, flags); 477 478 writel(USR1_RTSD, sport->port.membase + USR1); 479 val = readl(sport->port.membase + USR1) & USR1_RTSS; 480 uart_handle_cts_change(&sport->port, !!val); 481 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 482 483 spin_unlock_irqrestore(&sport->port.lock, flags); 484 return IRQ_HANDLED; 485 } 486 487 static irqreturn_t imx_txint(int irq, void *dev_id) 488 { 489 struct imx_port *sport = dev_id; 490 struct circ_buf *xmit = &sport->port.state->xmit; 491 unsigned long flags; 492 493 spin_lock_irqsave(&sport->port.lock, flags); 494 if (sport->port.x_char) { 495 /* Send next char */ 496 writel(sport->port.x_char, sport->port.membase + URTX0); 497 goto out; 498 } 499 500 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 501 imx_stop_tx(&sport->port); 502 goto out; 503 } 504 505 imx_transmit_buffer(sport); 506 507 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 508 uart_write_wakeup(&sport->port); 509 510 out: 511 spin_unlock_irqrestore(&sport->port.lock, flags); 512 return IRQ_HANDLED; 513 } 514 515 static irqreturn_t imx_rxint(int irq, void *dev_id) 516 { 517 struct imx_port *sport = dev_id; 518 unsigned int rx, flg, ignored = 0; 519 struct tty_port *port = &sport->port.state->port; 520 unsigned long flags, temp; 521 522 spin_lock_irqsave(&sport->port.lock, flags); 523 524 while (readl(sport->port.membase + USR2) & USR2_RDR) { 525 flg = TTY_NORMAL; 526 sport->port.icount.rx++; 527 528 rx = readl(sport->port.membase + URXD0); 529 530 temp = readl(sport->port.membase + USR2); 531 if (temp & USR2_BRCD) { 532 writel(USR2_BRCD, sport->port.membase + USR2); 533 if (uart_handle_break(&sport->port)) 534 continue; 535 } 536 537 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 538 continue; 539 540 if (unlikely(rx & URXD_ERR)) { 541 if (rx & URXD_BRK) 542 sport->port.icount.brk++; 543 else if (rx & URXD_PRERR) 544 sport->port.icount.parity++; 545 else if (rx & URXD_FRMERR) 546 sport->port.icount.frame++; 547 if (rx & URXD_OVRRUN) 548 sport->port.icount.overrun++; 549 550 if (rx & sport->port.ignore_status_mask) { 551 if (++ignored > 100) 552 goto out; 553 continue; 554 } 555 556 rx &= sport->port.read_status_mask; 557 558 if (rx & URXD_BRK) 559 flg = TTY_BREAK; 560 else if (rx & URXD_PRERR) 561 flg = TTY_PARITY; 562 else if (rx & URXD_FRMERR) 563 flg = TTY_FRAME; 564 if (rx & URXD_OVRRUN) 565 flg = TTY_OVERRUN; 566 567 #ifdef SUPPORT_SYSRQ 568 sport->port.sysrq = 0; 569 #endif 570 } 571 572 tty_insert_flip_char(port, rx, flg); 573 } 574 575 out: 576 spin_unlock_irqrestore(&sport->port.lock, flags); 577 tty_flip_buffer_push(port); 578 return IRQ_HANDLED; 579 } 580 581 static irqreturn_t imx_int(int irq, void *dev_id) 582 { 583 struct imx_port *sport = dev_id; 584 unsigned int sts; 585 586 sts = readl(sport->port.membase + USR1); 587 588 if (sts & USR1_RRDY) 589 imx_rxint(irq, dev_id); 590 591 if (sts & USR1_TRDY && 592 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 593 imx_txint(irq, dev_id); 594 595 if (sts & USR1_RTSD) 596 imx_rtsint(irq, dev_id); 597 598 if (sts & USR1_AWAKE) 599 writel(USR1_AWAKE, sport->port.membase + USR1); 600 601 return IRQ_HANDLED; 602 } 603 604 /* 605 * Return TIOCSER_TEMT when transmitter is not busy. 606 */ 607 static unsigned int imx_tx_empty(struct uart_port *port) 608 { 609 struct imx_port *sport = (struct imx_port *)port; 610 611 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 612 } 613 614 /* 615 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 616 */ 617 static unsigned int imx_get_mctrl(struct uart_port *port) 618 { 619 struct imx_port *sport = (struct imx_port *)port; 620 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 621 622 if (readl(sport->port.membase + USR1) & USR1_RTSS) 623 tmp |= TIOCM_CTS; 624 625 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 626 tmp |= TIOCM_RTS; 627 628 return tmp; 629 } 630 631 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 632 { 633 struct imx_port *sport = (struct imx_port *)port; 634 unsigned long temp; 635 636 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; 637 638 if (mctrl & TIOCM_RTS) 639 temp |= UCR2_CTS; 640 641 writel(temp, sport->port.membase + UCR2); 642 } 643 644 /* 645 * Interrupts always disabled. 646 */ 647 static void imx_break_ctl(struct uart_port *port, int break_state) 648 { 649 struct imx_port *sport = (struct imx_port *)port; 650 unsigned long flags, temp; 651 652 spin_lock_irqsave(&sport->port.lock, flags); 653 654 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 655 656 if (break_state != 0) 657 temp |= UCR1_SNDBRK; 658 659 writel(temp, sport->port.membase + UCR1); 660 661 spin_unlock_irqrestore(&sport->port.lock, flags); 662 } 663 664 #define TXTL 2 /* reset default */ 665 #define RXTL 1 /* reset default */ 666 667 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 668 { 669 unsigned int val; 670 671 /* set receiver / transmitter trigger level */ 672 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 673 val |= TXTL << UFCR_TXTL_SHF | RXTL; 674 writel(val, sport->port.membase + UFCR); 675 return 0; 676 } 677 678 /* half the RX buffer size */ 679 #define CTSTL 16 680 681 static int imx_startup(struct uart_port *port) 682 { 683 struct imx_port *sport = (struct imx_port *)port; 684 int retval; 685 unsigned long flags, temp; 686 687 imx_setup_ufcr(sport, 0); 688 689 /* disable the DREN bit (Data Ready interrupt enable) before 690 * requesting IRQs 691 */ 692 temp = readl(sport->port.membase + UCR4); 693 694 if (USE_IRDA(sport)) 695 temp |= UCR4_IRSC; 696 697 /* set the trigger level for CTS */ 698 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 699 temp |= CTSTL << UCR4_CTSTL_SHF; 700 701 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 702 703 if (USE_IRDA(sport)) { 704 /* reset fifo's and state machines */ 705 int i = 100; 706 temp = readl(sport->port.membase + UCR2); 707 temp &= ~UCR2_SRST; 708 writel(temp, sport->port.membase + UCR2); 709 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && 710 (--i > 0)) { 711 udelay(1); 712 } 713 } 714 715 /* 716 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 717 * chips only have one interrupt. 718 */ 719 if (sport->txirq > 0) { 720 retval = request_irq(sport->rxirq, imx_rxint, 0, 721 DRIVER_NAME, sport); 722 if (retval) 723 goto error_out1; 724 725 retval = request_irq(sport->txirq, imx_txint, 0, 726 DRIVER_NAME, sport); 727 if (retval) 728 goto error_out2; 729 730 /* do not use RTS IRQ on IrDA */ 731 if (!USE_IRDA(sport)) { 732 retval = request_irq(sport->rtsirq, imx_rtsint, 0, 733 DRIVER_NAME, sport); 734 if (retval) 735 goto error_out3; 736 } 737 } else { 738 retval = request_irq(sport->port.irq, imx_int, 0, 739 DRIVER_NAME, sport); 740 if (retval) { 741 free_irq(sport->port.irq, sport); 742 goto error_out1; 743 } 744 } 745 746 spin_lock_irqsave(&sport->port.lock, flags); 747 /* 748 * Finally, clear and enable interrupts 749 */ 750 writel(USR1_RTSD, sport->port.membase + USR1); 751 752 temp = readl(sport->port.membase + UCR1); 753 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 754 755 if (USE_IRDA(sport)) { 756 temp |= UCR1_IREN; 757 temp &= ~(UCR1_RTSDEN); 758 } 759 760 writel(temp, sport->port.membase + UCR1); 761 762 temp = readl(sport->port.membase + UCR2); 763 temp |= (UCR2_RXEN | UCR2_TXEN); 764 writel(temp, sport->port.membase + UCR2); 765 766 if (USE_IRDA(sport)) { 767 /* clear RX-FIFO */ 768 int i = 64; 769 while ((--i > 0) && 770 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { 771 barrier(); 772 } 773 } 774 775 if (is_imx21_uart(sport)) { 776 temp = readl(sport->port.membase + UCR3); 777 temp |= IMX21_UCR3_RXDMUXSEL; 778 writel(temp, sport->port.membase + UCR3); 779 } 780 781 if (USE_IRDA(sport)) { 782 temp = readl(sport->port.membase + UCR4); 783 if (sport->irda_inv_rx) 784 temp |= UCR4_INVR; 785 else 786 temp &= ~(UCR4_INVR); 787 writel(temp | UCR4_DREN, sport->port.membase + UCR4); 788 789 temp = readl(sport->port.membase + UCR3); 790 if (sport->irda_inv_tx) 791 temp |= UCR3_INVT; 792 else 793 temp &= ~(UCR3_INVT); 794 writel(temp, sport->port.membase + UCR3); 795 } 796 797 /* 798 * Enable modem status interrupts 799 */ 800 imx_enable_ms(&sport->port); 801 spin_unlock_irqrestore(&sport->port.lock, flags); 802 803 if (USE_IRDA(sport)) { 804 struct imxuart_platform_data *pdata; 805 pdata = sport->port.dev->platform_data; 806 sport->irda_inv_rx = pdata->irda_inv_rx; 807 sport->irda_inv_tx = pdata->irda_inv_tx; 808 sport->trcv_delay = pdata->transceiver_delay; 809 if (pdata->irda_enable) 810 pdata->irda_enable(1); 811 } 812 813 return 0; 814 815 error_out3: 816 if (sport->txirq) 817 free_irq(sport->txirq, sport); 818 error_out2: 819 if (sport->rxirq) 820 free_irq(sport->rxirq, sport); 821 error_out1: 822 return retval; 823 } 824 825 static void imx_shutdown(struct uart_port *port) 826 { 827 struct imx_port *sport = (struct imx_port *)port; 828 unsigned long temp; 829 unsigned long flags; 830 831 spin_lock_irqsave(&sport->port.lock, flags); 832 temp = readl(sport->port.membase + UCR2); 833 temp &= ~(UCR2_TXEN); 834 writel(temp, sport->port.membase + UCR2); 835 spin_unlock_irqrestore(&sport->port.lock, flags); 836 837 if (USE_IRDA(sport)) { 838 struct imxuart_platform_data *pdata; 839 pdata = sport->port.dev->platform_data; 840 if (pdata->irda_enable) 841 pdata->irda_enable(0); 842 } 843 844 /* 845 * Stop our timer. 846 */ 847 del_timer_sync(&sport->timer); 848 849 /* 850 * Free the interrupts 851 */ 852 if (sport->txirq > 0) { 853 if (!USE_IRDA(sport)) 854 free_irq(sport->rtsirq, sport); 855 free_irq(sport->txirq, sport); 856 free_irq(sport->rxirq, sport); 857 } else 858 free_irq(sport->port.irq, sport); 859 860 /* 861 * Disable all interrupts, port and break condition. 862 */ 863 864 spin_lock_irqsave(&sport->port.lock, flags); 865 temp = readl(sport->port.membase + UCR1); 866 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 867 if (USE_IRDA(sport)) 868 temp &= ~(UCR1_IREN); 869 870 writel(temp, sport->port.membase + UCR1); 871 spin_unlock_irqrestore(&sport->port.lock, flags); 872 } 873 874 static void 875 imx_set_termios(struct uart_port *port, struct ktermios *termios, 876 struct ktermios *old) 877 { 878 struct imx_port *sport = (struct imx_port *)port; 879 unsigned long flags; 880 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 881 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 882 unsigned int div, ufcr; 883 unsigned long num, denom; 884 uint64_t tdiv64; 885 886 /* 887 * If we don't support modem control lines, don't allow 888 * these to be set. 889 */ 890 if (0) { 891 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 892 termios->c_cflag |= CLOCAL; 893 } 894 895 /* 896 * We only support CS7 and CS8. 897 */ 898 while ((termios->c_cflag & CSIZE) != CS7 && 899 (termios->c_cflag & CSIZE) != CS8) { 900 termios->c_cflag &= ~CSIZE; 901 termios->c_cflag |= old_csize; 902 old_csize = CS8; 903 } 904 905 if ((termios->c_cflag & CSIZE) == CS8) 906 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 907 else 908 ucr2 = UCR2_SRST | UCR2_IRTS; 909 910 if (termios->c_cflag & CRTSCTS) { 911 if (sport->have_rtscts) { 912 ucr2 &= ~UCR2_IRTS; 913 ucr2 |= UCR2_CTSC; 914 } else { 915 termios->c_cflag &= ~CRTSCTS; 916 } 917 } 918 919 if (termios->c_cflag & CSTOPB) 920 ucr2 |= UCR2_STPB; 921 if (termios->c_cflag & PARENB) { 922 ucr2 |= UCR2_PREN; 923 if (termios->c_cflag & PARODD) 924 ucr2 |= UCR2_PROE; 925 } 926 927 del_timer_sync(&sport->timer); 928 929 /* 930 * Ask the core to calculate the divisor for us. 931 */ 932 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 933 quot = uart_get_divisor(port, baud); 934 935 spin_lock_irqsave(&sport->port.lock, flags); 936 937 sport->port.read_status_mask = 0; 938 if (termios->c_iflag & INPCK) 939 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 940 if (termios->c_iflag & (BRKINT | PARMRK)) 941 sport->port.read_status_mask |= URXD_BRK; 942 943 /* 944 * Characters to ignore 945 */ 946 sport->port.ignore_status_mask = 0; 947 if (termios->c_iflag & IGNPAR) 948 sport->port.ignore_status_mask |= URXD_PRERR; 949 if (termios->c_iflag & IGNBRK) { 950 sport->port.ignore_status_mask |= URXD_BRK; 951 /* 952 * If we're ignoring parity and break indicators, 953 * ignore overruns too (for real raw support). 954 */ 955 if (termios->c_iflag & IGNPAR) 956 sport->port.ignore_status_mask |= URXD_OVRRUN; 957 } 958 959 /* 960 * Update the per-port timeout. 961 */ 962 uart_update_timeout(port, termios->c_cflag, baud); 963 964 /* 965 * disable interrupts and drain transmitter 966 */ 967 old_ucr1 = readl(sport->port.membase + UCR1); 968 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 969 sport->port.membase + UCR1); 970 971 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 972 barrier(); 973 974 /* then, disable everything */ 975 old_txrxen = readl(sport->port.membase + UCR2); 976 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 977 sport->port.membase + UCR2); 978 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 979 980 if (USE_IRDA(sport)) { 981 /* 982 * use maximum available submodule frequency to 983 * avoid missing short pulses due to low sampling rate 984 */ 985 div = 1; 986 } else { 987 div = sport->port.uartclk / (baud * 16); 988 if (div > 7) 989 div = 7; 990 if (!div) 991 div = 1; 992 } 993 994 rational_best_approximation(16 * div * baud, sport->port.uartclk, 995 1 << 16, 1 << 16, &num, &denom); 996 997 tdiv64 = sport->port.uartclk; 998 tdiv64 *= num; 999 do_div(tdiv64, denom * 16 * div); 1000 tty_termios_encode_baud_rate(termios, 1001 (speed_t)tdiv64, (speed_t)tdiv64); 1002 1003 num -= 1; 1004 denom -= 1; 1005 1006 ufcr = readl(sport->port.membase + UFCR); 1007 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1008 writel(ufcr, sport->port.membase + UFCR); 1009 1010 writel(num, sport->port.membase + UBIR); 1011 writel(denom, sport->port.membase + UBMR); 1012 1013 if (is_imx21_uart(sport)) 1014 writel(sport->port.uartclk / div / 1000, 1015 sport->port.membase + IMX21_ONEMS); 1016 1017 writel(old_ucr1, sport->port.membase + UCR1); 1018 1019 /* set the parity, stop bits and data size */ 1020 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1021 1022 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1023 imx_enable_ms(&sport->port); 1024 1025 spin_unlock_irqrestore(&sport->port.lock, flags); 1026 } 1027 1028 static const char *imx_type(struct uart_port *port) 1029 { 1030 struct imx_port *sport = (struct imx_port *)port; 1031 1032 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1033 } 1034 1035 /* 1036 * Release the memory region(s) being used by 'port'. 1037 */ 1038 static void imx_release_port(struct uart_port *port) 1039 { 1040 struct platform_device *pdev = to_platform_device(port->dev); 1041 struct resource *mmres; 1042 1043 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1044 release_mem_region(mmres->start, resource_size(mmres)); 1045 } 1046 1047 /* 1048 * Request the memory region(s) being used by 'port'. 1049 */ 1050 static int imx_request_port(struct uart_port *port) 1051 { 1052 struct platform_device *pdev = to_platform_device(port->dev); 1053 struct resource *mmres; 1054 void *ret; 1055 1056 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1057 if (!mmres) 1058 return -ENODEV; 1059 1060 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart"); 1061 1062 return ret ? 0 : -EBUSY; 1063 } 1064 1065 /* 1066 * Configure/autoconfigure the port. 1067 */ 1068 static void imx_config_port(struct uart_port *port, int flags) 1069 { 1070 struct imx_port *sport = (struct imx_port *)port; 1071 1072 if (flags & UART_CONFIG_TYPE && 1073 imx_request_port(&sport->port) == 0) 1074 sport->port.type = PORT_IMX; 1075 } 1076 1077 /* 1078 * Verify the new serial_struct (for TIOCSSERIAL). 1079 * The only change we allow are to the flags and type, and 1080 * even then only between PORT_IMX and PORT_UNKNOWN 1081 */ 1082 static int 1083 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1084 { 1085 struct imx_port *sport = (struct imx_port *)port; 1086 int ret = 0; 1087 1088 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1089 ret = -EINVAL; 1090 if (sport->port.irq != ser->irq) 1091 ret = -EINVAL; 1092 if (ser->io_type != UPIO_MEM) 1093 ret = -EINVAL; 1094 if (sport->port.uartclk / 16 != ser->baud_base) 1095 ret = -EINVAL; 1096 if ((void *)sport->port.mapbase != ser->iomem_base) 1097 ret = -EINVAL; 1098 if (sport->port.iobase != ser->port) 1099 ret = -EINVAL; 1100 if (ser->hub6 != 0) 1101 ret = -EINVAL; 1102 return ret; 1103 } 1104 1105 #if defined(CONFIG_CONSOLE_POLL) 1106 static int imx_poll_get_char(struct uart_port *port) 1107 { 1108 struct imx_port_ucrs old_ucr; 1109 unsigned int status; 1110 unsigned char c; 1111 1112 /* save control registers */ 1113 imx_port_ucrs_save(port, &old_ucr); 1114 1115 /* disable interrupts */ 1116 writel(UCR1_UARTEN, port->membase + UCR1); 1117 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1118 port->membase + UCR2); 1119 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1120 port->membase + UCR3); 1121 1122 /* poll */ 1123 do { 1124 status = readl(port->membase + USR2); 1125 } while (~status & USR2_RDR); 1126 1127 /* read */ 1128 c = readl(port->membase + URXD0); 1129 1130 /* restore control registers */ 1131 imx_port_ucrs_restore(port, &old_ucr); 1132 1133 return c; 1134 } 1135 1136 static void imx_poll_put_char(struct uart_port *port, unsigned char c) 1137 { 1138 struct imx_port_ucrs old_ucr; 1139 unsigned int status; 1140 1141 /* save control registers */ 1142 imx_port_ucrs_save(port, &old_ucr); 1143 1144 /* disable interrupts */ 1145 writel(UCR1_UARTEN, port->membase + UCR1); 1146 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1147 port->membase + UCR2); 1148 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1149 port->membase + UCR3); 1150 1151 /* drain */ 1152 do { 1153 status = readl(port->membase + USR1); 1154 } while (~status & USR1_TRDY); 1155 1156 /* write */ 1157 writel(c, port->membase + URTX0); 1158 1159 /* flush */ 1160 do { 1161 status = readl(port->membase + USR2); 1162 } while (~status & USR2_TXDC); 1163 1164 /* restore control registers */ 1165 imx_port_ucrs_restore(port, &old_ucr); 1166 } 1167 #endif 1168 1169 static struct uart_ops imx_pops = { 1170 .tx_empty = imx_tx_empty, 1171 .set_mctrl = imx_set_mctrl, 1172 .get_mctrl = imx_get_mctrl, 1173 .stop_tx = imx_stop_tx, 1174 .start_tx = imx_start_tx, 1175 .stop_rx = imx_stop_rx, 1176 .enable_ms = imx_enable_ms, 1177 .break_ctl = imx_break_ctl, 1178 .startup = imx_startup, 1179 .shutdown = imx_shutdown, 1180 .set_termios = imx_set_termios, 1181 .type = imx_type, 1182 .release_port = imx_release_port, 1183 .request_port = imx_request_port, 1184 .config_port = imx_config_port, 1185 .verify_port = imx_verify_port, 1186 #if defined(CONFIG_CONSOLE_POLL) 1187 .poll_get_char = imx_poll_get_char, 1188 .poll_put_char = imx_poll_put_char, 1189 #endif 1190 }; 1191 1192 static struct imx_port *imx_ports[UART_NR]; 1193 1194 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1195 static void imx_console_putchar(struct uart_port *port, int ch) 1196 { 1197 struct imx_port *sport = (struct imx_port *)port; 1198 1199 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1200 barrier(); 1201 1202 writel(ch, sport->port.membase + URTX0); 1203 } 1204 1205 /* 1206 * Interrupts are disabled on entering 1207 */ 1208 static void 1209 imx_console_write(struct console *co, const char *s, unsigned int count) 1210 { 1211 struct imx_port *sport = imx_ports[co->index]; 1212 struct imx_port_ucrs old_ucr; 1213 unsigned int ucr1; 1214 unsigned long flags = 0; 1215 int locked = 1; 1216 1217 if (sport->port.sysrq) 1218 locked = 0; 1219 else if (oops_in_progress) 1220 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1221 else 1222 spin_lock_irqsave(&sport->port.lock, flags); 1223 1224 /* 1225 * First, save UCR1/2/3 and then disable interrupts 1226 */ 1227 imx_port_ucrs_save(&sport->port, &old_ucr); 1228 ucr1 = old_ucr.ucr1; 1229 1230 if (is_imx1_uart(sport)) 1231 ucr1 |= IMX1_UCR1_UARTCLKEN; 1232 ucr1 |= UCR1_UARTEN; 1233 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1234 1235 writel(ucr1, sport->port.membase + UCR1); 1236 1237 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1238 1239 uart_console_write(&sport->port, s, count, imx_console_putchar); 1240 1241 /* 1242 * Finally, wait for transmitter to become empty 1243 * and restore UCR1/2/3 1244 */ 1245 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1246 1247 imx_port_ucrs_restore(&sport->port, &old_ucr); 1248 1249 if (locked) 1250 spin_unlock_irqrestore(&sport->port.lock, flags); 1251 } 1252 1253 /* 1254 * If the port was already initialised (eg, by a boot loader), 1255 * try to determine the current setup. 1256 */ 1257 static void __init 1258 imx_console_get_options(struct imx_port *sport, int *baud, 1259 int *parity, int *bits) 1260 { 1261 1262 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1263 /* ok, the port was enabled */ 1264 unsigned int ucr2, ubir, ubmr, uartclk; 1265 unsigned int baud_raw; 1266 unsigned int ucfr_rfdiv; 1267 1268 ucr2 = readl(sport->port.membase + UCR2); 1269 1270 *parity = 'n'; 1271 if (ucr2 & UCR2_PREN) { 1272 if (ucr2 & UCR2_PROE) 1273 *parity = 'o'; 1274 else 1275 *parity = 'e'; 1276 } 1277 1278 if (ucr2 & UCR2_WS) 1279 *bits = 8; 1280 else 1281 *bits = 7; 1282 1283 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1284 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1285 1286 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1287 if (ucfr_rfdiv == 6) 1288 ucfr_rfdiv = 7; 1289 else 1290 ucfr_rfdiv = 6 - ucfr_rfdiv; 1291 1292 uartclk = clk_get_rate(sport->clk_per); 1293 uartclk /= ucfr_rfdiv; 1294 1295 { /* 1296 * The next code provides exact computation of 1297 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1298 * without need of float support or long long division, 1299 * which would be required to prevent 32bit arithmetic overflow 1300 */ 1301 unsigned int mul = ubir + 1; 1302 unsigned int div = 16 * (ubmr + 1); 1303 unsigned int rem = uartclk % div; 1304 1305 baud_raw = (uartclk / div) * mul; 1306 baud_raw += (rem * mul + div / 2) / div; 1307 *baud = (baud_raw + 50) / 100 * 100; 1308 } 1309 1310 if (*baud != baud_raw) 1311 pr_info("Console IMX rounded baud rate from %d to %d\n", 1312 baud_raw, *baud); 1313 } 1314 } 1315 1316 static int __init 1317 imx_console_setup(struct console *co, char *options) 1318 { 1319 struct imx_port *sport; 1320 int baud = 9600; 1321 int bits = 8; 1322 int parity = 'n'; 1323 int flow = 'n'; 1324 1325 /* 1326 * Check whether an invalid uart number has been specified, and 1327 * if so, search for the first available port that does have 1328 * console support. 1329 */ 1330 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1331 co->index = 0; 1332 sport = imx_ports[co->index]; 1333 if (sport == NULL) 1334 return -ENODEV; 1335 1336 if (options) 1337 uart_parse_options(options, &baud, &parity, &bits, &flow); 1338 else 1339 imx_console_get_options(sport, &baud, &parity, &bits); 1340 1341 imx_setup_ufcr(sport, 0); 1342 1343 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1344 } 1345 1346 static struct uart_driver imx_reg; 1347 static struct console imx_console = { 1348 .name = DEV_NAME, 1349 .write = imx_console_write, 1350 .device = uart_console_device, 1351 .setup = imx_console_setup, 1352 .flags = CON_PRINTBUFFER, 1353 .index = -1, 1354 .data = &imx_reg, 1355 }; 1356 1357 #define IMX_CONSOLE &imx_console 1358 #else 1359 #define IMX_CONSOLE NULL 1360 #endif 1361 1362 static struct uart_driver imx_reg = { 1363 .owner = THIS_MODULE, 1364 .driver_name = DRIVER_NAME, 1365 .dev_name = DEV_NAME, 1366 .major = SERIAL_IMX_MAJOR, 1367 .minor = MINOR_START, 1368 .nr = ARRAY_SIZE(imx_ports), 1369 .cons = IMX_CONSOLE, 1370 }; 1371 1372 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1373 { 1374 struct imx_port *sport = platform_get_drvdata(dev); 1375 unsigned int val; 1376 1377 /* enable wakeup from i.MX UART */ 1378 val = readl(sport->port.membase + UCR3); 1379 val |= UCR3_AWAKEN; 1380 writel(val, sport->port.membase + UCR3); 1381 1382 uart_suspend_port(&imx_reg, &sport->port); 1383 1384 return 0; 1385 } 1386 1387 static int serial_imx_resume(struct platform_device *dev) 1388 { 1389 struct imx_port *sport = platform_get_drvdata(dev); 1390 unsigned int val; 1391 1392 /* disable wakeup from i.MX UART */ 1393 val = readl(sport->port.membase + UCR3); 1394 val &= ~UCR3_AWAKEN; 1395 writel(val, sport->port.membase + UCR3); 1396 1397 uart_resume_port(&imx_reg, &sport->port); 1398 1399 return 0; 1400 } 1401 1402 #ifdef CONFIG_OF 1403 /* 1404 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 1405 * could successfully get all information from dt or a negative errno. 1406 */ 1407 static int serial_imx_probe_dt(struct imx_port *sport, 1408 struct platform_device *pdev) 1409 { 1410 struct device_node *np = pdev->dev.of_node; 1411 const struct of_device_id *of_id = 1412 of_match_device(imx_uart_dt_ids, &pdev->dev); 1413 int ret; 1414 1415 if (!np) 1416 /* no device tree device */ 1417 return 1; 1418 1419 ret = of_alias_get_id(np, "serial"); 1420 if (ret < 0) { 1421 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1422 return ret; 1423 } 1424 sport->port.line = ret; 1425 1426 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1427 sport->have_rtscts = 1; 1428 1429 if (of_get_property(np, "fsl,irda-mode", NULL)) 1430 sport->use_irda = 1; 1431 1432 sport->devdata = of_id->data; 1433 1434 return 0; 1435 } 1436 #else 1437 static inline int serial_imx_probe_dt(struct imx_port *sport, 1438 struct platform_device *pdev) 1439 { 1440 return 1; 1441 } 1442 #endif 1443 1444 static void serial_imx_probe_pdata(struct imx_port *sport, 1445 struct platform_device *pdev) 1446 { 1447 struct imxuart_platform_data *pdata = pdev->dev.platform_data; 1448 1449 sport->port.line = pdev->id; 1450 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 1451 1452 if (!pdata) 1453 return; 1454 1455 if (pdata->flags & IMXUART_HAVE_RTSCTS) 1456 sport->have_rtscts = 1; 1457 1458 if (pdata->flags & IMXUART_IRDA) 1459 sport->use_irda = 1; 1460 } 1461 1462 static int serial_imx_probe(struct platform_device *pdev) 1463 { 1464 struct imx_port *sport; 1465 struct imxuart_platform_data *pdata; 1466 void __iomem *base; 1467 int ret = 0; 1468 struct resource *res; 1469 struct pinctrl *pinctrl; 1470 1471 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1472 if (!sport) 1473 return -ENOMEM; 1474 1475 ret = serial_imx_probe_dt(sport, pdev); 1476 if (ret > 0) 1477 serial_imx_probe_pdata(sport, pdev); 1478 else if (ret < 0) 1479 return ret; 1480 1481 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1482 if (!res) 1483 return -ENODEV; 1484 1485 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE); 1486 if (!base) 1487 return -ENOMEM; 1488 1489 sport->port.dev = &pdev->dev; 1490 sport->port.mapbase = res->start; 1491 sport->port.membase = base; 1492 sport->port.type = PORT_IMX, 1493 sport->port.iotype = UPIO_MEM; 1494 sport->port.irq = platform_get_irq(pdev, 0); 1495 sport->rxirq = platform_get_irq(pdev, 0); 1496 sport->txirq = platform_get_irq(pdev, 1); 1497 sport->rtsirq = platform_get_irq(pdev, 2); 1498 sport->port.fifosize = 32; 1499 sport->port.ops = &imx_pops; 1500 sport->port.flags = UPF_BOOT_AUTOCONF; 1501 init_timer(&sport->timer); 1502 sport->timer.function = imx_timeout; 1503 sport->timer.data = (unsigned long)sport; 1504 1505 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 1506 if (IS_ERR(pinctrl)) { 1507 ret = PTR_ERR(pinctrl); 1508 dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret); 1509 return ret; 1510 } 1511 1512 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1513 if (IS_ERR(sport->clk_ipg)) { 1514 ret = PTR_ERR(sport->clk_ipg); 1515 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 1516 return ret; 1517 } 1518 1519 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 1520 if (IS_ERR(sport->clk_per)) { 1521 ret = PTR_ERR(sport->clk_per); 1522 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 1523 return ret; 1524 } 1525 1526 clk_prepare_enable(sport->clk_per); 1527 clk_prepare_enable(sport->clk_ipg); 1528 1529 sport->port.uartclk = clk_get_rate(sport->clk_per); 1530 1531 imx_ports[sport->port.line] = sport; 1532 1533 pdata = pdev->dev.platform_data; 1534 if (pdata && pdata->init) { 1535 ret = pdata->init(pdev); 1536 if (ret) 1537 goto clkput; 1538 } 1539 1540 ret = uart_add_one_port(&imx_reg, &sport->port); 1541 if (ret) 1542 goto deinit; 1543 platform_set_drvdata(pdev, sport); 1544 1545 return 0; 1546 deinit: 1547 if (pdata && pdata->exit) 1548 pdata->exit(pdev); 1549 clkput: 1550 clk_disable_unprepare(sport->clk_per); 1551 clk_disable_unprepare(sport->clk_ipg); 1552 return ret; 1553 } 1554 1555 static int serial_imx_remove(struct platform_device *pdev) 1556 { 1557 struct imxuart_platform_data *pdata; 1558 struct imx_port *sport = platform_get_drvdata(pdev); 1559 1560 pdata = pdev->dev.platform_data; 1561 1562 platform_set_drvdata(pdev, NULL); 1563 1564 uart_remove_one_port(&imx_reg, &sport->port); 1565 1566 clk_disable_unprepare(sport->clk_per); 1567 clk_disable_unprepare(sport->clk_ipg); 1568 1569 if (pdata && pdata->exit) 1570 pdata->exit(pdev); 1571 1572 return 0; 1573 } 1574 1575 static struct platform_driver serial_imx_driver = { 1576 .probe = serial_imx_probe, 1577 .remove = serial_imx_remove, 1578 1579 .suspend = serial_imx_suspend, 1580 .resume = serial_imx_resume, 1581 .id_table = imx_uart_devtype, 1582 .driver = { 1583 .name = "imx-uart", 1584 .owner = THIS_MODULE, 1585 .of_match_table = imx_uart_dt_ids, 1586 }, 1587 }; 1588 1589 static int __init imx_serial_init(void) 1590 { 1591 int ret; 1592 1593 pr_info("Serial: IMX driver\n"); 1594 1595 ret = uart_register_driver(&imx_reg); 1596 if (ret) 1597 return ret; 1598 1599 ret = platform_driver_register(&serial_imx_driver); 1600 if (ret != 0) 1601 uart_unregister_driver(&imx_reg); 1602 1603 return ret; 1604 } 1605 1606 static void __exit imx_serial_exit(void) 1607 { 1608 platform_driver_unregister(&serial_imx_driver); 1609 uart_unregister_driver(&imx_reg); 1610 } 1611 1612 module_init(imx_serial_init); 1613 module_exit(imx_serial_exit); 1614 1615 MODULE_AUTHOR("Sascha Hauer"); 1616 MODULE_DESCRIPTION("IMX generic serial port driver"); 1617 MODULE_LICENSE("GPL"); 1618 MODULE_ALIAS("platform:imx-uart"); 1619