1 /* 2 * Driver for Motorola IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * Copyright (C) 2009 emlix GmbH 10 * Author: Fabian Godehardt (added IrDA support for iMX) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 * [29-Mar-2005] Mike Lee 27 * Added hardware handshake 28 */ 29 30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31 #define SUPPORT_SYSRQ 32 #endif 33 34 #include <linux/module.h> 35 #include <linux/ioport.h> 36 #include <linux/init.h> 37 #include <linux/console.h> 38 #include <linux/sysrq.h> 39 #include <linux/platform_device.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/serial_core.h> 43 #include <linux/serial.h> 44 #include <linux/clk.h> 45 #include <linux/delay.h> 46 #include <linux/rational.h> 47 #include <linux/slab.h> 48 #include <linux/of.h> 49 #include <linux/of_device.h> 50 #include <linux/pinctrl/consumer.h> 51 52 #include <asm/io.h> 53 #include <asm/irq.h> 54 #include <mach/imx-uart.h> 55 56 /* Register definitions */ 57 #define URXD0 0x0 /* Receiver Register */ 58 #define URTX0 0x40 /* Transmitter Register */ 59 #define UCR1 0x80 /* Control Register 1 */ 60 #define UCR2 0x84 /* Control Register 2 */ 61 #define UCR3 0x88 /* Control Register 3 */ 62 #define UCR4 0x8c /* Control Register 4 */ 63 #define UFCR 0x90 /* FIFO Control Register */ 64 #define USR1 0x94 /* Status Register 1 */ 65 #define USR2 0x98 /* Status Register 2 */ 66 #define UESC 0x9c /* Escape Character Register */ 67 #define UTIM 0xa0 /* Escape Timer Register */ 68 #define UBIR 0xa4 /* BRM Incremental Register */ 69 #define UBMR 0xa8 /* BRM Modulator Register */ 70 #define UBRC 0xac /* Baud Rate Count Register */ 71 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 72 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 73 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 74 75 /* UART Control Register Bit Fields.*/ 76 #define URXD_CHARRDY (1<<15) 77 #define URXD_ERR (1<<14) 78 #define URXD_OVRRUN (1<<13) 79 #define URXD_FRMERR (1<<12) 80 #define URXD_BRK (1<<11) 81 #define URXD_PRERR (1<<10) 82 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 83 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 84 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 85 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 86 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 87 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 88 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 89 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 90 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 91 #define UCR1_SNDBRK (1<<4) /* Send break */ 92 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 93 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 94 #define UCR1_DOZE (1<<1) /* Doze */ 95 #define UCR1_UARTEN (1<<0) /* UART enabled */ 96 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 97 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 98 #define UCR2_CTSC (1<<13) /* CTS pin control */ 99 #define UCR2_CTS (1<<12) /* Clear to send */ 100 #define UCR2_ESCEN (1<<11) /* Escape enable */ 101 #define UCR2_PREN (1<<8) /* Parity enable */ 102 #define UCR2_PROE (1<<7) /* Parity odd/even */ 103 #define UCR2_STPB (1<<6) /* Stop */ 104 #define UCR2_WS (1<<5) /* Word size */ 105 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 106 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 107 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 108 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 109 #define UCR2_SRST (1<<0) /* SW reset */ 110 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 111 #define UCR3_PARERREN (1<<12) /* Parity enable */ 112 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 113 #define UCR3_DSR (1<<10) /* Data set ready */ 114 #define UCR3_DCD (1<<9) /* Data carrier detect */ 115 #define UCR3_RI (1<<8) /* Ring indicator */ 116 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 117 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 118 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 119 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 120 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 121 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 122 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 123 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 124 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 125 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 126 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 127 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 128 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 129 #define UCR4_IRSC (1<<5) /* IR special case */ 130 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 131 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 132 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 133 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 134 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 135 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 136 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 137 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 138 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 139 #define USR1_RTSS (1<<14) /* RTS pin status */ 140 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 141 #define USR1_RTSD (1<<12) /* RTS delta */ 142 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 143 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 144 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 145 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 146 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 147 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 148 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 149 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 150 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 151 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 152 #define USR2_IDLE (1<<12) /* Idle condition */ 153 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 154 #define USR2_WAKE (1<<7) /* Wake */ 155 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 156 #define USR2_TXDC (1<<3) /* Transmitter complete */ 157 #define USR2_BRCD (1<<2) /* Break condition */ 158 #define USR2_ORE (1<<1) /* Overrun error */ 159 #define USR2_RDR (1<<0) /* Recv data ready */ 160 #define UTS_FRCPERR (1<<13) /* Force parity error */ 161 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 162 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 163 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 164 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 165 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 166 #define UTS_SOFTRST (1<<0) /* Software reset */ 167 168 /* We've been assigned a range on the "Low-density serial ports" major */ 169 #define SERIAL_IMX_MAJOR 207 170 #define MINOR_START 16 171 #define DEV_NAME "ttymxc" 172 173 /* 174 * This determines how often we check the modem status signals 175 * for any change. They generally aren't connected to an IRQ 176 * so we have to poll them. We also check immediately before 177 * filling the TX fifo incase CTS has been dropped. 178 */ 179 #define MCTRL_TIMEOUT (250*HZ/1000) 180 181 #define DRIVER_NAME "IMX-uart" 182 183 #define UART_NR 8 184 185 /* i.mx21 type uart runs on all i.mx except i.mx1 */ 186 enum imx_uart_type { 187 IMX1_UART, 188 IMX21_UART, 189 }; 190 191 /* device type dependent stuff */ 192 struct imx_uart_data { 193 unsigned uts_reg; 194 enum imx_uart_type devtype; 195 }; 196 197 struct imx_port { 198 struct uart_port port; 199 struct timer_list timer; 200 unsigned int old_status; 201 int txirq,rxirq,rtsirq; 202 unsigned int have_rtscts:1; 203 unsigned int use_irda:1; 204 unsigned int irda_inv_rx:1; 205 unsigned int irda_inv_tx:1; 206 unsigned short trcv_delay; /* transceiver delay */ 207 struct clk *clk_ipg; 208 struct clk *clk_per; 209 struct imx_uart_data *devdata; 210 }; 211 212 struct imx_port_ucrs { 213 unsigned int ucr1; 214 unsigned int ucr2; 215 unsigned int ucr3; 216 }; 217 218 #ifdef CONFIG_IRDA 219 #define USE_IRDA(sport) ((sport)->use_irda) 220 #else 221 #define USE_IRDA(sport) (0) 222 #endif 223 224 static struct imx_uart_data imx_uart_devdata[] = { 225 [IMX1_UART] = { 226 .uts_reg = IMX1_UTS, 227 .devtype = IMX1_UART, 228 }, 229 [IMX21_UART] = { 230 .uts_reg = IMX21_UTS, 231 .devtype = IMX21_UART, 232 }, 233 }; 234 235 static struct platform_device_id imx_uart_devtype[] = { 236 { 237 .name = "imx1-uart", 238 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 239 }, { 240 .name = "imx21-uart", 241 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 242 }, { 243 /* sentinel */ 244 } 245 }; 246 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 247 248 static struct of_device_id imx_uart_dt_ids[] = { 249 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 250 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 251 { /* sentinel */ } 252 }; 253 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 254 255 static inline unsigned uts_reg(struct imx_port *sport) 256 { 257 return sport->devdata->uts_reg; 258 } 259 260 static inline int is_imx1_uart(struct imx_port *sport) 261 { 262 return sport->devdata->devtype == IMX1_UART; 263 } 264 265 static inline int is_imx21_uart(struct imx_port *sport) 266 { 267 return sport->devdata->devtype == IMX21_UART; 268 } 269 270 /* 271 * Save and restore functions for UCR1, UCR2 and UCR3 registers 272 */ 273 static void imx_port_ucrs_save(struct uart_port *port, 274 struct imx_port_ucrs *ucr) 275 { 276 /* save control registers */ 277 ucr->ucr1 = readl(port->membase + UCR1); 278 ucr->ucr2 = readl(port->membase + UCR2); 279 ucr->ucr3 = readl(port->membase + UCR3); 280 } 281 282 static void imx_port_ucrs_restore(struct uart_port *port, 283 struct imx_port_ucrs *ucr) 284 { 285 /* restore control registers */ 286 writel(ucr->ucr1, port->membase + UCR1); 287 writel(ucr->ucr2, port->membase + UCR2); 288 writel(ucr->ucr3, port->membase + UCR3); 289 } 290 291 /* 292 * Handle any change of modem status signal since we were last called. 293 */ 294 static void imx_mctrl_check(struct imx_port *sport) 295 { 296 unsigned int status, changed; 297 298 status = sport->port.ops->get_mctrl(&sport->port); 299 changed = status ^ sport->old_status; 300 301 if (changed == 0) 302 return; 303 304 sport->old_status = status; 305 306 if (changed & TIOCM_RI) 307 sport->port.icount.rng++; 308 if (changed & TIOCM_DSR) 309 sport->port.icount.dsr++; 310 if (changed & TIOCM_CAR) 311 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 312 if (changed & TIOCM_CTS) 313 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 314 315 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 316 } 317 318 /* 319 * This is our per-port timeout handler, for checking the 320 * modem status signals. 321 */ 322 static void imx_timeout(unsigned long data) 323 { 324 struct imx_port *sport = (struct imx_port *)data; 325 unsigned long flags; 326 327 if (sport->port.state) { 328 spin_lock_irqsave(&sport->port.lock, flags); 329 imx_mctrl_check(sport); 330 spin_unlock_irqrestore(&sport->port.lock, flags); 331 332 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 333 } 334 } 335 336 /* 337 * interrupts disabled on entry 338 */ 339 static void imx_stop_tx(struct uart_port *port) 340 { 341 struct imx_port *sport = (struct imx_port *)port; 342 unsigned long temp; 343 344 if (USE_IRDA(sport)) { 345 /* half duplex - wait for end of transmission */ 346 int n = 256; 347 while ((--n > 0) && 348 !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 349 udelay(5); 350 barrier(); 351 } 352 /* 353 * irda transceiver - wait a bit more to avoid 354 * cutoff, hardware dependent 355 */ 356 udelay(sport->trcv_delay); 357 358 /* 359 * half duplex - reactivate receive mode, 360 * flush receive pipe echo crap 361 */ 362 if (readl(sport->port.membase + USR2) & USR2_TXDC) { 363 temp = readl(sport->port.membase + UCR1); 364 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 365 writel(temp, sport->port.membase + UCR1); 366 367 temp = readl(sport->port.membase + UCR4); 368 temp &= ~(UCR4_TCEN); 369 writel(temp, sport->port.membase + UCR4); 370 371 while (readl(sport->port.membase + URXD0) & 372 URXD_CHARRDY) 373 barrier(); 374 375 temp = readl(sport->port.membase + UCR1); 376 temp |= UCR1_RRDYEN; 377 writel(temp, sport->port.membase + UCR1); 378 379 temp = readl(sport->port.membase + UCR4); 380 temp |= UCR4_DREN; 381 writel(temp, sport->port.membase + UCR4); 382 } 383 return; 384 } 385 386 temp = readl(sport->port.membase + UCR1); 387 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 388 } 389 390 /* 391 * interrupts disabled on entry 392 */ 393 static void imx_stop_rx(struct uart_port *port) 394 { 395 struct imx_port *sport = (struct imx_port *)port; 396 unsigned long temp; 397 398 temp = readl(sport->port.membase + UCR2); 399 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2); 400 } 401 402 /* 403 * Set the modem control timer to fire immediately. 404 */ 405 static void imx_enable_ms(struct uart_port *port) 406 { 407 struct imx_port *sport = (struct imx_port *)port; 408 409 mod_timer(&sport->timer, jiffies); 410 } 411 412 static inline void imx_transmit_buffer(struct imx_port *sport) 413 { 414 struct circ_buf *xmit = &sport->port.state->xmit; 415 416 while (!uart_circ_empty(xmit) && 417 !(readl(sport->port.membase + uts_reg(sport)) 418 & UTS_TXFULL)) { 419 /* send xmit->buf[xmit->tail] 420 * out the port here */ 421 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 422 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 423 sport->port.icount.tx++; 424 } 425 426 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 427 uart_write_wakeup(&sport->port); 428 429 if (uart_circ_empty(xmit)) 430 imx_stop_tx(&sport->port); 431 } 432 433 /* 434 * interrupts disabled on entry 435 */ 436 static void imx_start_tx(struct uart_port *port) 437 { 438 struct imx_port *sport = (struct imx_port *)port; 439 unsigned long temp; 440 441 if (USE_IRDA(sport)) { 442 /* half duplex in IrDA mode; have to disable receive mode */ 443 temp = readl(sport->port.membase + UCR4); 444 temp &= ~(UCR4_DREN); 445 writel(temp, sport->port.membase + UCR4); 446 447 temp = readl(sport->port.membase + UCR1); 448 temp &= ~(UCR1_RRDYEN); 449 writel(temp, sport->port.membase + UCR1); 450 } 451 452 temp = readl(sport->port.membase + UCR1); 453 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 454 455 if (USE_IRDA(sport)) { 456 temp = readl(sport->port.membase + UCR1); 457 temp |= UCR1_TRDYEN; 458 writel(temp, sport->port.membase + UCR1); 459 460 temp = readl(sport->port.membase + UCR4); 461 temp |= UCR4_TCEN; 462 writel(temp, sport->port.membase + UCR4); 463 } 464 465 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) 466 imx_transmit_buffer(sport); 467 } 468 469 static irqreturn_t imx_rtsint(int irq, void *dev_id) 470 { 471 struct imx_port *sport = dev_id; 472 unsigned int val; 473 unsigned long flags; 474 475 spin_lock_irqsave(&sport->port.lock, flags); 476 477 writel(USR1_RTSD, sport->port.membase + USR1); 478 val = readl(sport->port.membase + USR1) & USR1_RTSS; 479 uart_handle_cts_change(&sport->port, !!val); 480 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 481 482 spin_unlock_irqrestore(&sport->port.lock, flags); 483 return IRQ_HANDLED; 484 } 485 486 static irqreturn_t imx_txint(int irq, void *dev_id) 487 { 488 struct imx_port *sport = dev_id; 489 struct circ_buf *xmit = &sport->port.state->xmit; 490 unsigned long flags; 491 492 spin_lock_irqsave(&sport->port.lock,flags); 493 if (sport->port.x_char) 494 { 495 /* Send next char */ 496 writel(sport->port.x_char, sport->port.membase + URTX0); 497 goto out; 498 } 499 500 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 501 imx_stop_tx(&sport->port); 502 goto out; 503 } 504 505 imx_transmit_buffer(sport); 506 507 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 508 uart_write_wakeup(&sport->port); 509 510 out: 511 spin_unlock_irqrestore(&sport->port.lock,flags); 512 return IRQ_HANDLED; 513 } 514 515 static irqreturn_t imx_rxint(int irq, void *dev_id) 516 { 517 struct imx_port *sport = dev_id; 518 unsigned int rx,flg,ignored = 0; 519 struct tty_struct *tty = sport->port.state->port.tty; 520 unsigned long flags, temp; 521 522 spin_lock_irqsave(&sport->port.lock,flags); 523 524 while (readl(sport->port.membase + USR2) & USR2_RDR) { 525 flg = TTY_NORMAL; 526 sport->port.icount.rx++; 527 528 rx = readl(sport->port.membase + URXD0); 529 530 temp = readl(sport->port.membase + USR2); 531 if (temp & USR2_BRCD) { 532 writel(USR2_BRCD, sport->port.membase + USR2); 533 if (uart_handle_break(&sport->port)) 534 continue; 535 } 536 537 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 538 continue; 539 540 if (unlikely(rx & URXD_ERR)) { 541 if (rx & URXD_BRK) 542 sport->port.icount.brk++; 543 else if (rx & URXD_PRERR) 544 sport->port.icount.parity++; 545 else if (rx & URXD_FRMERR) 546 sport->port.icount.frame++; 547 if (rx & URXD_OVRRUN) 548 sport->port.icount.overrun++; 549 550 if (rx & sport->port.ignore_status_mask) { 551 if (++ignored > 100) 552 goto out; 553 continue; 554 } 555 556 rx &= sport->port.read_status_mask; 557 558 if (rx & URXD_BRK) 559 flg = TTY_BREAK; 560 else if (rx & URXD_PRERR) 561 flg = TTY_PARITY; 562 else if (rx & URXD_FRMERR) 563 flg = TTY_FRAME; 564 if (rx & URXD_OVRRUN) 565 flg = TTY_OVERRUN; 566 567 #ifdef SUPPORT_SYSRQ 568 sport->port.sysrq = 0; 569 #endif 570 } 571 572 tty_insert_flip_char(tty, rx, flg); 573 } 574 575 out: 576 spin_unlock_irqrestore(&sport->port.lock,flags); 577 tty_flip_buffer_push(tty); 578 return IRQ_HANDLED; 579 } 580 581 static irqreturn_t imx_int(int irq, void *dev_id) 582 { 583 struct imx_port *sport = dev_id; 584 unsigned int sts; 585 586 sts = readl(sport->port.membase + USR1); 587 588 if (sts & USR1_RRDY) 589 imx_rxint(irq, dev_id); 590 591 if (sts & USR1_TRDY && 592 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 593 imx_txint(irq, dev_id); 594 595 if (sts & USR1_RTSD) 596 imx_rtsint(irq, dev_id); 597 598 if (sts & USR1_AWAKE) 599 writel(USR1_AWAKE, sport->port.membase + USR1); 600 601 return IRQ_HANDLED; 602 } 603 604 /* 605 * Return TIOCSER_TEMT when transmitter is not busy. 606 */ 607 static unsigned int imx_tx_empty(struct uart_port *port) 608 { 609 struct imx_port *sport = (struct imx_port *)port; 610 611 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 612 } 613 614 /* 615 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 616 */ 617 static unsigned int imx_get_mctrl(struct uart_port *port) 618 { 619 struct imx_port *sport = (struct imx_port *)port; 620 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 621 622 if (readl(sport->port.membase + USR1) & USR1_RTSS) 623 tmp |= TIOCM_CTS; 624 625 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 626 tmp |= TIOCM_RTS; 627 628 return tmp; 629 } 630 631 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 632 { 633 struct imx_port *sport = (struct imx_port *)port; 634 unsigned long temp; 635 636 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; 637 638 if (mctrl & TIOCM_RTS) 639 temp |= UCR2_CTS; 640 641 writel(temp, sport->port.membase + UCR2); 642 } 643 644 /* 645 * Interrupts always disabled. 646 */ 647 static void imx_break_ctl(struct uart_port *port, int break_state) 648 { 649 struct imx_port *sport = (struct imx_port *)port; 650 unsigned long flags, temp; 651 652 spin_lock_irqsave(&sport->port.lock, flags); 653 654 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 655 656 if ( break_state != 0 ) 657 temp |= UCR1_SNDBRK; 658 659 writel(temp, sport->port.membase + UCR1); 660 661 spin_unlock_irqrestore(&sport->port.lock, flags); 662 } 663 664 #define TXTL 2 /* reset default */ 665 #define RXTL 1 /* reset default */ 666 667 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 668 { 669 unsigned int val; 670 unsigned int ufcr_rfdiv; 671 672 /* set receiver / transmitter trigger level. 673 * RFDIV is set such way to satisfy requested uartclk value 674 */ 675 val = TXTL << 10 | RXTL; 676 ufcr_rfdiv = (clk_get_rate(sport->clk_per) + sport->port.uartclk / 2) 677 / sport->port.uartclk; 678 679 if(!ufcr_rfdiv) 680 ufcr_rfdiv = 1; 681 682 val |= UFCR_RFDIV_REG(ufcr_rfdiv); 683 684 writel(val, sport->port.membase + UFCR); 685 686 return 0; 687 } 688 689 /* half the RX buffer size */ 690 #define CTSTL 16 691 692 static int imx_startup(struct uart_port *port) 693 { 694 struct imx_port *sport = (struct imx_port *)port; 695 int retval; 696 unsigned long flags, temp; 697 698 imx_setup_ufcr(sport, 0); 699 700 /* disable the DREN bit (Data Ready interrupt enable) before 701 * requesting IRQs 702 */ 703 temp = readl(sport->port.membase + UCR4); 704 705 if (USE_IRDA(sport)) 706 temp |= UCR4_IRSC; 707 708 /* set the trigger level for CTS */ 709 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF); 710 temp |= CTSTL<< UCR4_CTSTL_SHF; 711 712 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 713 714 if (USE_IRDA(sport)) { 715 /* reset fifo's and state machines */ 716 int i = 100; 717 temp = readl(sport->port.membase + UCR2); 718 temp &= ~UCR2_SRST; 719 writel(temp, sport->port.membase + UCR2); 720 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && 721 (--i > 0)) { 722 udelay(1); 723 } 724 } 725 726 /* 727 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 728 * chips only have one interrupt. 729 */ 730 if (sport->txirq > 0) { 731 retval = request_irq(sport->rxirq, imx_rxint, 0, 732 DRIVER_NAME, sport); 733 if (retval) 734 goto error_out1; 735 736 retval = request_irq(sport->txirq, imx_txint, 0, 737 DRIVER_NAME, sport); 738 if (retval) 739 goto error_out2; 740 741 /* do not use RTS IRQ on IrDA */ 742 if (!USE_IRDA(sport)) { 743 retval = request_irq(sport->rtsirq, imx_rtsint, 0, 744 DRIVER_NAME, sport); 745 if (retval) 746 goto error_out3; 747 } 748 } else { 749 retval = request_irq(sport->port.irq, imx_int, 0, 750 DRIVER_NAME, sport); 751 if (retval) { 752 free_irq(sport->port.irq, sport); 753 goto error_out1; 754 } 755 } 756 757 /* 758 * Finally, clear and enable interrupts 759 */ 760 writel(USR1_RTSD, sport->port.membase + USR1); 761 762 temp = readl(sport->port.membase + UCR1); 763 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 764 765 if (USE_IRDA(sport)) { 766 temp |= UCR1_IREN; 767 temp &= ~(UCR1_RTSDEN); 768 } 769 770 writel(temp, sport->port.membase + UCR1); 771 772 temp = readl(sport->port.membase + UCR2); 773 temp |= (UCR2_RXEN | UCR2_TXEN); 774 writel(temp, sport->port.membase + UCR2); 775 776 if (USE_IRDA(sport)) { 777 /* clear RX-FIFO */ 778 int i = 64; 779 while ((--i > 0) && 780 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { 781 barrier(); 782 } 783 } 784 785 if (is_imx21_uart(sport)) { 786 temp = readl(sport->port.membase + UCR3); 787 temp |= IMX21_UCR3_RXDMUXSEL; 788 writel(temp, sport->port.membase + UCR3); 789 } 790 791 if (USE_IRDA(sport)) { 792 temp = readl(sport->port.membase + UCR4); 793 if (sport->irda_inv_rx) 794 temp |= UCR4_INVR; 795 else 796 temp &= ~(UCR4_INVR); 797 writel(temp | UCR4_DREN, sport->port.membase + UCR4); 798 799 temp = readl(sport->port.membase + UCR3); 800 if (sport->irda_inv_tx) 801 temp |= UCR3_INVT; 802 else 803 temp &= ~(UCR3_INVT); 804 writel(temp, sport->port.membase + UCR3); 805 } 806 807 /* 808 * Enable modem status interrupts 809 */ 810 spin_lock_irqsave(&sport->port.lock,flags); 811 imx_enable_ms(&sport->port); 812 spin_unlock_irqrestore(&sport->port.lock,flags); 813 814 if (USE_IRDA(sport)) { 815 struct imxuart_platform_data *pdata; 816 pdata = sport->port.dev->platform_data; 817 sport->irda_inv_rx = pdata->irda_inv_rx; 818 sport->irda_inv_tx = pdata->irda_inv_tx; 819 sport->trcv_delay = pdata->transceiver_delay; 820 if (pdata->irda_enable) 821 pdata->irda_enable(1); 822 } 823 824 return 0; 825 826 error_out3: 827 if (sport->txirq) 828 free_irq(sport->txirq, sport); 829 error_out2: 830 if (sport->rxirq) 831 free_irq(sport->rxirq, sport); 832 error_out1: 833 return retval; 834 } 835 836 static void imx_shutdown(struct uart_port *port) 837 { 838 struct imx_port *sport = (struct imx_port *)port; 839 unsigned long temp; 840 841 temp = readl(sport->port.membase + UCR2); 842 temp &= ~(UCR2_TXEN); 843 writel(temp, sport->port.membase + UCR2); 844 845 if (USE_IRDA(sport)) { 846 struct imxuart_platform_data *pdata; 847 pdata = sport->port.dev->platform_data; 848 if (pdata->irda_enable) 849 pdata->irda_enable(0); 850 } 851 852 /* 853 * Stop our timer. 854 */ 855 del_timer_sync(&sport->timer); 856 857 /* 858 * Free the interrupts 859 */ 860 if (sport->txirq > 0) { 861 if (!USE_IRDA(sport)) 862 free_irq(sport->rtsirq, sport); 863 free_irq(sport->txirq, sport); 864 free_irq(sport->rxirq, sport); 865 } else 866 free_irq(sport->port.irq, sport); 867 868 /* 869 * Disable all interrupts, port and break condition. 870 */ 871 872 temp = readl(sport->port.membase + UCR1); 873 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 874 if (USE_IRDA(sport)) 875 temp &= ~(UCR1_IREN); 876 877 writel(temp, sport->port.membase + UCR1); 878 } 879 880 static void 881 imx_set_termios(struct uart_port *port, struct ktermios *termios, 882 struct ktermios *old) 883 { 884 struct imx_port *sport = (struct imx_port *)port; 885 unsigned long flags; 886 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 887 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 888 unsigned int div, ufcr; 889 unsigned long num, denom; 890 uint64_t tdiv64; 891 892 /* 893 * If we don't support modem control lines, don't allow 894 * these to be set. 895 */ 896 if (0) { 897 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 898 termios->c_cflag |= CLOCAL; 899 } 900 901 /* 902 * We only support CS7 and CS8. 903 */ 904 while ((termios->c_cflag & CSIZE) != CS7 && 905 (termios->c_cflag & CSIZE) != CS8) { 906 termios->c_cflag &= ~CSIZE; 907 termios->c_cflag |= old_csize; 908 old_csize = CS8; 909 } 910 911 if ((termios->c_cflag & CSIZE) == CS8) 912 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 913 else 914 ucr2 = UCR2_SRST | UCR2_IRTS; 915 916 if (termios->c_cflag & CRTSCTS) { 917 if( sport->have_rtscts ) { 918 ucr2 &= ~UCR2_IRTS; 919 ucr2 |= UCR2_CTSC; 920 } else { 921 termios->c_cflag &= ~CRTSCTS; 922 } 923 } 924 925 if (termios->c_cflag & CSTOPB) 926 ucr2 |= UCR2_STPB; 927 if (termios->c_cflag & PARENB) { 928 ucr2 |= UCR2_PREN; 929 if (termios->c_cflag & PARODD) 930 ucr2 |= UCR2_PROE; 931 } 932 933 del_timer_sync(&sport->timer); 934 935 /* 936 * Ask the core to calculate the divisor for us. 937 */ 938 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 939 quot = uart_get_divisor(port, baud); 940 941 spin_lock_irqsave(&sport->port.lock, flags); 942 943 sport->port.read_status_mask = 0; 944 if (termios->c_iflag & INPCK) 945 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 946 if (termios->c_iflag & (BRKINT | PARMRK)) 947 sport->port.read_status_mask |= URXD_BRK; 948 949 /* 950 * Characters to ignore 951 */ 952 sport->port.ignore_status_mask = 0; 953 if (termios->c_iflag & IGNPAR) 954 sport->port.ignore_status_mask |= URXD_PRERR; 955 if (termios->c_iflag & IGNBRK) { 956 sport->port.ignore_status_mask |= URXD_BRK; 957 /* 958 * If we're ignoring parity and break indicators, 959 * ignore overruns too (for real raw support). 960 */ 961 if (termios->c_iflag & IGNPAR) 962 sport->port.ignore_status_mask |= URXD_OVRRUN; 963 } 964 965 /* 966 * Update the per-port timeout. 967 */ 968 uart_update_timeout(port, termios->c_cflag, baud); 969 970 /* 971 * disable interrupts and drain transmitter 972 */ 973 old_ucr1 = readl(sport->port.membase + UCR1); 974 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 975 sport->port.membase + UCR1); 976 977 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC)) 978 barrier(); 979 980 /* then, disable everything */ 981 old_txrxen = readl(sport->port.membase + UCR2); 982 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN), 983 sport->port.membase + UCR2); 984 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 985 986 if (USE_IRDA(sport)) { 987 /* 988 * use maximum available submodule frequency to 989 * avoid missing short pulses due to low sampling rate 990 */ 991 div = 1; 992 } else { 993 div = sport->port.uartclk / (baud * 16); 994 if (div > 7) 995 div = 7; 996 if (!div) 997 div = 1; 998 } 999 1000 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1001 1 << 16, 1 << 16, &num, &denom); 1002 1003 tdiv64 = sport->port.uartclk; 1004 tdiv64 *= num; 1005 do_div(tdiv64, denom * 16 * div); 1006 tty_termios_encode_baud_rate(termios, 1007 (speed_t)tdiv64, (speed_t)tdiv64); 1008 1009 num -= 1; 1010 denom -= 1; 1011 1012 ufcr = readl(sport->port.membase + UFCR); 1013 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1014 writel(ufcr, sport->port.membase + UFCR); 1015 1016 writel(num, sport->port.membase + UBIR); 1017 writel(denom, sport->port.membase + UBMR); 1018 1019 if (is_imx21_uart(sport)) 1020 writel(sport->port.uartclk / div / 1000, 1021 sport->port.membase + IMX21_ONEMS); 1022 1023 writel(old_ucr1, sport->port.membase + UCR1); 1024 1025 /* set the parity, stop bits and data size */ 1026 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1027 1028 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1029 imx_enable_ms(&sport->port); 1030 1031 spin_unlock_irqrestore(&sport->port.lock, flags); 1032 } 1033 1034 static const char *imx_type(struct uart_port *port) 1035 { 1036 struct imx_port *sport = (struct imx_port *)port; 1037 1038 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1039 } 1040 1041 /* 1042 * Release the memory region(s) being used by 'port'. 1043 */ 1044 static void imx_release_port(struct uart_port *port) 1045 { 1046 struct platform_device *pdev = to_platform_device(port->dev); 1047 struct resource *mmres; 1048 1049 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1050 release_mem_region(mmres->start, resource_size(mmres)); 1051 } 1052 1053 /* 1054 * Request the memory region(s) being used by 'port'. 1055 */ 1056 static int imx_request_port(struct uart_port *port) 1057 { 1058 struct platform_device *pdev = to_platform_device(port->dev); 1059 struct resource *mmres; 1060 void *ret; 1061 1062 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1063 if (!mmres) 1064 return -ENODEV; 1065 1066 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart"); 1067 1068 return ret ? 0 : -EBUSY; 1069 } 1070 1071 /* 1072 * Configure/autoconfigure the port. 1073 */ 1074 static void imx_config_port(struct uart_port *port, int flags) 1075 { 1076 struct imx_port *sport = (struct imx_port *)port; 1077 1078 if (flags & UART_CONFIG_TYPE && 1079 imx_request_port(&sport->port) == 0) 1080 sport->port.type = PORT_IMX; 1081 } 1082 1083 /* 1084 * Verify the new serial_struct (for TIOCSSERIAL). 1085 * The only change we allow are to the flags and type, and 1086 * even then only between PORT_IMX and PORT_UNKNOWN 1087 */ 1088 static int 1089 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1090 { 1091 struct imx_port *sport = (struct imx_port *)port; 1092 int ret = 0; 1093 1094 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1095 ret = -EINVAL; 1096 if (sport->port.irq != ser->irq) 1097 ret = -EINVAL; 1098 if (ser->io_type != UPIO_MEM) 1099 ret = -EINVAL; 1100 if (sport->port.uartclk / 16 != ser->baud_base) 1101 ret = -EINVAL; 1102 if ((void *)sport->port.mapbase != ser->iomem_base) 1103 ret = -EINVAL; 1104 if (sport->port.iobase != ser->port) 1105 ret = -EINVAL; 1106 if (ser->hub6 != 0) 1107 ret = -EINVAL; 1108 return ret; 1109 } 1110 1111 #if defined(CONFIG_CONSOLE_POLL) 1112 static int imx_poll_get_char(struct uart_port *port) 1113 { 1114 struct imx_port_ucrs old_ucr; 1115 unsigned int status; 1116 unsigned char c; 1117 1118 /* save control registers */ 1119 imx_port_ucrs_save(port, &old_ucr); 1120 1121 /* disable interrupts */ 1122 writel(UCR1_UARTEN, port->membase + UCR1); 1123 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1124 port->membase + UCR2); 1125 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1126 port->membase + UCR3); 1127 1128 /* poll */ 1129 do { 1130 status = readl(port->membase + USR2); 1131 } while (~status & USR2_RDR); 1132 1133 /* read */ 1134 c = readl(port->membase + URXD0); 1135 1136 /* restore control registers */ 1137 imx_port_ucrs_restore(port, &old_ucr); 1138 1139 return c; 1140 } 1141 1142 static void imx_poll_put_char(struct uart_port *port, unsigned char c) 1143 { 1144 struct imx_port_ucrs old_ucr; 1145 unsigned int status; 1146 1147 /* save control registers */ 1148 imx_port_ucrs_save(port, &old_ucr); 1149 1150 /* disable interrupts */ 1151 writel(UCR1_UARTEN, port->membase + UCR1); 1152 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1153 port->membase + UCR2); 1154 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1155 port->membase + UCR3); 1156 1157 /* drain */ 1158 do { 1159 status = readl(port->membase + USR1); 1160 } while (~status & USR1_TRDY); 1161 1162 /* write */ 1163 writel(c, port->membase + URTX0); 1164 1165 /* flush */ 1166 do { 1167 status = readl(port->membase + USR2); 1168 } while (~status & USR2_TXDC); 1169 1170 /* restore control registers */ 1171 imx_port_ucrs_restore(port, &old_ucr); 1172 } 1173 #endif 1174 1175 static struct uart_ops imx_pops = { 1176 .tx_empty = imx_tx_empty, 1177 .set_mctrl = imx_set_mctrl, 1178 .get_mctrl = imx_get_mctrl, 1179 .stop_tx = imx_stop_tx, 1180 .start_tx = imx_start_tx, 1181 .stop_rx = imx_stop_rx, 1182 .enable_ms = imx_enable_ms, 1183 .break_ctl = imx_break_ctl, 1184 .startup = imx_startup, 1185 .shutdown = imx_shutdown, 1186 .set_termios = imx_set_termios, 1187 .type = imx_type, 1188 .release_port = imx_release_port, 1189 .request_port = imx_request_port, 1190 .config_port = imx_config_port, 1191 .verify_port = imx_verify_port, 1192 #if defined(CONFIG_CONSOLE_POLL) 1193 .poll_get_char = imx_poll_get_char, 1194 .poll_put_char = imx_poll_put_char, 1195 #endif 1196 }; 1197 1198 static struct imx_port *imx_ports[UART_NR]; 1199 1200 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1201 static void imx_console_putchar(struct uart_port *port, int ch) 1202 { 1203 struct imx_port *sport = (struct imx_port *)port; 1204 1205 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1206 barrier(); 1207 1208 writel(ch, sport->port.membase + URTX0); 1209 } 1210 1211 /* 1212 * Interrupts are disabled on entering 1213 */ 1214 static void 1215 imx_console_write(struct console *co, const char *s, unsigned int count) 1216 { 1217 struct imx_port *sport = imx_ports[co->index]; 1218 struct imx_port_ucrs old_ucr; 1219 unsigned int ucr1; 1220 1221 /* 1222 * First, save UCR1/2/3 and then disable interrupts 1223 */ 1224 imx_port_ucrs_save(&sport->port, &old_ucr); 1225 ucr1 = old_ucr.ucr1; 1226 1227 if (is_imx1_uart(sport)) 1228 ucr1 |= IMX1_UCR1_UARTCLKEN; 1229 ucr1 |= UCR1_UARTEN; 1230 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1231 1232 writel(ucr1, sport->port.membase + UCR1); 1233 1234 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1235 1236 uart_console_write(&sport->port, s, count, imx_console_putchar); 1237 1238 /* 1239 * Finally, wait for transmitter to become empty 1240 * and restore UCR1/2/3 1241 */ 1242 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1243 1244 imx_port_ucrs_restore(&sport->port, &old_ucr); 1245 } 1246 1247 /* 1248 * If the port was already initialised (eg, by a boot loader), 1249 * try to determine the current setup. 1250 */ 1251 static void __init 1252 imx_console_get_options(struct imx_port *sport, int *baud, 1253 int *parity, int *bits) 1254 { 1255 1256 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1257 /* ok, the port was enabled */ 1258 unsigned int ucr2, ubir,ubmr, uartclk; 1259 unsigned int baud_raw; 1260 unsigned int ucfr_rfdiv; 1261 1262 ucr2 = readl(sport->port.membase + UCR2); 1263 1264 *parity = 'n'; 1265 if (ucr2 & UCR2_PREN) { 1266 if (ucr2 & UCR2_PROE) 1267 *parity = 'o'; 1268 else 1269 *parity = 'e'; 1270 } 1271 1272 if (ucr2 & UCR2_WS) 1273 *bits = 8; 1274 else 1275 *bits = 7; 1276 1277 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1278 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1279 1280 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1281 if (ucfr_rfdiv == 6) 1282 ucfr_rfdiv = 7; 1283 else 1284 ucfr_rfdiv = 6 - ucfr_rfdiv; 1285 1286 uartclk = clk_get_rate(sport->clk_per); 1287 uartclk /= ucfr_rfdiv; 1288 1289 { /* 1290 * The next code provides exact computation of 1291 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1292 * without need of float support or long long division, 1293 * which would be required to prevent 32bit arithmetic overflow 1294 */ 1295 unsigned int mul = ubir + 1; 1296 unsigned int div = 16 * (ubmr + 1); 1297 unsigned int rem = uartclk % div; 1298 1299 baud_raw = (uartclk / div) * mul; 1300 baud_raw += (rem * mul + div / 2) / div; 1301 *baud = (baud_raw + 50) / 100 * 100; 1302 } 1303 1304 if(*baud != baud_raw) 1305 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n", 1306 baud_raw, *baud); 1307 } 1308 } 1309 1310 static int __init 1311 imx_console_setup(struct console *co, char *options) 1312 { 1313 struct imx_port *sport; 1314 int baud = 9600; 1315 int bits = 8; 1316 int parity = 'n'; 1317 int flow = 'n'; 1318 1319 /* 1320 * Check whether an invalid uart number has been specified, and 1321 * if so, search for the first available port that does have 1322 * console support. 1323 */ 1324 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1325 co->index = 0; 1326 sport = imx_ports[co->index]; 1327 if(sport == NULL) 1328 return -ENODEV; 1329 1330 if (options) 1331 uart_parse_options(options, &baud, &parity, &bits, &flow); 1332 else 1333 imx_console_get_options(sport, &baud, &parity, &bits); 1334 1335 imx_setup_ufcr(sport, 0); 1336 1337 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1338 } 1339 1340 static struct uart_driver imx_reg; 1341 static struct console imx_console = { 1342 .name = DEV_NAME, 1343 .write = imx_console_write, 1344 .device = uart_console_device, 1345 .setup = imx_console_setup, 1346 .flags = CON_PRINTBUFFER, 1347 .index = -1, 1348 .data = &imx_reg, 1349 }; 1350 1351 #define IMX_CONSOLE &imx_console 1352 #else 1353 #define IMX_CONSOLE NULL 1354 #endif 1355 1356 static struct uart_driver imx_reg = { 1357 .owner = THIS_MODULE, 1358 .driver_name = DRIVER_NAME, 1359 .dev_name = DEV_NAME, 1360 .major = SERIAL_IMX_MAJOR, 1361 .minor = MINOR_START, 1362 .nr = ARRAY_SIZE(imx_ports), 1363 .cons = IMX_CONSOLE, 1364 }; 1365 1366 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1367 { 1368 struct imx_port *sport = platform_get_drvdata(dev); 1369 unsigned int val; 1370 1371 /* enable wakeup from i.MX UART */ 1372 val = readl(sport->port.membase + UCR3); 1373 val |= UCR3_AWAKEN; 1374 writel(val, sport->port.membase + UCR3); 1375 1376 if (sport) 1377 uart_suspend_port(&imx_reg, &sport->port); 1378 1379 return 0; 1380 } 1381 1382 static int serial_imx_resume(struct platform_device *dev) 1383 { 1384 struct imx_port *sport = platform_get_drvdata(dev); 1385 unsigned int val; 1386 1387 /* disable wakeup from i.MX UART */ 1388 val = readl(sport->port.membase + UCR3); 1389 val &= ~UCR3_AWAKEN; 1390 writel(val, sport->port.membase + UCR3); 1391 1392 if (sport) 1393 uart_resume_port(&imx_reg, &sport->port); 1394 1395 return 0; 1396 } 1397 1398 #ifdef CONFIG_OF 1399 /* 1400 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 1401 * could successfully get all information from dt or a negative errno. 1402 */ 1403 static int serial_imx_probe_dt(struct imx_port *sport, 1404 struct platform_device *pdev) 1405 { 1406 struct device_node *np = pdev->dev.of_node; 1407 const struct of_device_id *of_id = 1408 of_match_device(imx_uart_dt_ids, &pdev->dev); 1409 int ret; 1410 1411 if (!np) 1412 /* no device tree device */ 1413 return 1; 1414 1415 ret = of_alias_get_id(np, "serial"); 1416 if (ret < 0) { 1417 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1418 return ret; 1419 } 1420 sport->port.line = ret; 1421 1422 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1423 sport->have_rtscts = 1; 1424 1425 if (of_get_property(np, "fsl,irda-mode", NULL)) 1426 sport->use_irda = 1; 1427 1428 sport->devdata = of_id->data; 1429 1430 return 0; 1431 } 1432 #else 1433 static inline int serial_imx_probe_dt(struct imx_port *sport, 1434 struct platform_device *pdev) 1435 { 1436 return 1; 1437 } 1438 #endif 1439 1440 static void serial_imx_probe_pdata(struct imx_port *sport, 1441 struct platform_device *pdev) 1442 { 1443 struct imxuart_platform_data *pdata = pdev->dev.platform_data; 1444 1445 sport->port.line = pdev->id; 1446 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 1447 1448 if (!pdata) 1449 return; 1450 1451 if (pdata->flags & IMXUART_HAVE_RTSCTS) 1452 sport->have_rtscts = 1; 1453 1454 if (pdata->flags & IMXUART_IRDA) 1455 sport->use_irda = 1; 1456 } 1457 1458 static int serial_imx_probe(struct platform_device *pdev) 1459 { 1460 struct imx_port *sport; 1461 struct imxuart_platform_data *pdata; 1462 void __iomem *base; 1463 int ret = 0; 1464 struct resource *res; 1465 struct pinctrl *pinctrl; 1466 1467 sport = kzalloc(sizeof(*sport), GFP_KERNEL); 1468 if (!sport) 1469 return -ENOMEM; 1470 1471 ret = serial_imx_probe_dt(sport, pdev); 1472 if (ret > 0) 1473 serial_imx_probe_pdata(sport, pdev); 1474 else if (ret < 0) 1475 goto free; 1476 1477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1478 if (!res) { 1479 ret = -ENODEV; 1480 goto free; 1481 } 1482 1483 base = ioremap(res->start, PAGE_SIZE); 1484 if (!base) { 1485 ret = -ENOMEM; 1486 goto free; 1487 } 1488 1489 sport->port.dev = &pdev->dev; 1490 sport->port.mapbase = res->start; 1491 sport->port.membase = base; 1492 sport->port.type = PORT_IMX, 1493 sport->port.iotype = UPIO_MEM; 1494 sport->port.irq = platform_get_irq(pdev, 0); 1495 sport->rxirq = platform_get_irq(pdev, 0); 1496 sport->txirq = platform_get_irq(pdev, 1); 1497 sport->rtsirq = platform_get_irq(pdev, 2); 1498 sport->port.fifosize = 32; 1499 sport->port.ops = &imx_pops; 1500 sport->port.flags = UPF_BOOT_AUTOCONF; 1501 init_timer(&sport->timer); 1502 sport->timer.function = imx_timeout; 1503 sport->timer.data = (unsigned long)sport; 1504 1505 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 1506 if (IS_ERR(pinctrl)) { 1507 ret = PTR_ERR(pinctrl); 1508 goto unmap; 1509 } 1510 1511 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1512 if (IS_ERR(sport->clk_ipg)) { 1513 ret = PTR_ERR(sport->clk_ipg); 1514 goto unmap; 1515 } 1516 1517 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 1518 if (IS_ERR(sport->clk_per)) { 1519 ret = PTR_ERR(sport->clk_per); 1520 goto unmap; 1521 } 1522 1523 clk_prepare_enable(sport->clk_per); 1524 clk_prepare_enable(sport->clk_ipg); 1525 1526 sport->port.uartclk = clk_get_rate(sport->clk_per); 1527 1528 imx_ports[sport->port.line] = sport; 1529 1530 pdata = pdev->dev.platform_data; 1531 if (pdata && pdata->init) { 1532 ret = pdata->init(pdev); 1533 if (ret) 1534 goto clkput; 1535 } 1536 1537 ret = uart_add_one_port(&imx_reg, &sport->port); 1538 if (ret) 1539 goto deinit; 1540 platform_set_drvdata(pdev, &sport->port); 1541 1542 return 0; 1543 deinit: 1544 if (pdata && pdata->exit) 1545 pdata->exit(pdev); 1546 clkput: 1547 clk_disable_unprepare(sport->clk_per); 1548 clk_disable_unprepare(sport->clk_ipg); 1549 unmap: 1550 iounmap(sport->port.membase); 1551 free: 1552 kfree(sport); 1553 1554 return ret; 1555 } 1556 1557 static int serial_imx_remove(struct platform_device *pdev) 1558 { 1559 struct imxuart_platform_data *pdata; 1560 struct imx_port *sport = platform_get_drvdata(pdev); 1561 1562 pdata = pdev->dev.platform_data; 1563 1564 platform_set_drvdata(pdev, NULL); 1565 1566 uart_remove_one_port(&imx_reg, &sport->port); 1567 1568 clk_disable_unprepare(sport->clk_per); 1569 clk_disable_unprepare(sport->clk_ipg); 1570 1571 if (pdata && pdata->exit) 1572 pdata->exit(pdev); 1573 1574 iounmap(sport->port.membase); 1575 kfree(sport); 1576 1577 return 0; 1578 } 1579 1580 static struct platform_driver serial_imx_driver = { 1581 .probe = serial_imx_probe, 1582 .remove = serial_imx_remove, 1583 1584 .suspend = serial_imx_suspend, 1585 .resume = serial_imx_resume, 1586 .id_table = imx_uart_devtype, 1587 .driver = { 1588 .name = "imx-uart", 1589 .owner = THIS_MODULE, 1590 .of_match_table = imx_uart_dt_ids, 1591 }, 1592 }; 1593 1594 static int __init imx_serial_init(void) 1595 { 1596 int ret; 1597 1598 printk(KERN_INFO "Serial: IMX driver\n"); 1599 1600 ret = uart_register_driver(&imx_reg); 1601 if (ret) 1602 return ret; 1603 1604 ret = platform_driver_register(&serial_imx_driver); 1605 if (ret != 0) 1606 uart_unregister_driver(&imx_reg); 1607 1608 return ret; 1609 } 1610 1611 static void __exit imx_serial_exit(void) 1612 { 1613 platform_driver_unregister(&serial_imx_driver); 1614 uart_unregister_driver(&imx_reg); 1615 } 1616 1617 module_init(imx_serial_init); 1618 module_exit(imx_serial_exit); 1619 1620 MODULE_AUTHOR("Sascha Hauer"); 1621 MODULE_DESCRIPTION("IMX generic serial port driver"); 1622 MODULE_LICENSE("GPL"); 1623 MODULE_ALIAS("platform:imx-uart"); 1624