1 /* 2 * Driver for Motorola IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * Copyright (C) 2009 emlix GmbH 10 * Author: Fabian Godehardt (added IrDA support for iMX) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 * [29-Mar-2005] Mike Lee 27 * Added hardware handshake 28 */ 29 30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31 #define SUPPORT_SYSRQ 32 #endif 33 34 #include <linux/module.h> 35 #include <linux/ioport.h> 36 #include <linux/init.h> 37 #include <linux/console.h> 38 #include <linux/sysrq.h> 39 #include <linux/platform_device.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/serial_core.h> 43 #include <linux/serial.h> 44 #include <linux/clk.h> 45 #include <linux/delay.h> 46 #include <linux/rational.h> 47 #include <linux/slab.h> 48 #include <linux/of.h> 49 #include <linux/of_device.h> 50 #include <linux/io.h> 51 #include <linux/dma-mapping.h> 52 53 #include <asm/irq.h> 54 #include <linux/platform_data/serial-imx.h> 55 #include <linux/platform_data/dma-imx.h> 56 57 /* Register definitions */ 58 #define URXD0 0x0 /* Receiver Register */ 59 #define URTX0 0x40 /* Transmitter Register */ 60 #define UCR1 0x80 /* Control Register 1 */ 61 #define UCR2 0x84 /* Control Register 2 */ 62 #define UCR3 0x88 /* Control Register 3 */ 63 #define UCR4 0x8c /* Control Register 4 */ 64 #define UFCR 0x90 /* FIFO Control Register */ 65 #define USR1 0x94 /* Status Register 1 */ 66 #define USR2 0x98 /* Status Register 2 */ 67 #define UESC 0x9c /* Escape Character Register */ 68 #define UTIM 0xa0 /* Escape Timer Register */ 69 #define UBIR 0xa4 /* BRM Incremental Register */ 70 #define UBMR 0xa8 /* BRM Modulator Register */ 71 #define UBRC 0xac /* Baud Rate Count Register */ 72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 75 76 /* UART Control Register Bit Fields.*/ 77 #define URXD_DUMMY_READ (1<<16) 78 #define URXD_CHARRDY (1<<15) 79 #define URXD_ERR (1<<14) 80 #define URXD_OVRRUN (1<<13) 81 #define URXD_FRMERR (1<<12) 82 #define URXD_BRK (1<<11) 83 #define URXD_PRERR (1<<10) 84 #define URXD_RX_DATA (0xFF<<0) 85 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 86 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 87 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 88 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 89 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 90 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 91 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 92 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 93 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 94 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 95 #define UCR1_SNDBRK (1<<4) /* Send break */ 96 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 97 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 98 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 99 #define UCR1_DOZE (1<<1) /* Doze */ 100 #define UCR1_UARTEN (1<<0) /* UART enabled */ 101 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 102 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 103 #define UCR2_CTSC (1<<13) /* CTS pin control */ 104 #define UCR2_CTS (1<<12) /* Clear to send */ 105 #define UCR2_ESCEN (1<<11) /* Escape enable */ 106 #define UCR2_PREN (1<<8) /* Parity enable */ 107 #define UCR2_PROE (1<<7) /* Parity odd/even */ 108 #define UCR2_STPB (1<<6) /* Stop */ 109 #define UCR2_WS (1<<5) /* Word size */ 110 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 111 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 112 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 113 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 114 #define UCR2_SRST (1<<0) /* SW reset */ 115 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 116 #define UCR3_PARERREN (1<<12) /* Parity enable */ 117 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 118 #define UCR3_DSR (1<<10) /* Data set ready */ 119 #define UCR3_DCD (1<<9) /* Data carrier detect */ 120 #define UCR3_RI (1<<8) /* Ring indicator */ 121 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 122 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 123 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 124 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 125 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 126 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 127 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 128 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 129 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 130 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 131 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 132 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 133 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 134 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 135 #define UCR4_IRSC (1<<5) /* IR special case */ 136 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 137 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 138 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 139 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 140 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 141 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 142 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 143 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 144 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 145 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 146 #define USR1_RTSS (1<<14) /* RTS pin status */ 147 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 148 #define USR1_RTSD (1<<12) /* RTS delta */ 149 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 150 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 151 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 152 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 153 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 154 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 155 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 156 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 157 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 158 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 159 #define USR2_IDLE (1<<12) /* Idle condition */ 160 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 161 #define USR2_WAKE (1<<7) /* Wake */ 162 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 163 #define USR2_TXDC (1<<3) /* Transmitter complete */ 164 #define USR2_BRCD (1<<2) /* Break condition */ 165 #define USR2_ORE (1<<1) /* Overrun error */ 166 #define USR2_RDR (1<<0) /* Recv data ready */ 167 #define UTS_FRCPERR (1<<13) /* Force parity error */ 168 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 169 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 170 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 171 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 172 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 173 #define UTS_SOFTRST (1<<0) /* Software reset */ 174 175 /* We've been assigned a range on the "Low-density serial ports" major */ 176 #define SERIAL_IMX_MAJOR 207 177 #define MINOR_START 16 178 #define DEV_NAME "ttymxc" 179 180 /* 181 * This determines how often we check the modem status signals 182 * for any change. They generally aren't connected to an IRQ 183 * so we have to poll them. We also check immediately before 184 * filling the TX fifo incase CTS has been dropped. 185 */ 186 #define MCTRL_TIMEOUT (250*HZ/1000) 187 188 #define DRIVER_NAME "IMX-uart" 189 190 #define UART_NR 8 191 192 /* i.mx21 type uart runs on all i.mx except i.mx1 */ 193 enum imx_uart_type { 194 IMX1_UART, 195 IMX21_UART, 196 IMX6Q_UART, 197 }; 198 199 /* device type dependent stuff */ 200 struct imx_uart_data { 201 unsigned uts_reg; 202 enum imx_uart_type devtype; 203 }; 204 205 struct imx_port { 206 struct uart_port port; 207 struct timer_list timer; 208 unsigned int old_status; 209 int txirq, rxirq, rtsirq; 210 unsigned int have_rtscts:1; 211 unsigned int dte_mode:1; 212 unsigned int use_irda:1; 213 unsigned int irda_inv_rx:1; 214 unsigned int irda_inv_tx:1; 215 unsigned short trcv_delay; /* transceiver delay */ 216 struct clk *clk_ipg; 217 struct clk *clk_per; 218 const struct imx_uart_data *devdata; 219 220 /* DMA fields */ 221 unsigned int dma_is_inited:1; 222 unsigned int dma_is_enabled:1; 223 unsigned int dma_is_rxing:1; 224 unsigned int dma_is_txing:1; 225 struct dma_chan *dma_chan_rx, *dma_chan_tx; 226 struct scatterlist rx_sgl, tx_sgl[2]; 227 void *rx_buf; 228 unsigned int tx_bytes; 229 unsigned int dma_tx_nents; 230 wait_queue_head_t dma_wait; 231 }; 232 233 struct imx_port_ucrs { 234 unsigned int ucr1; 235 unsigned int ucr2; 236 unsigned int ucr3; 237 }; 238 239 #ifdef CONFIG_IRDA 240 #define USE_IRDA(sport) ((sport)->use_irda) 241 #else 242 #define USE_IRDA(sport) (0) 243 #endif 244 245 static struct imx_uart_data imx_uart_devdata[] = { 246 [IMX1_UART] = { 247 .uts_reg = IMX1_UTS, 248 .devtype = IMX1_UART, 249 }, 250 [IMX21_UART] = { 251 .uts_reg = IMX21_UTS, 252 .devtype = IMX21_UART, 253 }, 254 [IMX6Q_UART] = { 255 .uts_reg = IMX21_UTS, 256 .devtype = IMX6Q_UART, 257 }, 258 }; 259 260 static struct platform_device_id imx_uart_devtype[] = { 261 { 262 .name = "imx1-uart", 263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 264 }, { 265 .name = "imx21-uart", 266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 267 }, { 268 .name = "imx6q-uart", 269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 270 }, { 271 /* sentinel */ 272 } 273 }; 274 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 275 276 static struct of_device_id imx_uart_dt_ids[] = { 277 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 280 { /* sentinel */ } 281 }; 282 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 283 284 static inline unsigned uts_reg(struct imx_port *sport) 285 { 286 return sport->devdata->uts_reg; 287 } 288 289 static inline int is_imx1_uart(struct imx_port *sport) 290 { 291 return sport->devdata->devtype == IMX1_UART; 292 } 293 294 static inline int is_imx21_uart(struct imx_port *sport) 295 { 296 return sport->devdata->devtype == IMX21_UART; 297 } 298 299 static inline int is_imx6q_uart(struct imx_port *sport) 300 { 301 return sport->devdata->devtype == IMX6Q_UART; 302 } 303 /* 304 * Save and restore functions for UCR1, UCR2 and UCR3 registers 305 */ 306 #if defined(CONFIG_SERIAL_IMX_CONSOLE) 307 static void imx_port_ucrs_save(struct uart_port *port, 308 struct imx_port_ucrs *ucr) 309 { 310 /* save control registers */ 311 ucr->ucr1 = readl(port->membase + UCR1); 312 ucr->ucr2 = readl(port->membase + UCR2); 313 ucr->ucr3 = readl(port->membase + UCR3); 314 } 315 316 static void imx_port_ucrs_restore(struct uart_port *port, 317 struct imx_port_ucrs *ucr) 318 { 319 /* restore control registers */ 320 writel(ucr->ucr1, port->membase + UCR1); 321 writel(ucr->ucr2, port->membase + UCR2); 322 writel(ucr->ucr3, port->membase + UCR3); 323 } 324 #endif 325 326 /* 327 * Handle any change of modem status signal since we were last called. 328 */ 329 static void imx_mctrl_check(struct imx_port *sport) 330 { 331 unsigned int status, changed; 332 333 status = sport->port.ops->get_mctrl(&sport->port); 334 changed = status ^ sport->old_status; 335 336 if (changed == 0) 337 return; 338 339 sport->old_status = status; 340 341 if (changed & TIOCM_RI) 342 sport->port.icount.rng++; 343 if (changed & TIOCM_DSR) 344 sport->port.icount.dsr++; 345 if (changed & TIOCM_CAR) 346 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 347 if (changed & TIOCM_CTS) 348 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 349 350 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 351 } 352 353 /* 354 * This is our per-port timeout handler, for checking the 355 * modem status signals. 356 */ 357 static void imx_timeout(unsigned long data) 358 { 359 struct imx_port *sport = (struct imx_port *)data; 360 unsigned long flags; 361 362 if (sport->port.state) { 363 spin_lock_irqsave(&sport->port.lock, flags); 364 imx_mctrl_check(sport); 365 spin_unlock_irqrestore(&sport->port.lock, flags); 366 367 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 368 } 369 } 370 371 /* 372 * interrupts disabled on entry 373 */ 374 static void imx_stop_tx(struct uart_port *port) 375 { 376 struct imx_port *sport = (struct imx_port *)port; 377 unsigned long temp; 378 379 if (USE_IRDA(sport)) { 380 /* half duplex - wait for end of transmission */ 381 int n = 256; 382 while ((--n > 0) && 383 !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 384 udelay(5); 385 barrier(); 386 } 387 /* 388 * irda transceiver - wait a bit more to avoid 389 * cutoff, hardware dependent 390 */ 391 udelay(sport->trcv_delay); 392 393 /* 394 * half duplex - reactivate receive mode, 395 * flush receive pipe echo crap 396 */ 397 if (readl(sport->port.membase + USR2) & USR2_TXDC) { 398 temp = readl(sport->port.membase + UCR1); 399 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 400 writel(temp, sport->port.membase + UCR1); 401 402 temp = readl(sport->port.membase + UCR4); 403 temp &= ~(UCR4_TCEN); 404 writel(temp, sport->port.membase + UCR4); 405 406 while (readl(sport->port.membase + URXD0) & 407 URXD_CHARRDY) 408 barrier(); 409 410 temp = readl(sport->port.membase + UCR1); 411 temp |= UCR1_RRDYEN; 412 writel(temp, sport->port.membase + UCR1); 413 414 temp = readl(sport->port.membase + UCR4); 415 temp |= UCR4_DREN; 416 writel(temp, sport->port.membase + UCR4); 417 } 418 return; 419 } 420 421 /* 422 * We are maybe in the SMP context, so if the DMA TX thread is running 423 * on other cpu, we have to wait for it to finish. 424 */ 425 if (sport->dma_is_enabled && sport->dma_is_txing) 426 return; 427 428 temp = readl(sport->port.membase + UCR1); 429 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 430 } 431 432 /* 433 * interrupts disabled on entry 434 */ 435 static void imx_stop_rx(struct uart_port *port) 436 { 437 struct imx_port *sport = (struct imx_port *)port; 438 unsigned long temp; 439 440 if (sport->dma_is_enabled && sport->dma_is_rxing) { 441 if (sport->port.suspended) { 442 dmaengine_terminate_all(sport->dma_chan_rx); 443 sport->dma_is_rxing = 0; 444 } else { 445 return; 446 } 447 } 448 449 temp = readl(sport->port.membase + UCR2); 450 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 451 452 /* disable the `Receiver Ready Interrrupt` */ 453 temp = readl(sport->port.membase + UCR1); 454 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 455 } 456 457 /* 458 * Set the modem control timer to fire immediately. 459 */ 460 static void imx_enable_ms(struct uart_port *port) 461 { 462 struct imx_port *sport = (struct imx_port *)port; 463 464 mod_timer(&sport->timer, jiffies); 465 } 466 467 static void imx_dma_tx(struct imx_port *sport); 468 static inline void imx_transmit_buffer(struct imx_port *sport) 469 { 470 struct circ_buf *xmit = &sport->port.state->xmit; 471 unsigned long temp; 472 473 if (sport->port.x_char) { 474 /* Send next char */ 475 writel(sport->port.x_char, sport->port.membase + URTX0); 476 sport->port.icount.tx++; 477 sport->port.x_char = 0; 478 return; 479 } 480 481 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 482 imx_stop_tx(&sport->port); 483 return; 484 } 485 486 if (sport->dma_is_enabled) { 487 /* 488 * We've just sent a X-char Ensure the TX DMA is enabled 489 * and the TX IRQ is disabled. 490 **/ 491 temp = readl(sport->port.membase + UCR1); 492 temp &= ~UCR1_TXMPTYEN; 493 if (sport->dma_is_txing) { 494 temp |= UCR1_TDMAEN; 495 writel(temp, sport->port.membase + UCR1); 496 } else { 497 writel(temp, sport->port.membase + UCR1); 498 imx_dma_tx(sport); 499 } 500 } 501 502 while (!uart_circ_empty(xmit) && 503 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 504 /* send xmit->buf[xmit->tail] 505 * out the port here */ 506 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 507 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 508 sport->port.icount.tx++; 509 } 510 511 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 512 uart_write_wakeup(&sport->port); 513 514 if (uart_circ_empty(xmit)) 515 imx_stop_tx(&sport->port); 516 } 517 518 static void dma_tx_callback(void *data) 519 { 520 struct imx_port *sport = data; 521 struct scatterlist *sgl = &sport->tx_sgl[0]; 522 struct circ_buf *xmit = &sport->port.state->xmit; 523 unsigned long flags; 524 unsigned long temp; 525 526 spin_lock_irqsave(&sport->port.lock, flags); 527 528 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 529 530 temp = readl(sport->port.membase + UCR1); 531 temp &= ~UCR1_TDMAEN; 532 writel(temp, sport->port.membase + UCR1); 533 534 /* update the stat */ 535 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 536 sport->port.icount.tx += sport->tx_bytes; 537 538 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 539 540 sport->dma_is_txing = 0; 541 542 spin_unlock_irqrestore(&sport->port.lock, flags); 543 544 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 545 uart_write_wakeup(&sport->port); 546 547 if (waitqueue_active(&sport->dma_wait)) { 548 wake_up(&sport->dma_wait); 549 dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 550 return; 551 } 552 553 spin_lock_irqsave(&sport->port.lock, flags); 554 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 555 imx_dma_tx(sport); 556 spin_unlock_irqrestore(&sport->port.lock, flags); 557 } 558 559 static void imx_dma_tx(struct imx_port *sport) 560 { 561 struct circ_buf *xmit = &sport->port.state->xmit; 562 struct scatterlist *sgl = sport->tx_sgl; 563 struct dma_async_tx_descriptor *desc; 564 struct dma_chan *chan = sport->dma_chan_tx; 565 struct device *dev = sport->port.dev; 566 unsigned long temp; 567 int ret; 568 569 if (sport->dma_is_txing) 570 return; 571 572 sport->tx_bytes = uart_circ_chars_pending(xmit); 573 574 if (xmit->tail < xmit->head) { 575 sport->dma_tx_nents = 1; 576 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 577 } else { 578 sport->dma_tx_nents = 2; 579 sg_init_table(sgl, 2); 580 sg_set_buf(sgl, xmit->buf + xmit->tail, 581 UART_XMIT_SIZE - xmit->tail); 582 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 583 } 584 585 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 586 if (ret == 0) { 587 dev_err(dev, "DMA mapping error for TX.\n"); 588 return; 589 } 590 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 591 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 592 if (!desc) { 593 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 594 DMA_TO_DEVICE); 595 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 596 return; 597 } 598 desc->callback = dma_tx_callback; 599 desc->callback_param = sport; 600 601 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 602 uart_circ_chars_pending(xmit)); 603 604 temp = readl(sport->port.membase + UCR1); 605 temp |= UCR1_TDMAEN; 606 writel(temp, sport->port.membase + UCR1); 607 608 /* fire it */ 609 sport->dma_is_txing = 1; 610 dmaengine_submit(desc); 611 dma_async_issue_pending(chan); 612 return; 613 } 614 615 /* 616 * interrupts disabled on entry 617 */ 618 static void imx_start_tx(struct uart_port *port) 619 { 620 struct imx_port *sport = (struct imx_port *)port; 621 unsigned long temp; 622 623 if (USE_IRDA(sport)) { 624 /* half duplex in IrDA mode; have to disable receive mode */ 625 temp = readl(sport->port.membase + UCR4); 626 temp &= ~(UCR4_DREN); 627 writel(temp, sport->port.membase + UCR4); 628 629 temp = readl(sport->port.membase + UCR1); 630 temp &= ~(UCR1_RRDYEN); 631 writel(temp, sport->port.membase + UCR1); 632 } 633 634 if (!sport->dma_is_enabled) { 635 temp = readl(sport->port.membase + UCR1); 636 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 637 } 638 639 if (USE_IRDA(sport)) { 640 temp = readl(sport->port.membase + UCR1); 641 temp |= UCR1_TRDYEN; 642 writel(temp, sport->port.membase + UCR1); 643 644 temp = readl(sport->port.membase + UCR4); 645 temp |= UCR4_TCEN; 646 writel(temp, sport->port.membase + UCR4); 647 } 648 649 if (sport->dma_is_enabled) { 650 if (sport->port.x_char) { 651 /* We have X-char to send, so enable TX IRQ and 652 * disable TX DMA to let TX interrupt to send X-char */ 653 temp = readl(sport->port.membase + UCR1); 654 temp &= ~UCR1_TDMAEN; 655 temp |= UCR1_TXMPTYEN; 656 writel(temp, sport->port.membase + UCR1); 657 return; 658 } 659 660 if (!uart_circ_empty(&port->state->xmit) && 661 !uart_tx_stopped(port)) 662 imx_dma_tx(sport); 663 return; 664 } 665 } 666 667 static irqreturn_t imx_rtsint(int irq, void *dev_id) 668 { 669 struct imx_port *sport = dev_id; 670 unsigned int val; 671 unsigned long flags; 672 673 spin_lock_irqsave(&sport->port.lock, flags); 674 675 writel(USR1_RTSD, sport->port.membase + USR1); 676 val = readl(sport->port.membase + USR1) & USR1_RTSS; 677 uart_handle_cts_change(&sport->port, !!val); 678 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 679 680 spin_unlock_irqrestore(&sport->port.lock, flags); 681 return IRQ_HANDLED; 682 } 683 684 static irqreturn_t imx_txint(int irq, void *dev_id) 685 { 686 struct imx_port *sport = dev_id; 687 unsigned long flags; 688 689 spin_lock_irqsave(&sport->port.lock, flags); 690 imx_transmit_buffer(sport); 691 spin_unlock_irqrestore(&sport->port.lock, flags); 692 return IRQ_HANDLED; 693 } 694 695 static irqreturn_t imx_rxint(int irq, void *dev_id) 696 { 697 struct imx_port *sport = dev_id; 698 unsigned int rx, flg, ignored = 0; 699 struct tty_port *port = &sport->port.state->port; 700 unsigned long flags, temp; 701 702 spin_lock_irqsave(&sport->port.lock, flags); 703 704 while (readl(sport->port.membase + USR2) & USR2_RDR) { 705 flg = TTY_NORMAL; 706 sport->port.icount.rx++; 707 708 rx = readl(sport->port.membase + URXD0); 709 710 temp = readl(sport->port.membase + USR2); 711 if (temp & USR2_BRCD) { 712 writel(USR2_BRCD, sport->port.membase + USR2); 713 if (uart_handle_break(&sport->port)) 714 continue; 715 } 716 717 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 718 continue; 719 720 if (unlikely(rx & URXD_ERR)) { 721 if (rx & URXD_BRK) 722 sport->port.icount.brk++; 723 else if (rx & URXD_PRERR) 724 sport->port.icount.parity++; 725 else if (rx & URXD_FRMERR) 726 sport->port.icount.frame++; 727 if (rx & URXD_OVRRUN) 728 sport->port.icount.overrun++; 729 730 if (rx & sport->port.ignore_status_mask) { 731 if (++ignored > 100) 732 goto out; 733 continue; 734 } 735 736 rx &= (sport->port.read_status_mask | 0xFF); 737 738 if (rx & URXD_BRK) 739 flg = TTY_BREAK; 740 else if (rx & URXD_PRERR) 741 flg = TTY_PARITY; 742 else if (rx & URXD_FRMERR) 743 flg = TTY_FRAME; 744 if (rx & URXD_OVRRUN) 745 flg = TTY_OVERRUN; 746 747 #ifdef SUPPORT_SYSRQ 748 sport->port.sysrq = 0; 749 #endif 750 } 751 752 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 753 goto out; 754 755 tty_insert_flip_char(port, rx, flg); 756 } 757 758 out: 759 spin_unlock_irqrestore(&sport->port.lock, flags); 760 tty_flip_buffer_push(port); 761 return IRQ_HANDLED; 762 } 763 764 static int start_rx_dma(struct imx_port *sport); 765 /* 766 * If the RXFIFO is filled with some data, and then we 767 * arise a DMA operation to receive them. 768 */ 769 static void imx_dma_rxint(struct imx_port *sport) 770 { 771 unsigned long temp; 772 unsigned long flags; 773 774 spin_lock_irqsave(&sport->port.lock, flags); 775 776 temp = readl(sport->port.membase + USR2); 777 if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 778 sport->dma_is_rxing = 1; 779 780 /* disable the `Recerver Ready Interrrupt` */ 781 temp = readl(sport->port.membase + UCR1); 782 temp &= ~(UCR1_RRDYEN); 783 writel(temp, sport->port.membase + UCR1); 784 785 /* tell the DMA to receive the data. */ 786 start_rx_dma(sport); 787 } 788 789 spin_unlock_irqrestore(&sport->port.lock, flags); 790 } 791 792 static irqreturn_t imx_int(int irq, void *dev_id) 793 { 794 struct imx_port *sport = dev_id; 795 unsigned int sts; 796 unsigned int sts2; 797 798 sts = readl(sport->port.membase + USR1); 799 800 if (sts & USR1_RRDY) { 801 if (sport->dma_is_enabled) 802 imx_dma_rxint(sport); 803 else 804 imx_rxint(irq, dev_id); 805 } 806 807 if (sts & USR1_TRDY && 808 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 809 imx_txint(irq, dev_id); 810 811 if (sts & USR1_RTSD) 812 imx_rtsint(irq, dev_id); 813 814 if (sts & USR1_AWAKE) 815 writel(USR1_AWAKE, sport->port.membase + USR1); 816 817 sts2 = readl(sport->port.membase + USR2); 818 if (sts2 & USR2_ORE) { 819 dev_err(sport->port.dev, "Rx FIFO overrun\n"); 820 sport->port.icount.overrun++; 821 writel(sts2 | USR2_ORE, sport->port.membase + USR2); 822 } 823 824 return IRQ_HANDLED; 825 } 826 827 /* 828 * Return TIOCSER_TEMT when transmitter is not busy. 829 */ 830 static unsigned int imx_tx_empty(struct uart_port *port) 831 { 832 struct imx_port *sport = (struct imx_port *)port; 833 unsigned int ret; 834 835 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 836 837 /* If the TX DMA is working, return 0. */ 838 if (sport->dma_is_enabled && sport->dma_is_txing) 839 ret = 0; 840 841 return ret; 842 } 843 844 /* 845 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 846 */ 847 static unsigned int imx_get_mctrl(struct uart_port *port) 848 { 849 struct imx_port *sport = (struct imx_port *)port; 850 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 851 852 if (readl(sport->port.membase + USR1) & USR1_RTSS) 853 tmp |= TIOCM_CTS; 854 855 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 856 tmp |= TIOCM_RTS; 857 858 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 859 tmp |= TIOCM_LOOP; 860 861 return tmp; 862 } 863 864 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 865 { 866 struct imx_port *sport = (struct imx_port *)port; 867 unsigned long temp; 868 869 temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC); 870 if (mctrl & TIOCM_RTS) 871 temp |= UCR2_CTS | UCR2_CTSC; 872 873 writel(temp, sport->port.membase + UCR2); 874 875 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 876 if (mctrl & TIOCM_LOOP) 877 temp |= UTS_LOOP; 878 writel(temp, sport->port.membase + uts_reg(sport)); 879 } 880 881 /* 882 * Interrupts always disabled. 883 */ 884 static void imx_break_ctl(struct uart_port *port, int break_state) 885 { 886 struct imx_port *sport = (struct imx_port *)port; 887 unsigned long flags, temp; 888 889 spin_lock_irqsave(&sport->port.lock, flags); 890 891 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 892 893 if (break_state != 0) 894 temp |= UCR1_SNDBRK; 895 896 writel(temp, sport->port.membase + UCR1); 897 898 spin_unlock_irqrestore(&sport->port.lock, flags); 899 } 900 901 #define TXTL 2 /* reset default */ 902 #define RXTL 1 /* reset default */ 903 904 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 905 { 906 unsigned int val; 907 908 /* set receiver / transmitter trigger level */ 909 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 910 val |= TXTL << UFCR_TXTL_SHF | RXTL; 911 writel(val, sport->port.membase + UFCR); 912 return 0; 913 } 914 915 #define RX_BUF_SIZE (PAGE_SIZE) 916 static void imx_rx_dma_done(struct imx_port *sport) 917 { 918 unsigned long temp; 919 unsigned long flags; 920 921 spin_lock_irqsave(&sport->port.lock, flags); 922 923 /* Enable this interrupt when the RXFIFO is empty. */ 924 temp = readl(sport->port.membase + UCR1); 925 temp |= UCR1_RRDYEN; 926 writel(temp, sport->port.membase + UCR1); 927 928 sport->dma_is_rxing = 0; 929 930 /* Is the shutdown waiting for us? */ 931 if (waitqueue_active(&sport->dma_wait)) 932 wake_up(&sport->dma_wait); 933 934 spin_unlock_irqrestore(&sport->port.lock, flags); 935 } 936 937 /* 938 * There are three kinds of RX DMA interrupts(such as in the MX6Q): 939 * [1] the RX DMA buffer is full. 940 * [2] the Aging timer expires(wait for 8 bytes long) 941 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 942 * 943 * The [2] is trigger when a character was been sitting in the FIFO 944 * meanwhile [3] can wait for 32 bytes long when the RX line is 945 * on IDLE state and RxFIFO is empty. 946 */ 947 static void dma_rx_callback(void *data) 948 { 949 struct imx_port *sport = data; 950 struct dma_chan *chan = sport->dma_chan_rx; 951 struct scatterlist *sgl = &sport->rx_sgl; 952 struct tty_port *port = &sport->port.state->port; 953 struct dma_tx_state state; 954 enum dma_status status; 955 unsigned int count; 956 957 /* unmap it first */ 958 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 959 960 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 961 count = RX_BUF_SIZE - state.residue; 962 dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 963 964 if (count) { 965 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) 966 tty_insert_flip_string(port, sport->rx_buf, count); 967 tty_flip_buffer_push(port); 968 969 start_rx_dma(sport); 970 } else if (readl(sport->port.membase + USR2) & USR2_RDR) { 971 /* 972 * start rx_dma directly once data in RXFIFO, more efficient 973 * than before: 974 * 1. call imx_rx_dma_done to stop dma if no data received 975 * 2. wait next RDR interrupt to start dma transfer. 976 */ 977 start_rx_dma(sport); 978 } else { 979 /* 980 * stop dma to prevent too many IDLE event trigged if no data 981 * in RXFIFO 982 */ 983 imx_rx_dma_done(sport); 984 } 985 } 986 987 static int start_rx_dma(struct imx_port *sport) 988 { 989 struct scatterlist *sgl = &sport->rx_sgl; 990 struct dma_chan *chan = sport->dma_chan_rx; 991 struct device *dev = sport->port.dev; 992 struct dma_async_tx_descriptor *desc; 993 int ret; 994 995 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 996 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 997 if (ret == 0) { 998 dev_err(dev, "DMA mapping error for RX.\n"); 999 return -EINVAL; 1000 } 1001 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 1002 DMA_PREP_INTERRUPT); 1003 if (!desc) { 1004 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1005 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1006 return -EINVAL; 1007 } 1008 desc->callback = dma_rx_callback; 1009 desc->callback_param = sport; 1010 1011 dev_dbg(dev, "RX: prepare for the DMA.\n"); 1012 dmaengine_submit(desc); 1013 dma_async_issue_pending(chan); 1014 return 0; 1015 } 1016 1017 static void imx_uart_dma_exit(struct imx_port *sport) 1018 { 1019 if (sport->dma_chan_rx) { 1020 dma_release_channel(sport->dma_chan_rx); 1021 sport->dma_chan_rx = NULL; 1022 1023 kfree(sport->rx_buf); 1024 sport->rx_buf = NULL; 1025 } 1026 1027 if (sport->dma_chan_tx) { 1028 dma_release_channel(sport->dma_chan_tx); 1029 sport->dma_chan_tx = NULL; 1030 } 1031 1032 sport->dma_is_inited = 0; 1033 } 1034 1035 static int imx_uart_dma_init(struct imx_port *sport) 1036 { 1037 struct dma_slave_config slave_config = {}; 1038 struct device *dev = sport->port.dev; 1039 int ret; 1040 1041 /* Prepare for RX : */ 1042 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1043 if (!sport->dma_chan_rx) { 1044 dev_dbg(dev, "cannot get the DMA channel.\n"); 1045 ret = -EINVAL; 1046 goto err; 1047 } 1048 1049 slave_config.direction = DMA_DEV_TO_MEM; 1050 slave_config.src_addr = sport->port.mapbase + URXD0; 1051 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1052 slave_config.src_maxburst = RXTL; 1053 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1054 if (ret) { 1055 dev_err(dev, "error in RX dma configuration.\n"); 1056 goto err; 1057 } 1058 1059 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1060 if (!sport->rx_buf) { 1061 ret = -ENOMEM; 1062 goto err; 1063 } 1064 1065 /* Prepare for TX : */ 1066 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1067 if (!sport->dma_chan_tx) { 1068 dev_err(dev, "cannot get the TX DMA channel!\n"); 1069 ret = -EINVAL; 1070 goto err; 1071 } 1072 1073 slave_config.direction = DMA_MEM_TO_DEV; 1074 slave_config.dst_addr = sport->port.mapbase + URTX0; 1075 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1076 slave_config.dst_maxburst = TXTL; 1077 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1078 if (ret) { 1079 dev_err(dev, "error in TX dma configuration."); 1080 goto err; 1081 } 1082 1083 sport->dma_is_inited = 1; 1084 1085 return 0; 1086 err: 1087 imx_uart_dma_exit(sport); 1088 return ret; 1089 } 1090 1091 static void imx_enable_dma(struct imx_port *sport) 1092 { 1093 unsigned long temp; 1094 1095 init_waitqueue_head(&sport->dma_wait); 1096 1097 /* set UCR1 */ 1098 temp = readl(sport->port.membase + UCR1); 1099 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1100 /* wait for 32 idle frames for IDDMA interrupt */ 1101 UCR1_ICD_REG(3); 1102 writel(temp, sport->port.membase + UCR1); 1103 1104 /* set UCR4 */ 1105 temp = readl(sport->port.membase + UCR4); 1106 temp |= UCR4_IDDMAEN; 1107 writel(temp, sport->port.membase + UCR4); 1108 1109 sport->dma_is_enabled = 1; 1110 } 1111 1112 static void imx_disable_dma(struct imx_port *sport) 1113 { 1114 unsigned long temp; 1115 1116 /* clear UCR1 */ 1117 temp = readl(sport->port.membase + UCR1); 1118 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1119 writel(temp, sport->port.membase + UCR1); 1120 1121 /* clear UCR2 */ 1122 temp = readl(sport->port.membase + UCR2); 1123 temp &= ~(UCR2_CTSC | UCR2_CTS); 1124 writel(temp, sport->port.membase + UCR2); 1125 1126 /* clear UCR4 */ 1127 temp = readl(sport->port.membase + UCR4); 1128 temp &= ~UCR4_IDDMAEN; 1129 writel(temp, sport->port.membase + UCR4); 1130 1131 sport->dma_is_enabled = 0; 1132 } 1133 1134 /* half the RX buffer size */ 1135 #define CTSTL 16 1136 1137 static int imx_startup(struct uart_port *port) 1138 { 1139 struct imx_port *sport = (struct imx_port *)port; 1140 int retval, i; 1141 unsigned long flags, temp; 1142 1143 retval = clk_prepare_enable(sport->clk_per); 1144 if (retval) 1145 return retval; 1146 retval = clk_prepare_enable(sport->clk_ipg); 1147 if (retval) { 1148 clk_disable_unprepare(sport->clk_per); 1149 return retval; 1150 } 1151 1152 imx_setup_ufcr(sport, 0); 1153 1154 /* disable the DREN bit (Data Ready interrupt enable) before 1155 * requesting IRQs 1156 */ 1157 temp = readl(sport->port.membase + UCR4); 1158 1159 if (USE_IRDA(sport)) 1160 temp |= UCR4_IRSC; 1161 1162 /* set the trigger level for CTS */ 1163 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1164 temp |= CTSTL << UCR4_CTSTL_SHF; 1165 1166 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1167 1168 /* Reset fifo's and state machines */ 1169 i = 100; 1170 1171 temp = readl(sport->port.membase + UCR2); 1172 temp &= ~UCR2_SRST; 1173 writel(temp, sport->port.membase + UCR2); 1174 1175 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1176 udelay(1); 1177 1178 /* Can we enable the DMA support? */ 1179 if (is_imx6q_uart(sport) && !uart_console(port) && 1180 !sport->dma_is_inited) 1181 imx_uart_dma_init(sport); 1182 1183 spin_lock_irqsave(&sport->port.lock, flags); 1184 /* 1185 * Finally, clear and enable interrupts 1186 */ 1187 writel(USR1_RTSD, sport->port.membase + USR1); 1188 1189 if (sport->dma_is_inited && !sport->dma_is_enabled) 1190 imx_enable_dma(sport); 1191 1192 temp = readl(sport->port.membase + UCR1); 1193 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1194 1195 if (USE_IRDA(sport)) { 1196 temp |= UCR1_IREN; 1197 temp &= ~(UCR1_RTSDEN); 1198 } 1199 1200 writel(temp, sport->port.membase + UCR1); 1201 1202 /* Clear any pending ORE flag before enabling interrupt */ 1203 temp = readl(sport->port.membase + USR2); 1204 writel(temp | USR2_ORE, sport->port.membase + USR2); 1205 1206 temp = readl(sport->port.membase + UCR4); 1207 temp |= UCR4_OREN; 1208 writel(temp, sport->port.membase + UCR4); 1209 1210 temp = readl(sport->port.membase + UCR2); 1211 temp |= (UCR2_RXEN | UCR2_TXEN); 1212 if (!sport->have_rtscts) 1213 temp |= UCR2_IRTS; 1214 writel(temp, sport->port.membase + UCR2); 1215 1216 if (!is_imx1_uart(sport)) { 1217 temp = readl(sport->port.membase + UCR3); 1218 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1219 writel(temp, sport->port.membase + UCR3); 1220 } 1221 1222 if (USE_IRDA(sport)) { 1223 temp = readl(sport->port.membase + UCR4); 1224 if (sport->irda_inv_rx) 1225 temp |= UCR4_INVR; 1226 else 1227 temp &= ~(UCR4_INVR); 1228 writel(temp | UCR4_DREN, sport->port.membase + UCR4); 1229 1230 temp = readl(sport->port.membase + UCR3); 1231 if (sport->irda_inv_tx) 1232 temp |= UCR3_INVT; 1233 else 1234 temp &= ~(UCR3_INVT); 1235 writel(temp, sport->port.membase + UCR3); 1236 } 1237 1238 /* 1239 * Enable modem status interrupts 1240 */ 1241 imx_enable_ms(&sport->port); 1242 spin_unlock_irqrestore(&sport->port.lock, flags); 1243 1244 if (USE_IRDA(sport)) { 1245 struct imxuart_platform_data *pdata; 1246 pdata = dev_get_platdata(sport->port.dev); 1247 sport->irda_inv_rx = pdata->irda_inv_rx; 1248 sport->irda_inv_tx = pdata->irda_inv_tx; 1249 sport->trcv_delay = pdata->transceiver_delay; 1250 if (pdata->irda_enable) 1251 pdata->irda_enable(1); 1252 } 1253 1254 return 0; 1255 } 1256 1257 static void imx_shutdown(struct uart_port *port) 1258 { 1259 struct imx_port *sport = (struct imx_port *)port; 1260 unsigned long temp; 1261 unsigned long flags; 1262 1263 if (sport->dma_is_enabled) { 1264 int ret; 1265 1266 /* We have to wait for the DMA to finish. */ 1267 ret = wait_event_interruptible(sport->dma_wait, 1268 !sport->dma_is_rxing && !sport->dma_is_txing); 1269 if (ret != 0) { 1270 sport->dma_is_rxing = 0; 1271 sport->dma_is_txing = 0; 1272 dmaengine_terminate_all(sport->dma_chan_tx); 1273 dmaengine_terminate_all(sport->dma_chan_rx); 1274 } 1275 spin_lock_irqsave(&sport->port.lock, flags); 1276 imx_stop_tx(port); 1277 imx_stop_rx(port); 1278 imx_disable_dma(sport); 1279 spin_unlock_irqrestore(&sport->port.lock, flags); 1280 imx_uart_dma_exit(sport); 1281 } 1282 1283 spin_lock_irqsave(&sport->port.lock, flags); 1284 temp = readl(sport->port.membase + UCR2); 1285 temp &= ~(UCR2_TXEN); 1286 writel(temp, sport->port.membase + UCR2); 1287 spin_unlock_irqrestore(&sport->port.lock, flags); 1288 1289 if (USE_IRDA(sport)) { 1290 struct imxuart_platform_data *pdata; 1291 pdata = dev_get_platdata(sport->port.dev); 1292 if (pdata->irda_enable) 1293 pdata->irda_enable(0); 1294 } 1295 1296 /* 1297 * Stop our timer. 1298 */ 1299 del_timer_sync(&sport->timer); 1300 1301 /* 1302 * Disable all interrupts, port and break condition. 1303 */ 1304 1305 spin_lock_irqsave(&sport->port.lock, flags); 1306 temp = readl(sport->port.membase + UCR1); 1307 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1308 if (USE_IRDA(sport)) 1309 temp &= ~(UCR1_IREN); 1310 1311 writel(temp, sport->port.membase + UCR1); 1312 spin_unlock_irqrestore(&sport->port.lock, flags); 1313 1314 clk_disable_unprepare(sport->clk_per); 1315 clk_disable_unprepare(sport->clk_ipg); 1316 } 1317 1318 static void imx_flush_buffer(struct uart_port *port) 1319 { 1320 struct imx_port *sport = (struct imx_port *)port; 1321 struct scatterlist *sgl = &sport->tx_sgl[0]; 1322 unsigned long temp; 1323 int i = 100, ubir, ubmr, ubrc, uts; 1324 1325 if (!sport->dma_chan_tx) 1326 return; 1327 1328 sport->tx_bytes = 0; 1329 dmaengine_terminate_all(sport->dma_chan_tx); 1330 if (sport->dma_is_txing) { 1331 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1332 DMA_TO_DEVICE); 1333 temp = readl(sport->port.membase + UCR1); 1334 temp &= ~UCR1_TDMAEN; 1335 writel(temp, sport->port.membase + UCR1); 1336 sport->dma_is_txing = false; 1337 } 1338 1339 /* 1340 * According to the Reference Manual description of the UART SRST bit: 1341 * "Reset the transmit and receive state machines, 1342 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1343 * and UTS[6-3]". As we don't need to restore the old values from 1344 * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1345 */ 1346 ubir = readl(sport->port.membase + UBIR); 1347 ubmr = readl(sport->port.membase + UBMR); 1348 ubrc = readl(sport->port.membase + UBRC); 1349 uts = readl(sport->port.membase + IMX21_UTS); 1350 1351 temp = readl(sport->port.membase + UCR2); 1352 temp &= ~UCR2_SRST; 1353 writel(temp, sport->port.membase + UCR2); 1354 1355 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1356 udelay(1); 1357 1358 /* Restore the registers */ 1359 writel(ubir, sport->port.membase + UBIR); 1360 writel(ubmr, sport->port.membase + UBMR); 1361 writel(ubrc, sport->port.membase + UBRC); 1362 writel(uts, sport->port.membase + IMX21_UTS); 1363 } 1364 1365 static void 1366 imx_set_termios(struct uart_port *port, struct ktermios *termios, 1367 struct ktermios *old) 1368 { 1369 struct imx_port *sport = (struct imx_port *)port; 1370 unsigned long flags; 1371 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1372 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1373 unsigned int div, ufcr; 1374 unsigned long num, denom; 1375 uint64_t tdiv64; 1376 1377 /* 1378 * If we don't support modem control lines, don't allow 1379 * these to be set. 1380 */ 1381 if (0) { 1382 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 1383 termios->c_cflag |= CLOCAL; 1384 } 1385 1386 /* 1387 * We only support CS7 and CS8. 1388 */ 1389 while ((termios->c_cflag & CSIZE) != CS7 && 1390 (termios->c_cflag & CSIZE) != CS8) { 1391 termios->c_cflag &= ~CSIZE; 1392 termios->c_cflag |= old_csize; 1393 old_csize = CS8; 1394 } 1395 1396 if ((termios->c_cflag & CSIZE) == CS8) 1397 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1398 else 1399 ucr2 = UCR2_SRST | UCR2_IRTS; 1400 1401 if (termios->c_cflag & CRTSCTS) { 1402 if (sport->have_rtscts) { 1403 ucr2 &= ~UCR2_IRTS; 1404 ucr2 |= UCR2_CTSC; 1405 } else { 1406 termios->c_cflag &= ~CRTSCTS; 1407 } 1408 } 1409 1410 if (termios->c_cflag & CSTOPB) 1411 ucr2 |= UCR2_STPB; 1412 if (termios->c_cflag & PARENB) { 1413 ucr2 |= UCR2_PREN; 1414 if (termios->c_cflag & PARODD) 1415 ucr2 |= UCR2_PROE; 1416 } 1417 1418 del_timer_sync(&sport->timer); 1419 1420 /* 1421 * Ask the core to calculate the divisor for us. 1422 */ 1423 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1424 quot = uart_get_divisor(port, baud); 1425 1426 spin_lock_irqsave(&sport->port.lock, flags); 1427 1428 sport->port.read_status_mask = 0; 1429 if (termios->c_iflag & INPCK) 1430 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1431 if (termios->c_iflag & (BRKINT | PARMRK)) 1432 sport->port.read_status_mask |= URXD_BRK; 1433 1434 /* 1435 * Characters to ignore 1436 */ 1437 sport->port.ignore_status_mask = 0; 1438 if (termios->c_iflag & IGNPAR) 1439 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1440 if (termios->c_iflag & IGNBRK) { 1441 sport->port.ignore_status_mask |= URXD_BRK; 1442 /* 1443 * If we're ignoring parity and break indicators, 1444 * ignore overruns too (for real raw support). 1445 */ 1446 if (termios->c_iflag & IGNPAR) 1447 sport->port.ignore_status_mask |= URXD_OVRRUN; 1448 } 1449 1450 if ((termios->c_cflag & CREAD) == 0) 1451 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1452 1453 /* 1454 * Update the per-port timeout. 1455 */ 1456 uart_update_timeout(port, termios->c_cflag, baud); 1457 1458 /* 1459 * disable interrupts and drain transmitter 1460 */ 1461 old_ucr1 = readl(sport->port.membase + UCR1); 1462 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1463 sport->port.membase + UCR1); 1464 1465 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1466 barrier(); 1467 1468 /* then, disable everything */ 1469 old_txrxen = readl(sport->port.membase + UCR2); 1470 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1471 sport->port.membase + UCR2); 1472 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1473 1474 if (USE_IRDA(sport)) { 1475 /* 1476 * use maximum available submodule frequency to 1477 * avoid missing short pulses due to low sampling rate 1478 */ 1479 div = 1; 1480 } else { 1481 /* custom-baudrate handling */ 1482 div = sport->port.uartclk / (baud * 16); 1483 if (baud == 38400 && quot != div) 1484 baud = sport->port.uartclk / (quot * 16); 1485 1486 div = sport->port.uartclk / (baud * 16); 1487 if (div > 7) 1488 div = 7; 1489 if (!div) 1490 div = 1; 1491 } 1492 1493 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1494 1 << 16, 1 << 16, &num, &denom); 1495 1496 tdiv64 = sport->port.uartclk; 1497 tdiv64 *= num; 1498 do_div(tdiv64, denom * 16 * div); 1499 tty_termios_encode_baud_rate(termios, 1500 (speed_t)tdiv64, (speed_t)tdiv64); 1501 1502 num -= 1; 1503 denom -= 1; 1504 1505 ufcr = readl(sport->port.membase + UFCR); 1506 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1507 if (sport->dte_mode) 1508 ufcr |= UFCR_DCEDTE; 1509 writel(ufcr, sport->port.membase + UFCR); 1510 1511 writel(num, sport->port.membase + UBIR); 1512 writel(denom, sport->port.membase + UBMR); 1513 1514 if (!is_imx1_uart(sport)) 1515 writel(sport->port.uartclk / div / 1000, 1516 sport->port.membase + IMX21_ONEMS); 1517 1518 writel(old_ucr1, sport->port.membase + UCR1); 1519 1520 /* set the parity, stop bits and data size */ 1521 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1522 1523 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1524 imx_enable_ms(&sport->port); 1525 1526 spin_unlock_irqrestore(&sport->port.lock, flags); 1527 } 1528 1529 static const char *imx_type(struct uart_port *port) 1530 { 1531 struct imx_port *sport = (struct imx_port *)port; 1532 1533 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1534 } 1535 1536 /* 1537 * Configure/autoconfigure the port. 1538 */ 1539 static void imx_config_port(struct uart_port *port, int flags) 1540 { 1541 struct imx_port *sport = (struct imx_port *)port; 1542 1543 if (flags & UART_CONFIG_TYPE) 1544 sport->port.type = PORT_IMX; 1545 } 1546 1547 /* 1548 * Verify the new serial_struct (for TIOCSSERIAL). 1549 * The only change we allow are to the flags and type, and 1550 * even then only between PORT_IMX and PORT_UNKNOWN 1551 */ 1552 static int 1553 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1554 { 1555 struct imx_port *sport = (struct imx_port *)port; 1556 int ret = 0; 1557 1558 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1559 ret = -EINVAL; 1560 if (sport->port.irq != ser->irq) 1561 ret = -EINVAL; 1562 if (ser->io_type != UPIO_MEM) 1563 ret = -EINVAL; 1564 if (sport->port.uartclk / 16 != ser->baud_base) 1565 ret = -EINVAL; 1566 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1567 ret = -EINVAL; 1568 if (sport->port.iobase != ser->port) 1569 ret = -EINVAL; 1570 if (ser->hub6 != 0) 1571 ret = -EINVAL; 1572 return ret; 1573 } 1574 1575 #if defined(CONFIG_CONSOLE_POLL) 1576 1577 static int imx_poll_init(struct uart_port *port) 1578 { 1579 struct imx_port *sport = (struct imx_port *)port; 1580 unsigned long flags; 1581 unsigned long temp; 1582 int retval; 1583 1584 retval = clk_prepare_enable(sport->clk_ipg); 1585 if (retval) 1586 return retval; 1587 retval = clk_prepare_enable(sport->clk_per); 1588 if (retval) 1589 clk_disable_unprepare(sport->clk_ipg); 1590 1591 imx_setup_ufcr(sport, 0); 1592 1593 spin_lock_irqsave(&sport->port.lock, flags); 1594 1595 temp = readl(sport->port.membase + UCR1); 1596 if (is_imx1_uart(sport)) 1597 temp |= IMX1_UCR1_UARTCLKEN; 1598 temp |= UCR1_UARTEN | UCR1_RRDYEN; 1599 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 1600 writel(temp, sport->port.membase + UCR1); 1601 1602 temp = readl(sport->port.membase + UCR2); 1603 temp |= UCR2_RXEN; 1604 writel(temp, sport->port.membase + UCR2); 1605 1606 spin_unlock_irqrestore(&sport->port.lock, flags); 1607 1608 return 0; 1609 } 1610 1611 static int imx_poll_get_char(struct uart_port *port) 1612 { 1613 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 1614 return NO_POLL_CHAR; 1615 1616 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 1617 } 1618 1619 static void imx_poll_put_char(struct uart_port *port, unsigned char c) 1620 { 1621 unsigned int status; 1622 1623 /* drain */ 1624 do { 1625 status = readl_relaxed(port->membase + USR1); 1626 } while (~status & USR1_TRDY); 1627 1628 /* write */ 1629 writel_relaxed(c, port->membase + URTX0); 1630 1631 /* flush */ 1632 do { 1633 status = readl_relaxed(port->membase + USR2); 1634 } while (~status & USR2_TXDC); 1635 } 1636 #endif 1637 1638 static struct uart_ops imx_pops = { 1639 .tx_empty = imx_tx_empty, 1640 .set_mctrl = imx_set_mctrl, 1641 .get_mctrl = imx_get_mctrl, 1642 .stop_tx = imx_stop_tx, 1643 .start_tx = imx_start_tx, 1644 .stop_rx = imx_stop_rx, 1645 .enable_ms = imx_enable_ms, 1646 .break_ctl = imx_break_ctl, 1647 .startup = imx_startup, 1648 .shutdown = imx_shutdown, 1649 .flush_buffer = imx_flush_buffer, 1650 .set_termios = imx_set_termios, 1651 .type = imx_type, 1652 .config_port = imx_config_port, 1653 .verify_port = imx_verify_port, 1654 #if defined(CONFIG_CONSOLE_POLL) 1655 .poll_init = imx_poll_init, 1656 .poll_get_char = imx_poll_get_char, 1657 .poll_put_char = imx_poll_put_char, 1658 #endif 1659 }; 1660 1661 static struct imx_port *imx_ports[UART_NR]; 1662 1663 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1664 static void imx_console_putchar(struct uart_port *port, int ch) 1665 { 1666 struct imx_port *sport = (struct imx_port *)port; 1667 1668 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1669 barrier(); 1670 1671 writel(ch, sport->port.membase + URTX0); 1672 } 1673 1674 /* 1675 * Interrupts are disabled on entering 1676 */ 1677 static void 1678 imx_console_write(struct console *co, const char *s, unsigned int count) 1679 { 1680 struct imx_port *sport = imx_ports[co->index]; 1681 struct imx_port_ucrs old_ucr; 1682 unsigned int ucr1; 1683 unsigned long flags = 0; 1684 int locked = 1; 1685 int retval; 1686 1687 retval = clk_enable(sport->clk_per); 1688 if (retval) 1689 return; 1690 retval = clk_enable(sport->clk_ipg); 1691 if (retval) { 1692 clk_disable(sport->clk_per); 1693 return; 1694 } 1695 1696 if (sport->port.sysrq) 1697 locked = 0; 1698 else if (oops_in_progress) 1699 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1700 else 1701 spin_lock_irqsave(&sport->port.lock, flags); 1702 1703 /* 1704 * First, save UCR1/2/3 and then disable interrupts 1705 */ 1706 imx_port_ucrs_save(&sport->port, &old_ucr); 1707 ucr1 = old_ucr.ucr1; 1708 1709 if (is_imx1_uart(sport)) 1710 ucr1 |= IMX1_UCR1_UARTCLKEN; 1711 ucr1 |= UCR1_UARTEN; 1712 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1713 1714 writel(ucr1, sport->port.membase + UCR1); 1715 1716 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1717 1718 uart_console_write(&sport->port, s, count, imx_console_putchar); 1719 1720 /* 1721 * Finally, wait for transmitter to become empty 1722 * and restore UCR1/2/3 1723 */ 1724 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1725 1726 imx_port_ucrs_restore(&sport->port, &old_ucr); 1727 1728 if (locked) 1729 spin_unlock_irqrestore(&sport->port.lock, flags); 1730 1731 clk_disable(sport->clk_ipg); 1732 clk_disable(sport->clk_per); 1733 } 1734 1735 /* 1736 * If the port was already initialised (eg, by a boot loader), 1737 * try to determine the current setup. 1738 */ 1739 static void __init 1740 imx_console_get_options(struct imx_port *sport, int *baud, 1741 int *parity, int *bits) 1742 { 1743 1744 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1745 /* ok, the port was enabled */ 1746 unsigned int ucr2, ubir, ubmr, uartclk; 1747 unsigned int baud_raw; 1748 unsigned int ucfr_rfdiv; 1749 1750 ucr2 = readl(sport->port.membase + UCR2); 1751 1752 *parity = 'n'; 1753 if (ucr2 & UCR2_PREN) { 1754 if (ucr2 & UCR2_PROE) 1755 *parity = 'o'; 1756 else 1757 *parity = 'e'; 1758 } 1759 1760 if (ucr2 & UCR2_WS) 1761 *bits = 8; 1762 else 1763 *bits = 7; 1764 1765 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1766 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1767 1768 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1769 if (ucfr_rfdiv == 6) 1770 ucfr_rfdiv = 7; 1771 else 1772 ucfr_rfdiv = 6 - ucfr_rfdiv; 1773 1774 uartclk = clk_get_rate(sport->clk_per); 1775 uartclk /= ucfr_rfdiv; 1776 1777 { /* 1778 * The next code provides exact computation of 1779 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1780 * without need of float support or long long division, 1781 * which would be required to prevent 32bit arithmetic overflow 1782 */ 1783 unsigned int mul = ubir + 1; 1784 unsigned int div = 16 * (ubmr + 1); 1785 unsigned int rem = uartclk % div; 1786 1787 baud_raw = (uartclk / div) * mul; 1788 baud_raw += (rem * mul + div / 2) / div; 1789 *baud = (baud_raw + 50) / 100 * 100; 1790 } 1791 1792 if (*baud != baud_raw) 1793 pr_info("Console IMX rounded baud rate from %d to %d\n", 1794 baud_raw, *baud); 1795 } 1796 } 1797 1798 static int __init 1799 imx_console_setup(struct console *co, char *options) 1800 { 1801 struct imx_port *sport; 1802 int baud = 9600; 1803 int bits = 8; 1804 int parity = 'n'; 1805 int flow = 'n'; 1806 int retval; 1807 1808 /* 1809 * Check whether an invalid uart number has been specified, and 1810 * if so, search for the first available port that does have 1811 * console support. 1812 */ 1813 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1814 co->index = 0; 1815 sport = imx_ports[co->index]; 1816 if (sport == NULL) 1817 return -ENODEV; 1818 1819 /* For setting the registers, we only need to enable the ipg clock. */ 1820 retval = clk_prepare_enable(sport->clk_ipg); 1821 if (retval) 1822 goto error_console; 1823 1824 if (options) 1825 uart_parse_options(options, &baud, &parity, &bits, &flow); 1826 else 1827 imx_console_get_options(sport, &baud, &parity, &bits); 1828 1829 imx_setup_ufcr(sport, 0); 1830 1831 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 1832 1833 clk_disable(sport->clk_ipg); 1834 if (retval) { 1835 clk_unprepare(sport->clk_ipg); 1836 goto error_console; 1837 } 1838 1839 retval = clk_prepare(sport->clk_per); 1840 if (retval) 1841 clk_disable_unprepare(sport->clk_ipg); 1842 1843 error_console: 1844 return retval; 1845 } 1846 1847 static struct uart_driver imx_reg; 1848 static struct console imx_console = { 1849 .name = DEV_NAME, 1850 .write = imx_console_write, 1851 .device = uart_console_device, 1852 .setup = imx_console_setup, 1853 .flags = CON_PRINTBUFFER, 1854 .index = -1, 1855 .data = &imx_reg, 1856 }; 1857 1858 #define IMX_CONSOLE &imx_console 1859 #else 1860 #define IMX_CONSOLE NULL 1861 #endif 1862 1863 static struct uart_driver imx_reg = { 1864 .owner = THIS_MODULE, 1865 .driver_name = DRIVER_NAME, 1866 .dev_name = DEV_NAME, 1867 .major = SERIAL_IMX_MAJOR, 1868 .minor = MINOR_START, 1869 .nr = ARRAY_SIZE(imx_ports), 1870 .cons = IMX_CONSOLE, 1871 }; 1872 1873 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1874 { 1875 struct imx_port *sport = platform_get_drvdata(dev); 1876 unsigned int val; 1877 1878 /* enable wakeup from i.MX UART */ 1879 val = readl(sport->port.membase + UCR3); 1880 val |= UCR3_AWAKEN; 1881 writel(val, sport->port.membase + UCR3); 1882 1883 uart_suspend_port(&imx_reg, &sport->port); 1884 1885 return 0; 1886 } 1887 1888 static int serial_imx_resume(struct platform_device *dev) 1889 { 1890 struct imx_port *sport = platform_get_drvdata(dev); 1891 unsigned int val; 1892 1893 /* disable wakeup from i.MX UART */ 1894 val = readl(sport->port.membase + UCR3); 1895 val &= ~UCR3_AWAKEN; 1896 writel(val, sport->port.membase + UCR3); 1897 1898 uart_resume_port(&imx_reg, &sport->port); 1899 1900 return 0; 1901 } 1902 1903 #ifdef CONFIG_OF 1904 /* 1905 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 1906 * could successfully get all information from dt or a negative errno. 1907 */ 1908 static int serial_imx_probe_dt(struct imx_port *sport, 1909 struct platform_device *pdev) 1910 { 1911 struct device_node *np = pdev->dev.of_node; 1912 const struct of_device_id *of_id = 1913 of_match_device(imx_uart_dt_ids, &pdev->dev); 1914 int ret; 1915 1916 if (!np) 1917 /* no device tree device */ 1918 return 1; 1919 1920 ret = of_alias_get_id(np, "serial"); 1921 if (ret < 0) { 1922 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1923 return ret; 1924 } 1925 sport->port.line = ret; 1926 1927 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1928 sport->have_rtscts = 1; 1929 1930 if (of_get_property(np, "fsl,irda-mode", NULL)) 1931 sport->use_irda = 1; 1932 1933 if (of_get_property(np, "fsl,dte-mode", NULL)) 1934 sport->dte_mode = 1; 1935 1936 sport->devdata = of_id->data; 1937 1938 return 0; 1939 } 1940 #else 1941 static inline int serial_imx_probe_dt(struct imx_port *sport, 1942 struct platform_device *pdev) 1943 { 1944 return 1; 1945 } 1946 #endif 1947 1948 static void serial_imx_probe_pdata(struct imx_port *sport, 1949 struct platform_device *pdev) 1950 { 1951 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 1952 1953 sport->port.line = pdev->id; 1954 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 1955 1956 if (!pdata) 1957 return; 1958 1959 if (pdata->flags & IMXUART_HAVE_RTSCTS) 1960 sport->have_rtscts = 1; 1961 1962 if (pdata->flags & IMXUART_IRDA) 1963 sport->use_irda = 1; 1964 } 1965 1966 static int serial_imx_probe(struct platform_device *pdev) 1967 { 1968 struct imx_port *sport; 1969 void __iomem *base; 1970 int ret = 0; 1971 struct resource *res; 1972 1973 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1974 if (!sport) 1975 return -ENOMEM; 1976 1977 ret = serial_imx_probe_dt(sport, pdev); 1978 if (ret > 0) 1979 serial_imx_probe_pdata(sport, pdev); 1980 else if (ret < 0) 1981 return ret; 1982 1983 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1984 base = devm_ioremap_resource(&pdev->dev, res); 1985 if (IS_ERR(base)) 1986 return PTR_ERR(base); 1987 1988 sport->port.dev = &pdev->dev; 1989 sport->port.mapbase = res->start; 1990 sport->port.membase = base; 1991 sport->port.type = PORT_IMX, 1992 sport->port.iotype = UPIO_MEM; 1993 sport->port.irq = platform_get_irq(pdev, 0); 1994 sport->rxirq = platform_get_irq(pdev, 0); 1995 sport->txirq = platform_get_irq(pdev, 1); 1996 sport->rtsirq = platform_get_irq(pdev, 2); 1997 sport->port.fifosize = 32; 1998 sport->port.ops = &imx_pops; 1999 sport->port.flags = UPF_BOOT_AUTOCONF; 2000 init_timer(&sport->timer); 2001 sport->timer.function = imx_timeout; 2002 sport->timer.data = (unsigned long)sport; 2003 2004 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2005 if (IS_ERR(sport->clk_ipg)) { 2006 ret = PTR_ERR(sport->clk_ipg); 2007 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 2008 return ret; 2009 } 2010 2011 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 2012 if (IS_ERR(sport->clk_per)) { 2013 ret = PTR_ERR(sport->clk_per); 2014 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 2015 return ret; 2016 } 2017 2018 sport->port.uartclk = clk_get_rate(sport->clk_per); 2019 2020 /* 2021 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2022 * chips only have one interrupt. 2023 */ 2024 if (sport->txirq > 0) { 2025 ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0, 2026 dev_name(&pdev->dev), sport); 2027 if (ret) 2028 return ret; 2029 2030 ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0, 2031 dev_name(&pdev->dev), sport); 2032 if (ret) 2033 return ret; 2034 2035 /* do not use RTS IRQ on IrDA */ 2036 if (!USE_IRDA(sport)) { 2037 ret = devm_request_irq(&pdev->dev, sport->rtsirq, 2038 imx_rtsint, 0, 2039 dev_name(&pdev->dev), sport); 2040 if (ret) 2041 return ret; 2042 } 2043 } else { 2044 ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0, 2045 dev_name(&pdev->dev), sport); 2046 if (ret) 2047 return ret; 2048 } 2049 2050 imx_ports[sport->port.line] = sport; 2051 2052 platform_set_drvdata(pdev, sport); 2053 2054 return uart_add_one_port(&imx_reg, &sport->port); 2055 } 2056 2057 static int serial_imx_remove(struct platform_device *pdev) 2058 { 2059 struct imx_port *sport = platform_get_drvdata(pdev); 2060 2061 return uart_remove_one_port(&imx_reg, &sport->port); 2062 } 2063 2064 static struct platform_driver serial_imx_driver = { 2065 .probe = serial_imx_probe, 2066 .remove = serial_imx_remove, 2067 2068 .suspend = serial_imx_suspend, 2069 .resume = serial_imx_resume, 2070 .id_table = imx_uart_devtype, 2071 .driver = { 2072 .name = "imx-uart", 2073 .of_match_table = imx_uart_dt_ids, 2074 }, 2075 }; 2076 2077 static int __init imx_serial_init(void) 2078 { 2079 int ret = uart_register_driver(&imx_reg); 2080 2081 if (ret) 2082 return ret; 2083 2084 ret = platform_driver_register(&serial_imx_driver); 2085 if (ret != 0) 2086 uart_unregister_driver(&imx_reg); 2087 2088 return ret; 2089 } 2090 2091 static void __exit imx_serial_exit(void) 2092 { 2093 platform_driver_unregister(&serial_imx_driver); 2094 uart_unregister_driver(&imx_reg); 2095 } 2096 2097 module_init(imx_serial_init); 2098 module_exit(imx_serial_exit); 2099 2100 MODULE_AUTHOR("Sascha Hauer"); 2101 MODULE_DESCRIPTION("IMX generic serial port driver"); 2102 MODULE_LICENSE("GPL"); 2103 MODULE_ALIAS("platform:imx-uart"); 2104