1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Motorola/Freescale IMX serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Author: Sascha Hauer <sascha@saschahauer.de> 8 * Copyright (C) 2004 Pengutronix 9 */ 10 11 #include <linux/module.h> 12 #include <linux/ioport.h> 13 #include <linux/init.h> 14 #include <linux/console.h> 15 #include <linux/sysrq.h> 16 #include <linux/platform_device.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/ktime.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/rational.h> 26 #include <linux/slab.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 #include <linux/io.h> 30 #include <linux/dma-mapping.h> 31 32 #include <asm/irq.h> 33 #include <linux/platform_data/serial-imx.h> 34 #include <linux/platform_data/dma-imx.h> 35 36 #include "serial_mctrl_gpio.h" 37 38 /* Register definitions */ 39 #define URXD0 0x0 /* Receiver Register */ 40 #define URTX0 0x40 /* Transmitter Register */ 41 #define UCR1 0x80 /* Control Register 1 */ 42 #define UCR2 0x84 /* Control Register 2 */ 43 #define UCR3 0x88 /* Control Register 3 */ 44 #define UCR4 0x8c /* Control Register 4 */ 45 #define UFCR 0x90 /* FIFO Control Register */ 46 #define USR1 0x94 /* Status Register 1 */ 47 #define USR2 0x98 /* Status Register 2 */ 48 #define UESC 0x9c /* Escape Character Register */ 49 #define UTIM 0xa0 /* Escape Timer Register */ 50 #define UBIR 0xa4 /* BRM Incremental Register */ 51 #define UBMR 0xa8 /* BRM Modulator Register */ 52 #define UBRC 0xac /* Baud Rate Count Register */ 53 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 54 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 55 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 56 57 /* UART Control Register Bit Fields.*/ 58 #define URXD_DUMMY_READ (1<<16) 59 #define URXD_CHARRDY (1<<15) 60 #define URXD_ERR (1<<14) 61 #define URXD_OVRRUN (1<<13) 62 #define URXD_FRMERR (1<<12) 63 #define URXD_BRK (1<<11) 64 #define URXD_PRERR (1<<10) 65 #define URXD_RX_DATA (0xFF<<0) 66 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 67 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 68 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 69 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 70 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 71 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 72 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 73 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 74 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 75 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 76 #define UCR1_SNDBRK (1<<4) /* Send break */ 77 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 78 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 79 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 80 #define UCR1_DOZE (1<<1) /* Doze */ 81 #define UCR1_UARTEN (1<<0) /* UART enabled */ 82 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 83 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 84 #define UCR2_CTSC (1<<13) /* CTS pin control */ 85 #define UCR2_CTS (1<<12) /* Clear to send */ 86 #define UCR2_ESCEN (1<<11) /* Escape enable */ 87 #define UCR2_PREN (1<<8) /* Parity enable */ 88 #define UCR2_PROE (1<<7) /* Parity odd/even */ 89 #define UCR2_STPB (1<<6) /* Stop */ 90 #define UCR2_WS (1<<5) /* Word size */ 91 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 92 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 93 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 94 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 95 #define UCR2_SRST (1<<0) /* SW reset */ 96 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 97 #define UCR3_PARERREN (1<<12) /* Parity enable */ 98 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 99 #define UCR3_DSR (1<<10) /* Data set ready */ 100 #define UCR3_DCD (1<<9) /* Data carrier detect */ 101 #define UCR3_RI (1<<8) /* Ring indicator */ 102 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 103 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 104 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 105 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 106 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 107 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 108 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 109 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 110 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 111 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 112 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 113 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 114 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 115 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 116 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 117 #define UCR4_IRSC (1<<5) /* IR special case */ 118 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 119 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 120 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 121 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 122 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 123 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 124 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 125 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 126 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 127 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 128 #define USR1_RTSS (1<<14) /* RTS pin status */ 129 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 130 #define USR1_RTSD (1<<12) /* RTS delta */ 131 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 132 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 133 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 134 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 135 #define USR1_DTRD (1<<7) /* DTR Delta */ 136 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 137 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 138 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 139 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 140 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 141 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 142 #define USR2_IDLE (1<<12) /* Idle condition */ 143 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 144 #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 145 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 146 #define USR2_WAKE (1<<7) /* Wake */ 147 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 148 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 149 #define USR2_TXDC (1<<3) /* Transmitter complete */ 150 #define USR2_BRCD (1<<2) /* Break condition */ 151 #define USR2_ORE (1<<1) /* Overrun error */ 152 #define USR2_RDR (1<<0) /* Recv data ready */ 153 #define UTS_FRCPERR (1<<13) /* Force parity error */ 154 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 155 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 156 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 157 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 158 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 159 #define UTS_SOFTRST (1<<0) /* Software reset */ 160 161 /* We've been assigned a range on the "Low-density serial ports" major */ 162 #define SERIAL_IMX_MAJOR 207 163 #define MINOR_START 16 164 #define DEV_NAME "ttymxc" 165 166 /* 167 * This determines how often we check the modem status signals 168 * for any change. They generally aren't connected to an IRQ 169 * so we have to poll them. We also check immediately before 170 * filling the TX fifo incase CTS has been dropped. 171 */ 172 #define MCTRL_TIMEOUT (250*HZ/1000) 173 174 #define DRIVER_NAME "IMX-uart" 175 176 #define UART_NR 8 177 178 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 179 enum imx_uart_type { 180 IMX1_UART, 181 IMX21_UART, 182 IMX53_UART, 183 IMX6Q_UART, 184 }; 185 186 /* device type dependent stuff */ 187 struct imx_uart_data { 188 unsigned uts_reg; 189 enum imx_uart_type devtype; 190 }; 191 192 enum imx_tx_state { 193 OFF, 194 WAIT_AFTER_RTS, 195 SEND, 196 WAIT_AFTER_SEND, 197 }; 198 199 struct imx_port { 200 struct uart_port port; 201 struct timer_list timer; 202 unsigned int old_status; 203 unsigned int have_rtscts:1; 204 unsigned int have_rtsgpio:1; 205 unsigned int dte_mode:1; 206 unsigned int inverted_tx:1; 207 unsigned int inverted_rx:1; 208 struct clk *clk_ipg; 209 struct clk *clk_per; 210 const struct imx_uart_data *devdata; 211 212 struct mctrl_gpios *gpios; 213 214 /* shadow registers */ 215 unsigned int ucr1; 216 unsigned int ucr2; 217 unsigned int ucr3; 218 unsigned int ucr4; 219 unsigned int ufcr; 220 221 /* DMA fields */ 222 unsigned int dma_is_enabled:1; 223 unsigned int dma_is_rxing:1; 224 unsigned int dma_is_txing:1; 225 struct dma_chan *dma_chan_rx, *dma_chan_tx; 226 struct scatterlist rx_sgl, tx_sgl[2]; 227 void *rx_buf; 228 struct circ_buf rx_ring; 229 unsigned int rx_periods; 230 dma_cookie_t rx_cookie; 231 unsigned int tx_bytes; 232 unsigned int dma_tx_nents; 233 unsigned int saved_reg[10]; 234 bool context_saved; 235 236 enum imx_tx_state tx_state; 237 struct hrtimer trigger_start_tx; 238 struct hrtimer trigger_stop_tx; 239 }; 240 241 struct imx_port_ucrs { 242 unsigned int ucr1; 243 unsigned int ucr2; 244 unsigned int ucr3; 245 }; 246 247 static struct imx_uart_data imx_uart_devdata[] = { 248 [IMX1_UART] = { 249 .uts_reg = IMX1_UTS, 250 .devtype = IMX1_UART, 251 }, 252 [IMX21_UART] = { 253 .uts_reg = IMX21_UTS, 254 .devtype = IMX21_UART, 255 }, 256 [IMX53_UART] = { 257 .uts_reg = IMX21_UTS, 258 .devtype = IMX53_UART, 259 }, 260 [IMX6Q_UART] = { 261 .uts_reg = IMX21_UTS, 262 .devtype = IMX6Q_UART, 263 }, 264 }; 265 266 static const struct platform_device_id imx_uart_devtype[] = { 267 { 268 .name = "imx1-uart", 269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 270 }, { 271 .name = "imx21-uart", 272 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 273 }, { 274 .name = "imx53-uart", 275 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 276 }, { 277 .name = "imx6q-uart", 278 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 279 }, { 280 /* sentinel */ 281 } 282 }; 283 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 284 285 static const struct of_device_id imx_uart_dt_ids[] = { 286 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 287 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 288 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 289 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 290 { /* sentinel */ } 291 }; 292 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 293 294 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 295 { 296 switch (offset) { 297 case UCR1: 298 sport->ucr1 = val; 299 break; 300 case UCR2: 301 sport->ucr2 = val; 302 break; 303 case UCR3: 304 sport->ucr3 = val; 305 break; 306 case UCR4: 307 sport->ucr4 = val; 308 break; 309 case UFCR: 310 sport->ufcr = val; 311 break; 312 default: 313 break; 314 } 315 writel(val, sport->port.membase + offset); 316 } 317 318 static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 319 { 320 switch (offset) { 321 case UCR1: 322 return sport->ucr1; 323 break; 324 case UCR2: 325 /* 326 * UCR2_SRST is the only bit in the cached registers that might 327 * differ from the value that was last written. As it only 328 * automatically becomes one after being cleared, reread 329 * conditionally. 330 */ 331 if (!(sport->ucr2 & UCR2_SRST)) 332 sport->ucr2 = readl(sport->port.membase + offset); 333 return sport->ucr2; 334 break; 335 case UCR3: 336 return sport->ucr3; 337 break; 338 case UCR4: 339 return sport->ucr4; 340 break; 341 case UFCR: 342 return sport->ufcr; 343 break; 344 default: 345 return readl(sport->port.membase + offset); 346 } 347 } 348 349 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 350 { 351 return sport->devdata->uts_reg; 352 } 353 354 static inline int imx_uart_is_imx1(struct imx_port *sport) 355 { 356 return sport->devdata->devtype == IMX1_UART; 357 } 358 359 static inline int imx_uart_is_imx21(struct imx_port *sport) 360 { 361 return sport->devdata->devtype == IMX21_UART; 362 } 363 364 static inline int imx_uart_is_imx53(struct imx_port *sport) 365 { 366 return sport->devdata->devtype == IMX53_UART; 367 } 368 369 static inline int imx_uart_is_imx6q(struct imx_port *sport) 370 { 371 return sport->devdata->devtype == IMX6Q_UART; 372 } 373 /* 374 * Save and restore functions for UCR1, UCR2 and UCR3 registers 375 */ 376 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 377 static void imx_uart_ucrs_save(struct imx_port *sport, 378 struct imx_port_ucrs *ucr) 379 { 380 /* save control registers */ 381 ucr->ucr1 = imx_uart_readl(sport, UCR1); 382 ucr->ucr2 = imx_uart_readl(sport, UCR2); 383 ucr->ucr3 = imx_uart_readl(sport, UCR3); 384 } 385 386 static void imx_uart_ucrs_restore(struct imx_port *sport, 387 struct imx_port_ucrs *ucr) 388 { 389 /* restore control registers */ 390 imx_uart_writel(sport, ucr->ucr1, UCR1); 391 imx_uart_writel(sport, ucr->ucr2, UCR2); 392 imx_uart_writel(sport, ucr->ucr3, UCR3); 393 } 394 #endif 395 396 /* called with port.lock taken and irqs caller dependent */ 397 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 398 { 399 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 400 401 sport->port.mctrl |= TIOCM_RTS; 402 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 403 } 404 405 /* called with port.lock taken and irqs caller dependent */ 406 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 407 { 408 *ucr2 &= ~UCR2_CTSC; 409 *ucr2 |= UCR2_CTS; 410 411 sport->port.mctrl &= ~TIOCM_RTS; 412 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 413 } 414 415 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 416 { 417 long sec = msec / MSEC_PER_SEC; 418 long nsec = (msec % MSEC_PER_SEC) * 1000000; 419 ktime_t t = ktime_set(sec, nsec); 420 421 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 422 } 423 424 /* called with port.lock taken and irqs off */ 425 static void imx_uart_start_rx(struct uart_port *port) 426 { 427 struct imx_port *sport = (struct imx_port *)port; 428 unsigned int ucr1, ucr2; 429 430 ucr1 = imx_uart_readl(sport, UCR1); 431 ucr2 = imx_uart_readl(sport, UCR2); 432 433 ucr2 |= UCR2_RXEN; 434 435 if (sport->dma_is_enabled) { 436 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 437 } else { 438 ucr1 |= UCR1_RRDYEN; 439 ucr2 |= UCR2_ATEN; 440 } 441 442 /* Write UCR2 first as it includes RXEN */ 443 imx_uart_writel(sport, ucr2, UCR2); 444 imx_uart_writel(sport, ucr1, UCR1); 445 } 446 447 /* called with port.lock taken and irqs off */ 448 static void imx_uart_stop_tx(struct uart_port *port) 449 { 450 struct imx_port *sport = (struct imx_port *)port; 451 u32 ucr1, ucr4, usr2; 452 453 if (sport->tx_state == OFF) 454 return; 455 456 /* 457 * We are maybe in the SMP context, so if the DMA TX thread is running 458 * on other cpu, we have to wait for it to finish. 459 */ 460 if (sport->dma_is_txing) 461 return; 462 463 ucr1 = imx_uart_readl(sport, UCR1); 464 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 465 466 usr2 = imx_uart_readl(sport, USR2); 467 if (!(usr2 & USR2_TXDC)) { 468 /* The shifter is still busy, so retry once TC triggers */ 469 return; 470 } 471 472 ucr4 = imx_uart_readl(sport, UCR4); 473 ucr4 &= ~UCR4_TCEN; 474 imx_uart_writel(sport, ucr4, UCR4); 475 476 /* in rs485 mode disable transmitter */ 477 if (port->rs485.flags & SER_RS485_ENABLED) { 478 if (sport->tx_state == SEND) { 479 sport->tx_state = WAIT_AFTER_SEND; 480 start_hrtimer_ms(&sport->trigger_stop_tx, 481 port->rs485.delay_rts_after_send); 482 return; 483 } 484 485 if (sport->tx_state == WAIT_AFTER_RTS || 486 sport->tx_state == WAIT_AFTER_SEND) { 487 u32 ucr2; 488 489 hrtimer_try_to_cancel(&sport->trigger_start_tx); 490 491 ucr2 = imx_uart_readl(sport, UCR2); 492 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 493 imx_uart_rts_active(sport, &ucr2); 494 else 495 imx_uart_rts_inactive(sport, &ucr2); 496 imx_uart_writel(sport, ucr2, UCR2); 497 498 imx_uart_start_rx(port); 499 500 sport->tx_state = OFF; 501 } 502 } else { 503 sport->tx_state = OFF; 504 } 505 } 506 507 /* called with port.lock taken and irqs off */ 508 static void imx_uart_stop_rx(struct uart_port *port) 509 { 510 struct imx_port *sport = (struct imx_port *)port; 511 u32 ucr1, ucr2; 512 513 ucr1 = imx_uart_readl(sport, UCR1); 514 ucr2 = imx_uart_readl(sport, UCR2); 515 516 if (sport->dma_is_enabled) { 517 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 518 } else { 519 ucr1 &= ~UCR1_RRDYEN; 520 ucr2 &= ~UCR2_ATEN; 521 } 522 imx_uart_writel(sport, ucr1, UCR1); 523 524 ucr2 &= ~UCR2_RXEN; 525 imx_uart_writel(sport, ucr2, UCR2); 526 } 527 528 /* called with port.lock taken and irqs off */ 529 static void imx_uart_enable_ms(struct uart_port *port) 530 { 531 struct imx_port *sport = (struct imx_port *)port; 532 533 mod_timer(&sport->timer, jiffies); 534 535 mctrl_gpio_enable_ms(sport->gpios); 536 } 537 538 static void imx_uart_dma_tx(struct imx_port *sport); 539 540 /* called with port.lock taken and irqs off */ 541 static inline void imx_uart_transmit_buffer(struct imx_port *sport) 542 { 543 struct circ_buf *xmit = &sport->port.state->xmit; 544 545 if (sport->port.x_char) { 546 /* Send next char */ 547 imx_uart_writel(sport, sport->port.x_char, URTX0); 548 sport->port.icount.tx++; 549 sport->port.x_char = 0; 550 return; 551 } 552 553 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 554 imx_uart_stop_tx(&sport->port); 555 return; 556 } 557 558 if (sport->dma_is_enabled) { 559 u32 ucr1; 560 /* 561 * We've just sent a X-char Ensure the TX DMA is enabled 562 * and the TX IRQ is disabled. 563 **/ 564 ucr1 = imx_uart_readl(sport, UCR1); 565 ucr1 &= ~UCR1_TRDYEN; 566 if (sport->dma_is_txing) { 567 ucr1 |= UCR1_TXDMAEN; 568 imx_uart_writel(sport, ucr1, UCR1); 569 } else { 570 imx_uart_writel(sport, ucr1, UCR1); 571 imx_uart_dma_tx(sport); 572 } 573 574 return; 575 } 576 577 while (!uart_circ_empty(xmit) && 578 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 579 /* send xmit->buf[xmit->tail] 580 * out the port here */ 581 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 582 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 583 sport->port.icount.tx++; 584 } 585 586 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 587 uart_write_wakeup(&sport->port); 588 589 if (uart_circ_empty(xmit)) 590 imx_uart_stop_tx(&sport->port); 591 } 592 593 static void imx_uart_dma_tx_callback(void *data) 594 { 595 struct imx_port *sport = data; 596 struct scatterlist *sgl = &sport->tx_sgl[0]; 597 struct circ_buf *xmit = &sport->port.state->xmit; 598 unsigned long flags; 599 u32 ucr1; 600 601 spin_lock_irqsave(&sport->port.lock, flags); 602 603 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 604 605 ucr1 = imx_uart_readl(sport, UCR1); 606 ucr1 &= ~UCR1_TXDMAEN; 607 imx_uart_writel(sport, ucr1, UCR1); 608 609 /* update the stat */ 610 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 611 sport->port.icount.tx += sport->tx_bytes; 612 613 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 614 615 sport->dma_is_txing = 0; 616 617 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 618 uart_write_wakeup(&sport->port); 619 620 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 621 imx_uart_dma_tx(sport); 622 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 623 u32 ucr4 = imx_uart_readl(sport, UCR4); 624 ucr4 |= UCR4_TCEN; 625 imx_uart_writel(sport, ucr4, UCR4); 626 } 627 628 spin_unlock_irqrestore(&sport->port.lock, flags); 629 } 630 631 /* called with port.lock taken and irqs off */ 632 static void imx_uart_dma_tx(struct imx_port *sport) 633 { 634 struct circ_buf *xmit = &sport->port.state->xmit; 635 struct scatterlist *sgl = sport->tx_sgl; 636 struct dma_async_tx_descriptor *desc; 637 struct dma_chan *chan = sport->dma_chan_tx; 638 struct device *dev = sport->port.dev; 639 u32 ucr1, ucr4; 640 int ret; 641 642 if (sport->dma_is_txing) 643 return; 644 645 ucr4 = imx_uart_readl(sport, UCR4); 646 ucr4 &= ~UCR4_TCEN; 647 imx_uart_writel(sport, ucr4, UCR4); 648 649 sport->tx_bytes = uart_circ_chars_pending(xmit); 650 651 if (xmit->tail < xmit->head || xmit->head == 0) { 652 sport->dma_tx_nents = 1; 653 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 654 } else { 655 sport->dma_tx_nents = 2; 656 sg_init_table(sgl, 2); 657 sg_set_buf(sgl, xmit->buf + xmit->tail, 658 UART_XMIT_SIZE - xmit->tail); 659 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 660 } 661 662 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 663 if (ret == 0) { 664 dev_err(dev, "DMA mapping error for TX.\n"); 665 return; 666 } 667 desc = dmaengine_prep_slave_sg(chan, sgl, ret, 668 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 669 if (!desc) { 670 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 671 DMA_TO_DEVICE); 672 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 673 return; 674 } 675 desc->callback = imx_uart_dma_tx_callback; 676 desc->callback_param = sport; 677 678 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 679 uart_circ_chars_pending(xmit)); 680 681 ucr1 = imx_uart_readl(sport, UCR1); 682 ucr1 |= UCR1_TXDMAEN; 683 imx_uart_writel(sport, ucr1, UCR1); 684 685 /* fire it */ 686 sport->dma_is_txing = 1; 687 dmaengine_submit(desc); 688 dma_async_issue_pending(chan); 689 return; 690 } 691 692 /* called with port.lock taken and irqs off */ 693 static void imx_uart_start_tx(struct uart_port *port) 694 { 695 struct imx_port *sport = (struct imx_port *)port; 696 u32 ucr1; 697 698 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 699 return; 700 701 /* 702 * We cannot simply do nothing here if sport->tx_state == SEND already 703 * because UCR1_TXMPTYEN might already have been cleared in 704 * imx_uart_stop_tx(), but tx_state is still SEND. 705 */ 706 707 if (port->rs485.flags & SER_RS485_ENABLED) { 708 if (sport->tx_state == OFF) { 709 u32 ucr2 = imx_uart_readl(sport, UCR2); 710 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 711 imx_uart_rts_active(sport, &ucr2); 712 else 713 imx_uart_rts_inactive(sport, &ucr2); 714 imx_uart_writel(sport, ucr2, UCR2); 715 716 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 717 imx_uart_stop_rx(port); 718 719 sport->tx_state = WAIT_AFTER_RTS; 720 start_hrtimer_ms(&sport->trigger_start_tx, 721 port->rs485.delay_rts_before_send); 722 return; 723 } 724 725 if (sport->tx_state == WAIT_AFTER_SEND 726 || sport->tx_state == WAIT_AFTER_RTS) { 727 728 hrtimer_try_to_cancel(&sport->trigger_stop_tx); 729 730 /* 731 * Enable transmitter and shifter empty irq only if DMA 732 * is off. In the DMA case this is done in the 733 * tx-callback. 734 */ 735 if (!sport->dma_is_enabled) { 736 u32 ucr4 = imx_uart_readl(sport, UCR4); 737 ucr4 |= UCR4_TCEN; 738 imx_uart_writel(sport, ucr4, UCR4); 739 } 740 741 sport->tx_state = SEND; 742 } 743 } else { 744 sport->tx_state = SEND; 745 } 746 747 if (!sport->dma_is_enabled) { 748 ucr1 = imx_uart_readl(sport, UCR1); 749 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 750 } 751 752 if (sport->dma_is_enabled) { 753 if (sport->port.x_char) { 754 /* We have X-char to send, so enable TX IRQ and 755 * disable TX DMA to let TX interrupt to send X-char */ 756 ucr1 = imx_uart_readl(sport, UCR1); 757 ucr1 &= ~UCR1_TXDMAEN; 758 ucr1 |= UCR1_TRDYEN; 759 imx_uart_writel(sport, ucr1, UCR1); 760 return; 761 } 762 763 if (!uart_circ_empty(&port->state->xmit) && 764 !uart_tx_stopped(port)) 765 imx_uart_dma_tx(sport); 766 return; 767 } 768 } 769 770 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 771 { 772 struct imx_port *sport = dev_id; 773 u32 usr1; 774 775 imx_uart_writel(sport, USR1_RTSD, USR1); 776 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 777 uart_handle_cts_change(&sport->port, !!usr1); 778 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 779 780 return IRQ_HANDLED; 781 } 782 783 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 784 { 785 struct imx_port *sport = dev_id; 786 irqreturn_t ret; 787 788 spin_lock(&sport->port.lock); 789 790 ret = __imx_uart_rtsint(irq, dev_id); 791 792 spin_unlock(&sport->port.lock); 793 794 return ret; 795 } 796 797 static irqreturn_t imx_uart_txint(int irq, void *dev_id) 798 { 799 struct imx_port *sport = dev_id; 800 801 spin_lock(&sport->port.lock); 802 imx_uart_transmit_buffer(sport); 803 spin_unlock(&sport->port.lock); 804 return IRQ_HANDLED; 805 } 806 807 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 808 { 809 struct imx_port *sport = dev_id; 810 unsigned int rx, flg, ignored = 0; 811 struct tty_port *port = &sport->port.state->port; 812 813 while (imx_uart_readl(sport, USR2) & USR2_RDR) { 814 u32 usr2; 815 816 flg = TTY_NORMAL; 817 sport->port.icount.rx++; 818 819 rx = imx_uart_readl(sport, URXD0); 820 821 usr2 = imx_uart_readl(sport, USR2); 822 if (usr2 & USR2_BRCD) { 823 imx_uart_writel(sport, USR2_BRCD, USR2); 824 if (uart_handle_break(&sport->port)) 825 continue; 826 } 827 828 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 829 continue; 830 831 if (unlikely(rx & URXD_ERR)) { 832 if (rx & URXD_BRK) 833 sport->port.icount.brk++; 834 else if (rx & URXD_PRERR) 835 sport->port.icount.parity++; 836 else if (rx & URXD_FRMERR) 837 sport->port.icount.frame++; 838 if (rx & URXD_OVRRUN) 839 sport->port.icount.overrun++; 840 841 if (rx & sport->port.ignore_status_mask) { 842 if (++ignored > 100) 843 goto out; 844 continue; 845 } 846 847 rx &= (sport->port.read_status_mask | 0xFF); 848 849 if (rx & URXD_BRK) 850 flg = TTY_BREAK; 851 else if (rx & URXD_PRERR) 852 flg = TTY_PARITY; 853 else if (rx & URXD_FRMERR) 854 flg = TTY_FRAME; 855 if (rx & URXD_OVRRUN) 856 flg = TTY_OVERRUN; 857 858 sport->port.sysrq = 0; 859 } 860 861 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 862 goto out; 863 864 if (tty_insert_flip_char(port, rx, flg) == 0) 865 sport->port.icount.buf_overrun++; 866 } 867 868 out: 869 tty_flip_buffer_push(port); 870 871 return IRQ_HANDLED; 872 } 873 874 static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 875 { 876 struct imx_port *sport = dev_id; 877 irqreturn_t ret; 878 879 spin_lock(&sport->port.lock); 880 881 ret = __imx_uart_rxint(irq, dev_id); 882 883 spin_unlock(&sport->port.lock); 884 885 return ret; 886 } 887 888 static void imx_uart_clear_rx_errors(struct imx_port *sport); 889 890 /* 891 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 892 */ 893 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 894 { 895 unsigned int tmp = TIOCM_DSR; 896 unsigned usr1 = imx_uart_readl(sport, USR1); 897 unsigned usr2 = imx_uart_readl(sport, USR2); 898 899 if (usr1 & USR1_RTSS) 900 tmp |= TIOCM_CTS; 901 902 /* in DCE mode DCDIN is always 0 */ 903 if (!(usr2 & USR2_DCDIN)) 904 tmp |= TIOCM_CAR; 905 906 if (sport->dte_mode) 907 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 908 tmp |= TIOCM_RI; 909 910 return tmp; 911 } 912 913 /* 914 * Handle any change of modem status signal since we were last called. 915 */ 916 static void imx_uart_mctrl_check(struct imx_port *sport) 917 { 918 unsigned int status, changed; 919 920 status = imx_uart_get_hwmctrl(sport); 921 changed = status ^ sport->old_status; 922 923 if (changed == 0) 924 return; 925 926 sport->old_status = status; 927 928 if (changed & TIOCM_RI && status & TIOCM_RI) 929 sport->port.icount.rng++; 930 if (changed & TIOCM_DSR) 931 sport->port.icount.dsr++; 932 if (changed & TIOCM_CAR) 933 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 934 if (changed & TIOCM_CTS) 935 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 936 937 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 938 } 939 940 static irqreturn_t imx_uart_int(int irq, void *dev_id) 941 { 942 struct imx_port *sport = dev_id; 943 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 944 irqreturn_t ret = IRQ_NONE; 945 unsigned long flags = 0; 946 947 /* 948 * IRQs might not be disabled upon entering this interrupt handler, 949 * e.g. when interrupt handlers are forced to be threaded. To support 950 * this scenario as well, disable IRQs when acquiring the spinlock. 951 */ 952 spin_lock_irqsave(&sport->port.lock, flags); 953 954 usr1 = imx_uart_readl(sport, USR1); 955 usr2 = imx_uart_readl(sport, USR2); 956 ucr1 = imx_uart_readl(sport, UCR1); 957 ucr2 = imx_uart_readl(sport, UCR2); 958 ucr3 = imx_uart_readl(sport, UCR3); 959 ucr4 = imx_uart_readl(sport, UCR4); 960 961 /* 962 * Even if a condition is true that can trigger an irq only handle it if 963 * the respective irq source is enabled. This prevents some undesired 964 * actions, for example if a character that sits in the RX FIFO and that 965 * should be fetched via DMA is tried to be fetched using PIO. Or the 966 * receiver is currently off and so reading from URXD0 results in an 967 * exception. So just mask the (raw) status bits for disabled irqs. 968 */ 969 if ((ucr1 & UCR1_RRDYEN) == 0) 970 usr1 &= ~USR1_RRDY; 971 if ((ucr2 & UCR2_ATEN) == 0) 972 usr1 &= ~USR1_AGTIM; 973 if ((ucr1 & UCR1_TRDYEN) == 0) 974 usr1 &= ~USR1_TRDY; 975 if ((ucr4 & UCR4_TCEN) == 0) 976 usr2 &= ~USR2_TXDC; 977 if ((ucr3 & UCR3_DTRDEN) == 0) 978 usr1 &= ~USR1_DTRD; 979 if ((ucr1 & UCR1_RTSDEN) == 0) 980 usr1 &= ~USR1_RTSD; 981 if ((ucr3 & UCR3_AWAKEN) == 0) 982 usr1 &= ~USR1_AWAKE; 983 if ((ucr4 & UCR4_OREN) == 0) 984 usr2 &= ~USR2_ORE; 985 986 if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 987 imx_uart_writel(sport, USR1_AGTIM, USR1); 988 989 __imx_uart_rxint(irq, dev_id); 990 ret = IRQ_HANDLED; 991 } 992 993 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 994 imx_uart_transmit_buffer(sport); 995 ret = IRQ_HANDLED; 996 } 997 998 if (usr1 & USR1_DTRD) { 999 imx_uart_writel(sport, USR1_DTRD, USR1); 1000 1001 imx_uart_mctrl_check(sport); 1002 1003 ret = IRQ_HANDLED; 1004 } 1005 1006 if (usr1 & USR1_RTSD) { 1007 __imx_uart_rtsint(irq, dev_id); 1008 ret = IRQ_HANDLED; 1009 } 1010 1011 if (usr1 & USR1_AWAKE) { 1012 imx_uart_writel(sport, USR1_AWAKE, USR1); 1013 ret = IRQ_HANDLED; 1014 } 1015 1016 if (usr2 & USR2_ORE) { 1017 sport->port.icount.overrun++; 1018 imx_uart_writel(sport, USR2_ORE, USR2); 1019 ret = IRQ_HANDLED; 1020 } 1021 1022 spin_unlock_irqrestore(&sport->port.lock, flags); 1023 1024 return ret; 1025 } 1026 1027 /* 1028 * Return TIOCSER_TEMT when transmitter is not busy. 1029 */ 1030 static unsigned int imx_uart_tx_empty(struct uart_port *port) 1031 { 1032 struct imx_port *sport = (struct imx_port *)port; 1033 unsigned int ret; 1034 1035 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 1036 1037 /* If the TX DMA is working, return 0. */ 1038 if (sport->dma_is_txing) 1039 ret = 0; 1040 1041 return ret; 1042 } 1043 1044 /* called with port.lock taken and irqs off */ 1045 static unsigned int imx_uart_get_mctrl(struct uart_port *port) 1046 { 1047 struct imx_port *sport = (struct imx_port *)port; 1048 unsigned int ret = imx_uart_get_hwmctrl(sport); 1049 1050 mctrl_gpio_get(sport->gpios, &ret); 1051 1052 return ret; 1053 } 1054 1055 /* called with port.lock taken and irqs off */ 1056 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1057 { 1058 struct imx_port *sport = (struct imx_port *)port; 1059 u32 ucr3, uts; 1060 1061 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 1062 u32 ucr2; 1063 1064 /* 1065 * Turn off autoRTS if RTS is lowered and restore autoRTS 1066 * setting if RTS is raised. 1067 */ 1068 ucr2 = imx_uart_readl(sport, UCR2); 1069 ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1070 if (mctrl & TIOCM_RTS) { 1071 ucr2 |= UCR2_CTS; 1072 /* 1073 * UCR2_IRTS is unset if and only if the port is 1074 * configured for CRTSCTS, so we use inverted UCR2_IRTS 1075 * to get the state to restore to. 1076 */ 1077 if (!(ucr2 & UCR2_IRTS)) 1078 ucr2 |= UCR2_CTSC; 1079 } 1080 imx_uart_writel(sport, ucr2, UCR2); 1081 } 1082 1083 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 1084 if (!(mctrl & TIOCM_DTR)) 1085 ucr3 |= UCR3_DSR; 1086 imx_uart_writel(sport, ucr3, UCR3); 1087 1088 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 1089 if (mctrl & TIOCM_LOOP) 1090 uts |= UTS_LOOP; 1091 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 1092 1093 mctrl_gpio_set(sport->gpios, mctrl); 1094 } 1095 1096 /* 1097 * Interrupts always disabled. 1098 */ 1099 static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1100 { 1101 struct imx_port *sport = (struct imx_port *)port; 1102 unsigned long flags; 1103 u32 ucr1; 1104 1105 spin_lock_irqsave(&sport->port.lock, flags); 1106 1107 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1108 1109 if (break_state != 0) 1110 ucr1 |= UCR1_SNDBRK; 1111 1112 imx_uart_writel(sport, ucr1, UCR1); 1113 1114 spin_unlock_irqrestore(&sport->port.lock, flags); 1115 } 1116 1117 /* 1118 * This is our per-port timeout handler, for checking the 1119 * modem status signals. 1120 */ 1121 static void imx_uart_timeout(struct timer_list *t) 1122 { 1123 struct imx_port *sport = from_timer(sport, t, timer); 1124 unsigned long flags; 1125 1126 if (sport->port.state) { 1127 spin_lock_irqsave(&sport->port.lock, flags); 1128 imx_uart_mctrl_check(sport); 1129 spin_unlock_irqrestore(&sport->port.lock, flags); 1130 1131 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1132 } 1133 } 1134 1135 /* 1136 * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1137 * [1] the RX DMA buffer is full. 1138 * [2] the aging timer expires 1139 * 1140 * Condition [2] is triggered when a character has been sitting in the FIFO 1141 * for at least 8 byte durations. 1142 */ 1143 static void imx_uart_dma_rx_callback(void *data) 1144 { 1145 struct imx_port *sport = data; 1146 struct dma_chan *chan = sport->dma_chan_rx; 1147 struct scatterlist *sgl = &sport->rx_sgl; 1148 struct tty_port *port = &sport->port.state->port; 1149 struct dma_tx_state state; 1150 struct circ_buf *rx_ring = &sport->rx_ring; 1151 enum dma_status status; 1152 unsigned int w_bytes = 0; 1153 unsigned int r_bytes; 1154 unsigned int bd_size; 1155 1156 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1157 1158 if (status == DMA_ERROR) { 1159 imx_uart_clear_rx_errors(sport); 1160 return; 1161 } 1162 1163 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1164 1165 /* 1166 * The state-residue variable represents the empty space 1167 * relative to the entire buffer. Taking this in consideration 1168 * the head is always calculated base on the buffer total 1169 * length - DMA transaction residue. The UART script from the 1170 * SDMA firmware will jump to the next buffer descriptor, 1171 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 1172 * Taking this in consideration the tail is always at the 1173 * beginning of the buffer descriptor that contains the head. 1174 */ 1175 1176 /* Calculate the head */ 1177 rx_ring->head = sg_dma_len(sgl) - state.residue; 1178 1179 /* Calculate the tail. */ 1180 bd_size = sg_dma_len(sgl) / sport->rx_periods; 1181 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 1182 1183 if (rx_ring->head <= sg_dma_len(sgl) && 1184 rx_ring->head > rx_ring->tail) { 1185 1186 /* Move data from tail to head */ 1187 r_bytes = rx_ring->head - rx_ring->tail; 1188 1189 /* CPU claims ownership of RX DMA buffer */ 1190 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 1191 DMA_FROM_DEVICE); 1192 1193 w_bytes = tty_insert_flip_string(port, 1194 sport->rx_buf + rx_ring->tail, r_bytes); 1195 1196 /* UART retrieves ownership of RX DMA buffer */ 1197 dma_sync_sg_for_device(sport->port.dev, sgl, 1, 1198 DMA_FROM_DEVICE); 1199 1200 if (w_bytes != r_bytes) 1201 sport->port.icount.buf_overrun++; 1202 1203 sport->port.icount.rx += w_bytes; 1204 } else { 1205 WARN_ON(rx_ring->head > sg_dma_len(sgl)); 1206 WARN_ON(rx_ring->head <= rx_ring->tail); 1207 } 1208 } 1209 1210 if (w_bytes) { 1211 tty_flip_buffer_push(port); 1212 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 1213 } 1214 } 1215 1216 /* RX DMA buffer periods */ 1217 #define RX_DMA_PERIODS 16 1218 #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4) 1219 1220 static int imx_uart_start_rx_dma(struct imx_port *sport) 1221 { 1222 struct scatterlist *sgl = &sport->rx_sgl; 1223 struct dma_chan *chan = sport->dma_chan_rx; 1224 struct device *dev = sport->port.dev; 1225 struct dma_async_tx_descriptor *desc; 1226 int ret; 1227 1228 sport->rx_ring.head = 0; 1229 sport->rx_ring.tail = 0; 1230 sport->rx_periods = RX_DMA_PERIODS; 1231 1232 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1233 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1234 if (ret == 0) { 1235 dev_err(dev, "DMA mapping error for RX.\n"); 1236 return -EINVAL; 1237 } 1238 1239 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 1240 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 1241 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1242 1243 if (!desc) { 1244 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1245 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1246 return -EINVAL; 1247 } 1248 desc->callback = imx_uart_dma_rx_callback; 1249 desc->callback_param = sport; 1250 1251 dev_dbg(dev, "RX: prepare for the DMA.\n"); 1252 sport->dma_is_rxing = 1; 1253 sport->rx_cookie = dmaengine_submit(desc); 1254 dma_async_issue_pending(chan); 1255 return 0; 1256 } 1257 1258 static void imx_uart_clear_rx_errors(struct imx_port *sport) 1259 { 1260 struct tty_port *port = &sport->port.state->port; 1261 u32 usr1, usr2; 1262 1263 usr1 = imx_uart_readl(sport, USR1); 1264 usr2 = imx_uart_readl(sport, USR2); 1265 1266 if (usr2 & USR2_BRCD) { 1267 sport->port.icount.brk++; 1268 imx_uart_writel(sport, USR2_BRCD, USR2); 1269 uart_handle_break(&sport->port); 1270 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 1271 sport->port.icount.buf_overrun++; 1272 tty_flip_buffer_push(port); 1273 } else { 1274 if (usr1 & USR1_FRAMERR) { 1275 sport->port.icount.frame++; 1276 imx_uart_writel(sport, USR1_FRAMERR, USR1); 1277 } else if (usr1 & USR1_PARITYERR) { 1278 sport->port.icount.parity++; 1279 imx_uart_writel(sport, USR1_PARITYERR, USR1); 1280 } 1281 } 1282 1283 if (usr2 & USR2_ORE) { 1284 sport->port.icount.overrun++; 1285 imx_uart_writel(sport, USR2_ORE, USR2); 1286 } 1287 1288 } 1289 1290 #define TXTL_DEFAULT 2 /* reset default */ 1291 #define RXTL_DEFAULT 1 /* reset default */ 1292 #define TXTL_DMA 8 /* DMA burst setting */ 1293 #define RXTL_DMA 9 /* DMA burst setting */ 1294 1295 static void imx_uart_setup_ufcr(struct imx_port *sport, 1296 unsigned char txwl, unsigned char rxwl) 1297 { 1298 unsigned int val; 1299 1300 /* set receiver / transmitter trigger level */ 1301 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1302 val |= txwl << UFCR_TXTL_SHF | rxwl; 1303 imx_uart_writel(sport, val, UFCR); 1304 } 1305 1306 static void imx_uart_dma_exit(struct imx_port *sport) 1307 { 1308 if (sport->dma_chan_rx) { 1309 dmaengine_terminate_sync(sport->dma_chan_rx); 1310 dma_release_channel(sport->dma_chan_rx); 1311 sport->dma_chan_rx = NULL; 1312 sport->rx_cookie = -EINVAL; 1313 kfree(sport->rx_buf); 1314 sport->rx_buf = NULL; 1315 } 1316 1317 if (sport->dma_chan_tx) { 1318 dmaengine_terminate_sync(sport->dma_chan_tx); 1319 dma_release_channel(sport->dma_chan_tx); 1320 sport->dma_chan_tx = NULL; 1321 } 1322 } 1323 1324 static int imx_uart_dma_init(struct imx_port *sport) 1325 { 1326 struct dma_slave_config slave_config = {}; 1327 struct device *dev = sport->port.dev; 1328 int ret; 1329 1330 /* Prepare for RX : */ 1331 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1332 if (!sport->dma_chan_rx) { 1333 dev_dbg(dev, "cannot get the DMA channel.\n"); 1334 ret = -EINVAL; 1335 goto err; 1336 } 1337 1338 slave_config.direction = DMA_DEV_TO_MEM; 1339 slave_config.src_addr = sport->port.mapbase + URXD0; 1340 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1341 /* one byte less than the watermark level to enable the aging timer */ 1342 slave_config.src_maxburst = RXTL_DMA - 1; 1343 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1344 if (ret) { 1345 dev_err(dev, "error in RX dma configuration.\n"); 1346 goto err; 1347 } 1348 1349 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1350 if (!sport->rx_buf) { 1351 ret = -ENOMEM; 1352 goto err; 1353 } 1354 sport->rx_ring.buf = sport->rx_buf; 1355 1356 /* Prepare for TX : */ 1357 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1358 if (!sport->dma_chan_tx) { 1359 dev_err(dev, "cannot get the TX DMA channel!\n"); 1360 ret = -EINVAL; 1361 goto err; 1362 } 1363 1364 slave_config.direction = DMA_MEM_TO_DEV; 1365 slave_config.dst_addr = sport->port.mapbase + URTX0; 1366 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1367 slave_config.dst_maxburst = TXTL_DMA; 1368 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1369 if (ret) { 1370 dev_err(dev, "error in TX dma configuration."); 1371 goto err; 1372 } 1373 1374 return 0; 1375 err: 1376 imx_uart_dma_exit(sport); 1377 return ret; 1378 } 1379 1380 static void imx_uart_enable_dma(struct imx_port *sport) 1381 { 1382 u32 ucr1; 1383 1384 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1385 1386 /* set UCR1 */ 1387 ucr1 = imx_uart_readl(sport, UCR1); 1388 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 1389 imx_uart_writel(sport, ucr1, UCR1); 1390 1391 sport->dma_is_enabled = 1; 1392 } 1393 1394 static void imx_uart_disable_dma(struct imx_port *sport) 1395 { 1396 u32 ucr1; 1397 1398 /* clear UCR1 */ 1399 ucr1 = imx_uart_readl(sport, UCR1); 1400 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 1401 imx_uart_writel(sport, ucr1, UCR1); 1402 1403 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1404 1405 sport->dma_is_enabled = 0; 1406 } 1407 1408 /* half the RX buffer size */ 1409 #define CTSTL 16 1410 1411 static int imx_uart_startup(struct uart_port *port) 1412 { 1413 struct imx_port *sport = (struct imx_port *)port; 1414 int retval, i; 1415 unsigned long flags; 1416 int dma_is_inited = 0; 1417 u32 ucr1, ucr2, ucr3, ucr4; 1418 1419 retval = clk_prepare_enable(sport->clk_per); 1420 if (retval) 1421 return retval; 1422 retval = clk_prepare_enable(sport->clk_ipg); 1423 if (retval) { 1424 clk_disable_unprepare(sport->clk_per); 1425 return retval; 1426 } 1427 1428 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1429 1430 /* disable the DREN bit (Data Ready interrupt enable) before 1431 * requesting IRQs 1432 */ 1433 ucr4 = imx_uart_readl(sport, UCR4); 1434 1435 /* set the trigger level for CTS */ 1436 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1437 ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1438 1439 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1440 1441 /* Can we enable the DMA support? */ 1442 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 1443 dma_is_inited = 1; 1444 1445 spin_lock_irqsave(&sport->port.lock, flags); 1446 /* Reset fifo's and state machines */ 1447 i = 100; 1448 1449 ucr2 = imx_uart_readl(sport, UCR2); 1450 ucr2 &= ~UCR2_SRST; 1451 imx_uart_writel(sport, ucr2, UCR2); 1452 1453 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1454 udelay(1); 1455 1456 /* 1457 * Finally, clear and enable interrupts 1458 */ 1459 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 1460 imx_uart_writel(sport, USR2_ORE, USR2); 1461 1462 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 1463 ucr1 |= UCR1_UARTEN; 1464 if (sport->have_rtscts) 1465 ucr1 |= UCR1_RTSDEN; 1466 1467 imx_uart_writel(sport, ucr1, UCR1); 1468 1469 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 1470 if (!sport->dma_is_enabled) 1471 ucr4 |= UCR4_OREN; 1472 if (sport->inverted_rx) 1473 ucr4 |= UCR4_INVR; 1474 imx_uart_writel(sport, ucr4, UCR4); 1475 1476 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 1477 /* 1478 * configure tx polarity before enabling tx 1479 */ 1480 if (sport->inverted_tx) 1481 ucr3 |= UCR3_INVT; 1482 1483 if (!imx_uart_is_imx1(sport)) { 1484 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 1485 1486 if (sport->dte_mode) 1487 /* disable broken interrupts */ 1488 ucr3 &= ~(UCR3_RI | UCR3_DCD); 1489 } 1490 imx_uart_writel(sport, ucr3, UCR3); 1491 1492 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 1493 ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1494 if (!sport->have_rtscts) 1495 ucr2 |= UCR2_IRTS; 1496 /* 1497 * make sure the edge sensitive RTS-irq is disabled, 1498 * we're using RTSD instead. 1499 */ 1500 if (!imx_uart_is_imx1(sport)) 1501 ucr2 &= ~UCR2_RTSEN; 1502 imx_uart_writel(sport, ucr2, UCR2); 1503 1504 /* 1505 * Enable modem status interrupts 1506 */ 1507 imx_uart_enable_ms(&sport->port); 1508 1509 if (dma_is_inited) { 1510 imx_uart_enable_dma(sport); 1511 imx_uart_start_rx_dma(sport); 1512 } else { 1513 ucr1 = imx_uart_readl(sport, UCR1); 1514 ucr1 |= UCR1_RRDYEN; 1515 imx_uart_writel(sport, ucr1, UCR1); 1516 1517 ucr2 = imx_uart_readl(sport, UCR2); 1518 ucr2 |= UCR2_ATEN; 1519 imx_uart_writel(sport, ucr2, UCR2); 1520 } 1521 1522 spin_unlock_irqrestore(&sport->port.lock, flags); 1523 1524 return 0; 1525 } 1526 1527 static void imx_uart_shutdown(struct uart_port *port) 1528 { 1529 struct imx_port *sport = (struct imx_port *)port; 1530 unsigned long flags; 1531 u32 ucr1, ucr2, ucr4; 1532 1533 if (sport->dma_is_enabled) { 1534 dmaengine_terminate_sync(sport->dma_chan_tx); 1535 if (sport->dma_is_txing) { 1536 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 1537 sport->dma_tx_nents, DMA_TO_DEVICE); 1538 sport->dma_is_txing = 0; 1539 } 1540 dmaengine_terminate_sync(sport->dma_chan_rx); 1541 if (sport->dma_is_rxing) { 1542 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1543 1, DMA_FROM_DEVICE); 1544 sport->dma_is_rxing = 0; 1545 } 1546 1547 spin_lock_irqsave(&sport->port.lock, flags); 1548 imx_uart_stop_tx(port); 1549 imx_uart_stop_rx(port); 1550 imx_uart_disable_dma(sport); 1551 spin_unlock_irqrestore(&sport->port.lock, flags); 1552 imx_uart_dma_exit(sport); 1553 } 1554 1555 mctrl_gpio_disable_ms(sport->gpios); 1556 1557 spin_lock_irqsave(&sport->port.lock, flags); 1558 ucr2 = imx_uart_readl(sport, UCR2); 1559 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 1560 imx_uart_writel(sport, ucr2, UCR2); 1561 spin_unlock_irqrestore(&sport->port.lock, flags); 1562 1563 /* 1564 * Stop our timer. 1565 */ 1566 del_timer_sync(&sport->timer); 1567 1568 /* 1569 * Disable all interrupts, port and break condition. 1570 */ 1571 1572 spin_lock_irqsave(&sport->port.lock, flags); 1573 1574 ucr1 = imx_uart_readl(sport, UCR1); 1575 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1576 imx_uart_writel(sport, ucr1, UCR1); 1577 1578 ucr4 = imx_uart_readl(sport, UCR4); 1579 ucr4 &= ~(UCR4_OREN | UCR4_TCEN); 1580 imx_uart_writel(sport, ucr4, UCR4); 1581 1582 spin_unlock_irqrestore(&sport->port.lock, flags); 1583 1584 clk_disable_unprepare(sport->clk_per); 1585 clk_disable_unprepare(sport->clk_ipg); 1586 } 1587 1588 /* called with port.lock taken and irqs off */ 1589 static void imx_uart_flush_buffer(struct uart_port *port) 1590 { 1591 struct imx_port *sport = (struct imx_port *)port; 1592 struct scatterlist *sgl = &sport->tx_sgl[0]; 1593 u32 ucr2; 1594 int i = 100, ubir, ubmr, uts; 1595 1596 if (!sport->dma_chan_tx) 1597 return; 1598 1599 sport->tx_bytes = 0; 1600 dmaengine_terminate_all(sport->dma_chan_tx); 1601 if (sport->dma_is_txing) { 1602 u32 ucr1; 1603 1604 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1605 DMA_TO_DEVICE); 1606 ucr1 = imx_uart_readl(sport, UCR1); 1607 ucr1 &= ~UCR1_TXDMAEN; 1608 imx_uart_writel(sport, ucr1, UCR1); 1609 sport->dma_is_txing = 0; 1610 } 1611 1612 /* 1613 * According to the Reference Manual description of the UART SRST bit: 1614 * 1615 * "Reset the transmit and receive state machines, 1616 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1617 * and UTS[6-3]". 1618 * 1619 * We don't need to restore the old values from USR1, USR2, URXD and 1620 * UTXD. UBRC is read only, so only save/restore the other three 1621 * registers. 1622 */ 1623 ubir = imx_uart_readl(sport, UBIR); 1624 ubmr = imx_uart_readl(sport, UBMR); 1625 uts = imx_uart_readl(sport, IMX21_UTS); 1626 1627 ucr2 = imx_uart_readl(sport, UCR2); 1628 ucr2 &= ~UCR2_SRST; 1629 imx_uart_writel(sport, ucr2, UCR2); 1630 1631 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1632 udelay(1); 1633 1634 /* Restore the registers */ 1635 imx_uart_writel(sport, ubir, UBIR); 1636 imx_uart_writel(sport, ubmr, UBMR); 1637 imx_uart_writel(sport, uts, IMX21_UTS); 1638 } 1639 1640 static void 1641 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1642 struct ktermios *old) 1643 { 1644 struct imx_port *sport = (struct imx_port *)port; 1645 unsigned long flags; 1646 u32 ucr2, old_ucr2, ufcr; 1647 unsigned int baud, quot; 1648 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1649 unsigned long div; 1650 unsigned long num, denom, old_ubir, old_ubmr; 1651 uint64_t tdiv64; 1652 1653 /* 1654 * We only support CS7 and CS8. 1655 */ 1656 while ((termios->c_cflag & CSIZE) != CS7 && 1657 (termios->c_cflag & CSIZE) != CS8) { 1658 termios->c_cflag &= ~CSIZE; 1659 termios->c_cflag |= old_csize; 1660 old_csize = CS8; 1661 } 1662 1663 del_timer_sync(&sport->timer); 1664 1665 /* 1666 * Ask the core to calculate the divisor for us. 1667 */ 1668 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1669 quot = uart_get_divisor(port, baud); 1670 1671 spin_lock_irqsave(&sport->port.lock, flags); 1672 1673 /* 1674 * Read current UCR2 and save it for future use, then clear all the bits 1675 * except those we will or may need to preserve. 1676 */ 1677 old_ucr2 = imx_uart_readl(sport, UCR2); 1678 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1679 1680 ucr2 |= UCR2_SRST | UCR2_IRTS; 1681 if ((termios->c_cflag & CSIZE) == CS8) 1682 ucr2 |= UCR2_WS; 1683 1684 if (!sport->have_rtscts) 1685 termios->c_cflag &= ~CRTSCTS; 1686 1687 if (port->rs485.flags & SER_RS485_ENABLED) { 1688 /* 1689 * RTS is mandatory for rs485 operation, so keep 1690 * it under manual control and keep transmitter 1691 * disabled. 1692 */ 1693 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1694 imx_uart_rts_active(sport, &ucr2); 1695 else 1696 imx_uart_rts_inactive(sport, &ucr2); 1697 1698 } else if (termios->c_cflag & CRTSCTS) { 1699 /* 1700 * Only let receiver control RTS output if we were not requested 1701 * to have RTS inactive (which then should take precedence). 1702 */ 1703 if (ucr2 & UCR2_CTS) 1704 ucr2 |= UCR2_CTSC; 1705 } 1706 1707 if (termios->c_cflag & CRTSCTS) 1708 ucr2 &= ~UCR2_IRTS; 1709 if (termios->c_cflag & CSTOPB) 1710 ucr2 |= UCR2_STPB; 1711 if (termios->c_cflag & PARENB) { 1712 ucr2 |= UCR2_PREN; 1713 if (termios->c_cflag & PARODD) 1714 ucr2 |= UCR2_PROE; 1715 } 1716 1717 sport->port.read_status_mask = 0; 1718 if (termios->c_iflag & INPCK) 1719 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1720 if (termios->c_iflag & (BRKINT | PARMRK)) 1721 sport->port.read_status_mask |= URXD_BRK; 1722 1723 /* 1724 * Characters to ignore 1725 */ 1726 sport->port.ignore_status_mask = 0; 1727 if (termios->c_iflag & IGNPAR) 1728 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1729 if (termios->c_iflag & IGNBRK) { 1730 sport->port.ignore_status_mask |= URXD_BRK; 1731 /* 1732 * If we're ignoring parity and break indicators, 1733 * ignore overruns too (for real raw support). 1734 */ 1735 if (termios->c_iflag & IGNPAR) 1736 sport->port.ignore_status_mask |= URXD_OVRRUN; 1737 } 1738 1739 if ((termios->c_cflag & CREAD) == 0) 1740 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1741 1742 /* 1743 * Update the per-port timeout. 1744 */ 1745 uart_update_timeout(port, termios->c_cflag, baud); 1746 1747 /* custom-baudrate handling */ 1748 div = sport->port.uartclk / (baud * 16); 1749 if (baud == 38400 && quot != div) 1750 baud = sport->port.uartclk / (quot * 16); 1751 1752 div = sport->port.uartclk / (baud * 16); 1753 if (div > 7) 1754 div = 7; 1755 if (!div) 1756 div = 1; 1757 1758 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1759 1 << 16, 1 << 16, &num, &denom); 1760 1761 tdiv64 = sport->port.uartclk; 1762 tdiv64 *= num; 1763 do_div(tdiv64, denom * 16 * div); 1764 tty_termios_encode_baud_rate(termios, 1765 (speed_t)tdiv64, (speed_t)tdiv64); 1766 1767 num -= 1; 1768 denom -= 1; 1769 1770 ufcr = imx_uart_readl(sport, UFCR); 1771 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1772 imx_uart_writel(sport, ufcr, UFCR); 1773 1774 /* 1775 * Two registers below should always be written both and in this 1776 * particular order. One consequence is that we need to check if any of 1777 * them changes and then update both. We do need the check for change 1778 * as even writing the same values seem to "restart" 1779 * transmission/receiving logic in the hardware, that leads to data 1780 * breakage even when rate doesn't in fact change. E.g., user switches 1781 * RTS/CTS handshake and suddenly gets broken bytes. 1782 */ 1783 old_ubir = imx_uart_readl(sport, UBIR); 1784 old_ubmr = imx_uart_readl(sport, UBMR); 1785 if (old_ubir != num || old_ubmr != denom) { 1786 imx_uart_writel(sport, num, UBIR); 1787 imx_uart_writel(sport, denom, UBMR); 1788 } 1789 1790 if (!imx_uart_is_imx1(sport)) 1791 imx_uart_writel(sport, sport->port.uartclk / div / 1000, 1792 IMX21_ONEMS); 1793 1794 imx_uart_writel(sport, ucr2, UCR2); 1795 1796 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1797 imx_uart_enable_ms(&sport->port); 1798 1799 spin_unlock_irqrestore(&sport->port.lock, flags); 1800 } 1801 1802 static const char *imx_uart_type(struct uart_port *port) 1803 { 1804 struct imx_port *sport = (struct imx_port *)port; 1805 1806 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1807 } 1808 1809 /* 1810 * Configure/autoconfigure the port. 1811 */ 1812 static void imx_uart_config_port(struct uart_port *port, int flags) 1813 { 1814 struct imx_port *sport = (struct imx_port *)port; 1815 1816 if (flags & UART_CONFIG_TYPE) 1817 sport->port.type = PORT_IMX; 1818 } 1819 1820 /* 1821 * Verify the new serial_struct (for TIOCSSERIAL). 1822 * The only change we allow are to the flags and type, and 1823 * even then only between PORT_IMX and PORT_UNKNOWN 1824 */ 1825 static int 1826 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1827 { 1828 struct imx_port *sport = (struct imx_port *)port; 1829 int ret = 0; 1830 1831 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1832 ret = -EINVAL; 1833 if (sport->port.irq != ser->irq) 1834 ret = -EINVAL; 1835 if (ser->io_type != UPIO_MEM) 1836 ret = -EINVAL; 1837 if (sport->port.uartclk / 16 != ser->baud_base) 1838 ret = -EINVAL; 1839 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1840 ret = -EINVAL; 1841 if (sport->port.iobase != ser->port) 1842 ret = -EINVAL; 1843 if (ser->hub6 != 0) 1844 ret = -EINVAL; 1845 return ret; 1846 } 1847 1848 #if defined(CONFIG_CONSOLE_POLL) 1849 1850 static int imx_uart_poll_init(struct uart_port *port) 1851 { 1852 struct imx_port *sport = (struct imx_port *)port; 1853 unsigned long flags; 1854 u32 ucr1, ucr2; 1855 int retval; 1856 1857 retval = clk_prepare_enable(sport->clk_ipg); 1858 if (retval) 1859 return retval; 1860 retval = clk_prepare_enable(sport->clk_per); 1861 if (retval) 1862 clk_disable_unprepare(sport->clk_ipg); 1863 1864 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1865 1866 spin_lock_irqsave(&sport->port.lock, flags); 1867 1868 /* 1869 * Be careful about the order of enabling bits here. First enable the 1870 * receiver (UARTEN + RXEN) and only then the corresponding irqs. 1871 * This prevents that a character that already sits in the RX fifo is 1872 * triggering an irq but the try to fetch it from there results in an 1873 * exception because UARTEN or RXEN is still off. 1874 */ 1875 ucr1 = imx_uart_readl(sport, UCR1); 1876 ucr2 = imx_uart_readl(sport, UCR2); 1877 1878 if (imx_uart_is_imx1(sport)) 1879 ucr1 |= IMX1_UCR1_UARTCLKEN; 1880 1881 ucr1 |= UCR1_UARTEN; 1882 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 1883 1884 ucr2 |= UCR2_RXEN; 1885 ucr2 &= ~UCR2_ATEN; 1886 1887 imx_uart_writel(sport, ucr1, UCR1); 1888 imx_uart_writel(sport, ucr2, UCR2); 1889 1890 /* now enable irqs */ 1891 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 1892 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 1893 1894 spin_unlock_irqrestore(&sport->port.lock, flags); 1895 1896 return 0; 1897 } 1898 1899 static int imx_uart_poll_get_char(struct uart_port *port) 1900 { 1901 struct imx_port *sport = (struct imx_port *)port; 1902 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 1903 return NO_POLL_CHAR; 1904 1905 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 1906 } 1907 1908 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 1909 { 1910 struct imx_port *sport = (struct imx_port *)port; 1911 unsigned int status; 1912 1913 /* drain */ 1914 do { 1915 status = imx_uart_readl(sport, USR1); 1916 } while (~status & USR1_TRDY); 1917 1918 /* write */ 1919 imx_uart_writel(sport, c, URTX0); 1920 1921 /* flush */ 1922 do { 1923 status = imx_uart_readl(sport, USR2); 1924 } while (~status & USR2_TXDC); 1925 } 1926 #endif 1927 1928 /* called with port.lock taken and irqs off or from .probe without locking */ 1929 static int imx_uart_rs485_config(struct uart_port *port, 1930 struct serial_rs485 *rs485conf) 1931 { 1932 struct imx_port *sport = (struct imx_port *)port; 1933 u32 ucr2; 1934 1935 /* RTS is required to control the transmitter */ 1936 if (!sport->have_rtscts && !sport->have_rtsgpio) 1937 rs485conf->flags &= ~SER_RS485_ENABLED; 1938 1939 if (rs485conf->flags & SER_RS485_ENABLED) { 1940 /* Enable receiver if low-active RTS signal is requested */ 1941 if (sport->have_rtscts && !sport->have_rtsgpio && 1942 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 1943 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1944 1945 /* disable transmitter */ 1946 ucr2 = imx_uart_readl(sport, UCR2); 1947 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1948 imx_uart_rts_active(sport, &ucr2); 1949 else 1950 imx_uart_rts_inactive(sport, &ucr2); 1951 imx_uart_writel(sport, ucr2, UCR2); 1952 } 1953 1954 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 1955 if (!(rs485conf->flags & SER_RS485_ENABLED) || 1956 rs485conf->flags & SER_RS485_RX_DURING_TX) 1957 imx_uart_start_rx(port); 1958 1959 port->rs485 = *rs485conf; 1960 1961 return 0; 1962 } 1963 1964 static const struct uart_ops imx_uart_pops = { 1965 .tx_empty = imx_uart_tx_empty, 1966 .set_mctrl = imx_uart_set_mctrl, 1967 .get_mctrl = imx_uart_get_mctrl, 1968 .stop_tx = imx_uart_stop_tx, 1969 .start_tx = imx_uart_start_tx, 1970 .stop_rx = imx_uart_stop_rx, 1971 .enable_ms = imx_uart_enable_ms, 1972 .break_ctl = imx_uart_break_ctl, 1973 .startup = imx_uart_startup, 1974 .shutdown = imx_uart_shutdown, 1975 .flush_buffer = imx_uart_flush_buffer, 1976 .set_termios = imx_uart_set_termios, 1977 .type = imx_uart_type, 1978 .config_port = imx_uart_config_port, 1979 .verify_port = imx_uart_verify_port, 1980 #if defined(CONFIG_CONSOLE_POLL) 1981 .poll_init = imx_uart_poll_init, 1982 .poll_get_char = imx_uart_poll_get_char, 1983 .poll_put_char = imx_uart_poll_put_char, 1984 #endif 1985 }; 1986 1987 static struct imx_port *imx_uart_ports[UART_NR]; 1988 1989 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 1990 static void imx_uart_console_putchar(struct uart_port *port, int ch) 1991 { 1992 struct imx_port *sport = (struct imx_port *)port; 1993 1994 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1995 barrier(); 1996 1997 imx_uart_writel(sport, ch, URTX0); 1998 } 1999 2000 /* 2001 * Interrupts are disabled on entering 2002 */ 2003 static void 2004 imx_uart_console_write(struct console *co, const char *s, unsigned int count) 2005 { 2006 struct imx_port *sport = imx_uart_ports[co->index]; 2007 struct imx_port_ucrs old_ucr; 2008 unsigned int ucr1; 2009 unsigned long flags = 0; 2010 int locked = 1; 2011 2012 if (sport->port.sysrq) 2013 locked = 0; 2014 else if (oops_in_progress) 2015 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2016 else 2017 spin_lock_irqsave(&sport->port.lock, flags); 2018 2019 /* 2020 * First, save UCR1/2/3 and then disable interrupts 2021 */ 2022 imx_uart_ucrs_save(sport, &old_ucr); 2023 ucr1 = old_ucr.ucr1; 2024 2025 if (imx_uart_is_imx1(sport)) 2026 ucr1 |= IMX1_UCR1_UARTCLKEN; 2027 ucr1 |= UCR1_UARTEN; 2028 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 2029 2030 imx_uart_writel(sport, ucr1, UCR1); 2031 2032 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2033 2034 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2035 2036 /* 2037 * Finally, wait for transmitter to become empty 2038 * and restore UCR1/2/3 2039 */ 2040 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2041 2042 imx_uart_ucrs_restore(sport, &old_ucr); 2043 2044 if (locked) 2045 spin_unlock_irqrestore(&sport->port.lock, flags); 2046 } 2047 2048 /* 2049 * If the port was already initialised (eg, by a boot loader), 2050 * try to determine the current setup. 2051 */ 2052 static void __init 2053 imx_uart_console_get_options(struct imx_port *sport, int *baud, 2054 int *parity, int *bits) 2055 { 2056 2057 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2058 /* ok, the port was enabled */ 2059 unsigned int ucr2, ubir, ubmr, uartclk; 2060 unsigned int baud_raw; 2061 unsigned int ucfr_rfdiv; 2062 2063 ucr2 = imx_uart_readl(sport, UCR2); 2064 2065 *parity = 'n'; 2066 if (ucr2 & UCR2_PREN) { 2067 if (ucr2 & UCR2_PROE) 2068 *parity = 'o'; 2069 else 2070 *parity = 'e'; 2071 } 2072 2073 if (ucr2 & UCR2_WS) 2074 *bits = 8; 2075 else 2076 *bits = 7; 2077 2078 ubir = imx_uart_readl(sport, UBIR) & 0xffff; 2079 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2080 2081 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2082 if (ucfr_rfdiv == 6) 2083 ucfr_rfdiv = 7; 2084 else 2085 ucfr_rfdiv = 6 - ucfr_rfdiv; 2086 2087 uartclk = clk_get_rate(sport->clk_per); 2088 uartclk /= ucfr_rfdiv; 2089 2090 { /* 2091 * The next code provides exact computation of 2092 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2093 * without need of float support or long long division, 2094 * which would be required to prevent 32bit arithmetic overflow 2095 */ 2096 unsigned int mul = ubir + 1; 2097 unsigned int div = 16 * (ubmr + 1); 2098 unsigned int rem = uartclk % div; 2099 2100 baud_raw = (uartclk / div) * mul; 2101 baud_raw += (rem * mul + div / 2) / div; 2102 *baud = (baud_raw + 50) / 100 * 100; 2103 } 2104 2105 if (*baud != baud_raw) 2106 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2107 baud_raw, *baud); 2108 } 2109 } 2110 2111 static int __init 2112 imx_uart_console_setup(struct console *co, char *options) 2113 { 2114 struct imx_port *sport; 2115 int baud = 9600; 2116 int bits = 8; 2117 int parity = 'n'; 2118 int flow = 'n'; 2119 int retval; 2120 2121 /* 2122 * Check whether an invalid uart number has been specified, and 2123 * if so, search for the first available port that does have 2124 * console support. 2125 */ 2126 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2127 co->index = 0; 2128 sport = imx_uart_ports[co->index]; 2129 if (sport == NULL) 2130 return -ENODEV; 2131 2132 /* For setting the registers, we only need to enable the ipg clock. */ 2133 retval = clk_prepare_enable(sport->clk_ipg); 2134 if (retval) 2135 goto error_console; 2136 2137 if (options) 2138 uart_parse_options(options, &baud, &parity, &bits, &flow); 2139 else 2140 imx_uart_console_get_options(sport, &baud, &parity, &bits); 2141 2142 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2143 2144 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 2145 2146 if (retval) { 2147 clk_disable_unprepare(sport->clk_ipg); 2148 goto error_console; 2149 } 2150 2151 retval = clk_prepare_enable(sport->clk_per); 2152 if (retval) 2153 clk_disable_unprepare(sport->clk_ipg); 2154 2155 error_console: 2156 return retval; 2157 } 2158 2159 static struct uart_driver imx_uart_uart_driver; 2160 static struct console imx_uart_console = { 2161 .name = DEV_NAME, 2162 .write = imx_uart_console_write, 2163 .device = uart_console_device, 2164 .setup = imx_uart_console_setup, 2165 .flags = CON_PRINTBUFFER, 2166 .index = -1, 2167 .data = &imx_uart_uart_driver, 2168 }; 2169 2170 #define IMX_CONSOLE &imx_uart_console 2171 2172 #else 2173 #define IMX_CONSOLE NULL 2174 #endif 2175 2176 static struct uart_driver imx_uart_uart_driver = { 2177 .owner = THIS_MODULE, 2178 .driver_name = DRIVER_NAME, 2179 .dev_name = DEV_NAME, 2180 .major = SERIAL_IMX_MAJOR, 2181 .minor = MINOR_START, 2182 .nr = ARRAY_SIZE(imx_uart_ports), 2183 .cons = IMX_CONSOLE, 2184 }; 2185 2186 #ifdef CONFIG_OF 2187 /* 2188 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 2189 * could successfully get all information from dt or a negative errno. 2190 */ 2191 static int imx_uart_probe_dt(struct imx_port *sport, 2192 struct platform_device *pdev) 2193 { 2194 struct device_node *np = pdev->dev.of_node; 2195 int ret; 2196 2197 sport->devdata = of_device_get_match_data(&pdev->dev); 2198 if (!sport->devdata) 2199 /* no device tree device */ 2200 return 1; 2201 2202 ret = of_alias_get_id(np, "serial"); 2203 if (ret < 0) { 2204 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2205 return ret; 2206 } 2207 sport->port.line = ret; 2208 2209 if (of_get_property(np, "uart-has-rtscts", NULL) || 2210 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 2211 sport->have_rtscts = 1; 2212 2213 if (of_get_property(np, "fsl,dte-mode", NULL)) 2214 sport->dte_mode = 1; 2215 2216 if (of_get_property(np, "rts-gpios", NULL)) 2217 sport->have_rtsgpio = 1; 2218 2219 if (of_get_property(np, "fsl,inverted-tx", NULL)) 2220 sport->inverted_tx = 1; 2221 2222 if (of_get_property(np, "fsl,inverted-rx", NULL)) 2223 sport->inverted_rx = 1; 2224 2225 return 0; 2226 } 2227 #else 2228 static inline int imx_uart_probe_dt(struct imx_port *sport, 2229 struct platform_device *pdev) 2230 { 2231 return 1; 2232 } 2233 #endif 2234 2235 static void imx_uart_probe_pdata(struct imx_port *sport, 2236 struct platform_device *pdev) 2237 { 2238 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 2239 2240 sport->port.line = pdev->id; 2241 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 2242 2243 if (!pdata) 2244 return; 2245 2246 if (pdata->flags & IMXUART_HAVE_RTSCTS) 2247 sport->have_rtscts = 1; 2248 } 2249 2250 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2251 { 2252 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2253 unsigned long flags; 2254 2255 spin_lock_irqsave(&sport->port.lock, flags); 2256 if (sport->tx_state == WAIT_AFTER_RTS) 2257 imx_uart_start_tx(&sport->port); 2258 spin_unlock_irqrestore(&sport->port.lock, flags); 2259 2260 return HRTIMER_NORESTART; 2261 } 2262 2263 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2264 { 2265 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2266 unsigned long flags; 2267 2268 spin_lock_irqsave(&sport->port.lock, flags); 2269 if (sport->tx_state == WAIT_AFTER_SEND) 2270 imx_uart_stop_tx(&sport->port); 2271 spin_unlock_irqrestore(&sport->port.lock, flags); 2272 2273 return HRTIMER_NORESTART; 2274 } 2275 2276 static int imx_uart_probe(struct platform_device *pdev) 2277 { 2278 struct imx_port *sport; 2279 void __iomem *base; 2280 int ret = 0; 2281 u32 ucr1; 2282 struct resource *res; 2283 int txirq, rxirq, rtsirq; 2284 2285 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2286 if (!sport) 2287 return -ENOMEM; 2288 2289 ret = imx_uart_probe_dt(sport, pdev); 2290 if (ret > 0) 2291 imx_uart_probe_pdata(sport, pdev); 2292 else if (ret < 0) 2293 return ret; 2294 2295 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 2296 dev_err(&pdev->dev, "serial%d out of range\n", 2297 sport->port.line); 2298 return -EINVAL; 2299 } 2300 2301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2302 base = devm_ioremap_resource(&pdev->dev, res); 2303 if (IS_ERR(base)) 2304 return PTR_ERR(base); 2305 2306 rxirq = platform_get_irq(pdev, 0); 2307 if (rxirq < 0) 2308 return rxirq; 2309 txirq = platform_get_irq_optional(pdev, 1); 2310 rtsirq = platform_get_irq_optional(pdev, 2); 2311 2312 sport->port.dev = &pdev->dev; 2313 sport->port.mapbase = res->start; 2314 sport->port.membase = base; 2315 sport->port.type = PORT_IMX, 2316 sport->port.iotype = UPIO_MEM; 2317 sport->port.irq = rxirq; 2318 sport->port.fifosize = 32; 2319 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 2320 sport->port.ops = &imx_uart_pops; 2321 sport->port.rs485_config = imx_uart_rs485_config; 2322 sport->port.flags = UPF_BOOT_AUTOCONF; 2323 timer_setup(&sport->timer, imx_uart_timeout, 0); 2324 2325 sport->gpios = mctrl_gpio_init(&sport->port, 0); 2326 if (IS_ERR(sport->gpios)) 2327 return PTR_ERR(sport->gpios); 2328 2329 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2330 if (IS_ERR(sport->clk_ipg)) { 2331 ret = PTR_ERR(sport->clk_ipg); 2332 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 2333 return ret; 2334 } 2335 2336 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 2337 if (IS_ERR(sport->clk_per)) { 2338 ret = PTR_ERR(sport->clk_per); 2339 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 2340 return ret; 2341 } 2342 2343 sport->port.uartclk = clk_get_rate(sport->clk_per); 2344 2345 /* For register access, we only need to enable the ipg clock. */ 2346 ret = clk_prepare_enable(sport->clk_ipg); 2347 if (ret) { 2348 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 2349 return ret; 2350 } 2351 2352 /* initialize shadow register values */ 2353 sport->ucr1 = readl(sport->port.membase + UCR1); 2354 sport->ucr2 = readl(sport->port.membase + UCR2); 2355 sport->ucr3 = readl(sport->port.membase + UCR3); 2356 sport->ucr4 = readl(sport->port.membase + UCR4); 2357 sport->ufcr = readl(sport->port.membase + UFCR); 2358 2359 ret = uart_get_rs485_mode(&sport->port); 2360 if (ret) { 2361 clk_disable_unprepare(sport->clk_ipg); 2362 return ret; 2363 } 2364 2365 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2366 (!sport->have_rtscts && !sport->have_rtsgpio)) 2367 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2368 2369 /* 2370 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 2371 * signal cannot be set low during transmission in case the 2372 * receiver is off (limitation of the i.MX UART IP). 2373 */ 2374 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2375 sport->have_rtscts && !sport->have_rtsgpio && 2376 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 2377 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 2378 dev_err(&pdev->dev, 2379 "low-active RTS not possible when receiver is off, enabling receiver\n"); 2380 2381 imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2382 2383 /* Disable interrupts before requesting them */ 2384 ucr1 = imx_uart_readl(sport, UCR1); 2385 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 2386 imx_uart_writel(sport, ucr1, UCR1); 2387 2388 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2389 /* 2390 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2391 * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2392 * and DCD (when they are outputs) or enables the respective 2393 * irqs. So set this bit early, i.e. before requesting irqs. 2394 */ 2395 u32 ufcr = imx_uart_readl(sport, UFCR); 2396 if (!(ufcr & UFCR_DCEDTE)) 2397 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2398 2399 /* 2400 * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2401 * enabled later because they cannot be cleared 2402 * (confirmed on i.MX25) which makes them unusable. 2403 */ 2404 imx_uart_writel(sport, 2405 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2406 UCR3); 2407 2408 } else { 2409 u32 ucr3 = UCR3_DSR; 2410 u32 ufcr = imx_uart_readl(sport, UFCR); 2411 if (ufcr & UFCR_DCEDTE) 2412 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 2413 2414 if (!imx_uart_is_imx1(sport)) 2415 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 2416 imx_uart_writel(sport, ucr3, UCR3); 2417 } 2418 2419 clk_disable_unprepare(sport->clk_ipg); 2420 2421 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2422 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2423 sport->trigger_start_tx.function = imx_trigger_start_tx; 2424 sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2425 2426 /* 2427 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2428 * chips only have one interrupt. 2429 */ 2430 if (txirq > 0) { 2431 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2432 dev_name(&pdev->dev), sport); 2433 if (ret) { 2434 dev_err(&pdev->dev, "failed to request rx irq: %d\n", 2435 ret); 2436 return ret; 2437 } 2438 2439 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2440 dev_name(&pdev->dev), sport); 2441 if (ret) { 2442 dev_err(&pdev->dev, "failed to request tx irq: %d\n", 2443 ret); 2444 return ret; 2445 } 2446 2447 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 2448 dev_name(&pdev->dev), sport); 2449 if (ret) { 2450 dev_err(&pdev->dev, "failed to request rts irq: %d\n", 2451 ret); 2452 return ret; 2453 } 2454 } else { 2455 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2456 dev_name(&pdev->dev), sport); 2457 if (ret) { 2458 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2459 return ret; 2460 } 2461 } 2462 2463 imx_uart_ports[sport->port.line] = sport; 2464 2465 platform_set_drvdata(pdev, sport); 2466 2467 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2468 } 2469 2470 static int imx_uart_remove(struct platform_device *pdev) 2471 { 2472 struct imx_port *sport = platform_get_drvdata(pdev); 2473 2474 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2475 } 2476 2477 static void imx_uart_restore_context(struct imx_port *sport) 2478 { 2479 unsigned long flags; 2480 2481 spin_lock_irqsave(&sport->port.lock, flags); 2482 if (!sport->context_saved) { 2483 spin_unlock_irqrestore(&sport->port.lock, flags); 2484 return; 2485 } 2486 2487 imx_uart_writel(sport, sport->saved_reg[4], UFCR); 2488 imx_uart_writel(sport, sport->saved_reg[5], UESC); 2489 imx_uart_writel(sport, sport->saved_reg[6], UTIM); 2490 imx_uart_writel(sport, sport->saved_reg[7], UBIR); 2491 imx_uart_writel(sport, sport->saved_reg[8], UBMR); 2492 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 2493 imx_uart_writel(sport, sport->saved_reg[0], UCR1); 2494 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 2495 imx_uart_writel(sport, sport->saved_reg[2], UCR3); 2496 imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2497 sport->context_saved = false; 2498 spin_unlock_irqrestore(&sport->port.lock, flags); 2499 } 2500 2501 static void imx_uart_save_context(struct imx_port *sport) 2502 { 2503 unsigned long flags; 2504 2505 /* Save necessary regs */ 2506 spin_lock_irqsave(&sport->port.lock, flags); 2507 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 2508 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 2509 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 2510 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 2511 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 2512 sport->saved_reg[5] = imx_uart_readl(sport, UESC); 2513 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 2514 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 2515 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 2516 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2517 sport->context_saved = true; 2518 spin_unlock_irqrestore(&sport->port.lock, flags); 2519 } 2520 2521 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2522 { 2523 u32 ucr3; 2524 2525 ucr3 = imx_uart_readl(sport, UCR3); 2526 if (on) { 2527 imx_uart_writel(sport, USR1_AWAKE, USR1); 2528 ucr3 |= UCR3_AWAKEN; 2529 } else { 2530 ucr3 &= ~UCR3_AWAKEN; 2531 } 2532 imx_uart_writel(sport, ucr3, UCR3); 2533 2534 if (sport->have_rtscts) { 2535 u32 ucr1 = imx_uart_readl(sport, UCR1); 2536 if (on) 2537 ucr1 |= UCR1_RTSDEN; 2538 else 2539 ucr1 &= ~UCR1_RTSDEN; 2540 imx_uart_writel(sport, ucr1, UCR1); 2541 } 2542 } 2543 2544 static int imx_uart_suspend_noirq(struct device *dev) 2545 { 2546 struct imx_port *sport = dev_get_drvdata(dev); 2547 2548 imx_uart_save_context(sport); 2549 2550 clk_disable(sport->clk_ipg); 2551 2552 pinctrl_pm_select_sleep_state(dev); 2553 2554 return 0; 2555 } 2556 2557 static int imx_uart_resume_noirq(struct device *dev) 2558 { 2559 struct imx_port *sport = dev_get_drvdata(dev); 2560 int ret; 2561 2562 pinctrl_pm_select_default_state(dev); 2563 2564 ret = clk_enable(sport->clk_ipg); 2565 if (ret) 2566 return ret; 2567 2568 imx_uart_restore_context(sport); 2569 2570 return 0; 2571 } 2572 2573 static int imx_uart_suspend(struct device *dev) 2574 { 2575 struct imx_port *sport = dev_get_drvdata(dev); 2576 int ret; 2577 2578 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2579 disable_irq(sport->port.irq); 2580 2581 ret = clk_prepare_enable(sport->clk_ipg); 2582 if (ret) 2583 return ret; 2584 2585 /* enable wakeup from i.MX UART */ 2586 imx_uart_enable_wakeup(sport, true); 2587 2588 return 0; 2589 } 2590 2591 static int imx_uart_resume(struct device *dev) 2592 { 2593 struct imx_port *sport = dev_get_drvdata(dev); 2594 2595 /* disable wakeup from i.MX UART */ 2596 imx_uart_enable_wakeup(sport, false); 2597 2598 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2599 enable_irq(sport->port.irq); 2600 2601 clk_disable_unprepare(sport->clk_ipg); 2602 2603 return 0; 2604 } 2605 2606 static int imx_uart_freeze(struct device *dev) 2607 { 2608 struct imx_port *sport = dev_get_drvdata(dev); 2609 2610 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2611 2612 return clk_prepare_enable(sport->clk_ipg); 2613 } 2614 2615 static int imx_uart_thaw(struct device *dev) 2616 { 2617 struct imx_port *sport = dev_get_drvdata(dev); 2618 2619 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2620 2621 clk_disable_unprepare(sport->clk_ipg); 2622 2623 return 0; 2624 } 2625 2626 static const struct dev_pm_ops imx_uart_pm_ops = { 2627 .suspend_noirq = imx_uart_suspend_noirq, 2628 .resume_noirq = imx_uart_resume_noirq, 2629 .freeze_noirq = imx_uart_suspend_noirq, 2630 .restore_noirq = imx_uart_resume_noirq, 2631 .suspend = imx_uart_suspend, 2632 .resume = imx_uart_resume, 2633 .freeze = imx_uart_freeze, 2634 .thaw = imx_uart_thaw, 2635 .restore = imx_uart_thaw, 2636 }; 2637 2638 static struct platform_driver imx_uart_platform_driver = { 2639 .probe = imx_uart_probe, 2640 .remove = imx_uart_remove, 2641 2642 .id_table = imx_uart_devtype, 2643 .driver = { 2644 .name = "imx-uart", 2645 .of_match_table = imx_uart_dt_ids, 2646 .pm = &imx_uart_pm_ops, 2647 }, 2648 }; 2649 2650 static int __init imx_uart_init(void) 2651 { 2652 int ret = uart_register_driver(&imx_uart_uart_driver); 2653 2654 if (ret) 2655 return ret; 2656 2657 ret = platform_driver_register(&imx_uart_platform_driver); 2658 if (ret != 0) 2659 uart_unregister_driver(&imx_uart_uart_driver); 2660 2661 return ret; 2662 } 2663 2664 static void __exit imx_uart_exit(void) 2665 { 2666 platform_driver_unregister(&imx_uart_platform_driver); 2667 uart_unregister_driver(&imx_uart_uart_driver); 2668 } 2669 2670 module_init(imx_uart_init); 2671 module_exit(imx_uart_exit); 2672 2673 MODULE_AUTHOR("Sascha Hauer"); 2674 MODULE_DESCRIPTION("IMX generic serial port driver"); 2675 MODULE_LICENSE("GPL"); 2676 MODULE_ALIAS("platform:imx-uart"); 2677