1 /* 2 * Driver for Motorola IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * Copyright (C) 2009 emlix GmbH 10 * Author: Fabian Godehardt (added IrDA support for iMX) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 * [29-Mar-2005] Mike Lee 27 * Added hardware handshake 28 */ 29 30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31 #define SUPPORT_SYSRQ 32 #endif 33 34 #include <linux/module.h> 35 #include <linux/ioport.h> 36 #include <linux/init.h> 37 #include <linux/console.h> 38 #include <linux/sysrq.h> 39 #include <linux/platform_device.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/serial_core.h> 43 #include <linux/serial.h> 44 #include <linux/clk.h> 45 #include <linux/delay.h> 46 #include <linux/rational.h> 47 #include <linux/slab.h> 48 #include <linux/of.h> 49 #include <linux/of_device.h> 50 51 #include <asm/io.h> 52 #include <asm/irq.h> 53 #include <mach/imx-uart.h> 54 55 /* Register definitions */ 56 #define URXD0 0x0 /* Receiver Register */ 57 #define URTX0 0x40 /* Transmitter Register */ 58 #define UCR1 0x80 /* Control Register 1 */ 59 #define UCR2 0x84 /* Control Register 2 */ 60 #define UCR3 0x88 /* Control Register 3 */ 61 #define UCR4 0x8c /* Control Register 4 */ 62 #define UFCR 0x90 /* FIFO Control Register */ 63 #define USR1 0x94 /* Status Register 1 */ 64 #define USR2 0x98 /* Status Register 2 */ 65 #define UESC 0x9c /* Escape Character Register */ 66 #define UTIM 0xa0 /* Escape Timer Register */ 67 #define UBIR 0xa4 /* BRM Incremental Register */ 68 #define UBMR 0xa8 /* BRM Modulator Register */ 69 #define UBRC 0xac /* Baud Rate Count Register */ 70 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 71 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 72 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 73 74 /* UART Control Register Bit Fields.*/ 75 #define URXD_CHARRDY (1<<15) 76 #define URXD_ERR (1<<14) 77 #define URXD_OVRRUN (1<<13) 78 #define URXD_FRMERR (1<<12) 79 #define URXD_BRK (1<<11) 80 #define URXD_PRERR (1<<10) 81 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 87 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 90 #define UCR1_SNDBRK (1<<4) /* Send break */ 91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 92 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 93 #define UCR1_DOZE (1<<1) /* Doze */ 94 #define UCR1_UARTEN (1<<0) /* UART enabled */ 95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 97 #define UCR2_CTSC (1<<13) /* CTS pin control */ 98 #define UCR2_CTS (1<<12) /* Clear to send */ 99 #define UCR2_ESCEN (1<<11) /* Escape enable */ 100 #define UCR2_PREN (1<<8) /* Parity enable */ 101 #define UCR2_PROE (1<<7) /* Parity odd/even */ 102 #define UCR2_STPB (1<<6) /* Stop */ 103 #define UCR2_WS (1<<5) /* Word size */ 104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 106 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 107 #define UCR2_SRST (1<<0) /* SW reset */ 108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 109 #define UCR3_PARERREN (1<<12) /* Parity enable */ 110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 111 #define UCR3_DSR (1<<10) /* Data set ready */ 112 #define UCR3_DCD (1<<9) /* Data carrier detect */ 113 #define UCR3_RI (1<<8) /* Ring indicator */ 114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 118 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 120 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 127 #define UCR4_IRSC (1<<5) /* IR special case */ 128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 134 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 135 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 136 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 137 #define USR1_RTSS (1<<14) /* RTS pin status */ 138 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 139 #define USR1_RTSD (1<<12) /* RTS delta */ 140 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 141 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 142 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 143 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 144 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 145 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 146 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 147 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 148 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 149 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 150 #define USR2_IDLE (1<<12) /* Idle condition */ 151 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 152 #define USR2_WAKE (1<<7) /* Wake */ 153 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 154 #define USR2_TXDC (1<<3) /* Transmitter complete */ 155 #define USR2_BRCD (1<<2) /* Break condition */ 156 #define USR2_ORE (1<<1) /* Overrun error */ 157 #define USR2_RDR (1<<0) /* Recv data ready */ 158 #define UTS_FRCPERR (1<<13) /* Force parity error */ 159 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 160 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 161 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 162 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 163 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 164 #define UTS_SOFTRST (1<<0) /* Software reset */ 165 166 /* We've been assigned a range on the "Low-density serial ports" major */ 167 #define SERIAL_IMX_MAJOR 207 168 #define MINOR_START 16 169 #define DEV_NAME "ttymxc" 170 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS 171 172 /* 173 * This determines how often we check the modem status signals 174 * for any change. They generally aren't connected to an IRQ 175 * so we have to poll them. We also check immediately before 176 * filling the TX fifo incase CTS has been dropped. 177 */ 178 #define MCTRL_TIMEOUT (250*HZ/1000) 179 180 #define DRIVER_NAME "IMX-uart" 181 182 #define UART_NR 8 183 184 /* i.mx21 type uart runs on all i.mx except i.mx1 */ 185 enum imx_uart_type { 186 IMX1_UART, 187 IMX21_UART, 188 }; 189 190 /* device type dependent stuff */ 191 struct imx_uart_data { 192 unsigned uts_reg; 193 enum imx_uart_type devtype; 194 }; 195 196 struct imx_port { 197 struct uart_port port; 198 struct timer_list timer; 199 unsigned int old_status; 200 int txirq,rxirq,rtsirq; 201 unsigned int have_rtscts:1; 202 unsigned int use_irda:1; 203 unsigned int irda_inv_rx:1; 204 unsigned int irda_inv_tx:1; 205 unsigned short trcv_delay; /* transceiver delay */ 206 struct clk *clk; 207 struct imx_uart_data *devdata; 208 }; 209 210 #ifdef CONFIG_IRDA 211 #define USE_IRDA(sport) ((sport)->use_irda) 212 #else 213 #define USE_IRDA(sport) (0) 214 #endif 215 216 static struct imx_uart_data imx_uart_devdata[] = { 217 [IMX1_UART] = { 218 .uts_reg = IMX1_UTS, 219 .devtype = IMX1_UART, 220 }, 221 [IMX21_UART] = { 222 .uts_reg = IMX21_UTS, 223 .devtype = IMX21_UART, 224 }, 225 }; 226 227 static struct platform_device_id imx_uart_devtype[] = { 228 { 229 .name = "imx1-uart", 230 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 231 }, { 232 .name = "imx21-uart", 233 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 234 }, { 235 /* sentinel */ 236 } 237 }; 238 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 239 240 static struct of_device_id imx_uart_dt_ids[] = { 241 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 242 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 243 { /* sentinel */ } 244 }; 245 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 246 247 static inline unsigned uts_reg(struct imx_port *sport) 248 { 249 return sport->devdata->uts_reg; 250 } 251 252 static inline int is_imx1_uart(struct imx_port *sport) 253 { 254 return sport->devdata->devtype == IMX1_UART; 255 } 256 257 static inline int is_imx21_uart(struct imx_port *sport) 258 { 259 return sport->devdata->devtype == IMX21_UART; 260 } 261 262 /* 263 * Handle any change of modem status signal since we were last called. 264 */ 265 static void imx_mctrl_check(struct imx_port *sport) 266 { 267 unsigned int status, changed; 268 269 status = sport->port.ops->get_mctrl(&sport->port); 270 changed = status ^ sport->old_status; 271 272 if (changed == 0) 273 return; 274 275 sport->old_status = status; 276 277 if (changed & TIOCM_RI) 278 sport->port.icount.rng++; 279 if (changed & TIOCM_DSR) 280 sport->port.icount.dsr++; 281 if (changed & TIOCM_CAR) 282 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 283 if (changed & TIOCM_CTS) 284 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 285 286 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 287 } 288 289 /* 290 * This is our per-port timeout handler, for checking the 291 * modem status signals. 292 */ 293 static void imx_timeout(unsigned long data) 294 { 295 struct imx_port *sport = (struct imx_port *)data; 296 unsigned long flags; 297 298 if (sport->port.state) { 299 spin_lock_irqsave(&sport->port.lock, flags); 300 imx_mctrl_check(sport); 301 spin_unlock_irqrestore(&sport->port.lock, flags); 302 303 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 304 } 305 } 306 307 /* 308 * interrupts disabled on entry 309 */ 310 static void imx_stop_tx(struct uart_port *port) 311 { 312 struct imx_port *sport = (struct imx_port *)port; 313 unsigned long temp; 314 315 if (USE_IRDA(sport)) { 316 /* half duplex - wait for end of transmission */ 317 int n = 256; 318 while ((--n > 0) && 319 !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 320 udelay(5); 321 barrier(); 322 } 323 /* 324 * irda transceiver - wait a bit more to avoid 325 * cutoff, hardware dependent 326 */ 327 udelay(sport->trcv_delay); 328 329 /* 330 * half duplex - reactivate receive mode, 331 * flush receive pipe echo crap 332 */ 333 if (readl(sport->port.membase + USR2) & USR2_TXDC) { 334 temp = readl(sport->port.membase + UCR1); 335 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 336 writel(temp, sport->port.membase + UCR1); 337 338 temp = readl(sport->port.membase + UCR4); 339 temp &= ~(UCR4_TCEN); 340 writel(temp, sport->port.membase + UCR4); 341 342 while (readl(sport->port.membase + URXD0) & 343 URXD_CHARRDY) 344 barrier(); 345 346 temp = readl(sport->port.membase + UCR1); 347 temp |= UCR1_RRDYEN; 348 writel(temp, sport->port.membase + UCR1); 349 350 temp = readl(sport->port.membase + UCR4); 351 temp |= UCR4_DREN; 352 writel(temp, sport->port.membase + UCR4); 353 } 354 return; 355 } 356 357 temp = readl(sport->port.membase + UCR1); 358 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 359 } 360 361 /* 362 * interrupts disabled on entry 363 */ 364 static void imx_stop_rx(struct uart_port *port) 365 { 366 struct imx_port *sport = (struct imx_port *)port; 367 unsigned long temp; 368 369 temp = readl(sport->port.membase + UCR2); 370 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2); 371 } 372 373 /* 374 * Set the modem control timer to fire immediately. 375 */ 376 static void imx_enable_ms(struct uart_port *port) 377 { 378 struct imx_port *sport = (struct imx_port *)port; 379 380 mod_timer(&sport->timer, jiffies); 381 } 382 383 static inline void imx_transmit_buffer(struct imx_port *sport) 384 { 385 struct circ_buf *xmit = &sport->port.state->xmit; 386 387 while (!uart_circ_empty(xmit) && 388 !(readl(sport->port.membase + uts_reg(sport)) 389 & UTS_TXFULL)) { 390 /* send xmit->buf[xmit->tail] 391 * out the port here */ 392 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 393 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 394 sport->port.icount.tx++; 395 } 396 397 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 398 uart_write_wakeup(&sport->port); 399 400 if (uart_circ_empty(xmit)) 401 imx_stop_tx(&sport->port); 402 } 403 404 /* 405 * interrupts disabled on entry 406 */ 407 static void imx_start_tx(struct uart_port *port) 408 { 409 struct imx_port *sport = (struct imx_port *)port; 410 unsigned long temp; 411 412 if (USE_IRDA(sport)) { 413 /* half duplex in IrDA mode; have to disable receive mode */ 414 temp = readl(sport->port.membase + UCR4); 415 temp &= ~(UCR4_DREN); 416 writel(temp, sport->port.membase + UCR4); 417 418 temp = readl(sport->port.membase + UCR1); 419 temp &= ~(UCR1_RRDYEN); 420 writel(temp, sport->port.membase + UCR1); 421 } 422 423 temp = readl(sport->port.membase + UCR1); 424 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 425 426 if (USE_IRDA(sport)) { 427 temp = readl(sport->port.membase + UCR1); 428 temp |= UCR1_TRDYEN; 429 writel(temp, sport->port.membase + UCR1); 430 431 temp = readl(sport->port.membase + UCR4); 432 temp |= UCR4_TCEN; 433 writel(temp, sport->port.membase + UCR4); 434 } 435 436 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) 437 imx_transmit_buffer(sport); 438 } 439 440 static irqreturn_t imx_rtsint(int irq, void *dev_id) 441 { 442 struct imx_port *sport = dev_id; 443 unsigned int val; 444 unsigned long flags; 445 446 spin_lock_irqsave(&sport->port.lock, flags); 447 448 writel(USR1_RTSD, sport->port.membase + USR1); 449 val = readl(sport->port.membase + USR1) & USR1_RTSS; 450 uart_handle_cts_change(&sport->port, !!val); 451 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 452 453 spin_unlock_irqrestore(&sport->port.lock, flags); 454 return IRQ_HANDLED; 455 } 456 457 static irqreturn_t imx_txint(int irq, void *dev_id) 458 { 459 struct imx_port *sport = dev_id; 460 struct circ_buf *xmit = &sport->port.state->xmit; 461 unsigned long flags; 462 463 spin_lock_irqsave(&sport->port.lock,flags); 464 if (sport->port.x_char) 465 { 466 /* Send next char */ 467 writel(sport->port.x_char, sport->port.membase + URTX0); 468 goto out; 469 } 470 471 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 472 imx_stop_tx(&sport->port); 473 goto out; 474 } 475 476 imx_transmit_buffer(sport); 477 478 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 479 uart_write_wakeup(&sport->port); 480 481 out: 482 spin_unlock_irqrestore(&sport->port.lock,flags); 483 return IRQ_HANDLED; 484 } 485 486 static irqreturn_t imx_rxint(int irq, void *dev_id) 487 { 488 struct imx_port *sport = dev_id; 489 unsigned int rx,flg,ignored = 0; 490 struct tty_struct *tty = sport->port.state->port.tty; 491 unsigned long flags, temp; 492 493 spin_lock_irqsave(&sport->port.lock,flags); 494 495 while (readl(sport->port.membase + USR2) & USR2_RDR) { 496 flg = TTY_NORMAL; 497 sport->port.icount.rx++; 498 499 rx = readl(sport->port.membase + URXD0); 500 501 temp = readl(sport->port.membase + USR2); 502 if (temp & USR2_BRCD) { 503 writel(USR2_BRCD, sport->port.membase + USR2); 504 if (uart_handle_break(&sport->port)) 505 continue; 506 } 507 508 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 509 continue; 510 511 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) { 512 if (rx & URXD_PRERR) 513 sport->port.icount.parity++; 514 else if (rx & URXD_FRMERR) 515 sport->port.icount.frame++; 516 if (rx & URXD_OVRRUN) 517 sport->port.icount.overrun++; 518 519 if (rx & sport->port.ignore_status_mask) { 520 if (++ignored > 100) 521 goto out; 522 continue; 523 } 524 525 rx &= sport->port.read_status_mask; 526 527 if (rx & URXD_PRERR) 528 flg = TTY_PARITY; 529 else if (rx & URXD_FRMERR) 530 flg = TTY_FRAME; 531 if (rx & URXD_OVRRUN) 532 flg = TTY_OVERRUN; 533 534 #ifdef SUPPORT_SYSRQ 535 sport->port.sysrq = 0; 536 #endif 537 } 538 539 tty_insert_flip_char(tty, rx, flg); 540 } 541 542 out: 543 spin_unlock_irqrestore(&sport->port.lock,flags); 544 tty_flip_buffer_push(tty); 545 return IRQ_HANDLED; 546 } 547 548 static irqreturn_t imx_int(int irq, void *dev_id) 549 { 550 struct imx_port *sport = dev_id; 551 unsigned int sts; 552 553 sts = readl(sport->port.membase + USR1); 554 555 if (sts & USR1_RRDY) 556 imx_rxint(irq, dev_id); 557 558 if (sts & USR1_TRDY && 559 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 560 imx_txint(irq, dev_id); 561 562 if (sts & USR1_RTSD) 563 imx_rtsint(irq, dev_id); 564 565 return IRQ_HANDLED; 566 } 567 568 /* 569 * Return TIOCSER_TEMT when transmitter is not busy. 570 */ 571 static unsigned int imx_tx_empty(struct uart_port *port) 572 { 573 struct imx_port *sport = (struct imx_port *)port; 574 575 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 576 } 577 578 /* 579 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 580 */ 581 static unsigned int imx_get_mctrl(struct uart_port *port) 582 { 583 struct imx_port *sport = (struct imx_port *)port; 584 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 585 586 if (readl(sport->port.membase + USR1) & USR1_RTSS) 587 tmp |= TIOCM_CTS; 588 589 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 590 tmp |= TIOCM_RTS; 591 592 return tmp; 593 } 594 595 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 596 { 597 struct imx_port *sport = (struct imx_port *)port; 598 unsigned long temp; 599 600 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; 601 602 if (mctrl & TIOCM_RTS) 603 temp |= UCR2_CTS; 604 605 writel(temp, sport->port.membase + UCR2); 606 } 607 608 /* 609 * Interrupts always disabled. 610 */ 611 static void imx_break_ctl(struct uart_port *port, int break_state) 612 { 613 struct imx_port *sport = (struct imx_port *)port; 614 unsigned long flags, temp; 615 616 spin_lock_irqsave(&sport->port.lock, flags); 617 618 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 619 620 if ( break_state != 0 ) 621 temp |= UCR1_SNDBRK; 622 623 writel(temp, sport->port.membase + UCR1); 624 625 spin_unlock_irqrestore(&sport->port.lock, flags); 626 } 627 628 #define TXTL 2 /* reset default */ 629 #define RXTL 1 /* reset default */ 630 631 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 632 { 633 unsigned int val; 634 unsigned int ufcr_rfdiv; 635 636 /* set receiver / transmitter trigger level. 637 * RFDIV is set such way to satisfy requested uartclk value 638 */ 639 val = TXTL << 10 | RXTL; 640 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2) 641 / sport->port.uartclk; 642 643 if(!ufcr_rfdiv) 644 ufcr_rfdiv = 1; 645 646 val |= UFCR_RFDIV_REG(ufcr_rfdiv); 647 648 writel(val, sport->port.membase + UFCR); 649 650 return 0; 651 } 652 653 /* half the RX buffer size */ 654 #define CTSTL 16 655 656 static int imx_startup(struct uart_port *port) 657 { 658 struct imx_port *sport = (struct imx_port *)port; 659 int retval; 660 unsigned long flags, temp; 661 662 imx_setup_ufcr(sport, 0); 663 664 /* disable the DREN bit (Data Ready interrupt enable) before 665 * requesting IRQs 666 */ 667 temp = readl(sport->port.membase + UCR4); 668 669 if (USE_IRDA(sport)) 670 temp |= UCR4_IRSC; 671 672 /* set the trigger level for CTS */ 673 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF); 674 temp |= CTSTL<< UCR4_CTSTL_SHF; 675 676 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 677 678 if (USE_IRDA(sport)) { 679 /* reset fifo's and state machines */ 680 int i = 100; 681 temp = readl(sport->port.membase + UCR2); 682 temp &= ~UCR2_SRST; 683 writel(temp, sport->port.membase + UCR2); 684 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && 685 (--i > 0)) { 686 udelay(1); 687 } 688 } 689 690 /* 691 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 692 * chips only have one interrupt. 693 */ 694 if (sport->txirq > 0) { 695 retval = request_irq(sport->rxirq, imx_rxint, 0, 696 DRIVER_NAME, sport); 697 if (retval) 698 goto error_out1; 699 700 retval = request_irq(sport->txirq, imx_txint, 0, 701 DRIVER_NAME, sport); 702 if (retval) 703 goto error_out2; 704 705 /* do not use RTS IRQ on IrDA */ 706 if (!USE_IRDA(sport)) { 707 retval = request_irq(sport->rtsirq, imx_rtsint, 708 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : 709 IRQF_TRIGGER_FALLING | 710 IRQF_TRIGGER_RISING, 711 DRIVER_NAME, sport); 712 if (retval) 713 goto error_out3; 714 } 715 } else { 716 retval = request_irq(sport->port.irq, imx_int, 0, 717 DRIVER_NAME, sport); 718 if (retval) { 719 free_irq(sport->port.irq, sport); 720 goto error_out1; 721 } 722 } 723 724 /* 725 * Finally, clear and enable interrupts 726 */ 727 writel(USR1_RTSD, sport->port.membase + USR1); 728 729 temp = readl(sport->port.membase + UCR1); 730 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 731 732 if (USE_IRDA(sport)) { 733 temp |= UCR1_IREN; 734 temp &= ~(UCR1_RTSDEN); 735 } 736 737 writel(temp, sport->port.membase + UCR1); 738 739 temp = readl(sport->port.membase + UCR2); 740 temp |= (UCR2_RXEN | UCR2_TXEN); 741 writel(temp, sport->port.membase + UCR2); 742 743 if (USE_IRDA(sport)) { 744 /* clear RX-FIFO */ 745 int i = 64; 746 while ((--i > 0) && 747 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { 748 barrier(); 749 } 750 } 751 752 if (is_imx21_uart(sport)) { 753 temp = readl(sport->port.membase + UCR3); 754 temp |= IMX21_UCR3_RXDMUXSEL; 755 writel(temp, sport->port.membase + UCR3); 756 } 757 758 if (USE_IRDA(sport)) { 759 temp = readl(sport->port.membase + UCR4); 760 if (sport->irda_inv_rx) 761 temp |= UCR4_INVR; 762 else 763 temp &= ~(UCR4_INVR); 764 writel(temp | UCR4_DREN, sport->port.membase + UCR4); 765 766 temp = readl(sport->port.membase + UCR3); 767 if (sport->irda_inv_tx) 768 temp |= UCR3_INVT; 769 else 770 temp &= ~(UCR3_INVT); 771 writel(temp, sport->port.membase + UCR3); 772 } 773 774 /* 775 * Enable modem status interrupts 776 */ 777 spin_lock_irqsave(&sport->port.lock,flags); 778 imx_enable_ms(&sport->port); 779 spin_unlock_irqrestore(&sport->port.lock,flags); 780 781 if (USE_IRDA(sport)) { 782 struct imxuart_platform_data *pdata; 783 pdata = sport->port.dev->platform_data; 784 sport->irda_inv_rx = pdata->irda_inv_rx; 785 sport->irda_inv_tx = pdata->irda_inv_tx; 786 sport->trcv_delay = pdata->transceiver_delay; 787 if (pdata->irda_enable) 788 pdata->irda_enable(1); 789 } 790 791 return 0; 792 793 error_out3: 794 if (sport->txirq) 795 free_irq(sport->txirq, sport); 796 error_out2: 797 if (sport->rxirq) 798 free_irq(sport->rxirq, sport); 799 error_out1: 800 return retval; 801 } 802 803 static void imx_shutdown(struct uart_port *port) 804 { 805 struct imx_port *sport = (struct imx_port *)port; 806 unsigned long temp; 807 808 temp = readl(sport->port.membase + UCR2); 809 temp &= ~(UCR2_TXEN); 810 writel(temp, sport->port.membase + UCR2); 811 812 if (USE_IRDA(sport)) { 813 struct imxuart_platform_data *pdata; 814 pdata = sport->port.dev->platform_data; 815 if (pdata->irda_enable) 816 pdata->irda_enable(0); 817 } 818 819 /* 820 * Stop our timer. 821 */ 822 del_timer_sync(&sport->timer); 823 824 /* 825 * Free the interrupts 826 */ 827 if (sport->txirq > 0) { 828 if (!USE_IRDA(sport)) 829 free_irq(sport->rtsirq, sport); 830 free_irq(sport->txirq, sport); 831 free_irq(sport->rxirq, sport); 832 } else 833 free_irq(sport->port.irq, sport); 834 835 /* 836 * Disable all interrupts, port and break condition. 837 */ 838 839 temp = readl(sport->port.membase + UCR1); 840 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 841 if (USE_IRDA(sport)) 842 temp &= ~(UCR1_IREN); 843 844 writel(temp, sport->port.membase + UCR1); 845 } 846 847 static void 848 imx_set_termios(struct uart_port *port, struct ktermios *termios, 849 struct ktermios *old) 850 { 851 struct imx_port *sport = (struct imx_port *)port; 852 unsigned long flags; 853 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 854 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 855 unsigned int div, ufcr; 856 unsigned long num, denom; 857 uint64_t tdiv64; 858 859 /* 860 * If we don't support modem control lines, don't allow 861 * these to be set. 862 */ 863 if (0) { 864 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 865 termios->c_cflag |= CLOCAL; 866 } 867 868 /* 869 * We only support CS7 and CS8. 870 */ 871 while ((termios->c_cflag & CSIZE) != CS7 && 872 (termios->c_cflag & CSIZE) != CS8) { 873 termios->c_cflag &= ~CSIZE; 874 termios->c_cflag |= old_csize; 875 old_csize = CS8; 876 } 877 878 if ((termios->c_cflag & CSIZE) == CS8) 879 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 880 else 881 ucr2 = UCR2_SRST | UCR2_IRTS; 882 883 if (termios->c_cflag & CRTSCTS) { 884 if( sport->have_rtscts ) { 885 ucr2 &= ~UCR2_IRTS; 886 ucr2 |= UCR2_CTSC; 887 } else { 888 termios->c_cflag &= ~CRTSCTS; 889 } 890 } 891 892 if (termios->c_cflag & CSTOPB) 893 ucr2 |= UCR2_STPB; 894 if (termios->c_cflag & PARENB) { 895 ucr2 |= UCR2_PREN; 896 if (termios->c_cflag & PARODD) 897 ucr2 |= UCR2_PROE; 898 } 899 900 /* 901 * Ask the core to calculate the divisor for us. 902 */ 903 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 904 quot = uart_get_divisor(port, baud); 905 906 spin_lock_irqsave(&sport->port.lock, flags); 907 908 sport->port.read_status_mask = 0; 909 if (termios->c_iflag & INPCK) 910 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 911 if (termios->c_iflag & (BRKINT | PARMRK)) 912 sport->port.read_status_mask |= URXD_BRK; 913 914 /* 915 * Characters to ignore 916 */ 917 sport->port.ignore_status_mask = 0; 918 if (termios->c_iflag & IGNPAR) 919 sport->port.ignore_status_mask |= URXD_PRERR; 920 if (termios->c_iflag & IGNBRK) { 921 sport->port.ignore_status_mask |= URXD_BRK; 922 /* 923 * If we're ignoring parity and break indicators, 924 * ignore overruns too (for real raw support). 925 */ 926 if (termios->c_iflag & IGNPAR) 927 sport->port.ignore_status_mask |= URXD_OVRRUN; 928 } 929 930 del_timer_sync(&sport->timer); 931 932 /* 933 * Update the per-port timeout. 934 */ 935 uart_update_timeout(port, termios->c_cflag, baud); 936 937 /* 938 * disable interrupts and drain transmitter 939 */ 940 old_ucr1 = readl(sport->port.membase + UCR1); 941 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 942 sport->port.membase + UCR1); 943 944 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC)) 945 barrier(); 946 947 /* then, disable everything */ 948 old_txrxen = readl(sport->port.membase + UCR2); 949 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN), 950 sport->port.membase + UCR2); 951 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 952 953 if (USE_IRDA(sport)) { 954 /* 955 * use maximum available submodule frequency to 956 * avoid missing short pulses due to low sampling rate 957 */ 958 div = 1; 959 } else { 960 div = sport->port.uartclk / (baud * 16); 961 if (div > 7) 962 div = 7; 963 if (!div) 964 div = 1; 965 } 966 967 rational_best_approximation(16 * div * baud, sport->port.uartclk, 968 1 << 16, 1 << 16, &num, &denom); 969 970 tdiv64 = sport->port.uartclk; 971 tdiv64 *= num; 972 do_div(tdiv64, denom * 16 * div); 973 tty_termios_encode_baud_rate(termios, 974 (speed_t)tdiv64, (speed_t)tdiv64); 975 976 num -= 1; 977 denom -= 1; 978 979 ufcr = readl(sport->port.membase + UFCR); 980 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 981 writel(ufcr, sport->port.membase + UFCR); 982 983 writel(num, sport->port.membase + UBIR); 984 writel(denom, sport->port.membase + UBMR); 985 986 if (is_imx21_uart(sport)) 987 writel(sport->port.uartclk / div / 1000, 988 sport->port.membase + IMX21_ONEMS); 989 990 writel(old_ucr1, sport->port.membase + UCR1); 991 992 /* set the parity, stop bits and data size */ 993 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 994 995 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 996 imx_enable_ms(&sport->port); 997 998 spin_unlock_irqrestore(&sport->port.lock, flags); 999 } 1000 1001 static const char *imx_type(struct uart_port *port) 1002 { 1003 struct imx_port *sport = (struct imx_port *)port; 1004 1005 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1006 } 1007 1008 /* 1009 * Release the memory region(s) being used by 'port'. 1010 */ 1011 static void imx_release_port(struct uart_port *port) 1012 { 1013 struct platform_device *pdev = to_platform_device(port->dev); 1014 struct resource *mmres; 1015 1016 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1017 release_mem_region(mmres->start, resource_size(mmres)); 1018 } 1019 1020 /* 1021 * Request the memory region(s) being used by 'port'. 1022 */ 1023 static int imx_request_port(struct uart_port *port) 1024 { 1025 struct platform_device *pdev = to_platform_device(port->dev); 1026 struct resource *mmres; 1027 void *ret; 1028 1029 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1030 if (!mmres) 1031 return -ENODEV; 1032 1033 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart"); 1034 1035 return ret ? 0 : -EBUSY; 1036 } 1037 1038 /* 1039 * Configure/autoconfigure the port. 1040 */ 1041 static void imx_config_port(struct uart_port *port, int flags) 1042 { 1043 struct imx_port *sport = (struct imx_port *)port; 1044 1045 if (flags & UART_CONFIG_TYPE && 1046 imx_request_port(&sport->port) == 0) 1047 sport->port.type = PORT_IMX; 1048 } 1049 1050 /* 1051 * Verify the new serial_struct (for TIOCSSERIAL). 1052 * The only change we allow are to the flags and type, and 1053 * even then only between PORT_IMX and PORT_UNKNOWN 1054 */ 1055 static int 1056 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1057 { 1058 struct imx_port *sport = (struct imx_port *)port; 1059 int ret = 0; 1060 1061 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1062 ret = -EINVAL; 1063 if (sport->port.irq != ser->irq) 1064 ret = -EINVAL; 1065 if (ser->io_type != UPIO_MEM) 1066 ret = -EINVAL; 1067 if (sport->port.uartclk / 16 != ser->baud_base) 1068 ret = -EINVAL; 1069 if ((void *)sport->port.mapbase != ser->iomem_base) 1070 ret = -EINVAL; 1071 if (sport->port.iobase != ser->port) 1072 ret = -EINVAL; 1073 if (ser->hub6 != 0) 1074 ret = -EINVAL; 1075 return ret; 1076 } 1077 1078 static struct uart_ops imx_pops = { 1079 .tx_empty = imx_tx_empty, 1080 .set_mctrl = imx_set_mctrl, 1081 .get_mctrl = imx_get_mctrl, 1082 .stop_tx = imx_stop_tx, 1083 .start_tx = imx_start_tx, 1084 .stop_rx = imx_stop_rx, 1085 .enable_ms = imx_enable_ms, 1086 .break_ctl = imx_break_ctl, 1087 .startup = imx_startup, 1088 .shutdown = imx_shutdown, 1089 .set_termios = imx_set_termios, 1090 .type = imx_type, 1091 .release_port = imx_release_port, 1092 .request_port = imx_request_port, 1093 .config_port = imx_config_port, 1094 .verify_port = imx_verify_port, 1095 }; 1096 1097 static struct imx_port *imx_ports[UART_NR]; 1098 1099 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1100 static void imx_console_putchar(struct uart_port *port, int ch) 1101 { 1102 struct imx_port *sport = (struct imx_port *)port; 1103 1104 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1105 barrier(); 1106 1107 writel(ch, sport->port.membase + URTX0); 1108 } 1109 1110 /* 1111 * Interrupts are disabled on entering 1112 */ 1113 static void 1114 imx_console_write(struct console *co, const char *s, unsigned int count) 1115 { 1116 struct imx_port *sport = imx_ports[co->index]; 1117 unsigned int old_ucr1, old_ucr2, ucr1; 1118 1119 /* 1120 * First, save UCR1/2 and then disable interrupts 1121 */ 1122 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1); 1123 old_ucr2 = readl(sport->port.membase + UCR2); 1124 1125 if (is_imx1_uart(sport)) 1126 ucr1 |= IMX1_UCR1_UARTCLKEN; 1127 ucr1 |= UCR1_UARTEN; 1128 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1129 1130 writel(ucr1, sport->port.membase + UCR1); 1131 1132 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1133 1134 uart_console_write(&sport->port, s, count, imx_console_putchar); 1135 1136 /* 1137 * Finally, wait for transmitter to become empty 1138 * and restore UCR1/2 1139 */ 1140 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1141 1142 writel(old_ucr1, sport->port.membase + UCR1); 1143 writel(old_ucr2, sport->port.membase + UCR2); 1144 } 1145 1146 /* 1147 * If the port was already initialised (eg, by a boot loader), 1148 * try to determine the current setup. 1149 */ 1150 static void __init 1151 imx_console_get_options(struct imx_port *sport, int *baud, 1152 int *parity, int *bits) 1153 { 1154 1155 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1156 /* ok, the port was enabled */ 1157 unsigned int ucr2, ubir,ubmr, uartclk; 1158 unsigned int baud_raw; 1159 unsigned int ucfr_rfdiv; 1160 1161 ucr2 = readl(sport->port.membase + UCR2); 1162 1163 *parity = 'n'; 1164 if (ucr2 & UCR2_PREN) { 1165 if (ucr2 & UCR2_PROE) 1166 *parity = 'o'; 1167 else 1168 *parity = 'e'; 1169 } 1170 1171 if (ucr2 & UCR2_WS) 1172 *bits = 8; 1173 else 1174 *bits = 7; 1175 1176 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1177 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1178 1179 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1180 if (ucfr_rfdiv == 6) 1181 ucfr_rfdiv = 7; 1182 else 1183 ucfr_rfdiv = 6 - ucfr_rfdiv; 1184 1185 uartclk = clk_get_rate(sport->clk); 1186 uartclk /= ucfr_rfdiv; 1187 1188 { /* 1189 * The next code provides exact computation of 1190 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1191 * without need of float support or long long division, 1192 * which would be required to prevent 32bit arithmetic overflow 1193 */ 1194 unsigned int mul = ubir + 1; 1195 unsigned int div = 16 * (ubmr + 1); 1196 unsigned int rem = uartclk % div; 1197 1198 baud_raw = (uartclk / div) * mul; 1199 baud_raw += (rem * mul + div / 2) / div; 1200 *baud = (baud_raw + 50) / 100 * 100; 1201 } 1202 1203 if(*baud != baud_raw) 1204 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n", 1205 baud_raw, *baud); 1206 } 1207 } 1208 1209 static int __init 1210 imx_console_setup(struct console *co, char *options) 1211 { 1212 struct imx_port *sport; 1213 int baud = 9600; 1214 int bits = 8; 1215 int parity = 'n'; 1216 int flow = 'n'; 1217 1218 /* 1219 * Check whether an invalid uart number has been specified, and 1220 * if so, search for the first available port that does have 1221 * console support. 1222 */ 1223 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1224 co->index = 0; 1225 sport = imx_ports[co->index]; 1226 if(sport == NULL) 1227 return -ENODEV; 1228 1229 if (options) 1230 uart_parse_options(options, &baud, &parity, &bits, &flow); 1231 else 1232 imx_console_get_options(sport, &baud, &parity, &bits); 1233 1234 imx_setup_ufcr(sport, 0); 1235 1236 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1237 } 1238 1239 static struct uart_driver imx_reg; 1240 static struct console imx_console = { 1241 .name = DEV_NAME, 1242 .write = imx_console_write, 1243 .device = uart_console_device, 1244 .setup = imx_console_setup, 1245 .flags = CON_PRINTBUFFER, 1246 .index = -1, 1247 .data = &imx_reg, 1248 }; 1249 1250 #define IMX_CONSOLE &imx_console 1251 #else 1252 #define IMX_CONSOLE NULL 1253 #endif 1254 1255 static struct uart_driver imx_reg = { 1256 .owner = THIS_MODULE, 1257 .driver_name = DRIVER_NAME, 1258 .dev_name = DEV_NAME, 1259 .major = SERIAL_IMX_MAJOR, 1260 .minor = MINOR_START, 1261 .nr = ARRAY_SIZE(imx_ports), 1262 .cons = IMX_CONSOLE, 1263 }; 1264 1265 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1266 { 1267 struct imx_port *sport = platform_get_drvdata(dev); 1268 1269 if (sport) 1270 uart_suspend_port(&imx_reg, &sport->port); 1271 1272 return 0; 1273 } 1274 1275 static int serial_imx_resume(struct platform_device *dev) 1276 { 1277 struct imx_port *sport = platform_get_drvdata(dev); 1278 1279 if (sport) 1280 uart_resume_port(&imx_reg, &sport->port); 1281 1282 return 0; 1283 } 1284 1285 #ifdef CONFIG_OF 1286 static int serial_imx_probe_dt(struct imx_port *sport, 1287 struct platform_device *pdev) 1288 { 1289 static int portnum = 0; 1290 struct device_node *np = pdev->dev.of_node; 1291 const struct of_device_id *of_id = 1292 of_match_device(imx_uart_dt_ids, &pdev->dev); 1293 1294 if (!np) 1295 return -ENODEV; 1296 1297 sport->port.line = portnum++; 1298 if (sport->port.line >= UART_NR) 1299 return -EINVAL; 1300 1301 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1302 sport->have_rtscts = 1; 1303 1304 if (of_get_property(np, "fsl,irda-mode", NULL)) 1305 sport->use_irda = 1; 1306 1307 sport->devdata = of_id->data; 1308 1309 return 0; 1310 } 1311 #else 1312 static inline int serial_imx_probe_dt(struct imx_port *sport, 1313 struct platform_device *pdev) 1314 { 1315 return -ENODEV; 1316 } 1317 #endif 1318 1319 static void serial_imx_probe_pdata(struct imx_port *sport, 1320 struct platform_device *pdev) 1321 { 1322 struct imxuart_platform_data *pdata = pdev->dev.platform_data; 1323 1324 sport->port.line = pdev->id; 1325 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 1326 1327 if (!pdata) 1328 return; 1329 1330 if (pdata->flags & IMXUART_HAVE_RTSCTS) 1331 sport->have_rtscts = 1; 1332 1333 if (pdata->flags & IMXUART_IRDA) 1334 sport->use_irda = 1; 1335 } 1336 1337 static int serial_imx_probe(struct platform_device *pdev) 1338 { 1339 struct imx_port *sport; 1340 struct imxuart_platform_data *pdata; 1341 void __iomem *base; 1342 int ret = 0; 1343 struct resource *res; 1344 1345 sport = kzalloc(sizeof(*sport), GFP_KERNEL); 1346 if (!sport) 1347 return -ENOMEM; 1348 1349 ret = serial_imx_probe_dt(sport, pdev); 1350 if (ret == -ENODEV) 1351 serial_imx_probe_pdata(sport, pdev); 1352 1353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1354 if (!res) { 1355 ret = -ENODEV; 1356 goto free; 1357 } 1358 1359 base = ioremap(res->start, PAGE_SIZE); 1360 if (!base) { 1361 ret = -ENOMEM; 1362 goto free; 1363 } 1364 1365 sport->port.dev = &pdev->dev; 1366 sport->port.mapbase = res->start; 1367 sport->port.membase = base; 1368 sport->port.type = PORT_IMX, 1369 sport->port.iotype = UPIO_MEM; 1370 sport->port.irq = platform_get_irq(pdev, 0); 1371 sport->rxirq = platform_get_irq(pdev, 0); 1372 sport->txirq = platform_get_irq(pdev, 1); 1373 sport->rtsirq = platform_get_irq(pdev, 2); 1374 sport->port.fifosize = 32; 1375 sport->port.ops = &imx_pops; 1376 sport->port.flags = UPF_BOOT_AUTOCONF; 1377 init_timer(&sport->timer); 1378 sport->timer.function = imx_timeout; 1379 sport->timer.data = (unsigned long)sport; 1380 1381 sport->clk = clk_get(&pdev->dev, "uart"); 1382 if (IS_ERR(sport->clk)) { 1383 ret = PTR_ERR(sport->clk); 1384 goto unmap; 1385 } 1386 clk_enable(sport->clk); 1387 1388 sport->port.uartclk = clk_get_rate(sport->clk); 1389 1390 imx_ports[sport->port.line] = sport; 1391 1392 pdata = pdev->dev.platform_data; 1393 if (pdata && pdata->init) { 1394 ret = pdata->init(pdev); 1395 if (ret) 1396 goto clkput; 1397 } 1398 1399 ret = uart_add_one_port(&imx_reg, &sport->port); 1400 if (ret) 1401 goto deinit; 1402 platform_set_drvdata(pdev, &sport->port); 1403 1404 return 0; 1405 deinit: 1406 if (pdata && pdata->exit) 1407 pdata->exit(pdev); 1408 clkput: 1409 clk_put(sport->clk); 1410 clk_disable(sport->clk); 1411 unmap: 1412 iounmap(sport->port.membase); 1413 free: 1414 kfree(sport); 1415 1416 return ret; 1417 } 1418 1419 static int serial_imx_remove(struct platform_device *pdev) 1420 { 1421 struct imxuart_platform_data *pdata; 1422 struct imx_port *sport = platform_get_drvdata(pdev); 1423 1424 pdata = pdev->dev.platform_data; 1425 1426 platform_set_drvdata(pdev, NULL); 1427 1428 if (sport) { 1429 uart_remove_one_port(&imx_reg, &sport->port); 1430 clk_put(sport->clk); 1431 } 1432 1433 clk_disable(sport->clk); 1434 1435 if (pdata && pdata->exit) 1436 pdata->exit(pdev); 1437 1438 iounmap(sport->port.membase); 1439 kfree(sport); 1440 1441 return 0; 1442 } 1443 1444 static struct platform_driver serial_imx_driver = { 1445 .probe = serial_imx_probe, 1446 .remove = serial_imx_remove, 1447 1448 .suspend = serial_imx_suspend, 1449 .resume = serial_imx_resume, 1450 .id_table = imx_uart_devtype, 1451 .driver = { 1452 .name = "imx-uart", 1453 .owner = THIS_MODULE, 1454 .of_match_table = imx_uart_dt_ids, 1455 }, 1456 }; 1457 1458 static int __init imx_serial_init(void) 1459 { 1460 int ret; 1461 1462 printk(KERN_INFO "Serial: IMX driver\n"); 1463 1464 ret = uart_register_driver(&imx_reg); 1465 if (ret) 1466 return ret; 1467 1468 ret = platform_driver_register(&serial_imx_driver); 1469 if (ret != 0) 1470 uart_unregister_driver(&imx_reg); 1471 1472 return 0; 1473 } 1474 1475 static void __exit imx_serial_exit(void) 1476 { 1477 platform_driver_unregister(&serial_imx_driver); 1478 uart_unregister_driver(&imx_reg); 1479 } 1480 1481 module_init(imx_serial_init); 1482 module_exit(imx_serial_exit); 1483 1484 MODULE_AUTHOR("Sascha Hauer"); 1485 MODULE_DESCRIPTION("IMX generic serial port driver"); 1486 MODULE_LICENSE("GPL"); 1487 MODULE_ALIAS("platform:imx-uart"); 1488