1 /* 2 * Driver for Motorola IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * Copyright (C) 2009 emlix GmbH 10 * Author: Fabian Godehardt (added IrDA support for iMX) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 * [29-Mar-2005] Mike Lee 27 * Added hardware handshake 28 */ 29 30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31 #define SUPPORT_SYSRQ 32 #endif 33 34 #include <linux/module.h> 35 #include <linux/ioport.h> 36 #include <linux/init.h> 37 #include <linux/console.h> 38 #include <linux/sysrq.h> 39 #include <linux/platform_device.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/serial_core.h> 43 #include <linux/serial.h> 44 #include <linux/clk.h> 45 #include <linux/delay.h> 46 #include <linux/rational.h> 47 #include <linux/slab.h> 48 #include <linux/of.h> 49 #include <linux/of_device.h> 50 51 #include <asm/io.h> 52 #include <asm/irq.h> 53 #include <mach/imx-uart.h> 54 55 /* Register definitions */ 56 #define URXD0 0x0 /* Receiver Register */ 57 #define URTX0 0x40 /* Transmitter Register */ 58 #define UCR1 0x80 /* Control Register 1 */ 59 #define UCR2 0x84 /* Control Register 2 */ 60 #define UCR3 0x88 /* Control Register 3 */ 61 #define UCR4 0x8c /* Control Register 4 */ 62 #define UFCR 0x90 /* FIFO Control Register */ 63 #define USR1 0x94 /* Status Register 1 */ 64 #define USR2 0x98 /* Status Register 2 */ 65 #define UESC 0x9c /* Escape Character Register */ 66 #define UTIM 0xa0 /* Escape Timer Register */ 67 #define UBIR 0xa4 /* BRM Incremental Register */ 68 #define UBMR 0xa8 /* BRM Modulator Register */ 69 #define UBRC 0xac /* Baud Rate Count Register */ 70 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 71 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 72 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 73 74 /* UART Control Register Bit Fields.*/ 75 #define URXD_CHARRDY (1<<15) 76 #define URXD_ERR (1<<14) 77 #define URXD_OVRRUN (1<<13) 78 #define URXD_FRMERR (1<<12) 79 #define URXD_BRK (1<<11) 80 #define URXD_PRERR (1<<10) 81 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 87 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 90 #define UCR1_SNDBRK (1<<4) /* Send break */ 91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 92 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 93 #define UCR1_DOZE (1<<1) /* Doze */ 94 #define UCR1_UARTEN (1<<0) /* UART enabled */ 95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 97 #define UCR2_CTSC (1<<13) /* CTS pin control */ 98 #define UCR2_CTS (1<<12) /* Clear to send */ 99 #define UCR2_ESCEN (1<<11) /* Escape enable */ 100 #define UCR2_PREN (1<<8) /* Parity enable */ 101 #define UCR2_PROE (1<<7) /* Parity odd/even */ 102 #define UCR2_STPB (1<<6) /* Stop */ 103 #define UCR2_WS (1<<5) /* Word size */ 104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 105 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 106 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 107 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 108 #define UCR2_SRST (1<<0) /* SW reset */ 109 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 110 #define UCR3_PARERREN (1<<12) /* Parity enable */ 111 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 112 #define UCR3_DSR (1<<10) /* Data set ready */ 113 #define UCR3_DCD (1<<9) /* Data carrier detect */ 114 #define UCR3_RI (1<<8) /* Ring indicator */ 115 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 116 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 117 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 118 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 119 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 121 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 122 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 123 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 124 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 125 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 126 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 127 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 128 #define UCR4_IRSC (1<<5) /* IR special case */ 129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 134 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 135 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 136 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 137 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 138 #define USR1_RTSS (1<<14) /* RTS pin status */ 139 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 140 #define USR1_RTSD (1<<12) /* RTS delta */ 141 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 142 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 143 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 144 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 145 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 146 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 147 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 148 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 149 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 150 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 151 #define USR2_IDLE (1<<12) /* Idle condition */ 152 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 153 #define USR2_WAKE (1<<7) /* Wake */ 154 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 155 #define USR2_TXDC (1<<3) /* Transmitter complete */ 156 #define USR2_BRCD (1<<2) /* Break condition */ 157 #define USR2_ORE (1<<1) /* Overrun error */ 158 #define USR2_RDR (1<<0) /* Recv data ready */ 159 #define UTS_FRCPERR (1<<13) /* Force parity error */ 160 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 161 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 162 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 163 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 164 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 165 #define UTS_SOFTRST (1<<0) /* Software reset */ 166 167 /* We've been assigned a range on the "Low-density serial ports" major */ 168 #define SERIAL_IMX_MAJOR 207 169 #define MINOR_START 16 170 #define DEV_NAME "ttymxc" 171 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS 172 173 /* 174 * This determines how often we check the modem status signals 175 * for any change. They generally aren't connected to an IRQ 176 * so we have to poll them. We also check immediately before 177 * filling the TX fifo incase CTS has been dropped. 178 */ 179 #define MCTRL_TIMEOUT (250*HZ/1000) 180 181 #define DRIVER_NAME "IMX-uart" 182 183 #define UART_NR 8 184 185 /* i.mx21 type uart runs on all i.mx except i.mx1 */ 186 enum imx_uart_type { 187 IMX1_UART, 188 IMX21_UART, 189 }; 190 191 /* device type dependent stuff */ 192 struct imx_uart_data { 193 unsigned uts_reg; 194 enum imx_uart_type devtype; 195 }; 196 197 struct imx_port { 198 struct uart_port port; 199 struct timer_list timer; 200 unsigned int old_status; 201 int txirq,rxirq,rtsirq; 202 unsigned int have_rtscts:1; 203 unsigned int use_irda:1; 204 unsigned int irda_inv_rx:1; 205 unsigned int irda_inv_tx:1; 206 unsigned short trcv_delay; /* transceiver delay */ 207 struct clk *clk; 208 struct imx_uart_data *devdata; 209 }; 210 211 struct imx_port_ucrs { 212 unsigned int ucr1; 213 unsigned int ucr2; 214 unsigned int ucr3; 215 }; 216 217 #ifdef CONFIG_IRDA 218 #define USE_IRDA(sport) ((sport)->use_irda) 219 #else 220 #define USE_IRDA(sport) (0) 221 #endif 222 223 static struct imx_uart_data imx_uart_devdata[] = { 224 [IMX1_UART] = { 225 .uts_reg = IMX1_UTS, 226 .devtype = IMX1_UART, 227 }, 228 [IMX21_UART] = { 229 .uts_reg = IMX21_UTS, 230 .devtype = IMX21_UART, 231 }, 232 }; 233 234 static struct platform_device_id imx_uart_devtype[] = { 235 { 236 .name = "imx1-uart", 237 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 238 }, { 239 .name = "imx21-uart", 240 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 241 }, { 242 /* sentinel */ 243 } 244 }; 245 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 246 247 static struct of_device_id imx_uart_dt_ids[] = { 248 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 249 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 250 { /* sentinel */ } 251 }; 252 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 253 254 static inline unsigned uts_reg(struct imx_port *sport) 255 { 256 return sport->devdata->uts_reg; 257 } 258 259 static inline int is_imx1_uart(struct imx_port *sport) 260 { 261 return sport->devdata->devtype == IMX1_UART; 262 } 263 264 static inline int is_imx21_uart(struct imx_port *sport) 265 { 266 return sport->devdata->devtype == IMX21_UART; 267 } 268 269 /* 270 * Save and restore functions for UCR1, UCR2 and UCR3 registers 271 */ 272 static void imx_port_ucrs_save(struct uart_port *port, 273 struct imx_port_ucrs *ucr) 274 { 275 /* save control registers */ 276 ucr->ucr1 = readl(port->membase + UCR1); 277 ucr->ucr2 = readl(port->membase + UCR2); 278 ucr->ucr3 = readl(port->membase + UCR3); 279 } 280 281 static void imx_port_ucrs_restore(struct uart_port *port, 282 struct imx_port_ucrs *ucr) 283 { 284 /* restore control registers */ 285 writel(ucr->ucr1, port->membase + UCR1); 286 writel(ucr->ucr2, port->membase + UCR2); 287 writel(ucr->ucr3, port->membase + UCR3); 288 } 289 290 /* 291 * Handle any change of modem status signal since we were last called. 292 */ 293 static void imx_mctrl_check(struct imx_port *sport) 294 { 295 unsigned int status, changed; 296 297 status = sport->port.ops->get_mctrl(&sport->port); 298 changed = status ^ sport->old_status; 299 300 if (changed == 0) 301 return; 302 303 sport->old_status = status; 304 305 if (changed & TIOCM_RI) 306 sport->port.icount.rng++; 307 if (changed & TIOCM_DSR) 308 sport->port.icount.dsr++; 309 if (changed & TIOCM_CAR) 310 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 311 if (changed & TIOCM_CTS) 312 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 313 314 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 315 } 316 317 /* 318 * This is our per-port timeout handler, for checking the 319 * modem status signals. 320 */ 321 static void imx_timeout(unsigned long data) 322 { 323 struct imx_port *sport = (struct imx_port *)data; 324 unsigned long flags; 325 326 if (sport->port.state) { 327 spin_lock_irqsave(&sport->port.lock, flags); 328 imx_mctrl_check(sport); 329 spin_unlock_irqrestore(&sport->port.lock, flags); 330 331 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 332 } 333 } 334 335 /* 336 * interrupts disabled on entry 337 */ 338 static void imx_stop_tx(struct uart_port *port) 339 { 340 struct imx_port *sport = (struct imx_port *)port; 341 unsigned long temp; 342 343 if (USE_IRDA(sport)) { 344 /* half duplex - wait for end of transmission */ 345 int n = 256; 346 while ((--n > 0) && 347 !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 348 udelay(5); 349 barrier(); 350 } 351 /* 352 * irda transceiver - wait a bit more to avoid 353 * cutoff, hardware dependent 354 */ 355 udelay(sport->trcv_delay); 356 357 /* 358 * half duplex - reactivate receive mode, 359 * flush receive pipe echo crap 360 */ 361 if (readl(sport->port.membase + USR2) & USR2_TXDC) { 362 temp = readl(sport->port.membase + UCR1); 363 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 364 writel(temp, sport->port.membase + UCR1); 365 366 temp = readl(sport->port.membase + UCR4); 367 temp &= ~(UCR4_TCEN); 368 writel(temp, sport->port.membase + UCR4); 369 370 while (readl(sport->port.membase + URXD0) & 371 URXD_CHARRDY) 372 barrier(); 373 374 temp = readl(sport->port.membase + UCR1); 375 temp |= UCR1_RRDYEN; 376 writel(temp, sport->port.membase + UCR1); 377 378 temp = readl(sport->port.membase + UCR4); 379 temp |= UCR4_DREN; 380 writel(temp, sport->port.membase + UCR4); 381 } 382 return; 383 } 384 385 temp = readl(sport->port.membase + UCR1); 386 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 387 } 388 389 /* 390 * interrupts disabled on entry 391 */ 392 static void imx_stop_rx(struct uart_port *port) 393 { 394 struct imx_port *sport = (struct imx_port *)port; 395 unsigned long temp; 396 397 temp = readl(sport->port.membase + UCR2); 398 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2); 399 } 400 401 /* 402 * Set the modem control timer to fire immediately. 403 */ 404 static void imx_enable_ms(struct uart_port *port) 405 { 406 struct imx_port *sport = (struct imx_port *)port; 407 408 mod_timer(&sport->timer, jiffies); 409 } 410 411 static inline void imx_transmit_buffer(struct imx_port *sport) 412 { 413 struct circ_buf *xmit = &sport->port.state->xmit; 414 415 while (!uart_circ_empty(xmit) && 416 !(readl(sport->port.membase + uts_reg(sport)) 417 & UTS_TXFULL)) { 418 /* send xmit->buf[xmit->tail] 419 * out the port here */ 420 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 421 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 422 sport->port.icount.tx++; 423 } 424 425 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 426 uart_write_wakeup(&sport->port); 427 428 if (uart_circ_empty(xmit)) 429 imx_stop_tx(&sport->port); 430 } 431 432 /* 433 * interrupts disabled on entry 434 */ 435 static void imx_start_tx(struct uart_port *port) 436 { 437 struct imx_port *sport = (struct imx_port *)port; 438 unsigned long temp; 439 440 if (USE_IRDA(sport)) { 441 /* half duplex in IrDA mode; have to disable receive mode */ 442 temp = readl(sport->port.membase + UCR4); 443 temp &= ~(UCR4_DREN); 444 writel(temp, sport->port.membase + UCR4); 445 446 temp = readl(sport->port.membase + UCR1); 447 temp &= ~(UCR1_RRDYEN); 448 writel(temp, sport->port.membase + UCR1); 449 } 450 451 temp = readl(sport->port.membase + UCR1); 452 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 453 454 if (USE_IRDA(sport)) { 455 temp = readl(sport->port.membase + UCR1); 456 temp |= UCR1_TRDYEN; 457 writel(temp, sport->port.membase + UCR1); 458 459 temp = readl(sport->port.membase + UCR4); 460 temp |= UCR4_TCEN; 461 writel(temp, sport->port.membase + UCR4); 462 } 463 464 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) 465 imx_transmit_buffer(sport); 466 } 467 468 static irqreturn_t imx_rtsint(int irq, void *dev_id) 469 { 470 struct imx_port *sport = dev_id; 471 unsigned int val; 472 unsigned long flags; 473 474 spin_lock_irqsave(&sport->port.lock, flags); 475 476 writel(USR1_RTSD, sport->port.membase + USR1); 477 val = readl(sport->port.membase + USR1) & USR1_RTSS; 478 uart_handle_cts_change(&sport->port, !!val); 479 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 480 481 spin_unlock_irqrestore(&sport->port.lock, flags); 482 return IRQ_HANDLED; 483 } 484 485 static irqreturn_t imx_txint(int irq, void *dev_id) 486 { 487 struct imx_port *sport = dev_id; 488 struct circ_buf *xmit = &sport->port.state->xmit; 489 unsigned long flags; 490 491 spin_lock_irqsave(&sport->port.lock,flags); 492 if (sport->port.x_char) 493 { 494 /* Send next char */ 495 writel(sport->port.x_char, sport->port.membase + URTX0); 496 goto out; 497 } 498 499 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 500 imx_stop_tx(&sport->port); 501 goto out; 502 } 503 504 imx_transmit_buffer(sport); 505 506 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 507 uart_write_wakeup(&sport->port); 508 509 out: 510 spin_unlock_irqrestore(&sport->port.lock,flags); 511 return IRQ_HANDLED; 512 } 513 514 static irqreturn_t imx_rxint(int irq, void *dev_id) 515 { 516 struct imx_port *sport = dev_id; 517 unsigned int rx,flg,ignored = 0; 518 struct tty_struct *tty = sport->port.state->port.tty; 519 unsigned long flags, temp; 520 521 spin_lock_irqsave(&sport->port.lock,flags); 522 523 while (readl(sport->port.membase + USR2) & USR2_RDR) { 524 flg = TTY_NORMAL; 525 sport->port.icount.rx++; 526 527 rx = readl(sport->port.membase + URXD0); 528 529 temp = readl(sport->port.membase + USR2); 530 if (temp & USR2_BRCD) { 531 writel(USR2_BRCD, sport->port.membase + USR2); 532 if (uart_handle_break(&sport->port)) 533 continue; 534 } 535 536 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 537 continue; 538 539 if (unlikely(rx & URXD_ERR)) { 540 if (rx & URXD_BRK) 541 sport->port.icount.brk++; 542 else if (rx & URXD_PRERR) 543 sport->port.icount.parity++; 544 else if (rx & URXD_FRMERR) 545 sport->port.icount.frame++; 546 if (rx & URXD_OVRRUN) 547 sport->port.icount.overrun++; 548 549 if (rx & sport->port.ignore_status_mask) { 550 if (++ignored > 100) 551 goto out; 552 continue; 553 } 554 555 rx &= sport->port.read_status_mask; 556 557 if (rx & URXD_BRK) 558 flg = TTY_BREAK; 559 else if (rx & URXD_PRERR) 560 flg = TTY_PARITY; 561 else if (rx & URXD_FRMERR) 562 flg = TTY_FRAME; 563 if (rx & URXD_OVRRUN) 564 flg = TTY_OVERRUN; 565 566 #ifdef SUPPORT_SYSRQ 567 sport->port.sysrq = 0; 568 #endif 569 } 570 571 tty_insert_flip_char(tty, rx, flg); 572 } 573 574 out: 575 spin_unlock_irqrestore(&sport->port.lock,flags); 576 tty_flip_buffer_push(tty); 577 return IRQ_HANDLED; 578 } 579 580 static irqreturn_t imx_int(int irq, void *dev_id) 581 { 582 struct imx_port *sport = dev_id; 583 unsigned int sts; 584 585 sts = readl(sport->port.membase + USR1); 586 587 if (sts & USR1_RRDY) 588 imx_rxint(irq, dev_id); 589 590 if (sts & USR1_TRDY && 591 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 592 imx_txint(irq, dev_id); 593 594 if (sts & USR1_RTSD) 595 imx_rtsint(irq, dev_id); 596 597 if (sts & USR1_AWAKE) 598 writel(USR1_AWAKE, sport->port.membase + USR1); 599 600 return IRQ_HANDLED; 601 } 602 603 /* 604 * Return TIOCSER_TEMT when transmitter is not busy. 605 */ 606 static unsigned int imx_tx_empty(struct uart_port *port) 607 { 608 struct imx_port *sport = (struct imx_port *)port; 609 610 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 611 } 612 613 /* 614 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 615 */ 616 static unsigned int imx_get_mctrl(struct uart_port *port) 617 { 618 struct imx_port *sport = (struct imx_port *)port; 619 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 620 621 if (readl(sport->port.membase + USR1) & USR1_RTSS) 622 tmp |= TIOCM_CTS; 623 624 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 625 tmp |= TIOCM_RTS; 626 627 return tmp; 628 } 629 630 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 631 { 632 struct imx_port *sport = (struct imx_port *)port; 633 unsigned long temp; 634 635 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; 636 637 if (mctrl & TIOCM_RTS) 638 temp |= UCR2_CTS; 639 640 writel(temp, sport->port.membase + UCR2); 641 } 642 643 /* 644 * Interrupts always disabled. 645 */ 646 static void imx_break_ctl(struct uart_port *port, int break_state) 647 { 648 struct imx_port *sport = (struct imx_port *)port; 649 unsigned long flags, temp; 650 651 spin_lock_irqsave(&sport->port.lock, flags); 652 653 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 654 655 if ( break_state != 0 ) 656 temp |= UCR1_SNDBRK; 657 658 writel(temp, sport->port.membase + UCR1); 659 660 spin_unlock_irqrestore(&sport->port.lock, flags); 661 } 662 663 #define TXTL 2 /* reset default */ 664 #define RXTL 1 /* reset default */ 665 666 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 667 { 668 unsigned int val; 669 unsigned int ufcr_rfdiv; 670 671 /* set receiver / transmitter trigger level. 672 * RFDIV is set such way to satisfy requested uartclk value 673 */ 674 val = TXTL << 10 | RXTL; 675 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2) 676 / sport->port.uartclk; 677 678 if(!ufcr_rfdiv) 679 ufcr_rfdiv = 1; 680 681 val |= UFCR_RFDIV_REG(ufcr_rfdiv); 682 683 writel(val, sport->port.membase + UFCR); 684 685 return 0; 686 } 687 688 /* half the RX buffer size */ 689 #define CTSTL 16 690 691 static int imx_startup(struct uart_port *port) 692 { 693 struct imx_port *sport = (struct imx_port *)port; 694 int retval; 695 unsigned long flags, temp; 696 697 imx_setup_ufcr(sport, 0); 698 699 /* disable the DREN bit (Data Ready interrupt enable) before 700 * requesting IRQs 701 */ 702 temp = readl(sport->port.membase + UCR4); 703 704 if (USE_IRDA(sport)) 705 temp |= UCR4_IRSC; 706 707 /* set the trigger level for CTS */ 708 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF); 709 temp |= CTSTL<< UCR4_CTSTL_SHF; 710 711 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 712 713 if (USE_IRDA(sport)) { 714 /* reset fifo's and state machines */ 715 int i = 100; 716 temp = readl(sport->port.membase + UCR2); 717 temp &= ~UCR2_SRST; 718 writel(temp, sport->port.membase + UCR2); 719 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && 720 (--i > 0)) { 721 udelay(1); 722 } 723 } 724 725 /* 726 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 727 * chips only have one interrupt. 728 */ 729 if (sport->txirq > 0) { 730 retval = request_irq(sport->rxirq, imx_rxint, 0, 731 DRIVER_NAME, sport); 732 if (retval) 733 goto error_out1; 734 735 retval = request_irq(sport->txirq, imx_txint, 0, 736 DRIVER_NAME, sport); 737 if (retval) 738 goto error_out2; 739 740 /* do not use RTS IRQ on IrDA */ 741 if (!USE_IRDA(sport)) { 742 retval = request_irq(sport->rtsirq, imx_rtsint, 743 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : 744 IRQF_TRIGGER_FALLING | 745 IRQF_TRIGGER_RISING, 746 DRIVER_NAME, sport); 747 if (retval) 748 goto error_out3; 749 } 750 } else { 751 retval = request_irq(sport->port.irq, imx_int, 0, 752 DRIVER_NAME, sport); 753 if (retval) { 754 free_irq(sport->port.irq, sport); 755 goto error_out1; 756 } 757 } 758 759 /* 760 * Finally, clear and enable interrupts 761 */ 762 writel(USR1_RTSD, sport->port.membase + USR1); 763 764 temp = readl(sport->port.membase + UCR1); 765 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 766 767 if (USE_IRDA(sport)) { 768 temp |= UCR1_IREN; 769 temp &= ~(UCR1_RTSDEN); 770 } 771 772 writel(temp, sport->port.membase + UCR1); 773 774 temp = readl(sport->port.membase + UCR2); 775 temp |= (UCR2_RXEN | UCR2_TXEN); 776 writel(temp, sport->port.membase + UCR2); 777 778 if (USE_IRDA(sport)) { 779 /* clear RX-FIFO */ 780 int i = 64; 781 while ((--i > 0) && 782 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { 783 barrier(); 784 } 785 } 786 787 if (is_imx21_uart(sport)) { 788 temp = readl(sport->port.membase + UCR3); 789 temp |= IMX21_UCR3_RXDMUXSEL; 790 writel(temp, sport->port.membase + UCR3); 791 } 792 793 if (USE_IRDA(sport)) { 794 temp = readl(sport->port.membase + UCR4); 795 if (sport->irda_inv_rx) 796 temp |= UCR4_INVR; 797 else 798 temp &= ~(UCR4_INVR); 799 writel(temp | UCR4_DREN, sport->port.membase + UCR4); 800 801 temp = readl(sport->port.membase + UCR3); 802 if (sport->irda_inv_tx) 803 temp |= UCR3_INVT; 804 else 805 temp &= ~(UCR3_INVT); 806 writel(temp, sport->port.membase + UCR3); 807 } 808 809 /* 810 * Enable modem status interrupts 811 */ 812 spin_lock_irqsave(&sport->port.lock,flags); 813 imx_enable_ms(&sport->port); 814 spin_unlock_irqrestore(&sport->port.lock,flags); 815 816 if (USE_IRDA(sport)) { 817 struct imxuart_platform_data *pdata; 818 pdata = sport->port.dev->platform_data; 819 sport->irda_inv_rx = pdata->irda_inv_rx; 820 sport->irda_inv_tx = pdata->irda_inv_tx; 821 sport->trcv_delay = pdata->transceiver_delay; 822 if (pdata->irda_enable) 823 pdata->irda_enable(1); 824 } 825 826 return 0; 827 828 error_out3: 829 if (sport->txirq) 830 free_irq(sport->txirq, sport); 831 error_out2: 832 if (sport->rxirq) 833 free_irq(sport->rxirq, sport); 834 error_out1: 835 return retval; 836 } 837 838 static void imx_shutdown(struct uart_port *port) 839 { 840 struct imx_port *sport = (struct imx_port *)port; 841 unsigned long temp; 842 843 temp = readl(sport->port.membase + UCR2); 844 temp &= ~(UCR2_TXEN); 845 writel(temp, sport->port.membase + UCR2); 846 847 if (USE_IRDA(sport)) { 848 struct imxuart_platform_data *pdata; 849 pdata = sport->port.dev->platform_data; 850 if (pdata->irda_enable) 851 pdata->irda_enable(0); 852 } 853 854 /* 855 * Stop our timer. 856 */ 857 del_timer_sync(&sport->timer); 858 859 /* 860 * Free the interrupts 861 */ 862 if (sport->txirq > 0) { 863 if (!USE_IRDA(sport)) 864 free_irq(sport->rtsirq, sport); 865 free_irq(sport->txirq, sport); 866 free_irq(sport->rxirq, sport); 867 } else 868 free_irq(sport->port.irq, sport); 869 870 /* 871 * Disable all interrupts, port and break condition. 872 */ 873 874 temp = readl(sport->port.membase + UCR1); 875 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 876 if (USE_IRDA(sport)) 877 temp &= ~(UCR1_IREN); 878 879 writel(temp, sport->port.membase + UCR1); 880 } 881 882 static void 883 imx_set_termios(struct uart_port *port, struct ktermios *termios, 884 struct ktermios *old) 885 { 886 struct imx_port *sport = (struct imx_port *)port; 887 unsigned long flags; 888 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 889 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 890 unsigned int div, ufcr; 891 unsigned long num, denom; 892 uint64_t tdiv64; 893 894 /* 895 * If we don't support modem control lines, don't allow 896 * these to be set. 897 */ 898 if (0) { 899 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 900 termios->c_cflag |= CLOCAL; 901 } 902 903 /* 904 * We only support CS7 and CS8. 905 */ 906 while ((termios->c_cflag & CSIZE) != CS7 && 907 (termios->c_cflag & CSIZE) != CS8) { 908 termios->c_cflag &= ~CSIZE; 909 termios->c_cflag |= old_csize; 910 old_csize = CS8; 911 } 912 913 if ((termios->c_cflag & CSIZE) == CS8) 914 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 915 else 916 ucr2 = UCR2_SRST | UCR2_IRTS; 917 918 if (termios->c_cflag & CRTSCTS) { 919 if( sport->have_rtscts ) { 920 ucr2 &= ~UCR2_IRTS; 921 ucr2 |= UCR2_CTSC; 922 } else { 923 termios->c_cflag &= ~CRTSCTS; 924 } 925 } 926 927 if (termios->c_cflag & CSTOPB) 928 ucr2 |= UCR2_STPB; 929 if (termios->c_cflag & PARENB) { 930 ucr2 |= UCR2_PREN; 931 if (termios->c_cflag & PARODD) 932 ucr2 |= UCR2_PROE; 933 } 934 935 del_timer_sync(&sport->timer); 936 937 /* 938 * Ask the core to calculate the divisor for us. 939 */ 940 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 941 quot = uart_get_divisor(port, baud); 942 943 spin_lock_irqsave(&sport->port.lock, flags); 944 945 sport->port.read_status_mask = 0; 946 if (termios->c_iflag & INPCK) 947 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 948 if (termios->c_iflag & (BRKINT | PARMRK)) 949 sport->port.read_status_mask |= URXD_BRK; 950 951 /* 952 * Characters to ignore 953 */ 954 sport->port.ignore_status_mask = 0; 955 if (termios->c_iflag & IGNPAR) 956 sport->port.ignore_status_mask |= URXD_PRERR; 957 if (termios->c_iflag & IGNBRK) { 958 sport->port.ignore_status_mask |= URXD_BRK; 959 /* 960 * If we're ignoring parity and break indicators, 961 * ignore overruns too (for real raw support). 962 */ 963 if (termios->c_iflag & IGNPAR) 964 sport->port.ignore_status_mask |= URXD_OVRRUN; 965 } 966 967 /* 968 * Update the per-port timeout. 969 */ 970 uart_update_timeout(port, termios->c_cflag, baud); 971 972 /* 973 * disable interrupts and drain transmitter 974 */ 975 old_ucr1 = readl(sport->port.membase + UCR1); 976 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 977 sport->port.membase + UCR1); 978 979 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC)) 980 barrier(); 981 982 /* then, disable everything */ 983 old_txrxen = readl(sport->port.membase + UCR2); 984 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN), 985 sport->port.membase + UCR2); 986 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 987 988 if (USE_IRDA(sport)) { 989 /* 990 * use maximum available submodule frequency to 991 * avoid missing short pulses due to low sampling rate 992 */ 993 div = 1; 994 } else { 995 div = sport->port.uartclk / (baud * 16); 996 if (div > 7) 997 div = 7; 998 if (!div) 999 div = 1; 1000 } 1001 1002 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1003 1 << 16, 1 << 16, &num, &denom); 1004 1005 tdiv64 = sport->port.uartclk; 1006 tdiv64 *= num; 1007 do_div(tdiv64, denom * 16 * div); 1008 tty_termios_encode_baud_rate(termios, 1009 (speed_t)tdiv64, (speed_t)tdiv64); 1010 1011 num -= 1; 1012 denom -= 1; 1013 1014 ufcr = readl(sport->port.membase + UFCR); 1015 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1016 writel(ufcr, sport->port.membase + UFCR); 1017 1018 writel(num, sport->port.membase + UBIR); 1019 writel(denom, sport->port.membase + UBMR); 1020 1021 if (is_imx21_uart(sport)) 1022 writel(sport->port.uartclk / div / 1000, 1023 sport->port.membase + IMX21_ONEMS); 1024 1025 writel(old_ucr1, sport->port.membase + UCR1); 1026 1027 /* set the parity, stop bits and data size */ 1028 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1029 1030 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1031 imx_enable_ms(&sport->port); 1032 1033 spin_unlock_irqrestore(&sport->port.lock, flags); 1034 } 1035 1036 static const char *imx_type(struct uart_port *port) 1037 { 1038 struct imx_port *sport = (struct imx_port *)port; 1039 1040 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1041 } 1042 1043 /* 1044 * Release the memory region(s) being used by 'port'. 1045 */ 1046 static void imx_release_port(struct uart_port *port) 1047 { 1048 struct platform_device *pdev = to_platform_device(port->dev); 1049 struct resource *mmres; 1050 1051 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1052 release_mem_region(mmres->start, resource_size(mmres)); 1053 } 1054 1055 /* 1056 * Request the memory region(s) being used by 'port'. 1057 */ 1058 static int imx_request_port(struct uart_port *port) 1059 { 1060 struct platform_device *pdev = to_platform_device(port->dev); 1061 struct resource *mmres; 1062 void *ret; 1063 1064 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1065 if (!mmres) 1066 return -ENODEV; 1067 1068 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart"); 1069 1070 return ret ? 0 : -EBUSY; 1071 } 1072 1073 /* 1074 * Configure/autoconfigure the port. 1075 */ 1076 static void imx_config_port(struct uart_port *port, int flags) 1077 { 1078 struct imx_port *sport = (struct imx_port *)port; 1079 1080 if (flags & UART_CONFIG_TYPE && 1081 imx_request_port(&sport->port) == 0) 1082 sport->port.type = PORT_IMX; 1083 } 1084 1085 /* 1086 * Verify the new serial_struct (for TIOCSSERIAL). 1087 * The only change we allow are to the flags and type, and 1088 * even then only between PORT_IMX and PORT_UNKNOWN 1089 */ 1090 static int 1091 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1092 { 1093 struct imx_port *sport = (struct imx_port *)port; 1094 int ret = 0; 1095 1096 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1097 ret = -EINVAL; 1098 if (sport->port.irq != ser->irq) 1099 ret = -EINVAL; 1100 if (ser->io_type != UPIO_MEM) 1101 ret = -EINVAL; 1102 if (sport->port.uartclk / 16 != ser->baud_base) 1103 ret = -EINVAL; 1104 if ((void *)sport->port.mapbase != ser->iomem_base) 1105 ret = -EINVAL; 1106 if (sport->port.iobase != ser->port) 1107 ret = -EINVAL; 1108 if (ser->hub6 != 0) 1109 ret = -EINVAL; 1110 return ret; 1111 } 1112 1113 #if defined(CONFIG_CONSOLE_POLL) 1114 static int imx_poll_get_char(struct uart_port *port) 1115 { 1116 struct imx_port_ucrs old_ucr; 1117 unsigned int status; 1118 unsigned char c; 1119 1120 /* save control registers */ 1121 imx_port_ucrs_save(port, &old_ucr); 1122 1123 /* disable interrupts */ 1124 writel(UCR1_UARTEN, port->membase + UCR1); 1125 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1126 port->membase + UCR2); 1127 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1128 port->membase + UCR3); 1129 1130 /* poll */ 1131 do { 1132 status = readl(port->membase + USR2); 1133 } while (~status & USR2_RDR); 1134 1135 /* read */ 1136 c = readl(port->membase + URXD0); 1137 1138 /* restore control registers */ 1139 imx_port_ucrs_restore(port, &old_ucr); 1140 1141 return c; 1142 } 1143 1144 static void imx_poll_put_char(struct uart_port *port, unsigned char c) 1145 { 1146 struct imx_port_ucrs old_ucr; 1147 unsigned int status; 1148 1149 /* save control registers */ 1150 imx_port_ucrs_save(port, &old_ucr); 1151 1152 /* disable interrupts */ 1153 writel(UCR1_UARTEN, port->membase + UCR1); 1154 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1155 port->membase + UCR2); 1156 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1157 port->membase + UCR3); 1158 1159 /* drain */ 1160 do { 1161 status = readl(port->membase + USR1); 1162 } while (~status & USR1_TRDY); 1163 1164 /* write */ 1165 writel(c, port->membase + URTX0); 1166 1167 /* flush */ 1168 do { 1169 status = readl(port->membase + USR2); 1170 } while (~status & USR2_TXDC); 1171 1172 /* restore control registers */ 1173 imx_port_ucrs_restore(port, &old_ucr); 1174 } 1175 #endif 1176 1177 static struct uart_ops imx_pops = { 1178 .tx_empty = imx_tx_empty, 1179 .set_mctrl = imx_set_mctrl, 1180 .get_mctrl = imx_get_mctrl, 1181 .stop_tx = imx_stop_tx, 1182 .start_tx = imx_start_tx, 1183 .stop_rx = imx_stop_rx, 1184 .enable_ms = imx_enable_ms, 1185 .break_ctl = imx_break_ctl, 1186 .startup = imx_startup, 1187 .shutdown = imx_shutdown, 1188 .set_termios = imx_set_termios, 1189 .type = imx_type, 1190 .release_port = imx_release_port, 1191 .request_port = imx_request_port, 1192 .config_port = imx_config_port, 1193 .verify_port = imx_verify_port, 1194 #if defined(CONFIG_CONSOLE_POLL) 1195 .poll_get_char = imx_poll_get_char, 1196 .poll_put_char = imx_poll_put_char, 1197 #endif 1198 }; 1199 1200 static struct imx_port *imx_ports[UART_NR]; 1201 1202 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1203 static void imx_console_putchar(struct uart_port *port, int ch) 1204 { 1205 struct imx_port *sport = (struct imx_port *)port; 1206 1207 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1208 barrier(); 1209 1210 writel(ch, sport->port.membase + URTX0); 1211 } 1212 1213 /* 1214 * Interrupts are disabled on entering 1215 */ 1216 static void 1217 imx_console_write(struct console *co, const char *s, unsigned int count) 1218 { 1219 struct imx_port *sport = imx_ports[co->index]; 1220 struct imx_port_ucrs old_ucr; 1221 unsigned int ucr1; 1222 1223 /* 1224 * First, save UCR1/2/3 and then disable interrupts 1225 */ 1226 imx_port_ucrs_save(&sport->port, &old_ucr); 1227 ucr1 = old_ucr.ucr1; 1228 1229 if (is_imx1_uart(sport)) 1230 ucr1 |= IMX1_UCR1_UARTCLKEN; 1231 ucr1 |= UCR1_UARTEN; 1232 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1233 1234 writel(ucr1, sport->port.membase + UCR1); 1235 1236 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1237 1238 uart_console_write(&sport->port, s, count, imx_console_putchar); 1239 1240 /* 1241 * Finally, wait for transmitter to become empty 1242 * and restore UCR1/2/3 1243 */ 1244 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1245 1246 imx_port_ucrs_restore(&sport->port, &old_ucr); 1247 } 1248 1249 /* 1250 * If the port was already initialised (eg, by a boot loader), 1251 * try to determine the current setup. 1252 */ 1253 static void __init 1254 imx_console_get_options(struct imx_port *sport, int *baud, 1255 int *parity, int *bits) 1256 { 1257 1258 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1259 /* ok, the port was enabled */ 1260 unsigned int ucr2, ubir,ubmr, uartclk; 1261 unsigned int baud_raw; 1262 unsigned int ucfr_rfdiv; 1263 1264 ucr2 = readl(sport->port.membase + UCR2); 1265 1266 *parity = 'n'; 1267 if (ucr2 & UCR2_PREN) { 1268 if (ucr2 & UCR2_PROE) 1269 *parity = 'o'; 1270 else 1271 *parity = 'e'; 1272 } 1273 1274 if (ucr2 & UCR2_WS) 1275 *bits = 8; 1276 else 1277 *bits = 7; 1278 1279 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1280 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1281 1282 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1283 if (ucfr_rfdiv == 6) 1284 ucfr_rfdiv = 7; 1285 else 1286 ucfr_rfdiv = 6 - ucfr_rfdiv; 1287 1288 uartclk = clk_get_rate(sport->clk); 1289 uartclk /= ucfr_rfdiv; 1290 1291 { /* 1292 * The next code provides exact computation of 1293 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1294 * without need of float support or long long division, 1295 * which would be required to prevent 32bit arithmetic overflow 1296 */ 1297 unsigned int mul = ubir + 1; 1298 unsigned int div = 16 * (ubmr + 1); 1299 unsigned int rem = uartclk % div; 1300 1301 baud_raw = (uartclk / div) * mul; 1302 baud_raw += (rem * mul + div / 2) / div; 1303 *baud = (baud_raw + 50) / 100 * 100; 1304 } 1305 1306 if(*baud != baud_raw) 1307 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n", 1308 baud_raw, *baud); 1309 } 1310 } 1311 1312 static int __init 1313 imx_console_setup(struct console *co, char *options) 1314 { 1315 struct imx_port *sport; 1316 int baud = 9600; 1317 int bits = 8; 1318 int parity = 'n'; 1319 int flow = 'n'; 1320 1321 /* 1322 * Check whether an invalid uart number has been specified, and 1323 * if so, search for the first available port that does have 1324 * console support. 1325 */ 1326 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1327 co->index = 0; 1328 sport = imx_ports[co->index]; 1329 if(sport == NULL) 1330 return -ENODEV; 1331 1332 if (options) 1333 uart_parse_options(options, &baud, &parity, &bits, &flow); 1334 else 1335 imx_console_get_options(sport, &baud, &parity, &bits); 1336 1337 imx_setup_ufcr(sport, 0); 1338 1339 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1340 } 1341 1342 static struct uart_driver imx_reg; 1343 static struct console imx_console = { 1344 .name = DEV_NAME, 1345 .write = imx_console_write, 1346 .device = uart_console_device, 1347 .setup = imx_console_setup, 1348 .flags = CON_PRINTBUFFER, 1349 .index = -1, 1350 .data = &imx_reg, 1351 }; 1352 1353 #define IMX_CONSOLE &imx_console 1354 #else 1355 #define IMX_CONSOLE NULL 1356 #endif 1357 1358 static struct uart_driver imx_reg = { 1359 .owner = THIS_MODULE, 1360 .driver_name = DRIVER_NAME, 1361 .dev_name = DEV_NAME, 1362 .major = SERIAL_IMX_MAJOR, 1363 .minor = MINOR_START, 1364 .nr = ARRAY_SIZE(imx_ports), 1365 .cons = IMX_CONSOLE, 1366 }; 1367 1368 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1369 { 1370 struct imx_port *sport = platform_get_drvdata(dev); 1371 unsigned int val; 1372 1373 /* enable wakeup from i.MX UART */ 1374 val = readl(sport->port.membase + UCR3); 1375 val |= UCR3_AWAKEN; 1376 writel(val, sport->port.membase + UCR3); 1377 1378 if (sport) 1379 uart_suspend_port(&imx_reg, &sport->port); 1380 1381 return 0; 1382 } 1383 1384 static int serial_imx_resume(struct platform_device *dev) 1385 { 1386 struct imx_port *sport = platform_get_drvdata(dev); 1387 unsigned int val; 1388 1389 /* disable wakeup from i.MX UART */ 1390 val = readl(sport->port.membase + UCR3); 1391 val &= ~UCR3_AWAKEN; 1392 writel(val, sport->port.membase + UCR3); 1393 1394 if (sport) 1395 uart_resume_port(&imx_reg, &sport->port); 1396 1397 return 0; 1398 } 1399 1400 #ifdef CONFIG_OF 1401 /* 1402 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 1403 * could successfully get all information from dt or a negative errno. 1404 */ 1405 static int serial_imx_probe_dt(struct imx_port *sport, 1406 struct platform_device *pdev) 1407 { 1408 struct device_node *np = pdev->dev.of_node; 1409 const struct of_device_id *of_id = 1410 of_match_device(imx_uart_dt_ids, &pdev->dev); 1411 int ret; 1412 1413 if (!np) 1414 /* no device tree device */ 1415 return 1; 1416 1417 ret = of_alias_get_id(np, "serial"); 1418 if (ret < 0) { 1419 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1420 return ret; 1421 } 1422 sport->port.line = ret; 1423 1424 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1425 sport->have_rtscts = 1; 1426 1427 if (of_get_property(np, "fsl,irda-mode", NULL)) 1428 sport->use_irda = 1; 1429 1430 sport->devdata = of_id->data; 1431 1432 return 0; 1433 } 1434 #else 1435 static inline int serial_imx_probe_dt(struct imx_port *sport, 1436 struct platform_device *pdev) 1437 { 1438 return 1; 1439 } 1440 #endif 1441 1442 static void serial_imx_probe_pdata(struct imx_port *sport, 1443 struct platform_device *pdev) 1444 { 1445 struct imxuart_platform_data *pdata = pdev->dev.platform_data; 1446 1447 sport->port.line = pdev->id; 1448 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 1449 1450 if (!pdata) 1451 return; 1452 1453 if (pdata->flags & IMXUART_HAVE_RTSCTS) 1454 sport->have_rtscts = 1; 1455 1456 if (pdata->flags & IMXUART_IRDA) 1457 sport->use_irda = 1; 1458 } 1459 1460 static int serial_imx_probe(struct platform_device *pdev) 1461 { 1462 struct imx_port *sport; 1463 struct imxuart_platform_data *pdata; 1464 void __iomem *base; 1465 int ret = 0; 1466 struct resource *res; 1467 1468 sport = kzalloc(sizeof(*sport), GFP_KERNEL); 1469 if (!sport) 1470 return -ENOMEM; 1471 1472 ret = serial_imx_probe_dt(sport, pdev); 1473 if (ret > 0) 1474 serial_imx_probe_pdata(sport, pdev); 1475 else if (ret < 0) 1476 goto free; 1477 1478 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1479 if (!res) { 1480 ret = -ENODEV; 1481 goto free; 1482 } 1483 1484 base = ioremap(res->start, PAGE_SIZE); 1485 if (!base) { 1486 ret = -ENOMEM; 1487 goto free; 1488 } 1489 1490 sport->port.dev = &pdev->dev; 1491 sport->port.mapbase = res->start; 1492 sport->port.membase = base; 1493 sport->port.type = PORT_IMX, 1494 sport->port.iotype = UPIO_MEM; 1495 sport->port.irq = platform_get_irq(pdev, 0); 1496 sport->rxirq = platform_get_irq(pdev, 0); 1497 sport->txirq = platform_get_irq(pdev, 1); 1498 sport->rtsirq = platform_get_irq(pdev, 2); 1499 sport->port.fifosize = 32; 1500 sport->port.ops = &imx_pops; 1501 sport->port.flags = UPF_BOOT_AUTOCONF; 1502 init_timer(&sport->timer); 1503 sport->timer.function = imx_timeout; 1504 sport->timer.data = (unsigned long)sport; 1505 1506 sport->clk = clk_get(&pdev->dev, "uart"); 1507 if (IS_ERR(sport->clk)) { 1508 ret = PTR_ERR(sport->clk); 1509 goto unmap; 1510 } 1511 clk_prepare_enable(sport->clk); 1512 1513 sport->port.uartclk = clk_get_rate(sport->clk); 1514 1515 imx_ports[sport->port.line] = sport; 1516 1517 pdata = pdev->dev.platform_data; 1518 if (pdata && pdata->init) { 1519 ret = pdata->init(pdev); 1520 if (ret) 1521 goto clkput; 1522 } 1523 1524 ret = uart_add_one_port(&imx_reg, &sport->port); 1525 if (ret) 1526 goto deinit; 1527 platform_set_drvdata(pdev, &sport->port); 1528 1529 return 0; 1530 deinit: 1531 if (pdata && pdata->exit) 1532 pdata->exit(pdev); 1533 clkput: 1534 clk_disable_unprepare(sport->clk); 1535 clk_put(sport->clk); 1536 unmap: 1537 iounmap(sport->port.membase); 1538 free: 1539 kfree(sport); 1540 1541 return ret; 1542 } 1543 1544 static int serial_imx_remove(struct platform_device *pdev) 1545 { 1546 struct imxuart_platform_data *pdata; 1547 struct imx_port *sport = platform_get_drvdata(pdev); 1548 1549 pdata = pdev->dev.platform_data; 1550 1551 platform_set_drvdata(pdev, NULL); 1552 1553 if (sport) { 1554 uart_remove_one_port(&imx_reg, &sport->port); 1555 clk_disable_unprepare(sport->clk); 1556 clk_put(sport->clk); 1557 } 1558 1559 if (pdata && pdata->exit) 1560 pdata->exit(pdev); 1561 1562 iounmap(sport->port.membase); 1563 kfree(sport); 1564 1565 return 0; 1566 } 1567 1568 static struct platform_driver serial_imx_driver = { 1569 .probe = serial_imx_probe, 1570 .remove = serial_imx_remove, 1571 1572 .suspend = serial_imx_suspend, 1573 .resume = serial_imx_resume, 1574 .id_table = imx_uart_devtype, 1575 .driver = { 1576 .name = "imx-uart", 1577 .owner = THIS_MODULE, 1578 .of_match_table = imx_uart_dt_ids, 1579 }, 1580 }; 1581 1582 static int __init imx_serial_init(void) 1583 { 1584 int ret; 1585 1586 printk(KERN_INFO "Serial: IMX driver\n"); 1587 1588 ret = uart_register_driver(&imx_reg); 1589 if (ret) 1590 return ret; 1591 1592 ret = platform_driver_register(&serial_imx_driver); 1593 if (ret != 0) 1594 uart_unregister_driver(&imx_reg); 1595 1596 return ret; 1597 } 1598 1599 static void __exit imx_serial_exit(void) 1600 { 1601 platform_driver_unregister(&serial_imx_driver); 1602 uart_unregister_driver(&imx_reg); 1603 } 1604 1605 module_init(imx_serial_init); 1606 module_exit(imx_serial_exit); 1607 1608 MODULE_AUTHOR("Sascha Hauer"); 1609 MODULE_DESCRIPTION("IMX generic serial port driver"); 1610 MODULE_LICENSE("GPL"); 1611 MODULE_ALIAS("platform:imx-uart"); 1612