1 /* 2 * Driver for Motorola IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * Copyright (C) 2009 emlix GmbH 10 * Author: Fabian Godehardt (added IrDA support for iMX) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 * [29-Mar-2005] Mike Lee 27 * Added hardware handshake 28 */ 29 30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31 #define SUPPORT_SYSRQ 32 #endif 33 34 #include <linux/module.h> 35 #include <linux/ioport.h> 36 #include <linux/init.h> 37 #include <linux/console.h> 38 #include <linux/sysrq.h> 39 #include <linux/platform_device.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/serial_core.h> 43 #include <linux/serial.h> 44 #include <linux/clk.h> 45 #include <linux/delay.h> 46 #include <linux/rational.h> 47 #include <linux/slab.h> 48 49 #include <asm/io.h> 50 #include <asm/irq.h> 51 #include <mach/hardware.h> 52 #include <mach/imx-uart.h> 53 54 /* Register definitions */ 55 #define URXD0 0x0 /* Receiver Register */ 56 #define URTX0 0x40 /* Transmitter Register */ 57 #define UCR1 0x80 /* Control Register 1 */ 58 #define UCR2 0x84 /* Control Register 2 */ 59 #define UCR3 0x88 /* Control Register 3 */ 60 #define UCR4 0x8c /* Control Register 4 */ 61 #define UFCR 0x90 /* FIFO Control Register */ 62 #define USR1 0x94 /* Status Register 1 */ 63 #define USR2 0x98 /* Status Register 2 */ 64 #define UESC 0x9c /* Escape Character Register */ 65 #define UTIM 0xa0 /* Escape Timer Register */ 66 #define UBIR 0xa4 /* BRM Incremental Register */ 67 #define UBMR 0xa8 /* BRM Modulator Register */ 68 #define UBRC 0xac /* Baud Rate Count Register */ 69 #define MX2_ONEMS 0xb0 /* One Millisecond register */ 70 #define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */ 71 72 /* UART Control Register Bit Fields.*/ 73 #define URXD_CHARRDY (1<<15) 74 #define URXD_ERR (1<<14) 75 #define URXD_OVRRUN (1<<13) 76 #define URXD_FRMERR (1<<12) 77 #define URXD_BRK (1<<11) 78 #define URXD_PRERR (1<<10) 79 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 80 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 81 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 82 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 83 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 84 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 85 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 86 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 87 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 88 #define UCR1_SNDBRK (1<<4) /* Send break */ 89 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 90 #define MX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, mx1 only */ 91 #define UCR1_DOZE (1<<1) /* Doze */ 92 #define UCR1_UARTEN (1<<0) /* UART enabled */ 93 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 94 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 95 #define UCR2_CTSC (1<<13) /* CTS pin control */ 96 #define UCR2_CTS (1<<12) /* Clear to send */ 97 #define UCR2_ESCEN (1<<11) /* Escape enable */ 98 #define UCR2_PREN (1<<8) /* Parity enable */ 99 #define UCR2_PROE (1<<7) /* Parity odd/even */ 100 #define UCR2_STPB (1<<6) /* Stop */ 101 #define UCR2_WS (1<<5) /* Word size */ 102 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 103 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 104 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 105 #define UCR2_SRST (1<<0) /* SW reset */ 106 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 107 #define UCR3_PARERREN (1<<12) /* Parity enable */ 108 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 109 #define UCR3_DSR (1<<10) /* Data set ready */ 110 #define UCR3_DCD (1<<9) /* Data carrier detect */ 111 #define UCR3_RI (1<<8) /* Ring indicator */ 112 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 113 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 114 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 115 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 116 #define MX1_UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ 117 #define MX1_UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ 118 #define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */ 119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 120 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 127 #define UCR4_IRSC (1<<5) /* IR special case */ 128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 134 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 135 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 136 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 137 #define USR1_RTSS (1<<14) /* RTS pin status */ 138 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 139 #define USR1_RTSD (1<<12) /* RTS delta */ 140 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 141 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 142 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 143 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 144 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 145 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 146 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 147 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 148 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 149 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 150 #define USR2_IDLE (1<<12) /* Idle condition */ 151 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 152 #define USR2_WAKE (1<<7) /* Wake */ 153 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 154 #define USR2_TXDC (1<<3) /* Transmitter complete */ 155 #define USR2_BRCD (1<<2) /* Break condition */ 156 #define USR2_ORE (1<<1) /* Overrun error */ 157 #define USR2_RDR (1<<0) /* Recv data ready */ 158 #define UTS_FRCPERR (1<<13) /* Force parity error */ 159 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 160 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 161 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 162 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 163 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 164 #define UTS_SOFTRST (1<<0) /* Software reset */ 165 166 /* We've been assigned a range on the "Low-density serial ports" major */ 167 #define SERIAL_IMX_MAJOR 207 168 #define MINOR_START 16 169 #define DEV_NAME "ttymxc" 170 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS 171 172 /* 173 * This determines how often we check the modem status signals 174 * for any change. They generally aren't connected to an IRQ 175 * so we have to poll them. We also check immediately before 176 * filling the TX fifo incase CTS has been dropped. 177 */ 178 #define MCTRL_TIMEOUT (250*HZ/1000) 179 180 #define DRIVER_NAME "IMX-uart" 181 182 #define UART_NR 8 183 184 struct imx_port { 185 struct uart_port port; 186 struct timer_list timer; 187 unsigned int old_status; 188 int txirq,rxirq,rtsirq; 189 unsigned int have_rtscts:1; 190 unsigned int use_irda:1; 191 unsigned int irda_inv_rx:1; 192 unsigned int irda_inv_tx:1; 193 unsigned short trcv_delay; /* transceiver delay */ 194 struct clk *clk; 195 }; 196 197 #ifdef CONFIG_IRDA 198 #define USE_IRDA(sport) ((sport)->use_irda) 199 #else 200 #define USE_IRDA(sport) (0) 201 #endif 202 203 /* 204 * Handle any change of modem status signal since we were last called. 205 */ 206 static void imx_mctrl_check(struct imx_port *sport) 207 { 208 unsigned int status, changed; 209 210 status = sport->port.ops->get_mctrl(&sport->port); 211 changed = status ^ sport->old_status; 212 213 if (changed == 0) 214 return; 215 216 sport->old_status = status; 217 218 if (changed & TIOCM_RI) 219 sport->port.icount.rng++; 220 if (changed & TIOCM_DSR) 221 sport->port.icount.dsr++; 222 if (changed & TIOCM_CAR) 223 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 224 if (changed & TIOCM_CTS) 225 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 226 227 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 228 } 229 230 /* 231 * This is our per-port timeout handler, for checking the 232 * modem status signals. 233 */ 234 static void imx_timeout(unsigned long data) 235 { 236 struct imx_port *sport = (struct imx_port *)data; 237 unsigned long flags; 238 239 if (sport->port.state) { 240 spin_lock_irqsave(&sport->port.lock, flags); 241 imx_mctrl_check(sport); 242 spin_unlock_irqrestore(&sport->port.lock, flags); 243 244 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 245 } 246 } 247 248 /* 249 * interrupts disabled on entry 250 */ 251 static void imx_stop_tx(struct uart_port *port) 252 { 253 struct imx_port *sport = (struct imx_port *)port; 254 unsigned long temp; 255 256 if (USE_IRDA(sport)) { 257 /* half duplex - wait for end of transmission */ 258 int n = 256; 259 while ((--n > 0) && 260 !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 261 udelay(5); 262 barrier(); 263 } 264 /* 265 * irda transceiver - wait a bit more to avoid 266 * cutoff, hardware dependent 267 */ 268 udelay(sport->trcv_delay); 269 270 /* 271 * half duplex - reactivate receive mode, 272 * flush receive pipe echo crap 273 */ 274 if (readl(sport->port.membase + USR2) & USR2_TXDC) { 275 temp = readl(sport->port.membase + UCR1); 276 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 277 writel(temp, sport->port.membase + UCR1); 278 279 temp = readl(sport->port.membase + UCR4); 280 temp &= ~(UCR4_TCEN); 281 writel(temp, sport->port.membase + UCR4); 282 283 while (readl(sport->port.membase + URXD0) & 284 URXD_CHARRDY) 285 barrier(); 286 287 temp = readl(sport->port.membase + UCR1); 288 temp |= UCR1_RRDYEN; 289 writel(temp, sport->port.membase + UCR1); 290 291 temp = readl(sport->port.membase + UCR4); 292 temp |= UCR4_DREN; 293 writel(temp, sport->port.membase + UCR4); 294 } 295 return; 296 } 297 298 temp = readl(sport->port.membase + UCR1); 299 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 300 } 301 302 /* 303 * interrupts disabled on entry 304 */ 305 static void imx_stop_rx(struct uart_port *port) 306 { 307 struct imx_port *sport = (struct imx_port *)port; 308 unsigned long temp; 309 310 temp = readl(sport->port.membase + UCR2); 311 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2); 312 } 313 314 /* 315 * Set the modem control timer to fire immediately. 316 */ 317 static void imx_enable_ms(struct uart_port *port) 318 { 319 struct imx_port *sport = (struct imx_port *)port; 320 321 mod_timer(&sport->timer, jiffies); 322 } 323 324 static inline void imx_transmit_buffer(struct imx_port *sport) 325 { 326 struct circ_buf *xmit = &sport->port.state->xmit; 327 328 while (!uart_circ_empty(xmit) && 329 !(readl(sport->port.membase + UTS) & UTS_TXFULL)) { 330 /* send xmit->buf[xmit->tail] 331 * out the port here */ 332 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 333 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 334 sport->port.icount.tx++; 335 } 336 337 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 338 uart_write_wakeup(&sport->port); 339 340 if (uart_circ_empty(xmit)) 341 imx_stop_tx(&sport->port); 342 } 343 344 /* 345 * interrupts disabled on entry 346 */ 347 static void imx_start_tx(struct uart_port *port) 348 { 349 struct imx_port *sport = (struct imx_port *)port; 350 unsigned long temp; 351 352 if (USE_IRDA(sport)) { 353 /* half duplex in IrDA mode; have to disable receive mode */ 354 temp = readl(sport->port.membase + UCR4); 355 temp &= ~(UCR4_DREN); 356 writel(temp, sport->port.membase + UCR4); 357 358 temp = readl(sport->port.membase + UCR1); 359 temp &= ~(UCR1_RRDYEN); 360 writel(temp, sport->port.membase + UCR1); 361 } 362 363 temp = readl(sport->port.membase + UCR1); 364 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 365 366 if (USE_IRDA(sport)) { 367 temp = readl(sport->port.membase + UCR1); 368 temp |= UCR1_TRDYEN; 369 writel(temp, sport->port.membase + UCR1); 370 371 temp = readl(sport->port.membase + UCR4); 372 temp |= UCR4_TCEN; 373 writel(temp, sport->port.membase + UCR4); 374 } 375 376 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY) 377 imx_transmit_buffer(sport); 378 } 379 380 static irqreturn_t imx_rtsint(int irq, void *dev_id) 381 { 382 struct imx_port *sport = dev_id; 383 unsigned int val; 384 unsigned long flags; 385 386 spin_lock_irqsave(&sport->port.lock, flags); 387 388 writel(USR1_RTSD, sport->port.membase + USR1); 389 val = readl(sport->port.membase + USR1) & USR1_RTSS; 390 uart_handle_cts_change(&sport->port, !!val); 391 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 392 393 spin_unlock_irqrestore(&sport->port.lock, flags); 394 return IRQ_HANDLED; 395 } 396 397 static irqreturn_t imx_txint(int irq, void *dev_id) 398 { 399 struct imx_port *sport = dev_id; 400 struct circ_buf *xmit = &sport->port.state->xmit; 401 unsigned long flags; 402 403 spin_lock_irqsave(&sport->port.lock,flags); 404 if (sport->port.x_char) 405 { 406 /* Send next char */ 407 writel(sport->port.x_char, sport->port.membase + URTX0); 408 goto out; 409 } 410 411 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 412 imx_stop_tx(&sport->port); 413 goto out; 414 } 415 416 imx_transmit_buffer(sport); 417 418 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 419 uart_write_wakeup(&sport->port); 420 421 out: 422 spin_unlock_irqrestore(&sport->port.lock,flags); 423 return IRQ_HANDLED; 424 } 425 426 static irqreturn_t imx_rxint(int irq, void *dev_id) 427 { 428 struct imx_port *sport = dev_id; 429 unsigned int rx,flg,ignored = 0; 430 struct tty_struct *tty = sport->port.state->port.tty; 431 unsigned long flags, temp; 432 433 spin_lock_irqsave(&sport->port.lock,flags); 434 435 while (readl(sport->port.membase + USR2) & USR2_RDR) { 436 flg = TTY_NORMAL; 437 sport->port.icount.rx++; 438 439 rx = readl(sport->port.membase + URXD0); 440 441 temp = readl(sport->port.membase + USR2); 442 if (temp & USR2_BRCD) { 443 writel(USR2_BRCD, sport->port.membase + USR2); 444 if (uart_handle_break(&sport->port)) 445 continue; 446 } 447 448 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 449 continue; 450 451 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) { 452 if (rx & URXD_PRERR) 453 sport->port.icount.parity++; 454 else if (rx & URXD_FRMERR) 455 sport->port.icount.frame++; 456 if (rx & URXD_OVRRUN) 457 sport->port.icount.overrun++; 458 459 if (rx & sport->port.ignore_status_mask) { 460 if (++ignored > 100) 461 goto out; 462 continue; 463 } 464 465 rx &= sport->port.read_status_mask; 466 467 if (rx & URXD_PRERR) 468 flg = TTY_PARITY; 469 else if (rx & URXD_FRMERR) 470 flg = TTY_FRAME; 471 if (rx & URXD_OVRRUN) 472 flg = TTY_OVERRUN; 473 474 #ifdef SUPPORT_SYSRQ 475 sport->port.sysrq = 0; 476 #endif 477 } 478 479 tty_insert_flip_char(tty, rx, flg); 480 } 481 482 out: 483 spin_unlock_irqrestore(&sport->port.lock,flags); 484 tty_flip_buffer_push(tty); 485 return IRQ_HANDLED; 486 } 487 488 static irqreturn_t imx_int(int irq, void *dev_id) 489 { 490 struct imx_port *sport = dev_id; 491 unsigned int sts; 492 493 sts = readl(sport->port.membase + USR1); 494 495 if (sts & USR1_RRDY) 496 imx_rxint(irq, dev_id); 497 498 if (sts & USR1_TRDY && 499 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 500 imx_txint(irq, dev_id); 501 502 if (sts & USR1_RTSD) 503 imx_rtsint(irq, dev_id); 504 505 return IRQ_HANDLED; 506 } 507 508 /* 509 * Return TIOCSER_TEMT when transmitter is not busy. 510 */ 511 static unsigned int imx_tx_empty(struct uart_port *port) 512 { 513 struct imx_port *sport = (struct imx_port *)port; 514 515 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 516 } 517 518 /* 519 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 520 */ 521 static unsigned int imx_get_mctrl(struct uart_port *port) 522 { 523 struct imx_port *sport = (struct imx_port *)port; 524 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 525 526 if (readl(sport->port.membase + USR1) & USR1_RTSS) 527 tmp |= TIOCM_CTS; 528 529 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 530 tmp |= TIOCM_RTS; 531 532 return tmp; 533 } 534 535 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 536 { 537 struct imx_port *sport = (struct imx_port *)port; 538 unsigned long temp; 539 540 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; 541 542 if (mctrl & TIOCM_RTS) 543 temp |= UCR2_CTS; 544 545 writel(temp, sport->port.membase + UCR2); 546 } 547 548 /* 549 * Interrupts always disabled. 550 */ 551 static void imx_break_ctl(struct uart_port *port, int break_state) 552 { 553 struct imx_port *sport = (struct imx_port *)port; 554 unsigned long flags, temp; 555 556 spin_lock_irqsave(&sport->port.lock, flags); 557 558 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 559 560 if ( break_state != 0 ) 561 temp |= UCR1_SNDBRK; 562 563 writel(temp, sport->port.membase + UCR1); 564 565 spin_unlock_irqrestore(&sport->port.lock, flags); 566 } 567 568 #define TXTL 2 /* reset default */ 569 #define RXTL 1 /* reset default */ 570 571 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 572 { 573 unsigned int val; 574 unsigned int ufcr_rfdiv; 575 576 /* set receiver / transmitter trigger level. 577 * RFDIV is set such way to satisfy requested uartclk value 578 */ 579 val = TXTL << 10 | RXTL; 580 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2) 581 / sport->port.uartclk; 582 583 if(!ufcr_rfdiv) 584 ufcr_rfdiv = 1; 585 586 val |= UFCR_RFDIV_REG(ufcr_rfdiv); 587 588 writel(val, sport->port.membase + UFCR); 589 590 return 0; 591 } 592 593 /* half the RX buffer size */ 594 #define CTSTL 16 595 596 static int imx_startup(struct uart_port *port) 597 { 598 struct imx_port *sport = (struct imx_port *)port; 599 int retval; 600 unsigned long flags, temp; 601 602 imx_setup_ufcr(sport, 0); 603 604 /* disable the DREN bit (Data Ready interrupt enable) before 605 * requesting IRQs 606 */ 607 temp = readl(sport->port.membase + UCR4); 608 609 if (USE_IRDA(sport)) 610 temp |= UCR4_IRSC; 611 612 /* set the trigger level for CTS */ 613 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF); 614 temp |= CTSTL<< UCR4_CTSTL_SHF; 615 616 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 617 618 if (USE_IRDA(sport)) { 619 /* reset fifo's and state machines */ 620 int i = 100; 621 temp = readl(sport->port.membase + UCR2); 622 temp &= ~UCR2_SRST; 623 writel(temp, sport->port.membase + UCR2); 624 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && 625 (--i > 0)) { 626 udelay(1); 627 } 628 } 629 630 /* 631 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 632 * chips only have one interrupt. 633 */ 634 if (sport->txirq > 0) { 635 retval = request_irq(sport->rxirq, imx_rxint, 0, 636 DRIVER_NAME, sport); 637 if (retval) 638 goto error_out1; 639 640 retval = request_irq(sport->txirq, imx_txint, 0, 641 DRIVER_NAME, sport); 642 if (retval) 643 goto error_out2; 644 645 /* do not use RTS IRQ on IrDA */ 646 if (!USE_IRDA(sport)) { 647 retval = request_irq(sport->rtsirq, imx_rtsint, 648 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : 649 IRQF_TRIGGER_FALLING | 650 IRQF_TRIGGER_RISING, 651 DRIVER_NAME, sport); 652 if (retval) 653 goto error_out3; 654 } 655 } else { 656 retval = request_irq(sport->port.irq, imx_int, 0, 657 DRIVER_NAME, sport); 658 if (retval) { 659 free_irq(sport->port.irq, sport); 660 goto error_out1; 661 } 662 } 663 664 /* 665 * Finally, clear and enable interrupts 666 */ 667 writel(USR1_RTSD, sport->port.membase + USR1); 668 669 temp = readl(sport->port.membase + UCR1); 670 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 671 672 if (USE_IRDA(sport)) { 673 temp |= UCR1_IREN; 674 temp &= ~(UCR1_RTSDEN); 675 } 676 677 writel(temp, sport->port.membase + UCR1); 678 679 temp = readl(sport->port.membase + UCR2); 680 temp |= (UCR2_RXEN | UCR2_TXEN); 681 writel(temp, sport->port.membase + UCR2); 682 683 if (USE_IRDA(sport)) { 684 /* clear RX-FIFO */ 685 int i = 64; 686 while ((--i > 0) && 687 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { 688 barrier(); 689 } 690 } 691 692 if (!cpu_is_mx1()) { 693 temp = readl(sport->port.membase + UCR3); 694 temp |= MX2_UCR3_RXDMUXSEL; 695 writel(temp, sport->port.membase + UCR3); 696 } 697 698 if (USE_IRDA(sport)) { 699 temp = readl(sport->port.membase + UCR4); 700 if (sport->irda_inv_rx) 701 temp |= UCR4_INVR; 702 else 703 temp &= ~(UCR4_INVR); 704 writel(temp | UCR4_DREN, sport->port.membase + UCR4); 705 706 temp = readl(sport->port.membase + UCR3); 707 if (sport->irda_inv_tx) 708 temp |= UCR3_INVT; 709 else 710 temp &= ~(UCR3_INVT); 711 writel(temp, sport->port.membase + UCR3); 712 } 713 714 /* 715 * Enable modem status interrupts 716 */ 717 spin_lock_irqsave(&sport->port.lock,flags); 718 imx_enable_ms(&sport->port); 719 spin_unlock_irqrestore(&sport->port.lock,flags); 720 721 if (USE_IRDA(sport)) { 722 struct imxuart_platform_data *pdata; 723 pdata = sport->port.dev->platform_data; 724 sport->irda_inv_rx = pdata->irda_inv_rx; 725 sport->irda_inv_tx = pdata->irda_inv_tx; 726 sport->trcv_delay = pdata->transceiver_delay; 727 if (pdata->irda_enable) 728 pdata->irda_enable(1); 729 } 730 731 return 0; 732 733 error_out3: 734 if (sport->txirq) 735 free_irq(sport->txirq, sport); 736 error_out2: 737 if (sport->rxirq) 738 free_irq(sport->rxirq, sport); 739 error_out1: 740 return retval; 741 } 742 743 static void imx_shutdown(struct uart_port *port) 744 { 745 struct imx_port *sport = (struct imx_port *)port; 746 unsigned long temp; 747 748 temp = readl(sport->port.membase + UCR2); 749 temp &= ~(UCR2_TXEN); 750 writel(temp, sport->port.membase + UCR2); 751 752 if (USE_IRDA(sport)) { 753 struct imxuart_platform_data *pdata; 754 pdata = sport->port.dev->platform_data; 755 if (pdata->irda_enable) 756 pdata->irda_enable(0); 757 } 758 759 /* 760 * Stop our timer. 761 */ 762 del_timer_sync(&sport->timer); 763 764 /* 765 * Free the interrupts 766 */ 767 if (sport->txirq > 0) { 768 if (!USE_IRDA(sport)) 769 free_irq(sport->rtsirq, sport); 770 free_irq(sport->txirq, sport); 771 free_irq(sport->rxirq, sport); 772 } else 773 free_irq(sport->port.irq, sport); 774 775 /* 776 * Disable all interrupts, port and break condition. 777 */ 778 779 temp = readl(sport->port.membase + UCR1); 780 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 781 if (USE_IRDA(sport)) 782 temp &= ~(UCR1_IREN); 783 784 writel(temp, sport->port.membase + UCR1); 785 } 786 787 static void 788 imx_set_termios(struct uart_port *port, struct ktermios *termios, 789 struct ktermios *old) 790 { 791 struct imx_port *sport = (struct imx_port *)port; 792 unsigned long flags; 793 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 794 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 795 unsigned int div, ufcr; 796 unsigned long num, denom; 797 uint64_t tdiv64; 798 799 /* 800 * If we don't support modem control lines, don't allow 801 * these to be set. 802 */ 803 if (0) { 804 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 805 termios->c_cflag |= CLOCAL; 806 } 807 808 /* 809 * We only support CS7 and CS8. 810 */ 811 while ((termios->c_cflag & CSIZE) != CS7 && 812 (termios->c_cflag & CSIZE) != CS8) { 813 termios->c_cflag &= ~CSIZE; 814 termios->c_cflag |= old_csize; 815 old_csize = CS8; 816 } 817 818 if ((termios->c_cflag & CSIZE) == CS8) 819 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 820 else 821 ucr2 = UCR2_SRST | UCR2_IRTS; 822 823 if (termios->c_cflag & CRTSCTS) { 824 if( sport->have_rtscts ) { 825 ucr2 &= ~UCR2_IRTS; 826 ucr2 |= UCR2_CTSC; 827 } else { 828 termios->c_cflag &= ~CRTSCTS; 829 } 830 } 831 832 if (termios->c_cflag & CSTOPB) 833 ucr2 |= UCR2_STPB; 834 if (termios->c_cflag & PARENB) { 835 ucr2 |= UCR2_PREN; 836 if (termios->c_cflag & PARODD) 837 ucr2 |= UCR2_PROE; 838 } 839 840 /* 841 * Ask the core to calculate the divisor for us. 842 */ 843 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 844 quot = uart_get_divisor(port, baud); 845 846 spin_lock_irqsave(&sport->port.lock, flags); 847 848 sport->port.read_status_mask = 0; 849 if (termios->c_iflag & INPCK) 850 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 851 if (termios->c_iflag & (BRKINT | PARMRK)) 852 sport->port.read_status_mask |= URXD_BRK; 853 854 /* 855 * Characters to ignore 856 */ 857 sport->port.ignore_status_mask = 0; 858 if (termios->c_iflag & IGNPAR) 859 sport->port.ignore_status_mask |= URXD_PRERR; 860 if (termios->c_iflag & IGNBRK) { 861 sport->port.ignore_status_mask |= URXD_BRK; 862 /* 863 * If we're ignoring parity and break indicators, 864 * ignore overruns too (for real raw support). 865 */ 866 if (termios->c_iflag & IGNPAR) 867 sport->port.ignore_status_mask |= URXD_OVRRUN; 868 } 869 870 del_timer_sync(&sport->timer); 871 872 /* 873 * Update the per-port timeout. 874 */ 875 uart_update_timeout(port, termios->c_cflag, baud); 876 877 /* 878 * disable interrupts and drain transmitter 879 */ 880 old_ucr1 = readl(sport->port.membase + UCR1); 881 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 882 sport->port.membase + UCR1); 883 884 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC)) 885 barrier(); 886 887 /* then, disable everything */ 888 old_txrxen = readl(sport->port.membase + UCR2); 889 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN), 890 sport->port.membase + UCR2); 891 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 892 893 if (USE_IRDA(sport)) { 894 /* 895 * use maximum available submodule frequency to 896 * avoid missing short pulses due to low sampling rate 897 */ 898 div = 1; 899 } else { 900 div = sport->port.uartclk / (baud * 16); 901 if (div > 7) 902 div = 7; 903 if (!div) 904 div = 1; 905 } 906 907 rational_best_approximation(16 * div * baud, sport->port.uartclk, 908 1 << 16, 1 << 16, &num, &denom); 909 910 tdiv64 = sport->port.uartclk; 911 tdiv64 *= num; 912 do_div(tdiv64, denom * 16 * div); 913 tty_termios_encode_baud_rate(termios, 914 (speed_t)tdiv64, (speed_t)tdiv64); 915 916 num -= 1; 917 denom -= 1; 918 919 ufcr = readl(sport->port.membase + UFCR); 920 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 921 writel(ufcr, sport->port.membase + UFCR); 922 923 writel(num, sport->port.membase + UBIR); 924 writel(denom, sport->port.membase + UBMR); 925 926 if (!cpu_is_mx1()) 927 writel(sport->port.uartclk / div / 1000, 928 sport->port.membase + MX2_ONEMS); 929 930 writel(old_ucr1, sport->port.membase + UCR1); 931 932 /* set the parity, stop bits and data size */ 933 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 934 935 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 936 imx_enable_ms(&sport->port); 937 938 spin_unlock_irqrestore(&sport->port.lock, flags); 939 } 940 941 static const char *imx_type(struct uart_port *port) 942 { 943 struct imx_port *sport = (struct imx_port *)port; 944 945 return sport->port.type == PORT_IMX ? "IMX" : NULL; 946 } 947 948 /* 949 * Release the memory region(s) being used by 'port'. 950 */ 951 static void imx_release_port(struct uart_port *port) 952 { 953 struct platform_device *pdev = to_platform_device(port->dev); 954 struct resource *mmres; 955 956 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 957 release_mem_region(mmres->start, mmres->end - mmres->start + 1); 958 } 959 960 /* 961 * Request the memory region(s) being used by 'port'. 962 */ 963 static int imx_request_port(struct uart_port *port) 964 { 965 struct platform_device *pdev = to_platform_device(port->dev); 966 struct resource *mmres; 967 void *ret; 968 969 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 970 if (!mmres) 971 return -ENODEV; 972 973 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1, 974 "imx-uart"); 975 976 return ret ? 0 : -EBUSY; 977 } 978 979 /* 980 * Configure/autoconfigure the port. 981 */ 982 static void imx_config_port(struct uart_port *port, int flags) 983 { 984 struct imx_port *sport = (struct imx_port *)port; 985 986 if (flags & UART_CONFIG_TYPE && 987 imx_request_port(&sport->port) == 0) 988 sport->port.type = PORT_IMX; 989 } 990 991 /* 992 * Verify the new serial_struct (for TIOCSSERIAL). 993 * The only change we allow are to the flags and type, and 994 * even then only between PORT_IMX and PORT_UNKNOWN 995 */ 996 static int 997 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 998 { 999 struct imx_port *sport = (struct imx_port *)port; 1000 int ret = 0; 1001 1002 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1003 ret = -EINVAL; 1004 if (sport->port.irq != ser->irq) 1005 ret = -EINVAL; 1006 if (ser->io_type != UPIO_MEM) 1007 ret = -EINVAL; 1008 if (sport->port.uartclk / 16 != ser->baud_base) 1009 ret = -EINVAL; 1010 if ((void *)sport->port.mapbase != ser->iomem_base) 1011 ret = -EINVAL; 1012 if (sport->port.iobase != ser->port) 1013 ret = -EINVAL; 1014 if (ser->hub6 != 0) 1015 ret = -EINVAL; 1016 return ret; 1017 } 1018 1019 static struct uart_ops imx_pops = { 1020 .tx_empty = imx_tx_empty, 1021 .set_mctrl = imx_set_mctrl, 1022 .get_mctrl = imx_get_mctrl, 1023 .stop_tx = imx_stop_tx, 1024 .start_tx = imx_start_tx, 1025 .stop_rx = imx_stop_rx, 1026 .enable_ms = imx_enable_ms, 1027 .break_ctl = imx_break_ctl, 1028 .startup = imx_startup, 1029 .shutdown = imx_shutdown, 1030 .set_termios = imx_set_termios, 1031 .type = imx_type, 1032 .release_port = imx_release_port, 1033 .request_port = imx_request_port, 1034 .config_port = imx_config_port, 1035 .verify_port = imx_verify_port, 1036 }; 1037 1038 static struct imx_port *imx_ports[UART_NR]; 1039 1040 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1041 static void imx_console_putchar(struct uart_port *port, int ch) 1042 { 1043 struct imx_port *sport = (struct imx_port *)port; 1044 1045 while (readl(sport->port.membase + UTS) & UTS_TXFULL) 1046 barrier(); 1047 1048 writel(ch, sport->port.membase + URTX0); 1049 } 1050 1051 /* 1052 * Interrupts are disabled on entering 1053 */ 1054 static void 1055 imx_console_write(struct console *co, const char *s, unsigned int count) 1056 { 1057 struct imx_port *sport = imx_ports[co->index]; 1058 unsigned int old_ucr1, old_ucr2, ucr1; 1059 1060 /* 1061 * First, save UCR1/2 and then disable interrupts 1062 */ 1063 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1); 1064 old_ucr2 = readl(sport->port.membase + UCR2); 1065 1066 if (cpu_is_mx1()) 1067 ucr1 |= MX1_UCR1_UARTCLKEN; 1068 ucr1 |= UCR1_UARTEN; 1069 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1070 1071 writel(ucr1, sport->port.membase + UCR1); 1072 1073 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1074 1075 uart_console_write(&sport->port, s, count, imx_console_putchar); 1076 1077 /* 1078 * Finally, wait for transmitter to become empty 1079 * and restore UCR1/2 1080 */ 1081 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1082 1083 writel(old_ucr1, sport->port.membase + UCR1); 1084 writel(old_ucr2, sport->port.membase + UCR2); 1085 } 1086 1087 /* 1088 * If the port was already initialised (eg, by a boot loader), 1089 * try to determine the current setup. 1090 */ 1091 static void __init 1092 imx_console_get_options(struct imx_port *sport, int *baud, 1093 int *parity, int *bits) 1094 { 1095 1096 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1097 /* ok, the port was enabled */ 1098 unsigned int ucr2, ubir,ubmr, uartclk; 1099 unsigned int baud_raw; 1100 unsigned int ucfr_rfdiv; 1101 1102 ucr2 = readl(sport->port.membase + UCR2); 1103 1104 *parity = 'n'; 1105 if (ucr2 & UCR2_PREN) { 1106 if (ucr2 & UCR2_PROE) 1107 *parity = 'o'; 1108 else 1109 *parity = 'e'; 1110 } 1111 1112 if (ucr2 & UCR2_WS) 1113 *bits = 8; 1114 else 1115 *bits = 7; 1116 1117 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1118 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1119 1120 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1121 if (ucfr_rfdiv == 6) 1122 ucfr_rfdiv = 7; 1123 else 1124 ucfr_rfdiv = 6 - ucfr_rfdiv; 1125 1126 uartclk = clk_get_rate(sport->clk); 1127 uartclk /= ucfr_rfdiv; 1128 1129 { /* 1130 * The next code provides exact computation of 1131 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1132 * without need of float support or long long division, 1133 * which would be required to prevent 32bit arithmetic overflow 1134 */ 1135 unsigned int mul = ubir + 1; 1136 unsigned int div = 16 * (ubmr + 1); 1137 unsigned int rem = uartclk % div; 1138 1139 baud_raw = (uartclk / div) * mul; 1140 baud_raw += (rem * mul + div / 2) / div; 1141 *baud = (baud_raw + 50) / 100 * 100; 1142 } 1143 1144 if(*baud != baud_raw) 1145 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n", 1146 baud_raw, *baud); 1147 } 1148 } 1149 1150 static int __init 1151 imx_console_setup(struct console *co, char *options) 1152 { 1153 struct imx_port *sport; 1154 int baud = 9600; 1155 int bits = 8; 1156 int parity = 'n'; 1157 int flow = 'n'; 1158 1159 /* 1160 * Check whether an invalid uart number has been specified, and 1161 * if so, search for the first available port that does have 1162 * console support. 1163 */ 1164 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1165 co->index = 0; 1166 sport = imx_ports[co->index]; 1167 if(sport == NULL) 1168 return -ENODEV; 1169 1170 if (options) 1171 uart_parse_options(options, &baud, &parity, &bits, &flow); 1172 else 1173 imx_console_get_options(sport, &baud, &parity, &bits); 1174 1175 imx_setup_ufcr(sport, 0); 1176 1177 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1178 } 1179 1180 static struct uart_driver imx_reg; 1181 static struct console imx_console = { 1182 .name = DEV_NAME, 1183 .write = imx_console_write, 1184 .device = uart_console_device, 1185 .setup = imx_console_setup, 1186 .flags = CON_PRINTBUFFER, 1187 .index = -1, 1188 .data = &imx_reg, 1189 }; 1190 1191 #define IMX_CONSOLE &imx_console 1192 #else 1193 #define IMX_CONSOLE NULL 1194 #endif 1195 1196 static struct uart_driver imx_reg = { 1197 .owner = THIS_MODULE, 1198 .driver_name = DRIVER_NAME, 1199 .dev_name = DEV_NAME, 1200 .major = SERIAL_IMX_MAJOR, 1201 .minor = MINOR_START, 1202 .nr = ARRAY_SIZE(imx_ports), 1203 .cons = IMX_CONSOLE, 1204 }; 1205 1206 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1207 { 1208 struct imx_port *sport = platform_get_drvdata(dev); 1209 1210 if (sport) 1211 uart_suspend_port(&imx_reg, &sport->port); 1212 1213 return 0; 1214 } 1215 1216 static int serial_imx_resume(struct platform_device *dev) 1217 { 1218 struct imx_port *sport = platform_get_drvdata(dev); 1219 1220 if (sport) 1221 uart_resume_port(&imx_reg, &sport->port); 1222 1223 return 0; 1224 } 1225 1226 static int serial_imx_probe(struct platform_device *pdev) 1227 { 1228 struct imx_port *sport; 1229 struct imxuart_platform_data *pdata; 1230 void __iomem *base; 1231 int ret = 0; 1232 struct resource *res; 1233 1234 sport = kzalloc(sizeof(*sport), GFP_KERNEL); 1235 if (!sport) 1236 return -ENOMEM; 1237 1238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1239 if (!res) { 1240 ret = -ENODEV; 1241 goto free; 1242 } 1243 1244 base = ioremap(res->start, PAGE_SIZE); 1245 if (!base) { 1246 ret = -ENOMEM; 1247 goto free; 1248 } 1249 1250 sport->port.dev = &pdev->dev; 1251 sport->port.mapbase = res->start; 1252 sport->port.membase = base; 1253 sport->port.type = PORT_IMX, 1254 sport->port.iotype = UPIO_MEM; 1255 sport->port.irq = platform_get_irq(pdev, 0); 1256 sport->rxirq = platform_get_irq(pdev, 0); 1257 sport->txirq = platform_get_irq(pdev, 1); 1258 sport->rtsirq = platform_get_irq(pdev, 2); 1259 sport->port.fifosize = 32; 1260 sport->port.ops = &imx_pops; 1261 sport->port.flags = UPF_BOOT_AUTOCONF; 1262 sport->port.line = pdev->id; 1263 init_timer(&sport->timer); 1264 sport->timer.function = imx_timeout; 1265 sport->timer.data = (unsigned long)sport; 1266 1267 sport->clk = clk_get(&pdev->dev, "uart"); 1268 if (IS_ERR(sport->clk)) { 1269 ret = PTR_ERR(sport->clk); 1270 goto unmap; 1271 } 1272 clk_enable(sport->clk); 1273 1274 sport->port.uartclk = clk_get_rate(sport->clk); 1275 1276 imx_ports[pdev->id] = sport; 1277 1278 pdata = pdev->dev.platform_data; 1279 if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS)) 1280 sport->have_rtscts = 1; 1281 1282 #ifdef CONFIG_IRDA 1283 if (pdata && (pdata->flags & IMXUART_IRDA)) 1284 sport->use_irda = 1; 1285 #endif 1286 1287 if (pdata && pdata->init) { 1288 ret = pdata->init(pdev); 1289 if (ret) 1290 goto clkput; 1291 } 1292 1293 ret = uart_add_one_port(&imx_reg, &sport->port); 1294 if (ret) 1295 goto deinit; 1296 platform_set_drvdata(pdev, &sport->port); 1297 1298 return 0; 1299 deinit: 1300 if (pdata && pdata->exit) 1301 pdata->exit(pdev); 1302 clkput: 1303 clk_put(sport->clk); 1304 clk_disable(sport->clk); 1305 unmap: 1306 iounmap(sport->port.membase); 1307 free: 1308 kfree(sport); 1309 1310 return ret; 1311 } 1312 1313 static int serial_imx_remove(struct platform_device *pdev) 1314 { 1315 struct imxuart_platform_data *pdata; 1316 struct imx_port *sport = platform_get_drvdata(pdev); 1317 1318 pdata = pdev->dev.platform_data; 1319 1320 platform_set_drvdata(pdev, NULL); 1321 1322 if (sport) { 1323 uart_remove_one_port(&imx_reg, &sport->port); 1324 clk_put(sport->clk); 1325 } 1326 1327 clk_disable(sport->clk); 1328 1329 if (pdata && pdata->exit) 1330 pdata->exit(pdev); 1331 1332 iounmap(sport->port.membase); 1333 kfree(sport); 1334 1335 return 0; 1336 } 1337 1338 static struct platform_driver serial_imx_driver = { 1339 .probe = serial_imx_probe, 1340 .remove = serial_imx_remove, 1341 1342 .suspend = serial_imx_suspend, 1343 .resume = serial_imx_resume, 1344 .driver = { 1345 .name = "imx-uart", 1346 .owner = THIS_MODULE, 1347 }, 1348 }; 1349 1350 static int __init imx_serial_init(void) 1351 { 1352 int ret; 1353 1354 printk(KERN_INFO "Serial: IMX driver\n"); 1355 1356 ret = uart_register_driver(&imx_reg); 1357 if (ret) 1358 return ret; 1359 1360 ret = platform_driver_register(&serial_imx_driver); 1361 if (ret != 0) 1362 uart_unregister_driver(&imx_reg); 1363 1364 return 0; 1365 } 1366 1367 static void __exit imx_serial_exit(void) 1368 { 1369 platform_driver_unregister(&serial_imx_driver); 1370 uart_unregister_driver(&imx_reg); 1371 } 1372 1373 module_init(imx_serial_init); 1374 module_exit(imx_serial_exit); 1375 1376 MODULE_AUTHOR("Sascha Hauer"); 1377 MODULE_DESCRIPTION("IMX generic serial port driver"); 1378 MODULE_LICENSE("GPL"); 1379 MODULE_ALIAS("platform:imx-uart"); 1380