1 /* 2 * Driver for Motorola IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * Copyright (C) 2009 emlix GmbH 10 * Author: Fabian Godehardt (added IrDA support for iMX) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 * [29-Mar-2005] Mike Lee 27 * Added hardware handshake 28 */ 29 30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31 #define SUPPORT_SYSRQ 32 #endif 33 34 #include <linux/module.h> 35 #include <linux/ioport.h> 36 #include <linux/init.h> 37 #include <linux/console.h> 38 #include <linux/sysrq.h> 39 #include <linux/platform_device.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/serial_core.h> 43 #include <linux/serial.h> 44 #include <linux/clk.h> 45 #include <linux/delay.h> 46 #include <linux/rational.h> 47 #include <linux/slab.h> 48 #include <linux/of.h> 49 #include <linux/of_device.h> 50 #include <linux/io.h> 51 #include <linux/dma-mapping.h> 52 53 #include <asm/irq.h> 54 #include <linux/platform_data/serial-imx.h> 55 #include <linux/platform_data/dma-imx.h> 56 57 /* Register definitions */ 58 #define URXD0 0x0 /* Receiver Register */ 59 #define URTX0 0x40 /* Transmitter Register */ 60 #define UCR1 0x80 /* Control Register 1 */ 61 #define UCR2 0x84 /* Control Register 2 */ 62 #define UCR3 0x88 /* Control Register 3 */ 63 #define UCR4 0x8c /* Control Register 4 */ 64 #define UFCR 0x90 /* FIFO Control Register */ 65 #define USR1 0x94 /* Status Register 1 */ 66 #define USR2 0x98 /* Status Register 2 */ 67 #define UESC 0x9c /* Escape Character Register */ 68 #define UTIM 0xa0 /* Escape Timer Register */ 69 #define UBIR 0xa4 /* BRM Incremental Register */ 70 #define UBMR 0xa8 /* BRM Modulator Register */ 71 #define UBRC 0xac /* Baud Rate Count Register */ 72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 75 76 /* UART Control Register Bit Fields.*/ 77 #define URXD_CHARRDY (1<<15) 78 #define URXD_ERR (1<<14) 79 #define URXD_OVRRUN (1<<13) 80 #define URXD_FRMERR (1<<12) 81 #define URXD_BRK (1<<11) 82 #define URXD_PRERR (1<<10) 83 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 84 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 85 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 86 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 87 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 88 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 89 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 90 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 91 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 92 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 93 #define UCR1_SNDBRK (1<<4) /* Send break */ 94 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 95 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 96 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 97 #define UCR1_DOZE (1<<1) /* Doze */ 98 #define UCR1_UARTEN (1<<0) /* UART enabled */ 99 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 100 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 101 #define UCR2_CTSC (1<<13) /* CTS pin control */ 102 #define UCR2_CTS (1<<12) /* Clear to send */ 103 #define UCR2_ESCEN (1<<11) /* Escape enable */ 104 #define UCR2_PREN (1<<8) /* Parity enable */ 105 #define UCR2_PROE (1<<7) /* Parity odd/even */ 106 #define UCR2_STPB (1<<6) /* Stop */ 107 #define UCR2_WS (1<<5) /* Word size */ 108 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 109 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 110 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 111 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 112 #define UCR2_SRST (1<<0) /* SW reset */ 113 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 114 #define UCR3_PARERREN (1<<12) /* Parity enable */ 115 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 116 #define UCR3_DSR (1<<10) /* Data set ready */ 117 #define UCR3_DCD (1<<9) /* Data carrier detect */ 118 #define UCR3_RI (1<<8) /* Ring indicator */ 119 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 120 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 121 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 122 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 123 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 124 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 125 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 126 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 127 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 128 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 129 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 130 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 131 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 132 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 133 #define UCR4_IRSC (1<<5) /* IR special case */ 134 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 135 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 136 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 137 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 138 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 139 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 140 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 141 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 142 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 143 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 144 #define USR1_RTSS (1<<14) /* RTS pin status */ 145 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 146 #define USR1_RTSD (1<<12) /* RTS delta */ 147 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 148 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 149 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 150 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 151 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 152 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 153 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 154 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 155 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 156 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 157 #define USR2_IDLE (1<<12) /* Idle condition */ 158 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 159 #define USR2_WAKE (1<<7) /* Wake */ 160 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 161 #define USR2_TXDC (1<<3) /* Transmitter complete */ 162 #define USR2_BRCD (1<<2) /* Break condition */ 163 #define USR2_ORE (1<<1) /* Overrun error */ 164 #define USR2_RDR (1<<0) /* Recv data ready */ 165 #define UTS_FRCPERR (1<<13) /* Force parity error */ 166 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 167 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 168 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 169 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 170 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 171 #define UTS_SOFTRST (1<<0) /* Software reset */ 172 173 /* We've been assigned a range on the "Low-density serial ports" major */ 174 #define SERIAL_IMX_MAJOR 207 175 #define MINOR_START 16 176 #define DEV_NAME "ttymxc" 177 178 /* 179 * This determines how often we check the modem status signals 180 * for any change. They generally aren't connected to an IRQ 181 * so we have to poll them. We also check immediately before 182 * filling the TX fifo incase CTS has been dropped. 183 */ 184 #define MCTRL_TIMEOUT (250*HZ/1000) 185 186 #define DRIVER_NAME "IMX-uart" 187 188 #define UART_NR 8 189 190 /* i.mx21 type uart runs on all i.mx except i.mx1 */ 191 enum imx_uart_type { 192 IMX1_UART, 193 IMX21_UART, 194 IMX6Q_UART, 195 }; 196 197 /* device type dependent stuff */ 198 struct imx_uart_data { 199 unsigned uts_reg; 200 enum imx_uart_type devtype; 201 }; 202 203 struct imx_port { 204 struct uart_port port; 205 struct timer_list timer; 206 unsigned int old_status; 207 int txirq, rxirq, rtsirq; 208 unsigned int have_rtscts:1; 209 unsigned int dte_mode:1; 210 unsigned int use_irda:1; 211 unsigned int irda_inv_rx:1; 212 unsigned int irda_inv_tx:1; 213 unsigned short trcv_delay; /* transceiver delay */ 214 struct clk *clk_ipg; 215 struct clk *clk_per; 216 const struct imx_uart_data *devdata; 217 218 /* DMA fields */ 219 unsigned int dma_is_inited:1; 220 unsigned int dma_is_enabled:1; 221 unsigned int dma_is_rxing:1; 222 unsigned int dma_is_txing:1; 223 struct dma_chan *dma_chan_rx, *dma_chan_tx; 224 struct scatterlist rx_sgl, tx_sgl[2]; 225 void *rx_buf; 226 unsigned int tx_bytes; 227 unsigned int dma_tx_nents; 228 wait_queue_head_t dma_wait; 229 }; 230 231 struct imx_port_ucrs { 232 unsigned int ucr1; 233 unsigned int ucr2; 234 unsigned int ucr3; 235 }; 236 237 #ifdef CONFIG_IRDA 238 #define USE_IRDA(sport) ((sport)->use_irda) 239 #else 240 #define USE_IRDA(sport) (0) 241 #endif 242 243 static struct imx_uart_data imx_uart_devdata[] = { 244 [IMX1_UART] = { 245 .uts_reg = IMX1_UTS, 246 .devtype = IMX1_UART, 247 }, 248 [IMX21_UART] = { 249 .uts_reg = IMX21_UTS, 250 .devtype = IMX21_UART, 251 }, 252 [IMX6Q_UART] = { 253 .uts_reg = IMX21_UTS, 254 .devtype = IMX6Q_UART, 255 }, 256 }; 257 258 static struct platform_device_id imx_uart_devtype[] = { 259 { 260 .name = "imx1-uart", 261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 262 }, { 263 .name = "imx21-uart", 264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 265 }, { 266 .name = "imx6q-uart", 267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 268 }, { 269 /* sentinel */ 270 } 271 }; 272 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 273 274 static struct of_device_id imx_uart_dt_ids[] = { 275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 276 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 277 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 278 { /* sentinel */ } 279 }; 280 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 281 282 static inline unsigned uts_reg(struct imx_port *sport) 283 { 284 return sport->devdata->uts_reg; 285 } 286 287 static inline int is_imx1_uart(struct imx_port *sport) 288 { 289 return sport->devdata->devtype == IMX1_UART; 290 } 291 292 static inline int is_imx21_uart(struct imx_port *sport) 293 { 294 return sport->devdata->devtype == IMX21_UART; 295 } 296 297 static inline int is_imx6q_uart(struct imx_port *sport) 298 { 299 return sport->devdata->devtype == IMX6Q_UART; 300 } 301 /* 302 * Save and restore functions for UCR1, UCR2 and UCR3 registers 303 */ 304 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE) 305 static void imx_port_ucrs_save(struct uart_port *port, 306 struct imx_port_ucrs *ucr) 307 { 308 /* save control registers */ 309 ucr->ucr1 = readl(port->membase + UCR1); 310 ucr->ucr2 = readl(port->membase + UCR2); 311 ucr->ucr3 = readl(port->membase + UCR3); 312 } 313 314 static void imx_port_ucrs_restore(struct uart_port *port, 315 struct imx_port_ucrs *ucr) 316 { 317 /* restore control registers */ 318 writel(ucr->ucr1, port->membase + UCR1); 319 writel(ucr->ucr2, port->membase + UCR2); 320 writel(ucr->ucr3, port->membase + UCR3); 321 } 322 #endif 323 324 /* 325 * Handle any change of modem status signal since we were last called. 326 */ 327 static void imx_mctrl_check(struct imx_port *sport) 328 { 329 unsigned int status, changed; 330 331 status = sport->port.ops->get_mctrl(&sport->port); 332 changed = status ^ sport->old_status; 333 334 if (changed == 0) 335 return; 336 337 sport->old_status = status; 338 339 if (changed & TIOCM_RI) 340 sport->port.icount.rng++; 341 if (changed & TIOCM_DSR) 342 sport->port.icount.dsr++; 343 if (changed & TIOCM_CAR) 344 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 345 if (changed & TIOCM_CTS) 346 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 347 348 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 349 } 350 351 /* 352 * This is our per-port timeout handler, for checking the 353 * modem status signals. 354 */ 355 static void imx_timeout(unsigned long data) 356 { 357 struct imx_port *sport = (struct imx_port *)data; 358 unsigned long flags; 359 360 if (sport->port.state) { 361 spin_lock_irqsave(&sport->port.lock, flags); 362 imx_mctrl_check(sport); 363 spin_unlock_irqrestore(&sport->port.lock, flags); 364 365 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 366 } 367 } 368 369 /* 370 * interrupts disabled on entry 371 */ 372 static void imx_stop_tx(struct uart_port *port) 373 { 374 struct imx_port *sport = (struct imx_port *)port; 375 unsigned long temp; 376 377 if (USE_IRDA(sport)) { 378 /* half duplex - wait for end of transmission */ 379 int n = 256; 380 while ((--n > 0) && 381 !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 382 udelay(5); 383 barrier(); 384 } 385 /* 386 * irda transceiver - wait a bit more to avoid 387 * cutoff, hardware dependent 388 */ 389 udelay(sport->trcv_delay); 390 391 /* 392 * half duplex - reactivate receive mode, 393 * flush receive pipe echo crap 394 */ 395 if (readl(sport->port.membase + USR2) & USR2_TXDC) { 396 temp = readl(sport->port.membase + UCR1); 397 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 398 writel(temp, sport->port.membase + UCR1); 399 400 temp = readl(sport->port.membase + UCR4); 401 temp &= ~(UCR4_TCEN); 402 writel(temp, sport->port.membase + UCR4); 403 404 while (readl(sport->port.membase + URXD0) & 405 URXD_CHARRDY) 406 barrier(); 407 408 temp = readl(sport->port.membase + UCR1); 409 temp |= UCR1_RRDYEN; 410 writel(temp, sport->port.membase + UCR1); 411 412 temp = readl(sport->port.membase + UCR4); 413 temp |= UCR4_DREN; 414 writel(temp, sport->port.membase + UCR4); 415 } 416 return; 417 } 418 419 /* 420 * We are maybe in the SMP context, so if the DMA TX thread is running 421 * on other cpu, we have to wait for it to finish. 422 */ 423 if (sport->dma_is_enabled && sport->dma_is_txing) 424 return; 425 426 temp = readl(sport->port.membase + UCR1); 427 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 428 } 429 430 /* 431 * interrupts disabled on entry 432 */ 433 static void imx_stop_rx(struct uart_port *port) 434 { 435 struct imx_port *sport = (struct imx_port *)port; 436 unsigned long temp; 437 438 /* 439 * We are maybe in the SMP context, so if the DMA TX thread is running 440 * on other cpu, we have to wait for it to finish. 441 */ 442 if (sport->dma_is_enabled && sport->dma_is_rxing) 443 return; 444 445 temp = readl(sport->port.membase + UCR2); 446 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 447 448 /* disable the `Receiver Ready Interrrupt` */ 449 temp = readl(sport->port.membase + UCR1); 450 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 451 } 452 453 /* 454 * Set the modem control timer to fire immediately. 455 */ 456 static void imx_enable_ms(struct uart_port *port) 457 { 458 struct imx_port *sport = (struct imx_port *)port; 459 460 mod_timer(&sport->timer, jiffies); 461 } 462 463 static inline void imx_transmit_buffer(struct imx_port *sport) 464 { 465 struct circ_buf *xmit = &sport->port.state->xmit; 466 467 while (!uart_circ_empty(xmit) && 468 !(readl(sport->port.membase + uts_reg(sport)) 469 & UTS_TXFULL)) { 470 /* send xmit->buf[xmit->tail] 471 * out the port here */ 472 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 473 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 474 sport->port.icount.tx++; 475 } 476 477 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 478 uart_write_wakeup(&sport->port); 479 480 if (uart_circ_empty(xmit)) 481 imx_stop_tx(&sport->port); 482 } 483 484 static void dma_tx_callback(void *data) 485 { 486 struct imx_port *sport = data; 487 struct scatterlist *sgl = &sport->tx_sgl[0]; 488 struct circ_buf *xmit = &sport->port.state->xmit; 489 unsigned long flags; 490 491 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 492 493 sport->dma_is_txing = 0; 494 495 /* update the stat */ 496 spin_lock_irqsave(&sport->port.lock, flags); 497 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 498 sport->port.icount.tx += sport->tx_bytes; 499 spin_unlock_irqrestore(&sport->port.lock, flags); 500 501 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 502 503 uart_write_wakeup(&sport->port); 504 505 if (waitqueue_active(&sport->dma_wait)) { 506 wake_up(&sport->dma_wait); 507 dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 508 return; 509 } 510 } 511 512 static void imx_dma_tx(struct imx_port *sport) 513 { 514 struct circ_buf *xmit = &sport->port.state->xmit; 515 struct scatterlist *sgl = sport->tx_sgl; 516 struct dma_async_tx_descriptor *desc; 517 struct dma_chan *chan = sport->dma_chan_tx; 518 struct device *dev = sport->port.dev; 519 enum dma_status status; 520 int ret; 521 522 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL); 523 if (DMA_IN_PROGRESS == status) 524 return; 525 526 sport->tx_bytes = uart_circ_chars_pending(xmit); 527 528 if (xmit->tail > xmit->head && xmit->head > 0) { 529 sport->dma_tx_nents = 2; 530 sg_init_table(sgl, 2); 531 sg_set_buf(sgl, xmit->buf + xmit->tail, 532 UART_XMIT_SIZE - xmit->tail); 533 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 534 } else { 535 sport->dma_tx_nents = 1; 536 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 537 } 538 539 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 540 if (ret == 0) { 541 dev_err(dev, "DMA mapping error for TX.\n"); 542 return; 543 } 544 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 545 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 546 if (!desc) { 547 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 548 return; 549 } 550 desc->callback = dma_tx_callback; 551 desc->callback_param = sport; 552 553 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 554 uart_circ_chars_pending(xmit)); 555 /* fire it */ 556 sport->dma_is_txing = 1; 557 dmaengine_submit(desc); 558 dma_async_issue_pending(chan); 559 return; 560 } 561 562 /* 563 * interrupts disabled on entry 564 */ 565 static void imx_start_tx(struct uart_port *port) 566 { 567 struct imx_port *sport = (struct imx_port *)port; 568 unsigned long temp; 569 570 if (USE_IRDA(sport)) { 571 /* half duplex in IrDA mode; have to disable receive mode */ 572 temp = readl(sport->port.membase + UCR4); 573 temp &= ~(UCR4_DREN); 574 writel(temp, sport->port.membase + UCR4); 575 576 temp = readl(sport->port.membase + UCR1); 577 temp &= ~(UCR1_RRDYEN); 578 writel(temp, sport->port.membase + UCR1); 579 } 580 /* Clear any pending ORE flag before enabling interrupt */ 581 temp = readl(sport->port.membase + USR2); 582 writel(temp | USR2_ORE, sport->port.membase + USR2); 583 584 temp = readl(sport->port.membase + UCR4); 585 temp |= UCR4_OREN; 586 writel(temp, sport->port.membase + UCR4); 587 588 if (!sport->dma_is_enabled) { 589 temp = readl(sport->port.membase + UCR1); 590 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 591 } 592 593 if (USE_IRDA(sport)) { 594 temp = readl(sport->port.membase + UCR1); 595 temp |= UCR1_TRDYEN; 596 writel(temp, sport->port.membase + UCR1); 597 598 temp = readl(sport->port.membase + UCR4); 599 temp |= UCR4_TCEN; 600 writel(temp, sport->port.membase + UCR4); 601 } 602 603 if (sport->dma_is_enabled) { 604 imx_dma_tx(sport); 605 return; 606 } 607 608 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) 609 imx_transmit_buffer(sport); 610 } 611 612 static irqreturn_t imx_rtsint(int irq, void *dev_id) 613 { 614 struct imx_port *sport = dev_id; 615 unsigned int val; 616 unsigned long flags; 617 618 spin_lock_irqsave(&sport->port.lock, flags); 619 620 writel(USR1_RTSD, sport->port.membase + USR1); 621 val = readl(sport->port.membase + USR1) & USR1_RTSS; 622 uart_handle_cts_change(&sport->port, !!val); 623 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 624 625 spin_unlock_irqrestore(&sport->port.lock, flags); 626 return IRQ_HANDLED; 627 } 628 629 static irqreturn_t imx_txint(int irq, void *dev_id) 630 { 631 struct imx_port *sport = dev_id; 632 struct circ_buf *xmit = &sport->port.state->xmit; 633 unsigned long flags; 634 635 spin_lock_irqsave(&sport->port.lock, flags); 636 if (sport->port.x_char) { 637 /* Send next char */ 638 writel(sport->port.x_char, sport->port.membase + URTX0); 639 goto out; 640 } 641 642 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 643 imx_stop_tx(&sport->port); 644 goto out; 645 } 646 647 imx_transmit_buffer(sport); 648 649 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 650 uart_write_wakeup(&sport->port); 651 652 out: 653 spin_unlock_irqrestore(&sport->port.lock, flags); 654 return IRQ_HANDLED; 655 } 656 657 static irqreturn_t imx_rxint(int irq, void *dev_id) 658 { 659 struct imx_port *sport = dev_id; 660 unsigned int rx, flg, ignored = 0; 661 struct tty_port *port = &sport->port.state->port; 662 unsigned long flags, temp; 663 664 spin_lock_irqsave(&sport->port.lock, flags); 665 666 while (readl(sport->port.membase + USR2) & USR2_RDR) { 667 flg = TTY_NORMAL; 668 sport->port.icount.rx++; 669 670 rx = readl(sport->port.membase + URXD0); 671 672 temp = readl(sport->port.membase + USR2); 673 if (temp & USR2_BRCD) { 674 writel(USR2_BRCD, sport->port.membase + USR2); 675 if (uart_handle_break(&sport->port)) 676 continue; 677 } 678 679 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 680 continue; 681 682 if (unlikely(rx & URXD_ERR)) { 683 if (rx & URXD_BRK) 684 sport->port.icount.brk++; 685 else if (rx & URXD_PRERR) 686 sport->port.icount.parity++; 687 else if (rx & URXD_FRMERR) 688 sport->port.icount.frame++; 689 if (rx & URXD_OVRRUN) 690 sport->port.icount.overrun++; 691 692 if (rx & sport->port.ignore_status_mask) { 693 if (++ignored > 100) 694 goto out; 695 continue; 696 } 697 698 rx &= sport->port.read_status_mask; 699 700 if (rx & URXD_BRK) 701 flg = TTY_BREAK; 702 else if (rx & URXD_PRERR) 703 flg = TTY_PARITY; 704 else if (rx & URXD_FRMERR) 705 flg = TTY_FRAME; 706 if (rx & URXD_OVRRUN) 707 flg = TTY_OVERRUN; 708 709 #ifdef SUPPORT_SYSRQ 710 sport->port.sysrq = 0; 711 #endif 712 } 713 714 tty_insert_flip_char(port, rx, flg); 715 } 716 717 out: 718 spin_unlock_irqrestore(&sport->port.lock, flags); 719 tty_flip_buffer_push(port); 720 return IRQ_HANDLED; 721 } 722 723 static int start_rx_dma(struct imx_port *sport); 724 /* 725 * If the RXFIFO is filled with some data, and then we 726 * arise a DMA operation to receive them. 727 */ 728 static void imx_dma_rxint(struct imx_port *sport) 729 { 730 unsigned long temp; 731 732 temp = readl(sport->port.membase + USR2); 733 if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 734 sport->dma_is_rxing = 1; 735 736 /* disable the `Recerver Ready Interrrupt` */ 737 temp = readl(sport->port.membase + UCR1); 738 temp &= ~(UCR1_RRDYEN); 739 writel(temp, sport->port.membase + UCR1); 740 741 /* tell the DMA to receive the data. */ 742 start_rx_dma(sport); 743 } 744 } 745 746 static irqreturn_t imx_int(int irq, void *dev_id) 747 { 748 struct imx_port *sport = dev_id; 749 unsigned int sts; 750 unsigned int sts2; 751 752 sts = readl(sport->port.membase + USR1); 753 754 if (sts & USR1_RRDY) { 755 if (sport->dma_is_enabled) 756 imx_dma_rxint(sport); 757 else 758 imx_rxint(irq, dev_id); 759 } 760 761 if (sts & USR1_TRDY && 762 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 763 imx_txint(irq, dev_id); 764 765 if (sts & USR1_RTSD) 766 imx_rtsint(irq, dev_id); 767 768 if (sts & USR1_AWAKE) 769 writel(USR1_AWAKE, sport->port.membase + USR1); 770 771 sts2 = readl(sport->port.membase + USR2); 772 if (sts2 & USR2_ORE) { 773 dev_err(sport->port.dev, "Rx FIFO overrun\n"); 774 sport->port.icount.overrun++; 775 writel(sts2 | USR2_ORE, sport->port.membase + USR2); 776 } 777 778 return IRQ_HANDLED; 779 } 780 781 /* 782 * Return TIOCSER_TEMT when transmitter is not busy. 783 */ 784 static unsigned int imx_tx_empty(struct uart_port *port) 785 { 786 struct imx_port *sport = (struct imx_port *)port; 787 unsigned int ret; 788 789 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 790 791 /* If the TX DMA is working, return 0. */ 792 if (sport->dma_is_enabled && sport->dma_is_txing) 793 ret = 0; 794 795 return ret; 796 } 797 798 /* 799 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 800 */ 801 static unsigned int imx_get_mctrl(struct uart_port *port) 802 { 803 struct imx_port *sport = (struct imx_port *)port; 804 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 805 806 if (readl(sport->port.membase + USR1) & USR1_RTSS) 807 tmp |= TIOCM_CTS; 808 809 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 810 tmp |= TIOCM_RTS; 811 812 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 813 tmp |= TIOCM_LOOP; 814 815 return tmp; 816 } 817 818 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 819 { 820 struct imx_port *sport = (struct imx_port *)port; 821 unsigned long temp; 822 823 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; 824 825 if (mctrl & TIOCM_RTS) 826 if (!sport->dma_is_enabled) 827 temp |= UCR2_CTS; 828 829 writel(temp, sport->port.membase + UCR2); 830 831 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 832 if (mctrl & TIOCM_LOOP) 833 temp |= UTS_LOOP; 834 writel(temp, sport->port.membase + uts_reg(sport)); 835 } 836 837 /* 838 * Interrupts always disabled. 839 */ 840 static void imx_break_ctl(struct uart_port *port, int break_state) 841 { 842 struct imx_port *sport = (struct imx_port *)port; 843 unsigned long flags, temp; 844 845 spin_lock_irqsave(&sport->port.lock, flags); 846 847 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 848 849 if (break_state != 0) 850 temp |= UCR1_SNDBRK; 851 852 writel(temp, sport->port.membase + UCR1); 853 854 spin_unlock_irqrestore(&sport->port.lock, flags); 855 } 856 857 #define TXTL 2 /* reset default */ 858 #define RXTL 1 /* reset default */ 859 860 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 861 { 862 unsigned int val; 863 864 /* set receiver / transmitter trigger level */ 865 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 866 val |= TXTL << UFCR_TXTL_SHF | RXTL; 867 writel(val, sport->port.membase + UFCR); 868 return 0; 869 } 870 871 #define RX_BUF_SIZE (PAGE_SIZE) 872 static void imx_rx_dma_done(struct imx_port *sport) 873 { 874 unsigned long temp; 875 876 /* Enable this interrupt when the RXFIFO is empty. */ 877 temp = readl(sport->port.membase + UCR1); 878 temp |= UCR1_RRDYEN; 879 writel(temp, sport->port.membase + UCR1); 880 881 sport->dma_is_rxing = 0; 882 883 /* Is the shutdown waiting for us? */ 884 if (waitqueue_active(&sport->dma_wait)) 885 wake_up(&sport->dma_wait); 886 } 887 888 /* 889 * There are three kinds of RX DMA interrupts(such as in the MX6Q): 890 * [1] the RX DMA buffer is full. 891 * [2] the Aging timer expires(wait for 8 bytes long) 892 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 893 * 894 * The [2] is trigger when a character was been sitting in the FIFO 895 * meanwhile [3] can wait for 32 bytes long when the RX line is 896 * on IDLE state and RxFIFO is empty. 897 */ 898 static void dma_rx_callback(void *data) 899 { 900 struct imx_port *sport = data; 901 struct dma_chan *chan = sport->dma_chan_rx; 902 struct scatterlist *sgl = &sport->rx_sgl; 903 struct tty_port *port = &sport->port.state->port; 904 struct dma_tx_state state; 905 enum dma_status status; 906 unsigned int count; 907 908 /* unmap it first */ 909 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 910 911 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 912 count = RX_BUF_SIZE - state.residue; 913 dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 914 915 if (count) { 916 tty_insert_flip_string(port, sport->rx_buf, count); 917 tty_flip_buffer_push(port); 918 919 start_rx_dma(sport); 920 } else 921 imx_rx_dma_done(sport); 922 } 923 924 static int start_rx_dma(struct imx_port *sport) 925 { 926 struct scatterlist *sgl = &sport->rx_sgl; 927 struct dma_chan *chan = sport->dma_chan_rx; 928 struct device *dev = sport->port.dev; 929 struct dma_async_tx_descriptor *desc; 930 int ret; 931 932 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 933 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 934 if (ret == 0) { 935 dev_err(dev, "DMA mapping error for RX.\n"); 936 return -EINVAL; 937 } 938 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 939 DMA_PREP_INTERRUPT); 940 if (!desc) { 941 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 942 return -EINVAL; 943 } 944 desc->callback = dma_rx_callback; 945 desc->callback_param = sport; 946 947 dev_dbg(dev, "RX: prepare for the DMA.\n"); 948 dmaengine_submit(desc); 949 dma_async_issue_pending(chan); 950 return 0; 951 } 952 953 static void imx_uart_dma_exit(struct imx_port *sport) 954 { 955 if (sport->dma_chan_rx) { 956 dma_release_channel(sport->dma_chan_rx); 957 sport->dma_chan_rx = NULL; 958 959 kfree(sport->rx_buf); 960 sport->rx_buf = NULL; 961 } 962 963 if (sport->dma_chan_tx) { 964 dma_release_channel(sport->dma_chan_tx); 965 sport->dma_chan_tx = NULL; 966 } 967 968 sport->dma_is_inited = 0; 969 } 970 971 static int imx_uart_dma_init(struct imx_port *sport) 972 { 973 struct dma_slave_config slave_config = {}; 974 struct device *dev = sport->port.dev; 975 int ret; 976 977 /* Prepare for RX : */ 978 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 979 if (!sport->dma_chan_rx) { 980 dev_dbg(dev, "cannot get the DMA channel.\n"); 981 ret = -EINVAL; 982 goto err; 983 } 984 985 slave_config.direction = DMA_DEV_TO_MEM; 986 slave_config.src_addr = sport->port.mapbase + URXD0; 987 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 988 slave_config.src_maxburst = RXTL; 989 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 990 if (ret) { 991 dev_err(dev, "error in RX dma configuration.\n"); 992 goto err; 993 } 994 995 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 996 if (!sport->rx_buf) { 997 dev_err(dev, "cannot alloc DMA buffer.\n"); 998 ret = -ENOMEM; 999 goto err; 1000 } 1001 1002 /* Prepare for TX : */ 1003 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1004 if (!sport->dma_chan_tx) { 1005 dev_err(dev, "cannot get the TX DMA channel!\n"); 1006 ret = -EINVAL; 1007 goto err; 1008 } 1009 1010 slave_config.direction = DMA_MEM_TO_DEV; 1011 slave_config.dst_addr = sport->port.mapbase + URTX0; 1012 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1013 slave_config.dst_maxburst = TXTL; 1014 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1015 if (ret) { 1016 dev_err(dev, "error in TX dma configuration."); 1017 goto err; 1018 } 1019 1020 sport->dma_is_inited = 1; 1021 1022 return 0; 1023 err: 1024 imx_uart_dma_exit(sport); 1025 return ret; 1026 } 1027 1028 static void imx_enable_dma(struct imx_port *sport) 1029 { 1030 unsigned long temp; 1031 1032 init_waitqueue_head(&sport->dma_wait); 1033 1034 /* set UCR1 */ 1035 temp = readl(sport->port.membase + UCR1); 1036 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1037 /* wait for 32 idle frames for IDDMA interrupt */ 1038 UCR1_ICD_REG(3); 1039 writel(temp, sport->port.membase + UCR1); 1040 1041 /* set UCR4 */ 1042 temp = readl(sport->port.membase + UCR4); 1043 temp |= UCR4_IDDMAEN; 1044 writel(temp, sport->port.membase + UCR4); 1045 1046 sport->dma_is_enabled = 1; 1047 } 1048 1049 static void imx_disable_dma(struct imx_port *sport) 1050 { 1051 unsigned long temp; 1052 1053 /* clear UCR1 */ 1054 temp = readl(sport->port.membase + UCR1); 1055 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1056 writel(temp, sport->port.membase + UCR1); 1057 1058 /* clear UCR2 */ 1059 temp = readl(sport->port.membase + UCR2); 1060 temp &= ~(UCR2_CTSC | UCR2_CTS); 1061 writel(temp, sport->port.membase + UCR2); 1062 1063 /* clear UCR4 */ 1064 temp = readl(sport->port.membase + UCR4); 1065 temp &= ~UCR4_IDDMAEN; 1066 writel(temp, sport->port.membase + UCR4); 1067 1068 sport->dma_is_enabled = 0; 1069 } 1070 1071 /* half the RX buffer size */ 1072 #define CTSTL 16 1073 1074 static int imx_startup(struct uart_port *port) 1075 { 1076 struct imx_port *sport = (struct imx_port *)port; 1077 int retval, i; 1078 unsigned long flags, temp; 1079 1080 retval = clk_prepare_enable(sport->clk_per); 1081 if (retval) 1082 goto error_out1; 1083 retval = clk_prepare_enable(sport->clk_ipg); 1084 if (retval) { 1085 clk_disable_unprepare(sport->clk_per); 1086 goto error_out1; 1087 } 1088 1089 imx_setup_ufcr(sport, 0); 1090 1091 /* disable the DREN bit (Data Ready interrupt enable) before 1092 * requesting IRQs 1093 */ 1094 temp = readl(sport->port.membase + UCR4); 1095 1096 if (USE_IRDA(sport)) 1097 temp |= UCR4_IRSC; 1098 1099 /* set the trigger level for CTS */ 1100 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1101 temp |= CTSTL << UCR4_CTSTL_SHF; 1102 1103 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1104 1105 /* Reset fifo's and state machines */ 1106 i = 100; 1107 1108 temp = readl(sport->port.membase + UCR2); 1109 temp &= ~UCR2_SRST; 1110 writel(temp, sport->port.membase + UCR2); 1111 1112 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1113 udelay(1); 1114 1115 /* 1116 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 1117 * chips only have one interrupt. 1118 */ 1119 if (sport->txirq > 0) { 1120 retval = request_irq(sport->rxirq, imx_rxint, 0, 1121 dev_name(port->dev), sport); 1122 if (retval) 1123 goto error_out1; 1124 1125 retval = request_irq(sport->txirq, imx_txint, 0, 1126 dev_name(port->dev), sport); 1127 if (retval) 1128 goto error_out2; 1129 1130 /* do not use RTS IRQ on IrDA */ 1131 if (!USE_IRDA(sport)) { 1132 retval = request_irq(sport->rtsirq, imx_rtsint, 0, 1133 dev_name(port->dev), sport); 1134 if (retval) 1135 goto error_out3; 1136 } 1137 } else { 1138 retval = request_irq(sport->port.irq, imx_int, 0, 1139 dev_name(port->dev), sport); 1140 if (retval) { 1141 free_irq(sport->port.irq, sport); 1142 goto error_out1; 1143 } 1144 } 1145 1146 spin_lock_irqsave(&sport->port.lock, flags); 1147 /* 1148 * Finally, clear and enable interrupts 1149 */ 1150 writel(USR1_RTSD, sport->port.membase + USR1); 1151 1152 temp = readl(sport->port.membase + UCR1); 1153 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1154 1155 if (USE_IRDA(sport)) { 1156 temp |= UCR1_IREN; 1157 temp &= ~(UCR1_RTSDEN); 1158 } 1159 1160 writel(temp, sport->port.membase + UCR1); 1161 1162 temp = readl(sport->port.membase + UCR2); 1163 temp |= (UCR2_RXEN | UCR2_TXEN); 1164 if (!sport->have_rtscts) 1165 temp |= UCR2_IRTS; 1166 writel(temp, sport->port.membase + UCR2); 1167 1168 if (!is_imx1_uart(sport)) { 1169 temp = readl(sport->port.membase + UCR3); 1170 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1171 writel(temp, sport->port.membase + UCR3); 1172 } 1173 1174 if (USE_IRDA(sport)) { 1175 temp = readl(sport->port.membase + UCR4); 1176 if (sport->irda_inv_rx) 1177 temp |= UCR4_INVR; 1178 else 1179 temp &= ~(UCR4_INVR); 1180 writel(temp | UCR4_DREN, sport->port.membase + UCR4); 1181 1182 temp = readl(sport->port.membase + UCR3); 1183 if (sport->irda_inv_tx) 1184 temp |= UCR3_INVT; 1185 else 1186 temp &= ~(UCR3_INVT); 1187 writel(temp, sport->port.membase + UCR3); 1188 } 1189 1190 /* 1191 * Enable modem status interrupts 1192 */ 1193 imx_enable_ms(&sport->port); 1194 spin_unlock_irqrestore(&sport->port.lock, flags); 1195 1196 if (USE_IRDA(sport)) { 1197 struct imxuart_platform_data *pdata; 1198 pdata = dev_get_platdata(sport->port.dev); 1199 sport->irda_inv_rx = pdata->irda_inv_rx; 1200 sport->irda_inv_tx = pdata->irda_inv_tx; 1201 sport->trcv_delay = pdata->transceiver_delay; 1202 if (pdata->irda_enable) 1203 pdata->irda_enable(1); 1204 } 1205 1206 return 0; 1207 1208 error_out3: 1209 if (sport->txirq) 1210 free_irq(sport->txirq, sport); 1211 error_out2: 1212 if (sport->rxirq) 1213 free_irq(sport->rxirq, sport); 1214 error_out1: 1215 return retval; 1216 } 1217 1218 static void imx_shutdown(struct uart_port *port) 1219 { 1220 struct imx_port *sport = (struct imx_port *)port; 1221 unsigned long temp; 1222 unsigned long flags; 1223 1224 if (sport->dma_is_enabled) { 1225 /* We have to wait for the DMA to finish. */ 1226 wait_event(sport->dma_wait, 1227 !sport->dma_is_rxing && !sport->dma_is_txing); 1228 imx_stop_rx(port); 1229 imx_disable_dma(sport); 1230 imx_uart_dma_exit(sport); 1231 } 1232 1233 spin_lock_irqsave(&sport->port.lock, flags); 1234 temp = readl(sport->port.membase + UCR2); 1235 temp &= ~(UCR2_TXEN); 1236 writel(temp, sport->port.membase + UCR2); 1237 spin_unlock_irqrestore(&sport->port.lock, flags); 1238 1239 if (USE_IRDA(sport)) { 1240 struct imxuart_platform_data *pdata; 1241 pdata = dev_get_platdata(sport->port.dev); 1242 if (pdata->irda_enable) 1243 pdata->irda_enable(0); 1244 } 1245 1246 /* 1247 * Stop our timer. 1248 */ 1249 del_timer_sync(&sport->timer); 1250 1251 /* 1252 * Free the interrupts 1253 */ 1254 if (sport->txirq > 0) { 1255 if (!USE_IRDA(sport)) 1256 free_irq(sport->rtsirq, sport); 1257 free_irq(sport->txirq, sport); 1258 free_irq(sport->rxirq, sport); 1259 } else 1260 free_irq(sport->port.irq, sport); 1261 1262 /* 1263 * Disable all interrupts, port and break condition. 1264 */ 1265 1266 spin_lock_irqsave(&sport->port.lock, flags); 1267 temp = readl(sport->port.membase + UCR1); 1268 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1269 if (USE_IRDA(sport)) 1270 temp &= ~(UCR1_IREN); 1271 1272 writel(temp, sport->port.membase + UCR1); 1273 spin_unlock_irqrestore(&sport->port.lock, flags); 1274 1275 clk_disable_unprepare(sport->clk_per); 1276 clk_disable_unprepare(sport->clk_ipg); 1277 } 1278 1279 static void imx_flush_buffer(struct uart_port *port) 1280 { 1281 struct imx_port *sport = (struct imx_port *)port; 1282 1283 if (sport->dma_is_enabled) { 1284 sport->tx_bytes = 0; 1285 dmaengine_terminate_all(sport->dma_chan_tx); 1286 } 1287 } 1288 1289 static void 1290 imx_set_termios(struct uart_port *port, struct ktermios *termios, 1291 struct ktermios *old) 1292 { 1293 struct imx_port *sport = (struct imx_port *)port; 1294 unsigned long flags; 1295 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1296 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1297 unsigned int div, ufcr; 1298 unsigned long num, denom; 1299 uint64_t tdiv64; 1300 1301 /* 1302 * If we don't support modem control lines, don't allow 1303 * these to be set. 1304 */ 1305 if (0) { 1306 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 1307 termios->c_cflag |= CLOCAL; 1308 } 1309 1310 /* 1311 * We only support CS7 and CS8. 1312 */ 1313 while ((termios->c_cflag & CSIZE) != CS7 && 1314 (termios->c_cflag & CSIZE) != CS8) { 1315 termios->c_cflag &= ~CSIZE; 1316 termios->c_cflag |= old_csize; 1317 old_csize = CS8; 1318 } 1319 1320 if ((termios->c_cflag & CSIZE) == CS8) 1321 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1322 else 1323 ucr2 = UCR2_SRST | UCR2_IRTS; 1324 1325 if (termios->c_cflag & CRTSCTS) { 1326 if (sport->have_rtscts) { 1327 ucr2 &= ~UCR2_IRTS; 1328 ucr2 |= UCR2_CTSC; 1329 1330 /* Can we enable the DMA support? */ 1331 if (is_imx6q_uart(sport) && !uart_console(port) 1332 && !sport->dma_is_inited) 1333 imx_uart_dma_init(sport); 1334 } else { 1335 termios->c_cflag &= ~CRTSCTS; 1336 } 1337 } 1338 1339 if (termios->c_cflag & CSTOPB) 1340 ucr2 |= UCR2_STPB; 1341 if (termios->c_cflag & PARENB) { 1342 ucr2 |= UCR2_PREN; 1343 if (termios->c_cflag & PARODD) 1344 ucr2 |= UCR2_PROE; 1345 } 1346 1347 del_timer_sync(&sport->timer); 1348 1349 /* 1350 * Ask the core to calculate the divisor for us. 1351 */ 1352 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1353 quot = uart_get_divisor(port, baud); 1354 1355 spin_lock_irqsave(&sport->port.lock, flags); 1356 1357 sport->port.read_status_mask = 0; 1358 if (termios->c_iflag & INPCK) 1359 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1360 if (termios->c_iflag & (BRKINT | PARMRK)) 1361 sport->port.read_status_mask |= URXD_BRK; 1362 1363 /* 1364 * Characters to ignore 1365 */ 1366 sport->port.ignore_status_mask = 0; 1367 if (termios->c_iflag & IGNPAR) 1368 sport->port.ignore_status_mask |= URXD_PRERR; 1369 if (termios->c_iflag & IGNBRK) { 1370 sport->port.ignore_status_mask |= URXD_BRK; 1371 /* 1372 * If we're ignoring parity and break indicators, 1373 * ignore overruns too (for real raw support). 1374 */ 1375 if (termios->c_iflag & IGNPAR) 1376 sport->port.ignore_status_mask |= URXD_OVRRUN; 1377 } 1378 1379 /* 1380 * Update the per-port timeout. 1381 */ 1382 uart_update_timeout(port, termios->c_cflag, baud); 1383 1384 /* 1385 * disable interrupts and drain transmitter 1386 */ 1387 old_ucr1 = readl(sport->port.membase + UCR1); 1388 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1389 sport->port.membase + UCR1); 1390 1391 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1392 barrier(); 1393 1394 /* then, disable everything */ 1395 old_txrxen = readl(sport->port.membase + UCR2); 1396 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1397 sport->port.membase + UCR2); 1398 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1399 1400 if (USE_IRDA(sport)) { 1401 /* 1402 * use maximum available submodule frequency to 1403 * avoid missing short pulses due to low sampling rate 1404 */ 1405 div = 1; 1406 } else { 1407 /* custom-baudrate handling */ 1408 div = sport->port.uartclk / (baud * 16); 1409 if (baud == 38400 && quot != div) 1410 baud = sport->port.uartclk / (quot * 16); 1411 1412 div = sport->port.uartclk / (baud * 16); 1413 if (div > 7) 1414 div = 7; 1415 if (!div) 1416 div = 1; 1417 } 1418 1419 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1420 1 << 16, 1 << 16, &num, &denom); 1421 1422 tdiv64 = sport->port.uartclk; 1423 tdiv64 *= num; 1424 do_div(tdiv64, denom * 16 * div); 1425 tty_termios_encode_baud_rate(termios, 1426 (speed_t)tdiv64, (speed_t)tdiv64); 1427 1428 num -= 1; 1429 denom -= 1; 1430 1431 ufcr = readl(sport->port.membase + UFCR); 1432 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1433 if (sport->dte_mode) 1434 ufcr |= UFCR_DCEDTE; 1435 writel(ufcr, sport->port.membase + UFCR); 1436 1437 writel(num, sport->port.membase + UBIR); 1438 writel(denom, sport->port.membase + UBMR); 1439 1440 if (!is_imx1_uart(sport)) 1441 writel(sport->port.uartclk / div / 1000, 1442 sport->port.membase + IMX21_ONEMS); 1443 1444 writel(old_ucr1, sport->port.membase + UCR1); 1445 1446 /* set the parity, stop bits and data size */ 1447 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1448 1449 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1450 imx_enable_ms(&sport->port); 1451 1452 if (sport->dma_is_inited && !sport->dma_is_enabled) 1453 imx_enable_dma(sport); 1454 spin_unlock_irqrestore(&sport->port.lock, flags); 1455 } 1456 1457 static const char *imx_type(struct uart_port *port) 1458 { 1459 struct imx_port *sport = (struct imx_port *)port; 1460 1461 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1462 } 1463 1464 /* 1465 * Configure/autoconfigure the port. 1466 */ 1467 static void imx_config_port(struct uart_port *port, int flags) 1468 { 1469 struct imx_port *sport = (struct imx_port *)port; 1470 1471 if (flags & UART_CONFIG_TYPE) 1472 sport->port.type = PORT_IMX; 1473 } 1474 1475 /* 1476 * Verify the new serial_struct (for TIOCSSERIAL). 1477 * The only change we allow are to the flags and type, and 1478 * even then only between PORT_IMX and PORT_UNKNOWN 1479 */ 1480 static int 1481 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1482 { 1483 struct imx_port *sport = (struct imx_port *)port; 1484 int ret = 0; 1485 1486 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1487 ret = -EINVAL; 1488 if (sport->port.irq != ser->irq) 1489 ret = -EINVAL; 1490 if (ser->io_type != UPIO_MEM) 1491 ret = -EINVAL; 1492 if (sport->port.uartclk / 16 != ser->baud_base) 1493 ret = -EINVAL; 1494 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1495 ret = -EINVAL; 1496 if (sport->port.iobase != ser->port) 1497 ret = -EINVAL; 1498 if (ser->hub6 != 0) 1499 ret = -EINVAL; 1500 return ret; 1501 } 1502 1503 #if defined(CONFIG_CONSOLE_POLL) 1504 static int imx_poll_get_char(struct uart_port *port) 1505 { 1506 struct imx_port_ucrs old_ucr; 1507 unsigned int status; 1508 unsigned char c; 1509 1510 /* save control registers */ 1511 imx_port_ucrs_save(port, &old_ucr); 1512 1513 /* disable interrupts */ 1514 writel(UCR1_UARTEN, port->membase + UCR1); 1515 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1516 port->membase + UCR2); 1517 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1518 port->membase + UCR3); 1519 1520 /* poll */ 1521 do { 1522 status = readl(port->membase + USR2); 1523 } while (~status & USR2_RDR); 1524 1525 /* read */ 1526 c = readl(port->membase + URXD0); 1527 1528 /* restore control registers */ 1529 imx_port_ucrs_restore(port, &old_ucr); 1530 1531 return c; 1532 } 1533 1534 static void imx_poll_put_char(struct uart_port *port, unsigned char c) 1535 { 1536 struct imx_port_ucrs old_ucr; 1537 unsigned int status; 1538 1539 /* save control registers */ 1540 imx_port_ucrs_save(port, &old_ucr); 1541 1542 /* disable interrupts */ 1543 writel(UCR1_UARTEN, port->membase + UCR1); 1544 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1545 port->membase + UCR2); 1546 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1547 port->membase + UCR3); 1548 1549 /* drain */ 1550 do { 1551 status = readl(port->membase + USR1); 1552 } while (~status & USR1_TRDY); 1553 1554 /* write */ 1555 writel(c, port->membase + URTX0); 1556 1557 /* flush */ 1558 do { 1559 status = readl(port->membase + USR2); 1560 } while (~status & USR2_TXDC); 1561 1562 /* restore control registers */ 1563 imx_port_ucrs_restore(port, &old_ucr); 1564 } 1565 #endif 1566 1567 static struct uart_ops imx_pops = { 1568 .tx_empty = imx_tx_empty, 1569 .set_mctrl = imx_set_mctrl, 1570 .get_mctrl = imx_get_mctrl, 1571 .stop_tx = imx_stop_tx, 1572 .start_tx = imx_start_tx, 1573 .stop_rx = imx_stop_rx, 1574 .enable_ms = imx_enable_ms, 1575 .break_ctl = imx_break_ctl, 1576 .startup = imx_startup, 1577 .shutdown = imx_shutdown, 1578 .flush_buffer = imx_flush_buffer, 1579 .set_termios = imx_set_termios, 1580 .type = imx_type, 1581 .config_port = imx_config_port, 1582 .verify_port = imx_verify_port, 1583 #if defined(CONFIG_CONSOLE_POLL) 1584 .poll_get_char = imx_poll_get_char, 1585 .poll_put_char = imx_poll_put_char, 1586 #endif 1587 }; 1588 1589 static struct imx_port *imx_ports[UART_NR]; 1590 1591 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1592 static void imx_console_putchar(struct uart_port *port, int ch) 1593 { 1594 struct imx_port *sport = (struct imx_port *)port; 1595 1596 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1597 barrier(); 1598 1599 writel(ch, sport->port.membase + URTX0); 1600 } 1601 1602 /* 1603 * Interrupts are disabled on entering 1604 */ 1605 static void 1606 imx_console_write(struct console *co, const char *s, unsigned int count) 1607 { 1608 struct imx_port *sport = imx_ports[co->index]; 1609 struct imx_port_ucrs old_ucr; 1610 unsigned int ucr1; 1611 unsigned long flags = 0; 1612 int locked = 1; 1613 int retval; 1614 1615 retval = clk_enable(sport->clk_per); 1616 if (retval) 1617 return; 1618 retval = clk_enable(sport->clk_ipg); 1619 if (retval) { 1620 clk_disable(sport->clk_per); 1621 return; 1622 } 1623 1624 if (sport->port.sysrq) 1625 locked = 0; 1626 else if (oops_in_progress) 1627 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1628 else 1629 spin_lock_irqsave(&sport->port.lock, flags); 1630 1631 /* 1632 * First, save UCR1/2/3 and then disable interrupts 1633 */ 1634 imx_port_ucrs_save(&sport->port, &old_ucr); 1635 ucr1 = old_ucr.ucr1; 1636 1637 if (is_imx1_uart(sport)) 1638 ucr1 |= IMX1_UCR1_UARTCLKEN; 1639 ucr1 |= UCR1_UARTEN; 1640 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1641 1642 writel(ucr1, sport->port.membase + UCR1); 1643 1644 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1645 1646 uart_console_write(&sport->port, s, count, imx_console_putchar); 1647 1648 /* 1649 * Finally, wait for transmitter to become empty 1650 * and restore UCR1/2/3 1651 */ 1652 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1653 1654 imx_port_ucrs_restore(&sport->port, &old_ucr); 1655 1656 if (locked) 1657 spin_unlock_irqrestore(&sport->port.lock, flags); 1658 1659 clk_disable(sport->clk_ipg); 1660 clk_disable(sport->clk_per); 1661 } 1662 1663 /* 1664 * If the port was already initialised (eg, by a boot loader), 1665 * try to determine the current setup. 1666 */ 1667 static void __init 1668 imx_console_get_options(struct imx_port *sport, int *baud, 1669 int *parity, int *bits) 1670 { 1671 1672 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1673 /* ok, the port was enabled */ 1674 unsigned int ucr2, ubir, ubmr, uartclk; 1675 unsigned int baud_raw; 1676 unsigned int ucfr_rfdiv; 1677 1678 ucr2 = readl(sport->port.membase + UCR2); 1679 1680 *parity = 'n'; 1681 if (ucr2 & UCR2_PREN) { 1682 if (ucr2 & UCR2_PROE) 1683 *parity = 'o'; 1684 else 1685 *parity = 'e'; 1686 } 1687 1688 if (ucr2 & UCR2_WS) 1689 *bits = 8; 1690 else 1691 *bits = 7; 1692 1693 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1694 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1695 1696 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1697 if (ucfr_rfdiv == 6) 1698 ucfr_rfdiv = 7; 1699 else 1700 ucfr_rfdiv = 6 - ucfr_rfdiv; 1701 1702 uartclk = clk_get_rate(sport->clk_per); 1703 uartclk /= ucfr_rfdiv; 1704 1705 { /* 1706 * The next code provides exact computation of 1707 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1708 * without need of float support or long long division, 1709 * which would be required to prevent 32bit arithmetic overflow 1710 */ 1711 unsigned int mul = ubir + 1; 1712 unsigned int div = 16 * (ubmr + 1); 1713 unsigned int rem = uartclk % div; 1714 1715 baud_raw = (uartclk / div) * mul; 1716 baud_raw += (rem * mul + div / 2) / div; 1717 *baud = (baud_raw + 50) / 100 * 100; 1718 } 1719 1720 if (*baud != baud_raw) 1721 pr_info("Console IMX rounded baud rate from %d to %d\n", 1722 baud_raw, *baud); 1723 } 1724 } 1725 1726 static int __init 1727 imx_console_setup(struct console *co, char *options) 1728 { 1729 struct imx_port *sport; 1730 int baud = 9600; 1731 int bits = 8; 1732 int parity = 'n'; 1733 int flow = 'n'; 1734 int retval; 1735 1736 /* 1737 * Check whether an invalid uart number has been specified, and 1738 * if so, search for the first available port that does have 1739 * console support. 1740 */ 1741 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1742 co->index = 0; 1743 sport = imx_ports[co->index]; 1744 if (sport == NULL) 1745 return -ENODEV; 1746 1747 /* For setting the registers, we only need to enable the ipg clock. */ 1748 retval = clk_prepare_enable(sport->clk_ipg); 1749 if (retval) 1750 goto error_console; 1751 1752 if (options) 1753 uart_parse_options(options, &baud, &parity, &bits, &flow); 1754 else 1755 imx_console_get_options(sport, &baud, &parity, &bits); 1756 1757 imx_setup_ufcr(sport, 0); 1758 1759 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 1760 1761 clk_disable(sport->clk_ipg); 1762 if (retval) { 1763 clk_unprepare(sport->clk_ipg); 1764 goto error_console; 1765 } 1766 1767 retval = clk_prepare(sport->clk_per); 1768 if (retval) 1769 clk_disable_unprepare(sport->clk_ipg); 1770 1771 error_console: 1772 return retval; 1773 } 1774 1775 static struct uart_driver imx_reg; 1776 static struct console imx_console = { 1777 .name = DEV_NAME, 1778 .write = imx_console_write, 1779 .device = uart_console_device, 1780 .setup = imx_console_setup, 1781 .flags = CON_PRINTBUFFER, 1782 .index = -1, 1783 .data = &imx_reg, 1784 }; 1785 1786 #define IMX_CONSOLE &imx_console 1787 #else 1788 #define IMX_CONSOLE NULL 1789 #endif 1790 1791 static struct uart_driver imx_reg = { 1792 .owner = THIS_MODULE, 1793 .driver_name = DRIVER_NAME, 1794 .dev_name = DEV_NAME, 1795 .major = SERIAL_IMX_MAJOR, 1796 .minor = MINOR_START, 1797 .nr = ARRAY_SIZE(imx_ports), 1798 .cons = IMX_CONSOLE, 1799 }; 1800 1801 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1802 { 1803 struct imx_port *sport = platform_get_drvdata(dev); 1804 unsigned int val; 1805 1806 /* enable wakeup from i.MX UART */ 1807 val = readl(sport->port.membase + UCR3); 1808 val |= UCR3_AWAKEN; 1809 writel(val, sport->port.membase + UCR3); 1810 1811 uart_suspend_port(&imx_reg, &sport->port); 1812 1813 return 0; 1814 } 1815 1816 static int serial_imx_resume(struct platform_device *dev) 1817 { 1818 struct imx_port *sport = platform_get_drvdata(dev); 1819 unsigned int val; 1820 1821 /* disable wakeup from i.MX UART */ 1822 val = readl(sport->port.membase + UCR3); 1823 val &= ~UCR3_AWAKEN; 1824 writel(val, sport->port.membase + UCR3); 1825 1826 uart_resume_port(&imx_reg, &sport->port); 1827 1828 return 0; 1829 } 1830 1831 #ifdef CONFIG_OF 1832 /* 1833 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 1834 * could successfully get all information from dt or a negative errno. 1835 */ 1836 static int serial_imx_probe_dt(struct imx_port *sport, 1837 struct platform_device *pdev) 1838 { 1839 struct device_node *np = pdev->dev.of_node; 1840 const struct of_device_id *of_id = 1841 of_match_device(imx_uart_dt_ids, &pdev->dev); 1842 int ret; 1843 1844 if (!np) 1845 /* no device tree device */ 1846 return 1; 1847 1848 ret = of_alias_get_id(np, "serial"); 1849 if (ret < 0) { 1850 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1851 return ret; 1852 } 1853 sport->port.line = ret; 1854 1855 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1856 sport->have_rtscts = 1; 1857 1858 if (of_get_property(np, "fsl,irda-mode", NULL)) 1859 sport->use_irda = 1; 1860 1861 if (of_get_property(np, "fsl,dte-mode", NULL)) 1862 sport->dte_mode = 1; 1863 1864 sport->devdata = of_id->data; 1865 1866 return 0; 1867 } 1868 #else 1869 static inline int serial_imx_probe_dt(struct imx_port *sport, 1870 struct platform_device *pdev) 1871 { 1872 return 1; 1873 } 1874 #endif 1875 1876 static void serial_imx_probe_pdata(struct imx_port *sport, 1877 struct platform_device *pdev) 1878 { 1879 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 1880 1881 sport->port.line = pdev->id; 1882 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 1883 1884 if (!pdata) 1885 return; 1886 1887 if (pdata->flags & IMXUART_HAVE_RTSCTS) 1888 sport->have_rtscts = 1; 1889 1890 if (pdata->flags & IMXUART_IRDA) 1891 sport->use_irda = 1; 1892 } 1893 1894 static int serial_imx_probe(struct platform_device *pdev) 1895 { 1896 struct imx_port *sport; 1897 void __iomem *base; 1898 int ret = 0; 1899 struct resource *res; 1900 1901 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1902 if (!sport) 1903 return -ENOMEM; 1904 1905 ret = serial_imx_probe_dt(sport, pdev); 1906 if (ret > 0) 1907 serial_imx_probe_pdata(sport, pdev); 1908 else if (ret < 0) 1909 return ret; 1910 1911 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1912 base = devm_ioremap_resource(&pdev->dev, res); 1913 if (IS_ERR(base)) 1914 return PTR_ERR(base); 1915 1916 sport->port.dev = &pdev->dev; 1917 sport->port.mapbase = res->start; 1918 sport->port.membase = base; 1919 sport->port.type = PORT_IMX, 1920 sport->port.iotype = UPIO_MEM; 1921 sport->port.irq = platform_get_irq(pdev, 0); 1922 sport->rxirq = platform_get_irq(pdev, 0); 1923 sport->txirq = platform_get_irq(pdev, 1); 1924 sport->rtsirq = platform_get_irq(pdev, 2); 1925 sport->port.fifosize = 32; 1926 sport->port.ops = &imx_pops; 1927 sport->port.flags = UPF_BOOT_AUTOCONF; 1928 init_timer(&sport->timer); 1929 sport->timer.function = imx_timeout; 1930 sport->timer.data = (unsigned long)sport; 1931 1932 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1933 if (IS_ERR(sport->clk_ipg)) { 1934 ret = PTR_ERR(sport->clk_ipg); 1935 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 1936 return ret; 1937 } 1938 1939 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 1940 if (IS_ERR(sport->clk_per)) { 1941 ret = PTR_ERR(sport->clk_per); 1942 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 1943 return ret; 1944 } 1945 1946 sport->port.uartclk = clk_get_rate(sport->clk_per); 1947 1948 imx_ports[sport->port.line] = sport; 1949 1950 platform_set_drvdata(pdev, sport); 1951 1952 return uart_add_one_port(&imx_reg, &sport->port); 1953 } 1954 1955 static int serial_imx_remove(struct platform_device *pdev) 1956 { 1957 struct imx_port *sport = platform_get_drvdata(pdev); 1958 1959 return uart_remove_one_port(&imx_reg, &sport->port); 1960 } 1961 1962 static struct platform_driver serial_imx_driver = { 1963 .probe = serial_imx_probe, 1964 .remove = serial_imx_remove, 1965 1966 .suspend = serial_imx_suspend, 1967 .resume = serial_imx_resume, 1968 .id_table = imx_uart_devtype, 1969 .driver = { 1970 .name = "imx-uart", 1971 .owner = THIS_MODULE, 1972 .of_match_table = imx_uart_dt_ids, 1973 }, 1974 }; 1975 1976 static int __init imx_serial_init(void) 1977 { 1978 int ret; 1979 1980 pr_info("Serial: IMX driver\n"); 1981 1982 ret = uart_register_driver(&imx_reg); 1983 if (ret) 1984 return ret; 1985 1986 ret = platform_driver_register(&serial_imx_driver); 1987 if (ret != 0) 1988 uart_unregister_driver(&imx_reg); 1989 1990 return ret; 1991 } 1992 1993 static void __exit imx_serial_exit(void) 1994 { 1995 platform_driver_unregister(&serial_imx_driver); 1996 uart_unregister_driver(&imx_reg); 1997 } 1998 1999 module_init(imx_serial_init); 2000 module_exit(imx_serial_exit); 2001 2002 MODULE_AUTHOR("Sascha Hauer"); 2003 MODULE_DESCRIPTION("IMX generic serial port driver"); 2004 MODULE_LICENSE("GPL"); 2005 MODULE_ALIAS("platform:imx-uart"); 2006