1 /* 2 * Driver for Motorola IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * Copyright (C) 2009 emlix GmbH 10 * Author: Fabian Godehardt (added IrDA support for iMX) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 * [29-Mar-2005] Mike Lee 27 * Added hardware handshake 28 */ 29 30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31 #define SUPPORT_SYSRQ 32 #endif 33 34 #include <linux/module.h> 35 #include <linux/ioport.h> 36 #include <linux/init.h> 37 #include <linux/console.h> 38 #include <linux/sysrq.h> 39 #include <linux/platform_device.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/serial_core.h> 43 #include <linux/serial.h> 44 #include <linux/clk.h> 45 #include <linux/delay.h> 46 #include <linux/rational.h> 47 #include <linux/slab.h> 48 #include <linux/of.h> 49 #include <linux/of_device.h> 50 #include <linux/io.h> 51 #include <linux/dma-mapping.h> 52 53 #include <asm/irq.h> 54 #include <linux/platform_data/serial-imx.h> 55 #include <linux/platform_data/dma-imx.h> 56 57 /* Register definitions */ 58 #define URXD0 0x0 /* Receiver Register */ 59 #define URTX0 0x40 /* Transmitter Register */ 60 #define UCR1 0x80 /* Control Register 1 */ 61 #define UCR2 0x84 /* Control Register 2 */ 62 #define UCR3 0x88 /* Control Register 3 */ 63 #define UCR4 0x8c /* Control Register 4 */ 64 #define UFCR 0x90 /* FIFO Control Register */ 65 #define USR1 0x94 /* Status Register 1 */ 66 #define USR2 0x98 /* Status Register 2 */ 67 #define UESC 0x9c /* Escape Character Register */ 68 #define UTIM 0xa0 /* Escape Timer Register */ 69 #define UBIR 0xa4 /* BRM Incremental Register */ 70 #define UBMR 0xa8 /* BRM Modulator Register */ 71 #define UBRC 0xac /* Baud Rate Count Register */ 72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 75 76 /* UART Control Register Bit Fields.*/ 77 #define URXD_CHARRDY (1<<15) 78 #define URXD_ERR (1<<14) 79 #define URXD_OVRRUN (1<<13) 80 #define URXD_FRMERR (1<<12) 81 #define URXD_BRK (1<<11) 82 #define URXD_PRERR (1<<10) 83 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 84 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 85 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 86 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 87 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 88 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 89 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 90 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 91 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 92 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 93 #define UCR1_SNDBRK (1<<4) /* Send break */ 94 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 95 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 96 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 97 #define UCR1_DOZE (1<<1) /* Doze */ 98 #define UCR1_UARTEN (1<<0) /* UART enabled */ 99 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 100 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 101 #define UCR2_CTSC (1<<13) /* CTS pin control */ 102 #define UCR2_CTS (1<<12) /* Clear to send */ 103 #define UCR2_ESCEN (1<<11) /* Escape enable */ 104 #define UCR2_PREN (1<<8) /* Parity enable */ 105 #define UCR2_PROE (1<<7) /* Parity odd/even */ 106 #define UCR2_STPB (1<<6) /* Stop */ 107 #define UCR2_WS (1<<5) /* Word size */ 108 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 109 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 110 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 111 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 112 #define UCR2_SRST (1<<0) /* SW reset */ 113 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 114 #define UCR3_PARERREN (1<<12) /* Parity enable */ 115 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 116 #define UCR3_DSR (1<<10) /* Data set ready */ 117 #define UCR3_DCD (1<<9) /* Data carrier detect */ 118 #define UCR3_RI (1<<8) /* Ring indicator */ 119 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 120 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 121 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 122 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 123 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 124 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 125 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 126 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 127 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 128 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 129 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 130 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 131 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 132 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 133 #define UCR4_IRSC (1<<5) /* IR special case */ 134 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 135 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 136 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 137 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 138 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 139 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 140 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 141 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 142 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 143 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 144 #define USR1_RTSS (1<<14) /* RTS pin status */ 145 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 146 #define USR1_RTSD (1<<12) /* RTS delta */ 147 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 148 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 149 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 150 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 151 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 152 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 153 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 154 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 155 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 156 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 157 #define USR2_IDLE (1<<12) /* Idle condition */ 158 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 159 #define USR2_WAKE (1<<7) /* Wake */ 160 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 161 #define USR2_TXDC (1<<3) /* Transmitter complete */ 162 #define USR2_BRCD (1<<2) /* Break condition */ 163 #define USR2_ORE (1<<1) /* Overrun error */ 164 #define USR2_RDR (1<<0) /* Recv data ready */ 165 #define UTS_FRCPERR (1<<13) /* Force parity error */ 166 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 167 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 168 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 169 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 170 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 171 #define UTS_SOFTRST (1<<0) /* Software reset */ 172 173 /* We've been assigned a range on the "Low-density serial ports" major */ 174 #define SERIAL_IMX_MAJOR 207 175 #define MINOR_START 16 176 #define DEV_NAME "ttymxc" 177 178 /* 179 * This determines how often we check the modem status signals 180 * for any change. They generally aren't connected to an IRQ 181 * so we have to poll them. We also check immediately before 182 * filling the TX fifo incase CTS has been dropped. 183 */ 184 #define MCTRL_TIMEOUT (250*HZ/1000) 185 186 #define DRIVER_NAME "IMX-uart" 187 188 #define UART_NR 8 189 190 /* i.mx21 type uart runs on all i.mx except i.mx1 */ 191 enum imx_uart_type { 192 IMX1_UART, 193 IMX21_UART, 194 IMX6Q_UART, 195 }; 196 197 /* device type dependent stuff */ 198 struct imx_uart_data { 199 unsigned uts_reg; 200 enum imx_uart_type devtype; 201 }; 202 203 struct imx_port { 204 struct uart_port port; 205 struct timer_list timer; 206 unsigned int old_status; 207 int txirq, rxirq, rtsirq; 208 unsigned int have_rtscts:1; 209 unsigned int dte_mode:1; 210 unsigned int use_irda:1; 211 unsigned int irda_inv_rx:1; 212 unsigned int irda_inv_tx:1; 213 unsigned short trcv_delay; /* transceiver delay */ 214 struct clk *clk_ipg; 215 struct clk *clk_per; 216 const struct imx_uart_data *devdata; 217 218 /* DMA fields */ 219 unsigned int dma_is_inited:1; 220 unsigned int dma_is_enabled:1; 221 unsigned int dma_is_rxing:1; 222 unsigned int dma_is_txing:1; 223 struct dma_chan *dma_chan_rx, *dma_chan_tx; 224 struct scatterlist rx_sgl, tx_sgl[2]; 225 void *rx_buf; 226 unsigned int rx_bytes, tx_bytes; 227 struct work_struct tsk_dma_rx, tsk_dma_tx; 228 unsigned int dma_tx_nents; 229 wait_queue_head_t dma_wait; 230 }; 231 232 struct imx_port_ucrs { 233 unsigned int ucr1; 234 unsigned int ucr2; 235 unsigned int ucr3; 236 }; 237 238 #ifdef CONFIG_IRDA 239 #define USE_IRDA(sport) ((sport)->use_irda) 240 #else 241 #define USE_IRDA(sport) (0) 242 #endif 243 244 static struct imx_uart_data imx_uart_devdata[] = { 245 [IMX1_UART] = { 246 .uts_reg = IMX1_UTS, 247 .devtype = IMX1_UART, 248 }, 249 [IMX21_UART] = { 250 .uts_reg = IMX21_UTS, 251 .devtype = IMX21_UART, 252 }, 253 [IMX6Q_UART] = { 254 .uts_reg = IMX21_UTS, 255 .devtype = IMX6Q_UART, 256 }, 257 }; 258 259 static struct platform_device_id imx_uart_devtype[] = { 260 { 261 .name = "imx1-uart", 262 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 263 }, { 264 .name = "imx21-uart", 265 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 266 }, { 267 .name = "imx6q-uart", 268 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 269 }, { 270 /* sentinel */ 271 } 272 }; 273 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 274 275 static struct of_device_id imx_uart_dt_ids[] = { 276 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 277 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 278 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 279 { /* sentinel */ } 280 }; 281 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 282 283 static inline unsigned uts_reg(struct imx_port *sport) 284 { 285 return sport->devdata->uts_reg; 286 } 287 288 static inline int is_imx1_uart(struct imx_port *sport) 289 { 290 return sport->devdata->devtype == IMX1_UART; 291 } 292 293 static inline int is_imx21_uart(struct imx_port *sport) 294 { 295 return sport->devdata->devtype == IMX21_UART; 296 } 297 298 static inline int is_imx6q_uart(struct imx_port *sport) 299 { 300 return sport->devdata->devtype == IMX6Q_UART; 301 } 302 /* 303 * Save and restore functions for UCR1, UCR2 and UCR3 registers 304 */ 305 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE) 306 static void imx_port_ucrs_save(struct uart_port *port, 307 struct imx_port_ucrs *ucr) 308 { 309 /* save control registers */ 310 ucr->ucr1 = readl(port->membase + UCR1); 311 ucr->ucr2 = readl(port->membase + UCR2); 312 ucr->ucr3 = readl(port->membase + UCR3); 313 } 314 315 static void imx_port_ucrs_restore(struct uart_port *port, 316 struct imx_port_ucrs *ucr) 317 { 318 /* restore control registers */ 319 writel(ucr->ucr1, port->membase + UCR1); 320 writel(ucr->ucr2, port->membase + UCR2); 321 writel(ucr->ucr3, port->membase + UCR3); 322 } 323 #endif 324 325 /* 326 * Handle any change of modem status signal since we were last called. 327 */ 328 static void imx_mctrl_check(struct imx_port *sport) 329 { 330 unsigned int status, changed; 331 332 status = sport->port.ops->get_mctrl(&sport->port); 333 changed = status ^ sport->old_status; 334 335 if (changed == 0) 336 return; 337 338 sport->old_status = status; 339 340 if (changed & TIOCM_RI) 341 sport->port.icount.rng++; 342 if (changed & TIOCM_DSR) 343 sport->port.icount.dsr++; 344 if (changed & TIOCM_CAR) 345 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 346 if (changed & TIOCM_CTS) 347 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 348 349 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 350 } 351 352 /* 353 * This is our per-port timeout handler, for checking the 354 * modem status signals. 355 */ 356 static void imx_timeout(unsigned long data) 357 { 358 struct imx_port *sport = (struct imx_port *)data; 359 unsigned long flags; 360 361 if (sport->port.state) { 362 spin_lock_irqsave(&sport->port.lock, flags); 363 imx_mctrl_check(sport); 364 spin_unlock_irqrestore(&sport->port.lock, flags); 365 366 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 367 } 368 } 369 370 /* 371 * interrupts disabled on entry 372 */ 373 static void imx_stop_tx(struct uart_port *port) 374 { 375 struct imx_port *sport = (struct imx_port *)port; 376 unsigned long temp; 377 378 if (USE_IRDA(sport)) { 379 /* half duplex - wait for end of transmission */ 380 int n = 256; 381 while ((--n > 0) && 382 !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 383 udelay(5); 384 barrier(); 385 } 386 /* 387 * irda transceiver - wait a bit more to avoid 388 * cutoff, hardware dependent 389 */ 390 udelay(sport->trcv_delay); 391 392 /* 393 * half duplex - reactivate receive mode, 394 * flush receive pipe echo crap 395 */ 396 if (readl(sport->port.membase + USR2) & USR2_TXDC) { 397 temp = readl(sport->port.membase + UCR1); 398 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 399 writel(temp, sport->port.membase + UCR1); 400 401 temp = readl(sport->port.membase + UCR4); 402 temp &= ~(UCR4_TCEN); 403 writel(temp, sport->port.membase + UCR4); 404 405 while (readl(sport->port.membase + URXD0) & 406 URXD_CHARRDY) 407 barrier(); 408 409 temp = readl(sport->port.membase + UCR1); 410 temp |= UCR1_RRDYEN; 411 writel(temp, sport->port.membase + UCR1); 412 413 temp = readl(sport->port.membase + UCR4); 414 temp |= UCR4_DREN; 415 writel(temp, sport->port.membase + UCR4); 416 } 417 return; 418 } 419 420 /* 421 * We are maybe in the SMP context, so if the DMA TX thread is running 422 * on other cpu, we have to wait for it to finish. 423 */ 424 if (sport->dma_is_enabled && sport->dma_is_txing) 425 return; 426 427 temp = readl(sport->port.membase + UCR1); 428 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 429 } 430 431 /* 432 * interrupts disabled on entry 433 */ 434 static void imx_stop_rx(struct uart_port *port) 435 { 436 struct imx_port *sport = (struct imx_port *)port; 437 unsigned long temp; 438 439 /* 440 * We are maybe in the SMP context, so if the DMA TX thread is running 441 * on other cpu, we have to wait for it to finish. 442 */ 443 if (sport->dma_is_enabled && sport->dma_is_rxing) 444 return; 445 446 temp = readl(sport->port.membase + UCR2); 447 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 448 } 449 450 /* 451 * Set the modem control timer to fire immediately. 452 */ 453 static void imx_enable_ms(struct uart_port *port) 454 { 455 struct imx_port *sport = (struct imx_port *)port; 456 457 mod_timer(&sport->timer, jiffies); 458 } 459 460 static inline void imx_transmit_buffer(struct imx_port *sport) 461 { 462 struct circ_buf *xmit = &sport->port.state->xmit; 463 464 while (!uart_circ_empty(xmit) && 465 !(readl(sport->port.membase + uts_reg(sport)) 466 & UTS_TXFULL)) { 467 /* send xmit->buf[xmit->tail] 468 * out the port here */ 469 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 470 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 471 sport->port.icount.tx++; 472 } 473 474 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 475 uart_write_wakeup(&sport->port); 476 477 if (uart_circ_empty(xmit)) 478 imx_stop_tx(&sport->port); 479 } 480 481 static void dma_tx_callback(void *data) 482 { 483 struct imx_port *sport = data; 484 struct scatterlist *sgl = &sport->tx_sgl[0]; 485 struct circ_buf *xmit = &sport->port.state->xmit; 486 unsigned long flags; 487 488 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 489 490 sport->dma_is_txing = 0; 491 492 /* update the stat */ 493 spin_lock_irqsave(&sport->port.lock, flags); 494 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 495 sport->port.icount.tx += sport->tx_bytes; 496 spin_unlock_irqrestore(&sport->port.lock, flags); 497 498 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 499 500 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 501 uart_write_wakeup(&sport->port); 502 503 if (waitqueue_active(&sport->dma_wait)) { 504 wake_up(&sport->dma_wait); 505 dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 506 return; 507 } 508 509 schedule_work(&sport->tsk_dma_tx); 510 } 511 512 static void dma_tx_work(struct work_struct *w) 513 { 514 struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_tx); 515 struct circ_buf *xmit = &sport->port.state->xmit; 516 struct scatterlist *sgl = sport->tx_sgl; 517 struct dma_async_tx_descriptor *desc; 518 struct dma_chan *chan = sport->dma_chan_tx; 519 struct device *dev = sport->port.dev; 520 enum dma_status status; 521 unsigned long flags; 522 int ret; 523 524 status = chan->device->device_tx_status(chan, (dma_cookie_t)0, NULL); 525 if (DMA_IN_PROGRESS == status) 526 return; 527 528 spin_lock_irqsave(&sport->port.lock, flags); 529 sport->tx_bytes = uart_circ_chars_pending(xmit); 530 if (sport->tx_bytes == 0) { 531 spin_unlock_irqrestore(&sport->port.lock, flags); 532 return; 533 } 534 535 if (xmit->tail > xmit->head) { 536 sport->dma_tx_nents = 2; 537 sg_init_table(sgl, 2); 538 sg_set_buf(sgl, xmit->buf + xmit->tail, 539 UART_XMIT_SIZE - xmit->tail); 540 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 541 } else { 542 sport->dma_tx_nents = 1; 543 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 544 } 545 spin_unlock_irqrestore(&sport->port.lock, flags); 546 547 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 548 if (ret == 0) { 549 dev_err(dev, "DMA mapping error for TX.\n"); 550 return; 551 } 552 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 553 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 554 if (!desc) { 555 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 556 return; 557 } 558 desc->callback = dma_tx_callback; 559 desc->callback_param = sport; 560 561 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 562 uart_circ_chars_pending(xmit)); 563 /* fire it */ 564 sport->dma_is_txing = 1; 565 dmaengine_submit(desc); 566 dma_async_issue_pending(chan); 567 return; 568 } 569 570 /* 571 * interrupts disabled on entry 572 */ 573 static void imx_start_tx(struct uart_port *port) 574 { 575 struct imx_port *sport = (struct imx_port *)port; 576 unsigned long temp; 577 578 if (USE_IRDA(sport)) { 579 /* half duplex in IrDA mode; have to disable receive mode */ 580 temp = readl(sport->port.membase + UCR4); 581 temp &= ~(UCR4_DREN); 582 writel(temp, sport->port.membase + UCR4); 583 584 temp = readl(sport->port.membase + UCR1); 585 temp &= ~(UCR1_RRDYEN); 586 writel(temp, sport->port.membase + UCR1); 587 } 588 /* Clear any pending ORE flag before enabling interrupt */ 589 temp = readl(sport->port.membase + USR2); 590 writel(temp | USR2_ORE, sport->port.membase + USR2); 591 592 temp = readl(sport->port.membase + UCR4); 593 temp |= UCR4_OREN; 594 writel(temp, sport->port.membase + UCR4); 595 596 if (!sport->dma_is_enabled) { 597 temp = readl(sport->port.membase + UCR1); 598 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 599 } 600 601 if (USE_IRDA(sport)) { 602 temp = readl(sport->port.membase + UCR1); 603 temp |= UCR1_TRDYEN; 604 writel(temp, sport->port.membase + UCR1); 605 606 temp = readl(sport->port.membase + UCR4); 607 temp |= UCR4_TCEN; 608 writel(temp, sport->port.membase + UCR4); 609 } 610 611 if (sport->dma_is_enabled) { 612 /* 613 * We may in the interrupt context, so arise a work_struct to 614 * do the real job. 615 */ 616 schedule_work(&sport->tsk_dma_tx); 617 return; 618 } 619 620 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) 621 imx_transmit_buffer(sport); 622 } 623 624 static irqreturn_t imx_rtsint(int irq, void *dev_id) 625 { 626 struct imx_port *sport = dev_id; 627 unsigned int val; 628 unsigned long flags; 629 630 spin_lock_irqsave(&sport->port.lock, flags); 631 632 writel(USR1_RTSD, sport->port.membase + USR1); 633 val = readl(sport->port.membase + USR1) & USR1_RTSS; 634 uart_handle_cts_change(&sport->port, !!val); 635 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 636 637 spin_unlock_irqrestore(&sport->port.lock, flags); 638 return IRQ_HANDLED; 639 } 640 641 static irqreturn_t imx_txint(int irq, void *dev_id) 642 { 643 struct imx_port *sport = dev_id; 644 struct circ_buf *xmit = &sport->port.state->xmit; 645 unsigned long flags; 646 647 spin_lock_irqsave(&sport->port.lock, flags); 648 if (sport->port.x_char) { 649 /* Send next char */ 650 writel(sport->port.x_char, sport->port.membase + URTX0); 651 goto out; 652 } 653 654 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 655 imx_stop_tx(&sport->port); 656 goto out; 657 } 658 659 imx_transmit_buffer(sport); 660 661 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 662 uart_write_wakeup(&sport->port); 663 664 out: 665 spin_unlock_irqrestore(&sport->port.lock, flags); 666 return IRQ_HANDLED; 667 } 668 669 static irqreturn_t imx_rxint(int irq, void *dev_id) 670 { 671 struct imx_port *sport = dev_id; 672 unsigned int rx, flg, ignored = 0; 673 struct tty_port *port = &sport->port.state->port; 674 unsigned long flags, temp; 675 676 spin_lock_irqsave(&sport->port.lock, flags); 677 678 while (readl(sport->port.membase + USR2) & USR2_RDR) { 679 flg = TTY_NORMAL; 680 sport->port.icount.rx++; 681 682 rx = readl(sport->port.membase + URXD0); 683 684 temp = readl(sport->port.membase + USR2); 685 if (temp & USR2_BRCD) { 686 writel(USR2_BRCD, sport->port.membase + USR2); 687 if (uart_handle_break(&sport->port)) 688 continue; 689 } 690 691 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 692 continue; 693 694 if (unlikely(rx & URXD_ERR)) { 695 if (rx & URXD_BRK) 696 sport->port.icount.brk++; 697 else if (rx & URXD_PRERR) 698 sport->port.icount.parity++; 699 else if (rx & URXD_FRMERR) 700 sport->port.icount.frame++; 701 if (rx & URXD_OVRRUN) 702 sport->port.icount.overrun++; 703 704 if (rx & sport->port.ignore_status_mask) { 705 if (++ignored > 100) 706 goto out; 707 continue; 708 } 709 710 rx &= sport->port.read_status_mask; 711 712 if (rx & URXD_BRK) 713 flg = TTY_BREAK; 714 else if (rx & URXD_PRERR) 715 flg = TTY_PARITY; 716 else if (rx & URXD_FRMERR) 717 flg = TTY_FRAME; 718 if (rx & URXD_OVRRUN) 719 flg = TTY_OVERRUN; 720 721 #ifdef SUPPORT_SYSRQ 722 sport->port.sysrq = 0; 723 #endif 724 } 725 726 tty_insert_flip_char(port, rx, flg); 727 } 728 729 out: 730 spin_unlock_irqrestore(&sport->port.lock, flags); 731 tty_flip_buffer_push(port); 732 return IRQ_HANDLED; 733 } 734 735 /* 736 * If the RXFIFO is filled with some data, and then we 737 * arise a DMA operation to receive them. 738 */ 739 static void imx_dma_rxint(struct imx_port *sport) 740 { 741 unsigned long temp; 742 743 temp = readl(sport->port.membase + USR2); 744 if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 745 sport->dma_is_rxing = 1; 746 747 /* disable the `Recerver Ready Interrrupt` */ 748 temp = readl(sport->port.membase + UCR1); 749 temp &= ~(UCR1_RRDYEN); 750 writel(temp, sport->port.membase + UCR1); 751 752 /* tell the DMA to receive the data. */ 753 schedule_work(&sport->tsk_dma_rx); 754 } 755 } 756 757 static irqreturn_t imx_int(int irq, void *dev_id) 758 { 759 struct imx_port *sport = dev_id; 760 unsigned int sts; 761 unsigned int sts2; 762 763 sts = readl(sport->port.membase + USR1); 764 765 if (sts & USR1_RRDY) { 766 if (sport->dma_is_enabled) 767 imx_dma_rxint(sport); 768 else 769 imx_rxint(irq, dev_id); 770 } 771 772 if (sts & USR1_TRDY && 773 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 774 imx_txint(irq, dev_id); 775 776 if (sts & USR1_RTSD) 777 imx_rtsint(irq, dev_id); 778 779 if (sts & USR1_AWAKE) 780 writel(USR1_AWAKE, sport->port.membase + USR1); 781 782 sts2 = readl(sport->port.membase + USR2); 783 if (sts2 & USR2_ORE) { 784 dev_err(sport->port.dev, "Rx FIFO overrun\n"); 785 sport->port.icount.overrun++; 786 writel(sts2 | USR2_ORE, sport->port.membase + USR2); 787 } 788 789 return IRQ_HANDLED; 790 } 791 792 /* 793 * Return TIOCSER_TEMT when transmitter is not busy. 794 */ 795 static unsigned int imx_tx_empty(struct uart_port *port) 796 { 797 struct imx_port *sport = (struct imx_port *)port; 798 799 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 800 } 801 802 /* 803 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 804 */ 805 static unsigned int imx_get_mctrl(struct uart_port *port) 806 { 807 struct imx_port *sport = (struct imx_port *)port; 808 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 809 810 if (readl(sport->port.membase + USR1) & USR1_RTSS) 811 tmp |= TIOCM_CTS; 812 813 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 814 tmp |= TIOCM_RTS; 815 816 return tmp; 817 } 818 819 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 820 { 821 struct imx_port *sport = (struct imx_port *)port; 822 unsigned long temp; 823 824 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; 825 826 if (mctrl & TIOCM_RTS) 827 if (!sport->dma_is_enabled) 828 temp |= UCR2_CTS; 829 830 writel(temp, sport->port.membase + UCR2); 831 } 832 833 /* 834 * Interrupts always disabled. 835 */ 836 static void imx_break_ctl(struct uart_port *port, int break_state) 837 { 838 struct imx_port *sport = (struct imx_port *)port; 839 unsigned long flags, temp; 840 841 spin_lock_irqsave(&sport->port.lock, flags); 842 843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 844 845 if (break_state != 0) 846 temp |= UCR1_SNDBRK; 847 848 writel(temp, sport->port.membase + UCR1); 849 850 spin_unlock_irqrestore(&sport->port.lock, flags); 851 } 852 853 #define TXTL 2 /* reset default */ 854 #define RXTL 1 /* reset default */ 855 856 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 857 { 858 unsigned int val; 859 860 /* set receiver / transmitter trigger level */ 861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 862 val |= TXTL << UFCR_TXTL_SHF | RXTL; 863 writel(val, sport->port.membase + UFCR); 864 return 0; 865 } 866 867 #define RX_BUF_SIZE (PAGE_SIZE) 868 static int start_rx_dma(struct imx_port *sport); 869 static void dma_rx_work(struct work_struct *w) 870 { 871 struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_rx); 872 struct tty_port *port = &sport->port.state->port; 873 874 if (sport->rx_bytes) { 875 tty_insert_flip_string(port, sport->rx_buf, sport->rx_bytes); 876 tty_flip_buffer_push(port); 877 sport->rx_bytes = 0; 878 } 879 880 if (sport->dma_is_rxing) 881 start_rx_dma(sport); 882 } 883 884 static void imx_rx_dma_done(struct imx_port *sport) 885 { 886 unsigned long temp; 887 888 /* Enable this interrupt when the RXFIFO is empty. */ 889 temp = readl(sport->port.membase + UCR1); 890 temp |= UCR1_RRDYEN; 891 writel(temp, sport->port.membase + UCR1); 892 893 sport->dma_is_rxing = 0; 894 895 /* Is the shutdown waiting for us? */ 896 if (waitqueue_active(&sport->dma_wait)) 897 wake_up(&sport->dma_wait); 898 } 899 900 /* 901 * There are three kinds of RX DMA interrupts(such as in the MX6Q): 902 * [1] the RX DMA buffer is full. 903 * [2] the Aging timer expires(wait for 8 bytes long) 904 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 905 * 906 * The [2] is trigger when a character was been sitting in the FIFO 907 * meanwhile [3] can wait for 32 bytes long when the RX line is 908 * on IDLE state and RxFIFO is empty. 909 */ 910 static void dma_rx_callback(void *data) 911 { 912 struct imx_port *sport = data; 913 struct dma_chan *chan = sport->dma_chan_rx; 914 struct scatterlist *sgl = &sport->rx_sgl; 915 struct dma_tx_state state; 916 enum dma_status status; 917 unsigned int count; 918 919 /* unmap it first */ 920 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 921 922 status = chan->device->device_tx_status(chan, (dma_cookie_t)0, &state); 923 count = RX_BUF_SIZE - state.residue; 924 dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 925 926 if (count) { 927 sport->rx_bytes = count; 928 schedule_work(&sport->tsk_dma_rx); 929 } else 930 imx_rx_dma_done(sport); 931 } 932 933 static int start_rx_dma(struct imx_port *sport) 934 { 935 struct scatterlist *sgl = &sport->rx_sgl; 936 struct dma_chan *chan = sport->dma_chan_rx; 937 struct device *dev = sport->port.dev; 938 struct dma_async_tx_descriptor *desc; 939 int ret; 940 941 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 942 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 943 if (ret == 0) { 944 dev_err(dev, "DMA mapping error for RX.\n"); 945 return -EINVAL; 946 } 947 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 948 DMA_PREP_INTERRUPT); 949 if (!desc) { 950 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 951 return -EINVAL; 952 } 953 desc->callback = dma_rx_callback; 954 desc->callback_param = sport; 955 956 dev_dbg(dev, "RX: prepare for the DMA.\n"); 957 dmaengine_submit(desc); 958 dma_async_issue_pending(chan); 959 return 0; 960 } 961 962 static void imx_uart_dma_exit(struct imx_port *sport) 963 { 964 if (sport->dma_chan_rx) { 965 dma_release_channel(sport->dma_chan_rx); 966 sport->dma_chan_rx = NULL; 967 968 kfree(sport->rx_buf); 969 sport->rx_buf = NULL; 970 } 971 972 if (sport->dma_chan_tx) { 973 dma_release_channel(sport->dma_chan_tx); 974 sport->dma_chan_tx = NULL; 975 } 976 977 sport->dma_is_inited = 0; 978 } 979 980 static int imx_uart_dma_init(struct imx_port *sport) 981 { 982 struct dma_slave_config slave_config = {}; 983 struct device *dev = sport->port.dev; 984 int ret; 985 986 /* Prepare for RX : */ 987 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 988 if (!sport->dma_chan_rx) { 989 dev_dbg(dev, "cannot get the DMA channel.\n"); 990 ret = -EINVAL; 991 goto err; 992 } 993 994 slave_config.direction = DMA_DEV_TO_MEM; 995 slave_config.src_addr = sport->port.mapbase + URXD0; 996 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 997 slave_config.src_maxburst = RXTL; 998 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 999 if (ret) { 1000 dev_err(dev, "error in RX dma configuration.\n"); 1001 goto err; 1002 } 1003 1004 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1005 if (!sport->rx_buf) { 1006 dev_err(dev, "cannot alloc DMA buffer.\n"); 1007 ret = -ENOMEM; 1008 goto err; 1009 } 1010 sport->rx_bytes = 0; 1011 1012 /* Prepare for TX : */ 1013 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1014 if (!sport->dma_chan_tx) { 1015 dev_err(dev, "cannot get the TX DMA channel!\n"); 1016 ret = -EINVAL; 1017 goto err; 1018 } 1019 1020 slave_config.direction = DMA_MEM_TO_DEV; 1021 slave_config.dst_addr = sport->port.mapbase + URTX0; 1022 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1023 slave_config.dst_maxburst = TXTL; 1024 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1025 if (ret) { 1026 dev_err(dev, "error in TX dma configuration."); 1027 goto err; 1028 } 1029 1030 sport->dma_is_inited = 1; 1031 1032 return 0; 1033 err: 1034 imx_uart_dma_exit(sport); 1035 return ret; 1036 } 1037 1038 static void imx_enable_dma(struct imx_port *sport) 1039 { 1040 unsigned long temp; 1041 struct tty_port *port = &sport->port.state->port; 1042 1043 port->low_latency = 1; 1044 INIT_WORK(&sport->tsk_dma_tx, dma_tx_work); 1045 INIT_WORK(&sport->tsk_dma_rx, dma_rx_work); 1046 init_waitqueue_head(&sport->dma_wait); 1047 1048 /* set UCR1 */ 1049 temp = readl(sport->port.membase + UCR1); 1050 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1051 /* wait for 32 idle frames for IDDMA interrupt */ 1052 UCR1_ICD_REG(3); 1053 writel(temp, sport->port.membase + UCR1); 1054 1055 /* set UCR4 */ 1056 temp = readl(sport->port.membase + UCR4); 1057 temp |= UCR4_IDDMAEN; 1058 writel(temp, sport->port.membase + UCR4); 1059 1060 sport->dma_is_enabled = 1; 1061 } 1062 1063 static void imx_disable_dma(struct imx_port *sport) 1064 { 1065 unsigned long temp; 1066 struct tty_port *port = &sport->port.state->port; 1067 1068 /* clear UCR1 */ 1069 temp = readl(sport->port.membase + UCR1); 1070 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1071 writel(temp, sport->port.membase + UCR1); 1072 1073 /* clear UCR2 */ 1074 temp = readl(sport->port.membase + UCR2); 1075 temp &= ~(UCR2_CTSC | UCR2_CTS); 1076 writel(temp, sport->port.membase + UCR2); 1077 1078 /* clear UCR4 */ 1079 temp = readl(sport->port.membase + UCR4); 1080 temp &= ~UCR4_IDDMAEN; 1081 writel(temp, sport->port.membase + UCR4); 1082 1083 sport->dma_is_enabled = 0; 1084 port->low_latency = 0; 1085 } 1086 1087 /* half the RX buffer size */ 1088 #define CTSTL 16 1089 1090 static int imx_startup(struct uart_port *port) 1091 { 1092 struct imx_port *sport = (struct imx_port *)port; 1093 int retval; 1094 unsigned long flags, temp; 1095 1096 retval = clk_prepare_enable(sport->clk_per); 1097 if (retval) 1098 goto error_out1; 1099 retval = clk_prepare_enable(sport->clk_ipg); 1100 if (retval) { 1101 clk_disable_unprepare(sport->clk_per); 1102 goto error_out1; 1103 } 1104 1105 imx_setup_ufcr(sport, 0); 1106 1107 /* disable the DREN bit (Data Ready interrupt enable) before 1108 * requesting IRQs 1109 */ 1110 temp = readl(sport->port.membase + UCR4); 1111 1112 if (USE_IRDA(sport)) 1113 temp |= UCR4_IRSC; 1114 1115 /* set the trigger level for CTS */ 1116 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1117 temp |= CTSTL << UCR4_CTSTL_SHF; 1118 1119 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1120 1121 if (USE_IRDA(sport)) { 1122 /* reset fifo's and state machines */ 1123 int i = 100; 1124 temp = readl(sport->port.membase + UCR2); 1125 temp &= ~UCR2_SRST; 1126 writel(temp, sport->port.membase + UCR2); 1127 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && 1128 (--i > 0)) { 1129 udelay(1); 1130 } 1131 } 1132 1133 /* 1134 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 1135 * chips only have one interrupt. 1136 */ 1137 if (sport->txirq > 0) { 1138 retval = request_irq(sport->rxirq, imx_rxint, 0, 1139 DRIVER_NAME, sport); 1140 if (retval) 1141 goto error_out1; 1142 1143 retval = request_irq(sport->txirq, imx_txint, 0, 1144 DRIVER_NAME, sport); 1145 if (retval) 1146 goto error_out2; 1147 1148 /* do not use RTS IRQ on IrDA */ 1149 if (!USE_IRDA(sport)) { 1150 retval = request_irq(sport->rtsirq, imx_rtsint, 0, 1151 DRIVER_NAME, sport); 1152 if (retval) 1153 goto error_out3; 1154 } 1155 } else { 1156 retval = request_irq(sport->port.irq, imx_int, 0, 1157 DRIVER_NAME, sport); 1158 if (retval) { 1159 free_irq(sport->port.irq, sport); 1160 goto error_out1; 1161 } 1162 } 1163 1164 spin_lock_irqsave(&sport->port.lock, flags); 1165 /* 1166 * Finally, clear and enable interrupts 1167 */ 1168 writel(USR1_RTSD, sport->port.membase + USR1); 1169 1170 temp = readl(sport->port.membase + UCR1); 1171 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1172 1173 if (USE_IRDA(sport)) { 1174 temp |= UCR1_IREN; 1175 temp &= ~(UCR1_RTSDEN); 1176 } 1177 1178 writel(temp, sport->port.membase + UCR1); 1179 1180 temp = readl(sport->port.membase + UCR2); 1181 temp |= (UCR2_RXEN | UCR2_TXEN); 1182 if (!sport->have_rtscts) 1183 temp |= UCR2_IRTS; 1184 writel(temp, sport->port.membase + UCR2); 1185 1186 if (USE_IRDA(sport)) { 1187 /* clear RX-FIFO */ 1188 int i = 64; 1189 while ((--i > 0) && 1190 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { 1191 barrier(); 1192 } 1193 } 1194 1195 if (!is_imx1_uart(sport)) { 1196 temp = readl(sport->port.membase + UCR3); 1197 temp |= IMX21_UCR3_RXDMUXSEL; 1198 writel(temp, sport->port.membase + UCR3); 1199 } 1200 1201 if (USE_IRDA(sport)) { 1202 temp = readl(sport->port.membase + UCR4); 1203 if (sport->irda_inv_rx) 1204 temp |= UCR4_INVR; 1205 else 1206 temp &= ~(UCR4_INVR); 1207 writel(temp | UCR4_DREN, sport->port.membase + UCR4); 1208 1209 temp = readl(sport->port.membase + UCR3); 1210 if (sport->irda_inv_tx) 1211 temp |= UCR3_INVT; 1212 else 1213 temp &= ~(UCR3_INVT); 1214 writel(temp, sport->port.membase + UCR3); 1215 } 1216 1217 /* 1218 * Enable modem status interrupts 1219 */ 1220 imx_enable_ms(&sport->port); 1221 spin_unlock_irqrestore(&sport->port.lock, flags); 1222 1223 if (USE_IRDA(sport)) { 1224 struct imxuart_platform_data *pdata; 1225 pdata = dev_get_platdata(sport->port.dev); 1226 sport->irda_inv_rx = pdata->irda_inv_rx; 1227 sport->irda_inv_tx = pdata->irda_inv_tx; 1228 sport->trcv_delay = pdata->transceiver_delay; 1229 if (pdata->irda_enable) 1230 pdata->irda_enable(1); 1231 } 1232 1233 return 0; 1234 1235 error_out3: 1236 if (sport->txirq) 1237 free_irq(sport->txirq, sport); 1238 error_out2: 1239 if (sport->rxirq) 1240 free_irq(sport->rxirq, sport); 1241 error_out1: 1242 return retval; 1243 } 1244 1245 static void imx_shutdown(struct uart_port *port) 1246 { 1247 struct imx_port *sport = (struct imx_port *)port; 1248 unsigned long temp; 1249 unsigned long flags; 1250 1251 if (sport->dma_is_enabled) { 1252 /* We have to wait for the DMA to finish. */ 1253 wait_event(sport->dma_wait, 1254 !sport->dma_is_rxing && !sport->dma_is_txing); 1255 imx_stop_rx(port); 1256 imx_disable_dma(sport); 1257 imx_uart_dma_exit(sport); 1258 } 1259 1260 spin_lock_irqsave(&sport->port.lock, flags); 1261 temp = readl(sport->port.membase + UCR2); 1262 temp &= ~(UCR2_TXEN); 1263 writel(temp, sport->port.membase + UCR2); 1264 spin_unlock_irqrestore(&sport->port.lock, flags); 1265 1266 if (USE_IRDA(sport)) { 1267 struct imxuart_platform_data *pdata; 1268 pdata = dev_get_platdata(sport->port.dev); 1269 if (pdata->irda_enable) 1270 pdata->irda_enable(0); 1271 } 1272 1273 /* 1274 * Stop our timer. 1275 */ 1276 del_timer_sync(&sport->timer); 1277 1278 /* 1279 * Free the interrupts 1280 */ 1281 if (sport->txirq > 0) { 1282 if (!USE_IRDA(sport)) 1283 free_irq(sport->rtsirq, sport); 1284 free_irq(sport->txirq, sport); 1285 free_irq(sport->rxirq, sport); 1286 } else 1287 free_irq(sport->port.irq, sport); 1288 1289 /* 1290 * Disable all interrupts, port and break condition. 1291 */ 1292 1293 spin_lock_irqsave(&sport->port.lock, flags); 1294 temp = readl(sport->port.membase + UCR1); 1295 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1296 if (USE_IRDA(sport)) 1297 temp &= ~(UCR1_IREN); 1298 1299 writel(temp, sport->port.membase + UCR1); 1300 spin_unlock_irqrestore(&sport->port.lock, flags); 1301 1302 clk_disable_unprepare(sport->clk_per); 1303 clk_disable_unprepare(sport->clk_ipg); 1304 } 1305 1306 static void 1307 imx_set_termios(struct uart_port *port, struct ktermios *termios, 1308 struct ktermios *old) 1309 { 1310 struct imx_port *sport = (struct imx_port *)port; 1311 unsigned long flags; 1312 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1313 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1314 unsigned int div, ufcr; 1315 unsigned long num, denom; 1316 uint64_t tdiv64; 1317 1318 /* 1319 * If we don't support modem control lines, don't allow 1320 * these to be set. 1321 */ 1322 if (0) { 1323 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 1324 termios->c_cflag |= CLOCAL; 1325 } 1326 1327 /* 1328 * We only support CS7 and CS8. 1329 */ 1330 while ((termios->c_cflag & CSIZE) != CS7 && 1331 (termios->c_cflag & CSIZE) != CS8) { 1332 termios->c_cflag &= ~CSIZE; 1333 termios->c_cflag |= old_csize; 1334 old_csize = CS8; 1335 } 1336 1337 if ((termios->c_cflag & CSIZE) == CS8) 1338 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1339 else 1340 ucr2 = UCR2_SRST | UCR2_IRTS; 1341 1342 if (termios->c_cflag & CRTSCTS) { 1343 if (sport->have_rtscts) { 1344 ucr2 &= ~UCR2_IRTS; 1345 ucr2 |= UCR2_CTSC; 1346 1347 /* Can we enable the DMA support? */ 1348 if (is_imx6q_uart(sport) && !uart_console(port) 1349 && !sport->dma_is_inited) 1350 imx_uart_dma_init(sport); 1351 } else { 1352 termios->c_cflag &= ~CRTSCTS; 1353 } 1354 } 1355 1356 if (termios->c_cflag & CSTOPB) 1357 ucr2 |= UCR2_STPB; 1358 if (termios->c_cflag & PARENB) { 1359 ucr2 |= UCR2_PREN; 1360 if (termios->c_cflag & PARODD) 1361 ucr2 |= UCR2_PROE; 1362 } 1363 1364 del_timer_sync(&sport->timer); 1365 1366 /* 1367 * Ask the core to calculate the divisor for us. 1368 */ 1369 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1370 quot = uart_get_divisor(port, baud); 1371 1372 spin_lock_irqsave(&sport->port.lock, flags); 1373 1374 sport->port.read_status_mask = 0; 1375 if (termios->c_iflag & INPCK) 1376 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1377 if (termios->c_iflag & (BRKINT | PARMRK)) 1378 sport->port.read_status_mask |= URXD_BRK; 1379 1380 /* 1381 * Characters to ignore 1382 */ 1383 sport->port.ignore_status_mask = 0; 1384 if (termios->c_iflag & IGNPAR) 1385 sport->port.ignore_status_mask |= URXD_PRERR; 1386 if (termios->c_iflag & IGNBRK) { 1387 sport->port.ignore_status_mask |= URXD_BRK; 1388 /* 1389 * If we're ignoring parity and break indicators, 1390 * ignore overruns too (for real raw support). 1391 */ 1392 if (termios->c_iflag & IGNPAR) 1393 sport->port.ignore_status_mask |= URXD_OVRRUN; 1394 } 1395 1396 /* 1397 * Update the per-port timeout. 1398 */ 1399 uart_update_timeout(port, termios->c_cflag, baud); 1400 1401 /* 1402 * disable interrupts and drain transmitter 1403 */ 1404 old_ucr1 = readl(sport->port.membase + UCR1); 1405 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1406 sport->port.membase + UCR1); 1407 1408 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1409 barrier(); 1410 1411 /* then, disable everything */ 1412 old_txrxen = readl(sport->port.membase + UCR2); 1413 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1414 sport->port.membase + UCR2); 1415 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1416 1417 if (USE_IRDA(sport)) { 1418 /* 1419 * use maximum available submodule frequency to 1420 * avoid missing short pulses due to low sampling rate 1421 */ 1422 div = 1; 1423 } else { 1424 /* custom-baudrate handling */ 1425 div = sport->port.uartclk / (baud * 16); 1426 if (baud == 38400 && quot != div) 1427 baud = sport->port.uartclk / (quot * 16); 1428 1429 div = sport->port.uartclk / (baud * 16); 1430 if (div > 7) 1431 div = 7; 1432 if (!div) 1433 div = 1; 1434 } 1435 1436 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1437 1 << 16, 1 << 16, &num, &denom); 1438 1439 tdiv64 = sport->port.uartclk; 1440 tdiv64 *= num; 1441 do_div(tdiv64, denom * 16 * div); 1442 tty_termios_encode_baud_rate(termios, 1443 (speed_t)tdiv64, (speed_t)tdiv64); 1444 1445 num -= 1; 1446 denom -= 1; 1447 1448 ufcr = readl(sport->port.membase + UFCR); 1449 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1450 if (sport->dte_mode) 1451 ufcr |= UFCR_DCEDTE; 1452 writel(ufcr, sport->port.membase + UFCR); 1453 1454 writel(num, sport->port.membase + UBIR); 1455 writel(denom, sport->port.membase + UBMR); 1456 1457 if (!is_imx1_uart(sport)) 1458 writel(sport->port.uartclk / div / 1000, 1459 sport->port.membase + IMX21_ONEMS); 1460 1461 writel(old_ucr1, sport->port.membase + UCR1); 1462 1463 /* set the parity, stop bits and data size */ 1464 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1465 1466 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1467 imx_enable_ms(&sport->port); 1468 1469 if (sport->dma_is_inited && !sport->dma_is_enabled) 1470 imx_enable_dma(sport); 1471 spin_unlock_irqrestore(&sport->port.lock, flags); 1472 } 1473 1474 static const char *imx_type(struct uart_port *port) 1475 { 1476 struct imx_port *sport = (struct imx_port *)port; 1477 1478 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1479 } 1480 1481 /* 1482 * Release the memory region(s) being used by 'port'. 1483 */ 1484 static void imx_release_port(struct uart_port *port) 1485 { 1486 struct platform_device *pdev = to_platform_device(port->dev); 1487 struct resource *mmres; 1488 1489 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1490 release_mem_region(mmres->start, resource_size(mmres)); 1491 } 1492 1493 /* 1494 * Request the memory region(s) being used by 'port'. 1495 */ 1496 static int imx_request_port(struct uart_port *port) 1497 { 1498 struct platform_device *pdev = to_platform_device(port->dev); 1499 struct resource *mmres; 1500 void *ret; 1501 1502 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1503 if (!mmres) 1504 return -ENODEV; 1505 1506 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart"); 1507 1508 return ret ? 0 : -EBUSY; 1509 } 1510 1511 /* 1512 * Configure/autoconfigure the port. 1513 */ 1514 static void imx_config_port(struct uart_port *port, int flags) 1515 { 1516 struct imx_port *sport = (struct imx_port *)port; 1517 1518 if (flags & UART_CONFIG_TYPE && 1519 imx_request_port(&sport->port) == 0) 1520 sport->port.type = PORT_IMX; 1521 } 1522 1523 /* 1524 * Verify the new serial_struct (for TIOCSSERIAL). 1525 * The only change we allow are to the flags and type, and 1526 * even then only between PORT_IMX and PORT_UNKNOWN 1527 */ 1528 static int 1529 imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1530 { 1531 struct imx_port *sport = (struct imx_port *)port; 1532 int ret = 0; 1533 1534 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1535 ret = -EINVAL; 1536 if (sport->port.irq != ser->irq) 1537 ret = -EINVAL; 1538 if (ser->io_type != UPIO_MEM) 1539 ret = -EINVAL; 1540 if (sport->port.uartclk / 16 != ser->baud_base) 1541 ret = -EINVAL; 1542 if ((void *)sport->port.mapbase != ser->iomem_base) 1543 ret = -EINVAL; 1544 if (sport->port.iobase != ser->port) 1545 ret = -EINVAL; 1546 if (ser->hub6 != 0) 1547 ret = -EINVAL; 1548 return ret; 1549 } 1550 1551 #if defined(CONFIG_CONSOLE_POLL) 1552 static int imx_poll_get_char(struct uart_port *port) 1553 { 1554 struct imx_port_ucrs old_ucr; 1555 unsigned int status; 1556 unsigned char c; 1557 1558 /* save control registers */ 1559 imx_port_ucrs_save(port, &old_ucr); 1560 1561 /* disable interrupts */ 1562 writel(UCR1_UARTEN, port->membase + UCR1); 1563 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1564 port->membase + UCR2); 1565 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1566 port->membase + UCR3); 1567 1568 /* poll */ 1569 do { 1570 status = readl(port->membase + USR2); 1571 } while (~status & USR2_RDR); 1572 1573 /* read */ 1574 c = readl(port->membase + URXD0); 1575 1576 /* restore control registers */ 1577 imx_port_ucrs_restore(port, &old_ucr); 1578 1579 return c; 1580 } 1581 1582 static void imx_poll_put_char(struct uart_port *port, unsigned char c) 1583 { 1584 struct imx_port_ucrs old_ucr; 1585 unsigned int status; 1586 1587 /* save control registers */ 1588 imx_port_ucrs_save(port, &old_ucr); 1589 1590 /* disable interrupts */ 1591 writel(UCR1_UARTEN, port->membase + UCR1); 1592 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 1593 port->membase + UCR2); 1594 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 1595 port->membase + UCR3); 1596 1597 /* drain */ 1598 do { 1599 status = readl(port->membase + USR1); 1600 } while (~status & USR1_TRDY); 1601 1602 /* write */ 1603 writel(c, port->membase + URTX0); 1604 1605 /* flush */ 1606 do { 1607 status = readl(port->membase + USR2); 1608 } while (~status & USR2_TXDC); 1609 1610 /* restore control registers */ 1611 imx_port_ucrs_restore(port, &old_ucr); 1612 } 1613 #endif 1614 1615 static struct uart_ops imx_pops = { 1616 .tx_empty = imx_tx_empty, 1617 .set_mctrl = imx_set_mctrl, 1618 .get_mctrl = imx_get_mctrl, 1619 .stop_tx = imx_stop_tx, 1620 .start_tx = imx_start_tx, 1621 .stop_rx = imx_stop_rx, 1622 .enable_ms = imx_enable_ms, 1623 .break_ctl = imx_break_ctl, 1624 .startup = imx_startup, 1625 .shutdown = imx_shutdown, 1626 .set_termios = imx_set_termios, 1627 .type = imx_type, 1628 .release_port = imx_release_port, 1629 .request_port = imx_request_port, 1630 .config_port = imx_config_port, 1631 .verify_port = imx_verify_port, 1632 #if defined(CONFIG_CONSOLE_POLL) 1633 .poll_get_char = imx_poll_get_char, 1634 .poll_put_char = imx_poll_put_char, 1635 #endif 1636 }; 1637 1638 static struct imx_port *imx_ports[UART_NR]; 1639 1640 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1641 static void imx_console_putchar(struct uart_port *port, int ch) 1642 { 1643 struct imx_port *sport = (struct imx_port *)port; 1644 1645 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1646 barrier(); 1647 1648 writel(ch, sport->port.membase + URTX0); 1649 } 1650 1651 /* 1652 * Interrupts are disabled on entering 1653 */ 1654 static void 1655 imx_console_write(struct console *co, const char *s, unsigned int count) 1656 { 1657 struct imx_port *sport = imx_ports[co->index]; 1658 struct imx_port_ucrs old_ucr; 1659 unsigned int ucr1; 1660 unsigned long flags = 0; 1661 int locked = 1; 1662 int retval; 1663 1664 retval = clk_enable(sport->clk_per); 1665 if (retval) 1666 return; 1667 retval = clk_enable(sport->clk_ipg); 1668 if (retval) { 1669 clk_disable(sport->clk_per); 1670 return; 1671 } 1672 1673 if (sport->port.sysrq) 1674 locked = 0; 1675 else if (oops_in_progress) 1676 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1677 else 1678 spin_lock_irqsave(&sport->port.lock, flags); 1679 1680 /* 1681 * First, save UCR1/2/3 and then disable interrupts 1682 */ 1683 imx_port_ucrs_save(&sport->port, &old_ucr); 1684 ucr1 = old_ucr.ucr1; 1685 1686 if (is_imx1_uart(sport)) 1687 ucr1 |= IMX1_UCR1_UARTCLKEN; 1688 ucr1 |= UCR1_UARTEN; 1689 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1690 1691 writel(ucr1, sport->port.membase + UCR1); 1692 1693 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1694 1695 uart_console_write(&sport->port, s, count, imx_console_putchar); 1696 1697 /* 1698 * Finally, wait for transmitter to become empty 1699 * and restore UCR1/2/3 1700 */ 1701 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1702 1703 imx_port_ucrs_restore(&sport->port, &old_ucr); 1704 1705 if (locked) 1706 spin_unlock_irqrestore(&sport->port.lock, flags); 1707 1708 clk_disable(sport->clk_ipg); 1709 clk_disable(sport->clk_per); 1710 } 1711 1712 /* 1713 * If the port was already initialised (eg, by a boot loader), 1714 * try to determine the current setup. 1715 */ 1716 static void __init 1717 imx_console_get_options(struct imx_port *sport, int *baud, 1718 int *parity, int *bits) 1719 { 1720 1721 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1722 /* ok, the port was enabled */ 1723 unsigned int ucr2, ubir, ubmr, uartclk; 1724 unsigned int baud_raw; 1725 unsigned int ucfr_rfdiv; 1726 1727 ucr2 = readl(sport->port.membase + UCR2); 1728 1729 *parity = 'n'; 1730 if (ucr2 & UCR2_PREN) { 1731 if (ucr2 & UCR2_PROE) 1732 *parity = 'o'; 1733 else 1734 *parity = 'e'; 1735 } 1736 1737 if (ucr2 & UCR2_WS) 1738 *bits = 8; 1739 else 1740 *bits = 7; 1741 1742 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1743 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1744 1745 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1746 if (ucfr_rfdiv == 6) 1747 ucfr_rfdiv = 7; 1748 else 1749 ucfr_rfdiv = 6 - ucfr_rfdiv; 1750 1751 uartclk = clk_get_rate(sport->clk_per); 1752 uartclk /= ucfr_rfdiv; 1753 1754 { /* 1755 * The next code provides exact computation of 1756 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1757 * without need of float support or long long division, 1758 * which would be required to prevent 32bit arithmetic overflow 1759 */ 1760 unsigned int mul = ubir + 1; 1761 unsigned int div = 16 * (ubmr + 1); 1762 unsigned int rem = uartclk % div; 1763 1764 baud_raw = (uartclk / div) * mul; 1765 baud_raw += (rem * mul + div / 2) / div; 1766 *baud = (baud_raw + 50) / 100 * 100; 1767 } 1768 1769 if (*baud != baud_raw) 1770 pr_info("Console IMX rounded baud rate from %d to %d\n", 1771 baud_raw, *baud); 1772 } 1773 } 1774 1775 static int __init 1776 imx_console_setup(struct console *co, char *options) 1777 { 1778 struct imx_port *sport; 1779 int baud = 9600; 1780 int bits = 8; 1781 int parity = 'n'; 1782 int flow = 'n'; 1783 int retval; 1784 1785 /* 1786 * Check whether an invalid uart number has been specified, and 1787 * if so, search for the first available port that does have 1788 * console support. 1789 */ 1790 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1791 co->index = 0; 1792 sport = imx_ports[co->index]; 1793 if (sport == NULL) 1794 return -ENODEV; 1795 1796 /* For setting the registers, we only need to enable the ipg clock. */ 1797 retval = clk_prepare_enable(sport->clk_ipg); 1798 if (retval) 1799 goto error_console; 1800 1801 if (options) 1802 uart_parse_options(options, &baud, &parity, &bits, &flow); 1803 else 1804 imx_console_get_options(sport, &baud, &parity, &bits); 1805 1806 imx_setup_ufcr(sport, 0); 1807 1808 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 1809 1810 clk_disable(sport->clk_ipg); 1811 if (retval) { 1812 clk_unprepare(sport->clk_ipg); 1813 goto error_console; 1814 } 1815 1816 retval = clk_prepare(sport->clk_per); 1817 if (retval) 1818 clk_disable_unprepare(sport->clk_ipg); 1819 1820 error_console: 1821 return retval; 1822 } 1823 1824 static struct uart_driver imx_reg; 1825 static struct console imx_console = { 1826 .name = DEV_NAME, 1827 .write = imx_console_write, 1828 .device = uart_console_device, 1829 .setup = imx_console_setup, 1830 .flags = CON_PRINTBUFFER, 1831 .index = -1, 1832 .data = &imx_reg, 1833 }; 1834 1835 #define IMX_CONSOLE &imx_console 1836 #else 1837 #define IMX_CONSOLE NULL 1838 #endif 1839 1840 static struct uart_driver imx_reg = { 1841 .owner = THIS_MODULE, 1842 .driver_name = DRIVER_NAME, 1843 .dev_name = DEV_NAME, 1844 .major = SERIAL_IMX_MAJOR, 1845 .minor = MINOR_START, 1846 .nr = ARRAY_SIZE(imx_ports), 1847 .cons = IMX_CONSOLE, 1848 }; 1849 1850 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1851 { 1852 struct imx_port *sport = platform_get_drvdata(dev); 1853 unsigned int val; 1854 1855 /* enable wakeup from i.MX UART */ 1856 val = readl(sport->port.membase + UCR3); 1857 val |= UCR3_AWAKEN; 1858 writel(val, sport->port.membase + UCR3); 1859 1860 uart_suspend_port(&imx_reg, &sport->port); 1861 1862 return 0; 1863 } 1864 1865 static int serial_imx_resume(struct platform_device *dev) 1866 { 1867 struct imx_port *sport = platform_get_drvdata(dev); 1868 unsigned int val; 1869 1870 /* disable wakeup from i.MX UART */ 1871 val = readl(sport->port.membase + UCR3); 1872 val &= ~UCR3_AWAKEN; 1873 writel(val, sport->port.membase + UCR3); 1874 1875 uart_resume_port(&imx_reg, &sport->port); 1876 1877 return 0; 1878 } 1879 1880 #ifdef CONFIG_OF 1881 /* 1882 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 1883 * could successfully get all information from dt or a negative errno. 1884 */ 1885 static int serial_imx_probe_dt(struct imx_port *sport, 1886 struct platform_device *pdev) 1887 { 1888 struct device_node *np = pdev->dev.of_node; 1889 const struct of_device_id *of_id = 1890 of_match_device(imx_uart_dt_ids, &pdev->dev); 1891 int ret; 1892 1893 if (!np) 1894 /* no device tree device */ 1895 return 1; 1896 1897 ret = of_alias_get_id(np, "serial"); 1898 if (ret < 0) { 1899 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1900 return ret; 1901 } 1902 sport->port.line = ret; 1903 1904 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1905 sport->have_rtscts = 1; 1906 1907 if (of_get_property(np, "fsl,irda-mode", NULL)) 1908 sport->use_irda = 1; 1909 1910 if (of_get_property(np, "fsl,dte-mode", NULL)) 1911 sport->dte_mode = 1; 1912 1913 sport->devdata = of_id->data; 1914 1915 if (of_device_is_stdout_path(np)) 1916 add_preferred_console(imx_reg.cons->name, sport->port.line, 0); 1917 1918 return 0; 1919 } 1920 #else 1921 static inline int serial_imx_probe_dt(struct imx_port *sport, 1922 struct platform_device *pdev) 1923 { 1924 return 1; 1925 } 1926 #endif 1927 1928 static void serial_imx_probe_pdata(struct imx_port *sport, 1929 struct platform_device *pdev) 1930 { 1931 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 1932 1933 sport->port.line = pdev->id; 1934 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 1935 1936 if (!pdata) 1937 return; 1938 1939 if (pdata->flags & IMXUART_HAVE_RTSCTS) 1940 sport->have_rtscts = 1; 1941 1942 if (pdata->flags & IMXUART_IRDA) 1943 sport->use_irda = 1; 1944 } 1945 1946 static int serial_imx_probe(struct platform_device *pdev) 1947 { 1948 struct imx_port *sport; 1949 struct imxuart_platform_data *pdata; 1950 void __iomem *base; 1951 int ret = 0; 1952 struct resource *res; 1953 1954 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1955 if (!sport) 1956 return -ENOMEM; 1957 1958 ret = serial_imx_probe_dt(sport, pdev); 1959 if (ret > 0) 1960 serial_imx_probe_pdata(sport, pdev); 1961 else if (ret < 0) 1962 return ret; 1963 1964 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1965 if (!res) 1966 return -ENODEV; 1967 1968 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE); 1969 if (!base) 1970 return -ENOMEM; 1971 1972 sport->port.dev = &pdev->dev; 1973 sport->port.mapbase = res->start; 1974 sport->port.membase = base; 1975 sport->port.type = PORT_IMX, 1976 sport->port.iotype = UPIO_MEM; 1977 sport->port.irq = platform_get_irq(pdev, 0); 1978 sport->rxirq = platform_get_irq(pdev, 0); 1979 sport->txirq = platform_get_irq(pdev, 1); 1980 sport->rtsirq = platform_get_irq(pdev, 2); 1981 sport->port.fifosize = 32; 1982 sport->port.ops = &imx_pops; 1983 sport->port.flags = UPF_BOOT_AUTOCONF; 1984 init_timer(&sport->timer); 1985 sport->timer.function = imx_timeout; 1986 sport->timer.data = (unsigned long)sport; 1987 1988 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1989 if (IS_ERR(sport->clk_ipg)) { 1990 ret = PTR_ERR(sport->clk_ipg); 1991 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 1992 return ret; 1993 } 1994 1995 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 1996 if (IS_ERR(sport->clk_per)) { 1997 ret = PTR_ERR(sport->clk_per); 1998 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 1999 return ret; 2000 } 2001 2002 sport->port.uartclk = clk_get_rate(sport->clk_per); 2003 2004 imx_ports[sport->port.line] = sport; 2005 2006 pdata = dev_get_platdata(&pdev->dev); 2007 if (pdata && pdata->init) { 2008 ret = pdata->init(pdev); 2009 if (ret) 2010 return ret; 2011 } 2012 2013 ret = uart_add_one_port(&imx_reg, &sport->port); 2014 if (ret) 2015 goto deinit; 2016 platform_set_drvdata(pdev, sport); 2017 2018 return 0; 2019 deinit: 2020 if (pdata && pdata->exit) 2021 pdata->exit(pdev); 2022 return ret; 2023 } 2024 2025 static int serial_imx_remove(struct platform_device *pdev) 2026 { 2027 struct imxuart_platform_data *pdata; 2028 struct imx_port *sport = platform_get_drvdata(pdev); 2029 2030 pdata = dev_get_platdata(&pdev->dev); 2031 2032 uart_remove_one_port(&imx_reg, &sport->port); 2033 2034 if (pdata && pdata->exit) 2035 pdata->exit(pdev); 2036 2037 return 0; 2038 } 2039 2040 static struct platform_driver serial_imx_driver = { 2041 .probe = serial_imx_probe, 2042 .remove = serial_imx_remove, 2043 2044 .suspend = serial_imx_suspend, 2045 .resume = serial_imx_resume, 2046 .id_table = imx_uart_devtype, 2047 .driver = { 2048 .name = "imx-uart", 2049 .owner = THIS_MODULE, 2050 .of_match_table = imx_uart_dt_ids, 2051 }, 2052 }; 2053 2054 static int __init imx_serial_init(void) 2055 { 2056 int ret; 2057 2058 pr_info("Serial: IMX driver\n"); 2059 2060 ret = uart_register_driver(&imx_reg); 2061 if (ret) 2062 return ret; 2063 2064 ret = platform_driver_register(&serial_imx_driver); 2065 if (ret != 0) 2066 uart_unregister_driver(&imx_reg); 2067 2068 return ret; 2069 } 2070 2071 static void __exit imx_serial_exit(void) 2072 { 2073 platform_driver_unregister(&serial_imx_driver); 2074 uart_unregister_driver(&imx_reg); 2075 } 2076 2077 module_init(imx_serial_init); 2078 module_exit(imx_serial_exit); 2079 2080 MODULE_AUTHOR("Sascha Hauer"); 2081 MODULE_DESCRIPTION("IMX generic serial port driver"); 2082 MODULE_LICENSE("GPL"); 2083 MODULE_ALIAS("platform:imx-uart"); 2084