xref: /openbmc/linux/drivers/tty/serial/imx.c (revision b5f1844c)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Driver for Motorola/Freescale IMX serial ports
4  *
5  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6  *
7  * Author: Sascha Hauer <sascha@saschahauer.de>
8  * Copyright (C) 2004 Pengutronix
9  */
10 
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/io.h>
29 #include <linux/iopoll.h>
30 #include <linux/dma-mapping.h>
31 
32 #include <asm/irq.h>
33 #include <linux/dma/imx-dma.h>
34 
35 #include "serial_mctrl_gpio.h"
36 
37 /* Register definitions */
38 #define URXD0 0x0  /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1  0x80 /* Control Register 1 */
41 #define UCR2  0x84 /* Control Register 2 */
42 #define UCR3  0x88 /* Control Register 3 */
43 #define UCR4  0x8c /* Control Register 4 */
44 #define UFCR  0x90 /* FIFO Control Register */
45 #define USR1  0x94 /* Status Register 1 */
46 #define USR2  0x98 /* Status Register 2 */
47 #define UESC  0x9c /* Escape Character Register */
48 #define UTIM  0xa0 /* Escape Timer Register */
49 #define UBIR  0xa4 /* BRM Incremental Register */
50 #define UBMR  0xa8 /* BRM Modulator Register */
51 #define UBRC  0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55 
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY	(1<<15)
59 #define URXD_ERR	(1<<14)
60 #define URXD_OVRRUN	(1<<13)
61 #define URXD_FRMERR	(1<<12)
62 #define URXD_BRK	(1<<11)
63 #define URXD_PRERR	(1<<10)
64 #define URXD_RX_DATA	(0xFF<<0)
65 #define UCR1_ADEN	(1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR	(1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN	(1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN	(1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN	(1<<9)	/* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN	(1<<8)	/* Recv ready DMA enable */
72 #define UCR1_IREN	(1<<7)	/* Infrared interface enable */
73 #define UCR1_TXMPTYEN	(1<<6)	/* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN	(1<<5)	/* RTS delta interrupt enable */
75 #define UCR1_SNDBRK	(1<<4)	/* Send break */
76 #define UCR1_TXDMAEN	(1<<3)	/* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
79 #define UCR1_DOZE	(1<<1)	/* Doze */
80 #define UCR1_UARTEN	(1<<0)	/* UART enabled */
81 #define UCR2_ESCI	(1<<15)	/* Escape seq interrupt enable */
82 #define UCR2_IRTS	(1<<14)	/* Ignore RTS pin */
83 #define UCR2_CTSC	(1<<13)	/* CTS pin control */
84 #define UCR2_CTS	(1<<12)	/* Clear to send */
85 #define UCR2_ESCEN	(1<<11)	/* Escape enable */
86 #define UCR2_PREN	(1<<8)	/* Parity enable */
87 #define UCR2_PROE	(1<<7)	/* Parity odd/even */
88 #define UCR2_STPB	(1<<6)	/* Stop */
89 #define UCR2_WS		(1<<5)	/* Word size */
90 #define UCR2_RTSEN	(1<<4)	/* Request to send interrupt enable */
91 #define UCR2_ATEN	(1<<3)	/* Aging Timer Enable */
92 #define UCR2_TXEN	(1<<2)	/* Transmitter enabled */
93 #define UCR2_RXEN	(1<<1)	/* Receiver enabled */
94 #define UCR2_SRST	(1<<0)	/* SW reset */
95 #define UCR3_DTREN	(1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN	(1<<12) /* Parity enable */
97 #define UCR3_FRAERREN	(1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR	(1<<10) /* Data set ready */
99 #define UCR3_DCD	(1<<9)	/* Data carrier detect */
100 #define UCR3_RI		(1<<8)	/* Ring indicator */
101 #define UCR3_ADNIMP	(1<<7)	/* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN	(1<<6)	/* Receive status interrupt enable */
103 #define UCR3_AIRINTEN	(1<<5)	/* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN	(1<<4)	/* Async wake interrupt enable */
105 #define UCR3_DTRDEN	(1<<3)	/* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL	(1<<2)	/* RXD Muxed Input Select */
107 #define UCR3_INVT	(1<<1)	/* Inverted Infrared transmission */
108 #define UCR3_BPEN	(1<<0)	/* Preset registers enable */
109 #define UCR4_CTSTL_SHF	10	/* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK	0x3F	/* CTS trigger is 6 bits wide */
111 #define UCR4_INVR	(1<<9)	/* Inverted infrared reception */
112 #define UCR4_ENIRI	(1<<8)	/* Serial infrared interrupt enable */
113 #define UCR4_WKEN	(1<<7)	/* Wake interrupt enable */
114 #define UCR4_REF16	(1<<6)	/* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC	(1<<5)	/* IR special case */
117 #define UCR4_TCEN	(1<<3)	/* Transmit complete interrupt enable */
118 #define UCR4_BKEN	(1<<2)	/* Break condition interrupt enable */
119 #define UCR4_OREN	(1<<1)	/* Receiver overrun interrupt enable */
120 #define UCR4_DREN	(1<<0)	/* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF	0	/* Receiver trigger level shift */
122 #define UFCR_RXTL_MASK	0x3F	/* Receiver trigger 6 bits wide */
123 #define UFCR_DCEDTE	(1<<6)	/* DCE/DTE mode select */
124 #define UFCR_RFDIV	(7<<7)	/* Reference freq divider mask */
125 #define UFCR_RFDIV_REG(x)	(((x) < 7 ? 6 - (x) : 6) << 7)
126 #define UFCR_TXTL_SHF	10	/* Transmitter trigger level shift */
127 #define USR1_PARITYERR	(1<<15) /* Parity error interrupt flag */
128 #define USR1_RTSS	(1<<14) /* RTS pin status */
129 #define USR1_TRDY	(1<<13) /* Transmitter ready interrupt/dma flag */
130 #define USR1_RTSD	(1<<12) /* RTS delta */
131 #define USR1_ESCF	(1<<11) /* Escape seq interrupt flag */
132 #define USR1_FRAMERR	(1<<10) /* Frame error interrupt flag */
133 #define USR1_RRDY	(1<<9)	 /* Receiver ready interrupt/dma flag */
134 #define USR1_AGTIM	(1<<8)	 /* Ageing timer interrupt flag */
135 #define USR1_DTRD	(1<<7)	 /* DTR Delta */
136 #define USR1_RXDS	 (1<<6)	 /* Receiver idle interrupt flag */
137 #define USR1_AIRINT	 (1<<5)	 /* Async IR wake interrupt flag */
138 #define USR1_AWAKE	 (1<<4)	 /* Aysnc wake interrupt flag */
139 #define USR2_ADET	 (1<<15) /* Auto baud rate detect complete */
140 #define USR2_TXFE	 (1<<14) /* Transmit buffer FIFO empty */
141 #define USR2_DTRF	 (1<<13) /* DTR edge interrupt flag */
142 #define USR2_IDLE	 (1<<12) /* Idle condition */
143 #define USR2_RIDELT	 (1<<10) /* Ring Interrupt Delta */
144 #define USR2_RIIN	 (1<<9)	 /* Ring Indicator Input */
145 #define USR2_IRINT	 (1<<8)	 /* Serial infrared interrupt flag */
146 #define USR2_WAKE	 (1<<7)	 /* Wake */
147 #define USR2_DCDIN	 (1<<5)	 /* Data Carrier Detect Input */
148 #define USR2_RTSF	 (1<<4)	 /* RTS edge interrupt flag */
149 #define USR2_TXDC	 (1<<3)	 /* Transmitter complete */
150 #define USR2_BRCD	 (1<<2)	 /* Break condition */
151 #define USR2_ORE	(1<<1)	 /* Overrun error */
152 #define USR2_RDR	(1<<0)	 /* Recv data ready */
153 #define UTS_FRCPERR	(1<<13) /* Force parity error */
154 #define UTS_LOOP	(1<<12)	 /* Loop tx and rx */
155 #define UTS_TXEMPTY	 (1<<6)	 /* TxFIFO empty */
156 #define UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
157 #define UTS_TXFULL	 (1<<4)	 /* TxFIFO full */
158 #define UTS_RXFULL	 (1<<3)	 /* RxFIFO full */
159 #define UTS_SOFTRST	 (1<<0)	 /* Software reset */
160 
161 /* We've been assigned a range on the "Low-density serial ports" major */
162 #define SERIAL_IMX_MAJOR	207
163 #define MINOR_START		16
164 #define DEV_NAME		"ttymxc"
165 
166 /*
167  * This determines how often we check the modem status signals
168  * for any change.  They generally aren't connected to an IRQ
169  * so we have to poll them.  We also check immediately before
170  * filling the TX fifo incase CTS has been dropped.
171  */
172 #define MCTRL_TIMEOUT	(250*HZ/1000)
173 
174 #define DRIVER_NAME "IMX-uart"
175 
176 #define UART_NR 8
177 
178 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
179 enum imx_uart_type {
180 	IMX1_UART,
181 	IMX21_UART,
182 	IMX53_UART,
183 	IMX6Q_UART,
184 };
185 
186 /* device type dependent stuff */
187 struct imx_uart_data {
188 	unsigned uts_reg;
189 	enum imx_uart_type devtype;
190 };
191 
192 enum imx_tx_state {
193 	OFF,
194 	WAIT_AFTER_RTS,
195 	SEND,
196 	WAIT_AFTER_SEND,
197 };
198 
199 struct imx_port {
200 	struct uart_port	port;
201 	struct timer_list	timer;
202 	unsigned int		old_status;
203 	unsigned int		have_rtscts:1;
204 	unsigned int		have_rtsgpio:1;
205 	unsigned int		dte_mode:1;
206 	unsigned int		inverted_tx:1;
207 	unsigned int		inverted_rx:1;
208 	struct clk		*clk_ipg;
209 	struct clk		*clk_per;
210 	const struct imx_uart_data *devdata;
211 
212 	struct mctrl_gpios *gpios;
213 
214 	/* counter to stop 0xff flood */
215 	int idle_counter;
216 
217 	/* DMA fields */
218 	unsigned int		dma_is_enabled:1;
219 	unsigned int		dma_is_rxing:1;
220 	unsigned int		dma_is_txing:1;
221 	struct dma_chan		*dma_chan_rx, *dma_chan_tx;
222 	struct scatterlist	rx_sgl, tx_sgl[2];
223 	void			*rx_buf;
224 	struct circ_buf		rx_ring;
225 	unsigned int		rx_buf_size;
226 	unsigned int		rx_period_length;
227 	unsigned int		rx_periods;
228 	dma_cookie_t		rx_cookie;
229 	unsigned int		tx_bytes;
230 	unsigned int		dma_tx_nents;
231 	unsigned int            saved_reg[10];
232 	bool			context_saved;
233 
234 	enum imx_tx_state	tx_state;
235 	struct hrtimer		trigger_start_tx;
236 	struct hrtimer		trigger_stop_tx;
237 };
238 
239 struct imx_port_ucrs {
240 	unsigned int	ucr1;
241 	unsigned int	ucr2;
242 	unsigned int	ucr3;
243 };
244 
245 static struct imx_uart_data imx_uart_devdata[] = {
246 	[IMX1_UART] = {
247 		.uts_reg = IMX1_UTS,
248 		.devtype = IMX1_UART,
249 	},
250 	[IMX21_UART] = {
251 		.uts_reg = IMX21_UTS,
252 		.devtype = IMX21_UART,
253 	},
254 	[IMX53_UART] = {
255 		.uts_reg = IMX21_UTS,
256 		.devtype = IMX53_UART,
257 	},
258 	[IMX6Q_UART] = {
259 		.uts_reg = IMX21_UTS,
260 		.devtype = IMX6Q_UART,
261 	},
262 };
263 
264 static const struct of_device_id imx_uart_dt_ids[] = {
265 	{ .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
266 	{ .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
267 	{ .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
268 	{ .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
269 	{ /* sentinel */ }
270 };
271 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
272 
273 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
274 {
275 	writel(val, sport->port.membase + offset);
276 }
277 
278 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
279 {
280 	return readl(sport->port.membase + offset);
281 }
282 
283 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
284 {
285 	return sport->devdata->uts_reg;
286 }
287 
288 static inline int imx_uart_is_imx1(struct imx_port *sport)
289 {
290 	return sport->devdata->devtype == IMX1_UART;
291 }
292 
293 /*
294  * Save and restore functions for UCR1, UCR2 and UCR3 registers
295  */
296 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
297 static void imx_uart_ucrs_save(struct imx_port *sport,
298 			       struct imx_port_ucrs *ucr)
299 {
300 	/* save control registers */
301 	ucr->ucr1 = imx_uart_readl(sport, UCR1);
302 	ucr->ucr2 = imx_uart_readl(sport, UCR2);
303 	ucr->ucr3 = imx_uart_readl(sport, UCR3);
304 }
305 
306 static void imx_uart_ucrs_restore(struct imx_port *sport,
307 				  struct imx_port_ucrs *ucr)
308 {
309 	/* restore control registers */
310 	imx_uart_writel(sport, ucr->ucr1, UCR1);
311 	imx_uart_writel(sport, ucr->ucr2, UCR2);
312 	imx_uart_writel(sport, ucr->ucr3, UCR3);
313 }
314 #endif
315 
316 /* called with port.lock taken and irqs caller dependent */
317 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
318 {
319 	*ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
320 
321 	mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
322 }
323 
324 /* called with port.lock taken and irqs caller dependent */
325 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
326 {
327 	*ucr2 &= ~UCR2_CTSC;
328 	*ucr2 |= UCR2_CTS;
329 
330 	mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
331 }
332 
333 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
334 {
335        hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
336 }
337 
338 /* called with port.lock taken and irqs off */
339 static void imx_uart_soft_reset(struct imx_port *sport)
340 {
341 	int i = 10;
342 	u32 ucr2, ubir, ubmr, uts;
343 
344 	/*
345 	 * According to the Reference Manual description of the UART SRST bit:
346 	 *
347 	 * "Reset the transmit and receive state machines,
348 	 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
349 	 * and UTS[6-3]".
350 	 *
351 	 * We don't need to restore the old values from USR1, USR2, URXD and
352 	 * UTXD. UBRC is read only, so only save/restore the other three
353 	 * registers.
354 	 */
355 	ubir = imx_uart_readl(sport, UBIR);
356 	ubmr = imx_uart_readl(sport, UBMR);
357 	uts = imx_uart_readl(sport, IMX21_UTS);
358 
359 	ucr2 = imx_uart_readl(sport, UCR2);
360 	imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
361 
362 	while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
363 		udelay(1);
364 
365 	/* Restore the registers */
366 	imx_uart_writel(sport, ubir, UBIR);
367 	imx_uart_writel(sport, ubmr, UBMR);
368 	imx_uart_writel(sport, uts, IMX21_UTS);
369 
370 	sport->idle_counter = 0;
371 }
372 
373 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
374 {
375 	unsigned int uts;
376 
377 	/* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
378 	uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
379 	uts &= ~UTS_LOOP;
380 	imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
381 }
382 
383 /* called with port.lock taken and irqs off */
384 static void imx_uart_start_rx(struct uart_port *port)
385 {
386 	struct imx_port *sport = (struct imx_port *)port;
387 	unsigned int ucr1, ucr2;
388 
389 	ucr1 = imx_uart_readl(sport, UCR1);
390 	ucr2 = imx_uart_readl(sport, UCR2);
391 
392 	ucr2 |= UCR2_RXEN;
393 
394 	if (sport->dma_is_enabled) {
395 		ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
396 	} else {
397 		ucr1 |= UCR1_RRDYEN;
398 		ucr2 |= UCR2_ATEN;
399 	}
400 
401 	/* Write UCR2 first as it includes RXEN */
402 	imx_uart_writel(sport, ucr2, UCR2);
403 	imx_uart_writel(sport, ucr1, UCR1);
404 	imx_uart_disable_loopback_rs485(sport);
405 }
406 
407 /* called with port.lock taken and irqs off */
408 static void imx_uart_stop_tx(struct uart_port *port)
409 {
410 	struct imx_port *sport = (struct imx_port *)port;
411 	u32 ucr1, ucr4, usr2;
412 
413 	if (sport->tx_state == OFF)
414 		return;
415 
416 	/*
417 	 * We are maybe in the SMP context, so if the DMA TX thread is running
418 	 * on other cpu, we have to wait for it to finish.
419 	 */
420 	if (sport->dma_is_txing)
421 		return;
422 
423 	ucr1 = imx_uart_readl(sport, UCR1);
424 	imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
425 
426 	ucr4 = imx_uart_readl(sport, UCR4);
427 	usr2 = imx_uart_readl(sport, USR2);
428 	if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
429 		/* The shifter is still busy, so retry once TC triggers */
430 		return;
431 	}
432 
433 	ucr4 &= ~UCR4_TCEN;
434 	imx_uart_writel(sport, ucr4, UCR4);
435 
436 	/* in rs485 mode disable transmitter */
437 	if (port->rs485.flags & SER_RS485_ENABLED) {
438 		if (sport->tx_state == SEND) {
439 			sport->tx_state = WAIT_AFTER_SEND;
440 
441 			if (port->rs485.delay_rts_after_send > 0) {
442 				start_hrtimer_ms(&sport->trigger_stop_tx,
443 					 port->rs485.delay_rts_after_send);
444 				return;
445 			}
446 
447 			/* continue without any delay */
448 		}
449 
450 		if (sport->tx_state == WAIT_AFTER_RTS ||
451 		    sport->tx_state == WAIT_AFTER_SEND) {
452 			u32 ucr2;
453 
454 			hrtimer_try_to_cancel(&sport->trigger_start_tx);
455 
456 			ucr2 = imx_uart_readl(sport, UCR2);
457 			if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
458 				imx_uart_rts_active(sport, &ucr2);
459 			else
460 				imx_uart_rts_inactive(sport, &ucr2);
461 			imx_uart_writel(sport, ucr2, UCR2);
462 
463 			if (!port->rs485_rx_during_tx_gpio)
464 				imx_uart_start_rx(port);
465 
466 			sport->tx_state = OFF;
467 		}
468 	} else {
469 		sport->tx_state = OFF;
470 	}
471 }
472 
473 static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
474 {
475 	struct imx_port *sport = (struct imx_port *)port;
476 	u32 ucr1, ucr2, ucr4, uts;
477 
478 	ucr1 = imx_uart_readl(sport, UCR1);
479 	ucr2 = imx_uart_readl(sport, UCR2);
480 	ucr4 = imx_uart_readl(sport, UCR4);
481 
482 	if (sport->dma_is_enabled) {
483 		ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
484 	} else {
485 		ucr1 &= ~UCR1_RRDYEN;
486 		ucr2 &= ~UCR2_ATEN;
487 		ucr4 &= ~UCR4_OREN;
488 	}
489 	imx_uart_writel(sport, ucr1, UCR1);
490 	imx_uart_writel(sport, ucr4, UCR4);
491 
492 	/* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
493 	if (port->rs485.flags & SER_RS485_ENABLED &&
494 	    port->rs485.flags & SER_RS485_RTS_ON_SEND &&
495 	    sport->have_rtscts && !sport->have_rtsgpio && loopback) {
496 		uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
497 		uts |= UTS_LOOP;
498 		imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
499 		ucr2 |= UCR2_RXEN;
500 	} else {
501 		ucr2 &= ~UCR2_RXEN;
502 	}
503 
504 	imx_uart_writel(sport, ucr2, UCR2);
505 }
506 
507 /* called with port.lock taken and irqs off */
508 static void imx_uart_stop_rx(struct uart_port *port)
509 {
510 	/*
511 	 * Stop RX and enable loopback in order to make sure RS485 bus
512 	 * is not blocked. Se comment in imx_uart_probe().
513 	 */
514 	imx_uart_stop_rx_with_loopback_ctrl(port, true);
515 }
516 
517 /* called with port.lock taken and irqs off */
518 static void imx_uart_enable_ms(struct uart_port *port)
519 {
520 	struct imx_port *sport = (struct imx_port *)port;
521 
522 	mod_timer(&sport->timer, jiffies);
523 
524 	mctrl_gpio_enable_ms(sport->gpios);
525 }
526 
527 static void imx_uart_dma_tx(struct imx_port *sport);
528 
529 /* called with port.lock taken and irqs off */
530 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
531 {
532 	struct circ_buf *xmit = &sport->port.state->xmit;
533 
534 	if (sport->port.x_char) {
535 		/* Send next char */
536 		imx_uart_writel(sport, sport->port.x_char, URTX0);
537 		sport->port.icount.tx++;
538 		sport->port.x_char = 0;
539 		return;
540 	}
541 
542 	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
543 		imx_uart_stop_tx(&sport->port);
544 		return;
545 	}
546 
547 	if (sport->dma_is_enabled) {
548 		u32 ucr1;
549 		/*
550 		 * We've just sent a X-char Ensure the TX DMA is enabled
551 		 * and the TX IRQ is disabled.
552 		 **/
553 		ucr1 = imx_uart_readl(sport, UCR1);
554 		ucr1 &= ~UCR1_TRDYEN;
555 		if (sport->dma_is_txing) {
556 			ucr1 |= UCR1_TXDMAEN;
557 			imx_uart_writel(sport, ucr1, UCR1);
558 		} else {
559 			imx_uart_writel(sport, ucr1, UCR1);
560 			imx_uart_dma_tx(sport);
561 		}
562 
563 		return;
564 	}
565 
566 	while (!uart_circ_empty(xmit) &&
567 	       !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
568 		/* send xmit->buf[xmit->tail]
569 		 * out the port here */
570 		imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
571 		uart_xmit_advance(&sport->port, 1);
572 	}
573 
574 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
575 		uart_write_wakeup(&sport->port);
576 
577 	if (uart_circ_empty(xmit))
578 		imx_uart_stop_tx(&sport->port);
579 }
580 
581 static void imx_uart_dma_tx_callback(void *data)
582 {
583 	struct imx_port *sport = data;
584 	struct scatterlist *sgl = &sport->tx_sgl[0];
585 	struct circ_buf *xmit = &sport->port.state->xmit;
586 	unsigned long flags;
587 	u32 ucr1;
588 
589 	spin_lock_irqsave(&sport->port.lock, flags);
590 
591 	dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
592 
593 	ucr1 = imx_uart_readl(sport, UCR1);
594 	ucr1 &= ~UCR1_TXDMAEN;
595 	imx_uart_writel(sport, ucr1, UCR1);
596 
597 	uart_xmit_advance(&sport->port, sport->tx_bytes);
598 
599 	dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
600 
601 	sport->dma_is_txing = 0;
602 
603 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
604 		uart_write_wakeup(&sport->port);
605 
606 	if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
607 		imx_uart_dma_tx(sport);
608 	else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
609 		u32 ucr4 = imx_uart_readl(sport, UCR4);
610 		ucr4 |= UCR4_TCEN;
611 		imx_uart_writel(sport, ucr4, UCR4);
612 	}
613 
614 	spin_unlock_irqrestore(&sport->port.lock, flags);
615 }
616 
617 /* called with port.lock taken and irqs off */
618 static void imx_uart_dma_tx(struct imx_port *sport)
619 {
620 	struct circ_buf *xmit = &sport->port.state->xmit;
621 	struct scatterlist *sgl = sport->tx_sgl;
622 	struct dma_async_tx_descriptor *desc;
623 	struct dma_chan	*chan = sport->dma_chan_tx;
624 	struct device *dev = sport->port.dev;
625 	u32 ucr1, ucr4;
626 	int ret;
627 
628 	if (sport->dma_is_txing)
629 		return;
630 
631 	ucr4 = imx_uart_readl(sport, UCR4);
632 	ucr4 &= ~UCR4_TCEN;
633 	imx_uart_writel(sport, ucr4, UCR4);
634 
635 	sport->tx_bytes = uart_circ_chars_pending(xmit);
636 
637 	if (xmit->tail < xmit->head || xmit->head == 0) {
638 		sport->dma_tx_nents = 1;
639 		sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
640 	} else {
641 		sport->dma_tx_nents = 2;
642 		sg_init_table(sgl, 2);
643 		sg_set_buf(sgl, xmit->buf + xmit->tail,
644 				UART_XMIT_SIZE - xmit->tail);
645 		sg_set_buf(sgl + 1, xmit->buf, xmit->head);
646 	}
647 
648 	ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
649 	if (ret == 0) {
650 		dev_err(dev, "DMA mapping error for TX.\n");
651 		return;
652 	}
653 	desc = dmaengine_prep_slave_sg(chan, sgl, ret,
654 					DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
655 	if (!desc) {
656 		dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
657 			     DMA_TO_DEVICE);
658 		dev_err(dev, "We cannot prepare for the TX slave dma!\n");
659 		return;
660 	}
661 	desc->callback = imx_uart_dma_tx_callback;
662 	desc->callback_param = sport;
663 
664 	dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
665 			uart_circ_chars_pending(xmit));
666 
667 	ucr1 = imx_uart_readl(sport, UCR1);
668 	ucr1 |= UCR1_TXDMAEN;
669 	imx_uart_writel(sport, ucr1, UCR1);
670 
671 	/* fire it */
672 	sport->dma_is_txing = 1;
673 	dmaengine_submit(desc);
674 	dma_async_issue_pending(chan);
675 	return;
676 }
677 
678 /* called with port.lock taken and irqs off */
679 static void imx_uart_start_tx(struct uart_port *port)
680 {
681 	struct imx_port *sport = (struct imx_port *)port;
682 	u32 ucr1;
683 
684 	if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
685 		return;
686 
687 	/*
688 	 * We cannot simply do nothing here if sport->tx_state == SEND already
689 	 * because UCR1_TXMPTYEN might already have been cleared in
690 	 * imx_uart_stop_tx(), but tx_state is still SEND.
691 	 */
692 
693 	if (port->rs485.flags & SER_RS485_ENABLED) {
694 		if (sport->tx_state == OFF) {
695 			u32 ucr2 = imx_uart_readl(sport, UCR2);
696 			if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
697 				imx_uart_rts_active(sport, &ucr2);
698 			else
699 				imx_uart_rts_inactive(sport, &ucr2);
700 			imx_uart_writel(sport, ucr2, UCR2);
701 
702 			/*
703 			 * Since we are about to transmit we can not stop RX
704 			 * with loopback enabled because that will make our
705 			 * transmitted data being just looped to RX.
706 			 */
707 			if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
708 			    !port->rs485_rx_during_tx_gpio)
709 				imx_uart_stop_rx_with_loopback_ctrl(port, false);
710 
711 			sport->tx_state = WAIT_AFTER_RTS;
712 
713 			if (port->rs485.delay_rts_before_send > 0) {
714 				start_hrtimer_ms(&sport->trigger_start_tx,
715 					 port->rs485.delay_rts_before_send);
716 				return;
717 			}
718 
719 			/* continue without any delay */
720 		}
721 
722 		if (sport->tx_state == WAIT_AFTER_SEND
723 		    || sport->tx_state == WAIT_AFTER_RTS) {
724 
725 			hrtimer_try_to_cancel(&sport->trigger_stop_tx);
726 
727 			/*
728 			 * Enable transmitter and shifter empty irq only if DMA
729 			 * is off.  In the DMA case this is done in the
730 			 * tx-callback.
731 			 */
732 			if (!sport->dma_is_enabled) {
733 				u32 ucr4 = imx_uart_readl(sport, UCR4);
734 				ucr4 |= UCR4_TCEN;
735 				imx_uart_writel(sport, ucr4, UCR4);
736 			}
737 
738 			sport->tx_state = SEND;
739 		}
740 	} else {
741 		sport->tx_state = SEND;
742 	}
743 
744 	if (!sport->dma_is_enabled) {
745 		ucr1 = imx_uart_readl(sport, UCR1);
746 		imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
747 	}
748 
749 	if (sport->dma_is_enabled) {
750 		if (sport->port.x_char) {
751 			/* We have X-char to send, so enable TX IRQ and
752 			 * disable TX DMA to let TX interrupt to send X-char */
753 			ucr1 = imx_uart_readl(sport, UCR1);
754 			ucr1 &= ~UCR1_TXDMAEN;
755 			ucr1 |= UCR1_TRDYEN;
756 			imx_uart_writel(sport, ucr1, UCR1);
757 			return;
758 		}
759 
760 		if (!uart_circ_empty(&port->state->xmit) &&
761 		    !uart_tx_stopped(port))
762 			imx_uart_dma_tx(sport);
763 		return;
764 	}
765 }
766 
767 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
768 {
769 	struct imx_port *sport = dev_id;
770 	u32 usr1;
771 
772 	imx_uart_writel(sport, USR1_RTSD, USR1);
773 	usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
774 	uart_handle_cts_change(&sport->port, usr1);
775 	wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
776 
777 	return IRQ_HANDLED;
778 }
779 
780 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
781 {
782 	struct imx_port *sport = dev_id;
783 	irqreturn_t ret;
784 
785 	spin_lock(&sport->port.lock);
786 
787 	ret = __imx_uart_rtsint(irq, dev_id);
788 
789 	spin_unlock(&sport->port.lock);
790 
791 	return ret;
792 }
793 
794 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
795 {
796 	struct imx_port *sport = dev_id;
797 
798 	spin_lock(&sport->port.lock);
799 	imx_uart_transmit_buffer(sport);
800 	spin_unlock(&sport->port.lock);
801 	return IRQ_HANDLED;
802 }
803 
804 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
805  * This is to be called from Rx ISRs only when some bytes were actually
806  * received.
807  *
808  * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
809  * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
810  * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
811  * that is terminated by any activity on RxD line, or could be stopped by
812  * issuing soft reset to the UART (just stop/start of RX does not help). Note
813  * that what we do here is sending isolated start bit about 2.4 times shorter
814  * than it is to be on UART configured baud rate.
815  */
816 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
817 {
818 	/* To detect hardware 0xff flood we monitor RxD line between RX
819 	 * interrupts to isolate "receiving" of char(s) with no activity
820 	 * on RxD line, that'd never happen on actual data transfers.
821 	 *
822 	 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
823 	 * race here if we clear USR2_WAKE when receiving of a char is in
824 	 * progress, so we might get RX interrupt later with USR2_WAKE bit
825 	 * cleared. Note though that as we don't try to clear USR2_WAKE when we
826 	 * detected no activity, this race may hide actual activity only once.
827 	 *
828 	 * Yet another case where receive interrupt may occur without RxD
829 	 * activity is expiration of aging timer, so we consider this as well.
830 	 *
831 	 * We use 'idle_counter' to ensure that we got at least so many RX
832 	 * interrupts without any detected activity on RxD line. 2 cases
833 	 * described plus 1 to be on the safe side gives us a margin of 3,
834 	 * below. In practice I was not able to produce a false positive to
835 	 * induce soft reset at regular data transfers even using 1 as the
836 	 * margin, so 3 is actually very strong.
837 	 *
838 	 * We count interrupts, not chars in 'idle-counter' for simplicity.
839 	 */
840 
841 	if (usr2 & USR2_WAKE) {
842 		imx_uart_writel(sport, USR2_WAKE, USR2);
843 		sport->idle_counter = 0;
844 	} else if (++sport->idle_counter > 3) {
845 		dev_warn(sport->port.dev, "RX flood detected: soft reset.");
846 		imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
847 	}
848 }
849 
850 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
851 {
852 	struct imx_port *sport = dev_id;
853 	struct tty_port *port = &sport->port.state->port;
854 	u32 usr2, rx;
855 
856 	/* If we received something, check for 0xff flood */
857 	usr2 = imx_uart_readl(sport, USR2);
858 	if (usr2 & USR2_RDR)
859 		imx_uart_check_flood(sport, usr2);
860 
861 	while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
862 		unsigned int flg = TTY_NORMAL;
863 		sport->port.icount.rx++;
864 
865 		if (unlikely(rx & URXD_ERR)) {
866 			if (rx & URXD_BRK) {
867 				sport->port.icount.brk++;
868 				if (uart_handle_break(&sport->port))
869 					continue;
870 			}
871 			else if (rx & URXD_PRERR)
872 				sport->port.icount.parity++;
873 			else if (rx & URXD_FRMERR)
874 				sport->port.icount.frame++;
875 			if (rx & URXD_OVRRUN)
876 				sport->port.icount.overrun++;
877 
878 			if (rx & sport->port.ignore_status_mask)
879 				continue;
880 
881 			rx &= (sport->port.read_status_mask | 0xFF);
882 
883 			if (rx & URXD_BRK)
884 				flg = TTY_BREAK;
885 			else if (rx & URXD_PRERR)
886 				flg = TTY_PARITY;
887 			else if (rx & URXD_FRMERR)
888 				flg = TTY_FRAME;
889 			if (rx & URXD_OVRRUN)
890 				flg = TTY_OVERRUN;
891 
892 			sport->port.sysrq = 0;
893 		} else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
894 			continue;
895 		}
896 
897 		if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
898 			continue;
899 
900 		if (tty_insert_flip_char(port, rx, flg) == 0)
901 			sport->port.icount.buf_overrun++;
902 	}
903 
904 	tty_flip_buffer_push(port);
905 
906 	return IRQ_HANDLED;
907 }
908 
909 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
910 {
911 	struct imx_port *sport = dev_id;
912 	irqreturn_t ret;
913 
914 	spin_lock(&sport->port.lock);
915 
916 	ret = __imx_uart_rxint(irq, dev_id);
917 
918 	spin_unlock(&sport->port.lock);
919 
920 	return ret;
921 }
922 
923 static void imx_uart_clear_rx_errors(struct imx_port *sport);
924 
925 /*
926  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
927  */
928 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
929 {
930 	unsigned int tmp = TIOCM_DSR;
931 	unsigned usr1 = imx_uart_readl(sport, USR1);
932 	unsigned usr2 = imx_uart_readl(sport, USR2);
933 
934 	if (usr1 & USR1_RTSS)
935 		tmp |= TIOCM_CTS;
936 
937 	/* in DCE mode DCDIN is always 0 */
938 	if (!(usr2 & USR2_DCDIN))
939 		tmp |= TIOCM_CAR;
940 
941 	if (sport->dte_mode)
942 		if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
943 			tmp |= TIOCM_RI;
944 
945 	return tmp;
946 }
947 
948 /*
949  * Handle any change of modem status signal since we were last called.
950  */
951 static void imx_uart_mctrl_check(struct imx_port *sport)
952 {
953 	unsigned int status, changed;
954 
955 	status = imx_uart_get_hwmctrl(sport);
956 	changed = status ^ sport->old_status;
957 
958 	if (changed == 0)
959 		return;
960 
961 	sport->old_status = status;
962 
963 	if (changed & TIOCM_RI && status & TIOCM_RI)
964 		sport->port.icount.rng++;
965 	if (changed & TIOCM_DSR)
966 		sport->port.icount.dsr++;
967 	if (changed & TIOCM_CAR)
968 		uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
969 	if (changed & TIOCM_CTS)
970 		uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
971 
972 	wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
973 }
974 
975 static irqreturn_t imx_uart_int(int irq, void *dev_id)
976 {
977 	struct imx_port *sport = dev_id;
978 	unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
979 	irqreturn_t ret = IRQ_NONE;
980 
981 	spin_lock(&sport->port.lock);
982 
983 	usr1 = imx_uart_readl(sport, USR1);
984 	usr2 = imx_uart_readl(sport, USR2);
985 	ucr1 = imx_uart_readl(sport, UCR1);
986 	ucr2 = imx_uart_readl(sport, UCR2);
987 	ucr3 = imx_uart_readl(sport, UCR3);
988 	ucr4 = imx_uart_readl(sport, UCR4);
989 
990 	/*
991 	 * Even if a condition is true that can trigger an irq only handle it if
992 	 * the respective irq source is enabled. This prevents some undesired
993 	 * actions, for example if a character that sits in the RX FIFO and that
994 	 * should be fetched via DMA is tried to be fetched using PIO. Or the
995 	 * receiver is currently off and so reading from URXD0 results in an
996 	 * exception. So just mask the (raw) status bits for disabled irqs.
997 	 */
998 	if ((ucr1 & UCR1_RRDYEN) == 0)
999 		usr1 &= ~USR1_RRDY;
1000 	if ((ucr2 & UCR2_ATEN) == 0)
1001 		usr1 &= ~USR1_AGTIM;
1002 	if ((ucr1 & UCR1_TRDYEN) == 0)
1003 		usr1 &= ~USR1_TRDY;
1004 	if ((ucr4 & UCR4_TCEN) == 0)
1005 		usr2 &= ~USR2_TXDC;
1006 	if ((ucr3 & UCR3_DTRDEN) == 0)
1007 		usr1 &= ~USR1_DTRD;
1008 	if ((ucr1 & UCR1_RTSDEN) == 0)
1009 		usr1 &= ~USR1_RTSD;
1010 	if ((ucr3 & UCR3_AWAKEN) == 0)
1011 		usr1 &= ~USR1_AWAKE;
1012 	if ((ucr4 & UCR4_OREN) == 0)
1013 		usr2 &= ~USR2_ORE;
1014 
1015 	if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1016 		imx_uart_writel(sport, USR1_AGTIM, USR1);
1017 
1018 		__imx_uart_rxint(irq, dev_id);
1019 		ret = IRQ_HANDLED;
1020 	}
1021 
1022 	if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1023 		imx_uart_transmit_buffer(sport);
1024 		ret = IRQ_HANDLED;
1025 	}
1026 
1027 	if (usr1 & USR1_DTRD) {
1028 		imx_uart_writel(sport, USR1_DTRD, USR1);
1029 
1030 		imx_uart_mctrl_check(sport);
1031 
1032 		ret = IRQ_HANDLED;
1033 	}
1034 
1035 	if (usr1 & USR1_RTSD) {
1036 		__imx_uart_rtsint(irq, dev_id);
1037 		ret = IRQ_HANDLED;
1038 	}
1039 
1040 	if (usr1 & USR1_AWAKE) {
1041 		imx_uart_writel(sport, USR1_AWAKE, USR1);
1042 		ret = IRQ_HANDLED;
1043 	}
1044 
1045 	if (usr2 & USR2_ORE) {
1046 		sport->port.icount.overrun++;
1047 		imx_uart_writel(sport, USR2_ORE, USR2);
1048 		ret = IRQ_HANDLED;
1049 	}
1050 
1051 	spin_unlock(&sport->port.lock);
1052 
1053 	return ret;
1054 }
1055 
1056 /*
1057  * Return TIOCSER_TEMT when transmitter is not busy.
1058  */
1059 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1060 {
1061 	struct imx_port *sport = (struct imx_port *)port;
1062 	unsigned int ret;
1063 
1064 	ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
1065 
1066 	/* If the TX DMA is working, return 0. */
1067 	if (sport->dma_is_txing)
1068 		ret = 0;
1069 
1070 	return ret;
1071 }
1072 
1073 /* called with port.lock taken and irqs off */
1074 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1075 {
1076 	struct imx_port *sport = (struct imx_port *)port;
1077 	unsigned int ret = imx_uart_get_hwmctrl(sport);
1078 
1079 	mctrl_gpio_get(sport->gpios, &ret);
1080 
1081 	return ret;
1082 }
1083 
1084 /* called with port.lock taken and irqs off */
1085 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1086 {
1087 	struct imx_port *sport = (struct imx_port *)port;
1088 	u32 ucr3, uts;
1089 
1090 	if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1091 		u32 ucr2;
1092 
1093 		/*
1094 		 * Turn off autoRTS if RTS is lowered and restore autoRTS
1095 		 * setting if RTS is raised.
1096 		 */
1097 		ucr2 = imx_uart_readl(sport, UCR2);
1098 		ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1099 		if (mctrl & TIOCM_RTS) {
1100 			ucr2 |= UCR2_CTS;
1101 			/*
1102 			 * UCR2_IRTS is unset if and only if the port is
1103 			 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1104 			 * to get the state to restore to.
1105 			 */
1106 			if (!(ucr2 & UCR2_IRTS))
1107 				ucr2 |= UCR2_CTSC;
1108 		}
1109 		imx_uart_writel(sport, ucr2, UCR2);
1110 	}
1111 
1112 	ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1113 	if (!(mctrl & TIOCM_DTR))
1114 		ucr3 |= UCR3_DSR;
1115 	imx_uart_writel(sport, ucr3, UCR3);
1116 
1117 	uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1118 	if (mctrl & TIOCM_LOOP)
1119 		uts |= UTS_LOOP;
1120 	imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1121 
1122 	mctrl_gpio_set(sport->gpios, mctrl);
1123 }
1124 
1125 /*
1126  * Interrupts always disabled.
1127  */
1128 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1129 {
1130 	struct imx_port *sport = (struct imx_port *)port;
1131 	unsigned long flags;
1132 	u32 ucr1;
1133 
1134 	spin_lock_irqsave(&sport->port.lock, flags);
1135 
1136 	ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1137 
1138 	if (break_state != 0)
1139 		ucr1 |= UCR1_SNDBRK;
1140 
1141 	imx_uart_writel(sport, ucr1, UCR1);
1142 
1143 	spin_unlock_irqrestore(&sport->port.lock, flags);
1144 }
1145 
1146 /*
1147  * This is our per-port timeout handler, for checking the
1148  * modem status signals.
1149  */
1150 static void imx_uart_timeout(struct timer_list *t)
1151 {
1152 	struct imx_port *sport = from_timer(sport, t, timer);
1153 	unsigned long flags;
1154 
1155 	if (sport->port.state) {
1156 		spin_lock_irqsave(&sport->port.lock, flags);
1157 		imx_uart_mctrl_check(sport);
1158 		spin_unlock_irqrestore(&sport->port.lock, flags);
1159 
1160 		mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1161 	}
1162 }
1163 
1164 /*
1165  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1166  *   [1] the RX DMA buffer is full.
1167  *   [2] the aging timer expires
1168  *
1169  * Condition [2] is triggered when a character has been sitting in the FIFO
1170  * for at least 8 byte durations.
1171  */
1172 static void imx_uart_dma_rx_callback(void *data)
1173 {
1174 	struct imx_port *sport = data;
1175 	struct dma_chan	*chan = sport->dma_chan_rx;
1176 	struct scatterlist *sgl = &sport->rx_sgl;
1177 	struct tty_port *port = &sport->port.state->port;
1178 	struct dma_tx_state state;
1179 	struct circ_buf *rx_ring = &sport->rx_ring;
1180 	enum dma_status status;
1181 	unsigned int w_bytes = 0;
1182 	unsigned int r_bytes;
1183 	unsigned int bd_size;
1184 
1185 	status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1186 
1187 	if (status == DMA_ERROR) {
1188 		spin_lock(&sport->port.lock);
1189 		imx_uart_clear_rx_errors(sport);
1190 		spin_unlock(&sport->port.lock);
1191 		return;
1192 	}
1193 
1194 	/*
1195 	 * The state-residue variable represents the empty space
1196 	 * relative to the entire buffer. Taking this in consideration
1197 	 * the head is always calculated base on the buffer total
1198 	 * length - DMA transaction residue. The UART script from the
1199 	 * SDMA firmware will jump to the next buffer descriptor,
1200 	 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1201 	 * Taking this in consideration the tail is always at the
1202 	 * beginning of the buffer descriptor that contains the head.
1203 	 */
1204 
1205 	/* Calculate the head */
1206 	rx_ring->head = sg_dma_len(sgl) - state.residue;
1207 
1208 	/* Calculate the tail. */
1209 	bd_size = sg_dma_len(sgl) / sport->rx_periods;
1210 	rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1211 
1212 	if (rx_ring->head <= sg_dma_len(sgl) &&
1213 	    rx_ring->head > rx_ring->tail) {
1214 
1215 		/* Move data from tail to head */
1216 		r_bytes = rx_ring->head - rx_ring->tail;
1217 
1218 		/* If we received something, check for 0xff flood */
1219 		spin_lock(&sport->port.lock);
1220 		imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1221 		spin_unlock(&sport->port.lock);
1222 
1223 		if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1224 
1225 			/* CPU claims ownership of RX DMA buffer */
1226 			dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1227 					    DMA_FROM_DEVICE);
1228 
1229 			w_bytes = tty_insert_flip_string(port,
1230 							 sport->rx_buf + rx_ring->tail, r_bytes);
1231 
1232 			/* UART retrieves ownership of RX DMA buffer */
1233 			dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1234 					       DMA_FROM_DEVICE);
1235 
1236 			if (w_bytes != r_bytes)
1237 				sport->port.icount.buf_overrun++;
1238 
1239 			sport->port.icount.rx += w_bytes;
1240 		}
1241 	} else	{
1242 		WARN_ON(rx_ring->head > sg_dma_len(sgl));
1243 		WARN_ON(rx_ring->head <= rx_ring->tail);
1244 	}
1245 
1246 	if (w_bytes) {
1247 		tty_flip_buffer_push(port);
1248 		dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1249 	}
1250 }
1251 
1252 static int imx_uart_start_rx_dma(struct imx_port *sport)
1253 {
1254 	struct scatterlist *sgl = &sport->rx_sgl;
1255 	struct dma_chan	*chan = sport->dma_chan_rx;
1256 	struct device *dev = sport->port.dev;
1257 	struct dma_async_tx_descriptor *desc;
1258 	int ret;
1259 
1260 	sport->rx_ring.head = 0;
1261 	sport->rx_ring.tail = 0;
1262 
1263 	sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1264 	ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1265 	if (ret == 0) {
1266 		dev_err(dev, "DMA mapping error for RX.\n");
1267 		return -EINVAL;
1268 	}
1269 
1270 	desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1271 		sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1272 		DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1273 
1274 	if (!desc) {
1275 		dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1276 		dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1277 		return -EINVAL;
1278 	}
1279 	desc->callback = imx_uart_dma_rx_callback;
1280 	desc->callback_param = sport;
1281 
1282 	dev_dbg(dev, "RX: prepare for the DMA.\n");
1283 	sport->dma_is_rxing = 1;
1284 	sport->rx_cookie = dmaengine_submit(desc);
1285 	dma_async_issue_pending(chan);
1286 	return 0;
1287 }
1288 
1289 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1290 {
1291 	struct tty_port *port = &sport->port.state->port;
1292 	u32 usr1, usr2;
1293 
1294 	usr1 = imx_uart_readl(sport, USR1);
1295 	usr2 = imx_uart_readl(sport, USR2);
1296 
1297 	if (usr2 & USR2_BRCD) {
1298 		sport->port.icount.brk++;
1299 		imx_uart_writel(sport, USR2_BRCD, USR2);
1300 		uart_handle_break(&sport->port);
1301 		if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1302 			sport->port.icount.buf_overrun++;
1303 		tty_flip_buffer_push(port);
1304 	} else {
1305 		if (usr1 & USR1_FRAMERR) {
1306 			sport->port.icount.frame++;
1307 			imx_uart_writel(sport, USR1_FRAMERR, USR1);
1308 		} else if (usr1 & USR1_PARITYERR) {
1309 			sport->port.icount.parity++;
1310 			imx_uart_writel(sport, USR1_PARITYERR, USR1);
1311 		}
1312 	}
1313 
1314 	if (usr2 & USR2_ORE) {
1315 		sport->port.icount.overrun++;
1316 		imx_uart_writel(sport, USR2_ORE, USR2);
1317 	}
1318 
1319 	sport->idle_counter = 0;
1320 
1321 }
1322 
1323 #define TXTL_DEFAULT 8
1324 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1325 #define TXTL_DMA 8 /* DMA burst setting */
1326 #define RXTL_DMA 9 /* DMA burst setting */
1327 
1328 static void imx_uart_setup_ufcr(struct imx_port *sport,
1329 				unsigned char txwl, unsigned char rxwl)
1330 {
1331 	unsigned int val;
1332 
1333 	/* set receiver / transmitter trigger level */
1334 	val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1335 	val |= txwl << UFCR_TXTL_SHF | rxwl;
1336 	imx_uart_writel(sport, val, UFCR);
1337 }
1338 
1339 static void imx_uart_dma_exit(struct imx_port *sport)
1340 {
1341 	if (sport->dma_chan_rx) {
1342 		dmaengine_terminate_sync(sport->dma_chan_rx);
1343 		dma_release_channel(sport->dma_chan_rx);
1344 		sport->dma_chan_rx = NULL;
1345 		sport->rx_cookie = -EINVAL;
1346 		kfree(sport->rx_buf);
1347 		sport->rx_buf = NULL;
1348 	}
1349 
1350 	if (sport->dma_chan_tx) {
1351 		dmaengine_terminate_sync(sport->dma_chan_tx);
1352 		dma_release_channel(sport->dma_chan_tx);
1353 		sport->dma_chan_tx = NULL;
1354 	}
1355 }
1356 
1357 static int imx_uart_dma_init(struct imx_port *sport)
1358 {
1359 	struct dma_slave_config slave_config = {};
1360 	struct device *dev = sport->port.dev;
1361 	int ret;
1362 
1363 	/* Prepare for RX : */
1364 	sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1365 	if (!sport->dma_chan_rx) {
1366 		dev_dbg(dev, "cannot get the DMA channel.\n");
1367 		ret = -EINVAL;
1368 		goto err;
1369 	}
1370 
1371 	slave_config.direction = DMA_DEV_TO_MEM;
1372 	slave_config.src_addr = sport->port.mapbase + URXD0;
1373 	slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1374 	/* one byte less than the watermark level to enable the aging timer */
1375 	slave_config.src_maxburst = RXTL_DMA - 1;
1376 	ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1377 	if (ret) {
1378 		dev_err(dev, "error in RX dma configuration.\n");
1379 		goto err;
1380 	}
1381 
1382 	sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1383 	sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1384 	if (!sport->rx_buf) {
1385 		ret = -ENOMEM;
1386 		goto err;
1387 	}
1388 	sport->rx_ring.buf = sport->rx_buf;
1389 
1390 	/* Prepare for TX : */
1391 	sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1392 	if (!sport->dma_chan_tx) {
1393 		dev_err(dev, "cannot get the TX DMA channel!\n");
1394 		ret = -EINVAL;
1395 		goto err;
1396 	}
1397 
1398 	slave_config.direction = DMA_MEM_TO_DEV;
1399 	slave_config.dst_addr = sport->port.mapbase + URTX0;
1400 	slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1401 	slave_config.dst_maxburst = TXTL_DMA;
1402 	ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1403 	if (ret) {
1404 		dev_err(dev, "error in TX dma configuration.");
1405 		goto err;
1406 	}
1407 
1408 	return 0;
1409 err:
1410 	imx_uart_dma_exit(sport);
1411 	return ret;
1412 }
1413 
1414 static void imx_uart_enable_dma(struct imx_port *sport)
1415 {
1416 	u32 ucr1;
1417 
1418 	imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1419 
1420 	/* set UCR1 */
1421 	ucr1 = imx_uart_readl(sport, UCR1);
1422 	ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1423 	imx_uart_writel(sport, ucr1, UCR1);
1424 
1425 	sport->dma_is_enabled = 1;
1426 }
1427 
1428 static void imx_uart_disable_dma(struct imx_port *sport)
1429 {
1430 	u32 ucr1;
1431 
1432 	/* clear UCR1 */
1433 	ucr1 = imx_uart_readl(sport, UCR1);
1434 	ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1435 	imx_uart_writel(sport, ucr1, UCR1);
1436 
1437 	imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1438 
1439 	sport->dma_is_enabled = 0;
1440 }
1441 
1442 /* half the RX buffer size */
1443 #define CTSTL 16
1444 
1445 static int imx_uart_startup(struct uart_port *port)
1446 {
1447 	struct imx_port *sport = (struct imx_port *)port;
1448 	int retval;
1449 	unsigned long flags;
1450 	int dma_is_inited = 0;
1451 	u32 ucr1, ucr2, ucr3, ucr4;
1452 
1453 	retval = clk_prepare_enable(sport->clk_per);
1454 	if (retval)
1455 		return retval;
1456 	retval = clk_prepare_enable(sport->clk_ipg);
1457 	if (retval) {
1458 		clk_disable_unprepare(sport->clk_per);
1459 		return retval;
1460 	}
1461 
1462 	imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1463 
1464 	/* disable the DREN bit (Data Ready interrupt enable) before
1465 	 * requesting IRQs
1466 	 */
1467 	ucr4 = imx_uart_readl(sport, UCR4);
1468 
1469 	/* set the trigger level for CTS */
1470 	ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1471 	ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1472 
1473 	imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1474 
1475 	/* Can we enable the DMA support? */
1476 	if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1477 		dma_is_inited = 1;
1478 
1479 	spin_lock_irqsave(&sport->port.lock, flags);
1480 
1481 	/* Reset fifo's and state machines */
1482 	imx_uart_soft_reset(sport);
1483 
1484 	/*
1485 	 * Finally, clear and enable interrupts
1486 	 */
1487 	imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1488 	imx_uart_writel(sport, USR2_ORE, USR2);
1489 
1490 	ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1491 	ucr1 |= UCR1_UARTEN;
1492 	if (sport->have_rtscts)
1493 		ucr1 |= UCR1_RTSDEN;
1494 
1495 	imx_uart_writel(sport, ucr1, UCR1);
1496 
1497 	ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1498 	if (!dma_is_inited)
1499 		ucr4 |= UCR4_OREN;
1500 	if (sport->inverted_rx)
1501 		ucr4 |= UCR4_INVR;
1502 	imx_uart_writel(sport, ucr4, UCR4);
1503 
1504 	ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1505 	/*
1506 	 * configure tx polarity before enabling tx
1507 	 */
1508 	if (sport->inverted_tx)
1509 		ucr3 |= UCR3_INVT;
1510 
1511 	if (!imx_uart_is_imx1(sport)) {
1512 		ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1513 
1514 		if (sport->dte_mode)
1515 			/* disable broken interrupts */
1516 			ucr3 &= ~(UCR3_RI | UCR3_DCD);
1517 	}
1518 	imx_uart_writel(sport, ucr3, UCR3);
1519 
1520 	ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1521 	ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1522 	if (!sport->have_rtscts)
1523 		ucr2 |= UCR2_IRTS;
1524 	/*
1525 	 * make sure the edge sensitive RTS-irq is disabled,
1526 	 * we're using RTSD instead.
1527 	 */
1528 	if (!imx_uart_is_imx1(sport))
1529 		ucr2 &= ~UCR2_RTSEN;
1530 	imx_uart_writel(sport, ucr2, UCR2);
1531 
1532 	/*
1533 	 * Enable modem status interrupts
1534 	 */
1535 	imx_uart_enable_ms(&sport->port);
1536 
1537 	if (dma_is_inited) {
1538 		imx_uart_enable_dma(sport);
1539 		imx_uart_start_rx_dma(sport);
1540 	} else {
1541 		ucr1 = imx_uart_readl(sport, UCR1);
1542 		ucr1 |= UCR1_RRDYEN;
1543 		imx_uart_writel(sport, ucr1, UCR1);
1544 
1545 		ucr2 = imx_uart_readl(sport, UCR2);
1546 		ucr2 |= UCR2_ATEN;
1547 		imx_uart_writel(sport, ucr2, UCR2);
1548 	}
1549 
1550 	imx_uart_disable_loopback_rs485(sport);
1551 
1552 	spin_unlock_irqrestore(&sport->port.lock, flags);
1553 
1554 	return 0;
1555 }
1556 
1557 static void imx_uart_shutdown(struct uart_port *port)
1558 {
1559 	struct imx_port *sport = (struct imx_port *)port;
1560 	unsigned long flags;
1561 	u32 ucr1, ucr2, ucr4, uts;
1562 
1563 	if (sport->dma_is_enabled) {
1564 		dmaengine_terminate_sync(sport->dma_chan_tx);
1565 		if (sport->dma_is_txing) {
1566 			dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1567 				     sport->dma_tx_nents, DMA_TO_DEVICE);
1568 			sport->dma_is_txing = 0;
1569 		}
1570 		dmaengine_terminate_sync(sport->dma_chan_rx);
1571 		if (sport->dma_is_rxing) {
1572 			dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1573 				     1, DMA_FROM_DEVICE);
1574 			sport->dma_is_rxing = 0;
1575 		}
1576 
1577 		spin_lock_irqsave(&sport->port.lock, flags);
1578 		imx_uart_stop_tx(port);
1579 		imx_uart_stop_rx(port);
1580 		imx_uart_disable_dma(sport);
1581 		spin_unlock_irqrestore(&sport->port.lock, flags);
1582 		imx_uart_dma_exit(sport);
1583 	}
1584 
1585 	mctrl_gpio_disable_ms(sport->gpios);
1586 
1587 	spin_lock_irqsave(&sport->port.lock, flags);
1588 	ucr2 = imx_uart_readl(sport, UCR2);
1589 	ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1590 	imx_uart_writel(sport, ucr2, UCR2);
1591 	spin_unlock_irqrestore(&sport->port.lock, flags);
1592 
1593 	/*
1594 	 * Stop our timer.
1595 	 */
1596 	del_timer_sync(&sport->timer);
1597 
1598 	/*
1599 	 * Disable all interrupts, port and break condition.
1600 	 */
1601 
1602 	spin_lock_irqsave(&sport->port.lock, flags);
1603 
1604 	ucr1 = imx_uart_readl(sport, UCR1);
1605 	ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1606 		  UCR1_ATDMAEN | UCR1_SNDBRK);
1607 	/* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1608 	if (port->rs485.flags & SER_RS485_ENABLED &&
1609 	    port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1610 	    sport->have_rtscts && !sport->have_rtsgpio) {
1611 		uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1612 		uts |= UTS_LOOP;
1613 		imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1614 		ucr1 |= UCR1_UARTEN;
1615 	} else {
1616 		ucr1 &= ~UCR1_UARTEN;
1617 	}
1618 	imx_uart_writel(sport, ucr1, UCR1);
1619 
1620 	ucr4 = imx_uart_readl(sport, UCR4);
1621 	ucr4 &= ~UCR4_TCEN;
1622 	imx_uart_writel(sport, ucr4, UCR4);
1623 
1624 	spin_unlock_irqrestore(&sport->port.lock, flags);
1625 
1626 	clk_disable_unprepare(sport->clk_per);
1627 	clk_disable_unprepare(sport->clk_ipg);
1628 }
1629 
1630 /* called with port.lock taken and irqs off */
1631 static void imx_uart_flush_buffer(struct uart_port *port)
1632 {
1633 	struct imx_port *sport = (struct imx_port *)port;
1634 	struct scatterlist *sgl = &sport->tx_sgl[0];
1635 
1636 	if (!sport->dma_chan_tx)
1637 		return;
1638 
1639 	sport->tx_bytes = 0;
1640 	dmaengine_terminate_all(sport->dma_chan_tx);
1641 	if (sport->dma_is_txing) {
1642 		u32 ucr1;
1643 
1644 		dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1645 			     DMA_TO_DEVICE);
1646 		ucr1 = imx_uart_readl(sport, UCR1);
1647 		ucr1 &= ~UCR1_TXDMAEN;
1648 		imx_uart_writel(sport, ucr1, UCR1);
1649 		sport->dma_is_txing = 0;
1650 	}
1651 
1652 	imx_uart_soft_reset(sport);
1653 
1654 }
1655 
1656 static void
1657 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1658 		     const struct ktermios *old)
1659 {
1660 	struct imx_port *sport = (struct imx_port *)port;
1661 	unsigned long flags;
1662 	u32 ucr2, old_ucr2, ufcr;
1663 	unsigned int baud, quot;
1664 	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1665 	unsigned long div;
1666 	unsigned long num, denom, old_ubir, old_ubmr;
1667 	uint64_t tdiv64;
1668 
1669 	/*
1670 	 * We only support CS7 and CS8.
1671 	 */
1672 	while ((termios->c_cflag & CSIZE) != CS7 &&
1673 	       (termios->c_cflag & CSIZE) != CS8) {
1674 		termios->c_cflag &= ~CSIZE;
1675 		termios->c_cflag |= old_csize;
1676 		old_csize = CS8;
1677 	}
1678 
1679 	del_timer_sync(&sport->timer);
1680 
1681 	/*
1682 	 * Ask the core to calculate the divisor for us.
1683 	 */
1684 	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1685 	quot = uart_get_divisor(port, baud);
1686 
1687 	spin_lock_irqsave(&sport->port.lock, flags);
1688 
1689 	/*
1690 	 * Read current UCR2 and save it for future use, then clear all the bits
1691 	 * except those we will or may need to preserve.
1692 	 */
1693 	old_ucr2 = imx_uart_readl(sport, UCR2);
1694 	ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1695 
1696 	ucr2 |= UCR2_SRST | UCR2_IRTS;
1697 	if ((termios->c_cflag & CSIZE) == CS8)
1698 		ucr2 |= UCR2_WS;
1699 
1700 	if (!sport->have_rtscts)
1701 		termios->c_cflag &= ~CRTSCTS;
1702 
1703 	if (port->rs485.flags & SER_RS485_ENABLED) {
1704 		/*
1705 		 * RTS is mandatory for rs485 operation, so keep
1706 		 * it under manual control and keep transmitter
1707 		 * disabled.
1708 		 */
1709 		if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1710 			imx_uart_rts_active(sport, &ucr2);
1711 		else
1712 			imx_uart_rts_inactive(sport, &ucr2);
1713 
1714 	} else if (termios->c_cflag & CRTSCTS) {
1715 		/*
1716 		 * Only let receiver control RTS output if we were not requested
1717 		 * to have RTS inactive (which then should take precedence).
1718 		 */
1719 		if (ucr2 & UCR2_CTS)
1720 			ucr2 |= UCR2_CTSC;
1721 	}
1722 
1723 	if (termios->c_cflag & CRTSCTS)
1724 		ucr2 &= ~UCR2_IRTS;
1725 	if (termios->c_cflag & CSTOPB)
1726 		ucr2 |= UCR2_STPB;
1727 	if (termios->c_cflag & PARENB) {
1728 		ucr2 |= UCR2_PREN;
1729 		if (termios->c_cflag & PARODD)
1730 			ucr2 |= UCR2_PROE;
1731 	}
1732 
1733 	sport->port.read_status_mask = 0;
1734 	if (termios->c_iflag & INPCK)
1735 		sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1736 	if (termios->c_iflag & (BRKINT | PARMRK))
1737 		sport->port.read_status_mask |= URXD_BRK;
1738 
1739 	/*
1740 	 * Characters to ignore
1741 	 */
1742 	sport->port.ignore_status_mask = 0;
1743 	if (termios->c_iflag & IGNPAR)
1744 		sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1745 	if (termios->c_iflag & IGNBRK) {
1746 		sport->port.ignore_status_mask |= URXD_BRK;
1747 		/*
1748 		 * If we're ignoring parity and break indicators,
1749 		 * ignore overruns too (for real raw support).
1750 		 */
1751 		if (termios->c_iflag & IGNPAR)
1752 			sport->port.ignore_status_mask |= URXD_OVRRUN;
1753 	}
1754 
1755 	if ((termios->c_cflag & CREAD) == 0)
1756 		sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1757 
1758 	/*
1759 	 * Update the per-port timeout.
1760 	 */
1761 	uart_update_timeout(port, termios->c_cflag, baud);
1762 
1763 	/* custom-baudrate handling */
1764 	div = sport->port.uartclk / (baud * 16);
1765 	if (baud == 38400 && quot != div)
1766 		baud = sport->port.uartclk / (quot * 16);
1767 
1768 	div = sport->port.uartclk / (baud * 16);
1769 	if (div > 7)
1770 		div = 7;
1771 	if (!div)
1772 		div = 1;
1773 
1774 	rational_best_approximation(16 * div * baud, sport->port.uartclk,
1775 		1 << 16, 1 << 16, &num, &denom);
1776 
1777 	tdiv64 = sport->port.uartclk;
1778 	tdiv64 *= num;
1779 	do_div(tdiv64, denom * 16 * div);
1780 	tty_termios_encode_baud_rate(termios,
1781 				(speed_t)tdiv64, (speed_t)tdiv64);
1782 
1783 	num -= 1;
1784 	denom -= 1;
1785 
1786 	ufcr = imx_uart_readl(sport, UFCR);
1787 	ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1788 	imx_uart_writel(sport, ufcr, UFCR);
1789 
1790 	/*
1791 	 *  Two registers below should always be written both and in this
1792 	 *  particular order. One consequence is that we need to check if any of
1793 	 *  them changes and then update both. We do need the check for change
1794 	 *  as even writing the same values seem to "restart"
1795 	 *  transmission/receiving logic in the hardware, that leads to data
1796 	 *  breakage even when rate doesn't in fact change. E.g., user switches
1797 	 *  RTS/CTS handshake and suddenly gets broken bytes.
1798 	 */
1799 	old_ubir = imx_uart_readl(sport, UBIR);
1800 	old_ubmr = imx_uart_readl(sport, UBMR);
1801 	if (old_ubir != num || old_ubmr != denom) {
1802 		imx_uart_writel(sport, num, UBIR);
1803 		imx_uart_writel(sport, denom, UBMR);
1804 	}
1805 
1806 	if (!imx_uart_is_imx1(sport))
1807 		imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1808 				IMX21_ONEMS);
1809 
1810 	imx_uart_writel(sport, ucr2, UCR2);
1811 
1812 	if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1813 		imx_uart_enable_ms(&sport->port);
1814 
1815 	spin_unlock_irqrestore(&sport->port.lock, flags);
1816 }
1817 
1818 static const char *imx_uart_type(struct uart_port *port)
1819 {
1820 	return port->type == PORT_IMX ? "IMX" : NULL;
1821 }
1822 
1823 /*
1824  * Configure/autoconfigure the port.
1825  */
1826 static void imx_uart_config_port(struct uart_port *port, int flags)
1827 {
1828 	if (flags & UART_CONFIG_TYPE)
1829 		port->type = PORT_IMX;
1830 }
1831 
1832 /*
1833  * Verify the new serial_struct (for TIOCSSERIAL).
1834  * The only change we allow are to the flags and type, and
1835  * even then only between PORT_IMX and PORT_UNKNOWN
1836  */
1837 static int
1838 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1839 {
1840 	int ret = 0;
1841 
1842 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1843 		ret = -EINVAL;
1844 	if (port->irq != ser->irq)
1845 		ret = -EINVAL;
1846 	if (ser->io_type != UPIO_MEM)
1847 		ret = -EINVAL;
1848 	if (port->uartclk / 16 != ser->baud_base)
1849 		ret = -EINVAL;
1850 	if (port->mapbase != (unsigned long)ser->iomem_base)
1851 		ret = -EINVAL;
1852 	if (port->iobase != ser->port)
1853 		ret = -EINVAL;
1854 	if (ser->hub6 != 0)
1855 		ret = -EINVAL;
1856 	return ret;
1857 }
1858 
1859 #if defined(CONFIG_CONSOLE_POLL)
1860 
1861 static int imx_uart_poll_init(struct uart_port *port)
1862 {
1863 	struct imx_port *sport = (struct imx_port *)port;
1864 	unsigned long flags;
1865 	u32 ucr1, ucr2;
1866 	int retval;
1867 
1868 	retval = clk_prepare_enable(sport->clk_ipg);
1869 	if (retval)
1870 		return retval;
1871 	retval = clk_prepare_enable(sport->clk_per);
1872 	if (retval)
1873 		clk_disable_unprepare(sport->clk_ipg);
1874 
1875 	imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1876 
1877 	spin_lock_irqsave(&sport->port.lock, flags);
1878 
1879 	/*
1880 	 * Be careful about the order of enabling bits here. First enable the
1881 	 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1882 	 * This prevents that a character that already sits in the RX fifo is
1883 	 * triggering an irq but the try to fetch it from there results in an
1884 	 * exception because UARTEN or RXEN is still off.
1885 	 */
1886 	ucr1 = imx_uart_readl(sport, UCR1);
1887 	ucr2 = imx_uart_readl(sport, UCR2);
1888 
1889 	if (imx_uart_is_imx1(sport))
1890 		ucr1 |= IMX1_UCR1_UARTCLKEN;
1891 
1892 	ucr1 |= UCR1_UARTEN;
1893 	ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1894 
1895 	ucr2 |= UCR2_RXEN | UCR2_TXEN;
1896 	ucr2 &= ~UCR2_ATEN;
1897 
1898 	imx_uart_writel(sport, ucr1, UCR1);
1899 	imx_uart_writel(sport, ucr2, UCR2);
1900 
1901 	/* now enable irqs */
1902 	imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1903 	imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1904 
1905 	spin_unlock_irqrestore(&sport->port.lock, flags);
1906 
1907 	return 0;
1908 }
1909 
1910 static int imx_uart_poll_get_char(struct uart_port *port)
1911 {
1912 	struct imx_port *sport = (struct imx_port *)port;
1913 	if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1914 		return NO_POLL_CHAR;
1915 
1916 	return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1917 }
1918 
1919 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1920 {
1921 	struct imx_port *sport = (struct imx_port *)port;
1922 	unsigned int status;
1923 
1924 	/* drain */
1925 	do {
1926 		status = imx_uart_readl(sport, USR1);
1927 	} while (~status & USR1_TRDY);
1928 
1929 	/* write */
1930 	imx_uart_writel(sport, c, URTX0);
1931 
1932 	/* flush */
1933 	do {
1934 		status = imx_uart_readl(sport, USR2);
1935 	} while (~status & USR2_TXDC);
1936 }
1937 #endif
1938 
1939 /* called with port.lock taken and irqs off or from .probe without locking */
1940 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1941 				 struct serial_rs485 *rs485conf)
1942 {
1943 	struct imx_port *sport = (struct imx_port *)port;
1944 	u32 ucr2, ufcr;
1945 
1946 	if (rs485conf->flags & SER_RS485_ENABLED) {
1947 		/* Enable receiver if low-active RTS signal is requested */
1948 		if (sport->have_rtscts &&  !sport->have_rtsgpio &&
1949 		    !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1950 			rs485conf->flags |= SER_RS485_RX_DURING_TX;
1951 
1952 		/* disable transmitter */
1953 		ucr2 = imx_uart_readl(sport, UCR2);
1954 		if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1955 			imx_uart_rts_active(sport, &ucr2);
1956 		else
1957 			imx_uart_rts_inactive(sport, &ucr2);
1958 		imx_uart_writel(sport, ucr2, UCR2);
1959 	}
1960 
1961 	/* Make sure Rx is enabled in case Tx is active with Rx disabled */
1962 	if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1963 	    rs485conf->flags & SER_RS485_RX_DURING_TX) {
1964 		/* If the receiver trigger is 0, set it to a default value */
1965 		ufcr = imx_uart_readl(sport, UFCR);
1966 		if ((ufcr & UFCR_RXTL_MASK) == 0)
1967 			imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1968 		imx_uart_start_rx(port);
1969 	}
1970 
1971 	return 0;
1972 }
1973 
1974 static const struct uart_ops imx_uart_pops = {
1975 	.tx_empty	= imx_uart_tx_empty,
1976 	.set_mctrl	= imx_uart_set_mctrl,
1977 	.get_mctrl	= imx_uart_get_mctrl,
1978 	.stop_tx	= imx_uart_stop_tx,
1979 	.start_tx	= imx_uart_start_tx,
1980 	.stop_rx	= imx_uart_stop_rx,
1981 	.enable_ms	= imx_uart_enable_ms,
1982 	.break_ctl	= imx_uart_break_ctl,
1983 	.startup	= imx_uart_startup,
1984 	.shutdown	= imx_uart_shutdown,
1985 	.flush_buffer	= imx_uart_flush_buffer,
1986 	.set_termios	= imx_uart_set_termios,
1987 	.type		= imx_uart_type,
1988 	.config_port	= imx_uart_config_port,
1989 	.verify_port	= imx_uart_verify_port,
1990 #if defined(CONFIG_CONSOLE_POLL)
1991 	.poll_init      = imx_uart_poll_init,
1992 	.poll_get_char  = imx_uart_poll_get_char,
1993 	.poll_put_char  = imx_uart_poll_put_char,
1994 #endif
1995 };
1996 
1997 static struct imx_port *imx_uart_ports[UART_NR];
1998 
1999 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
2000 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
2001 {
2002 	struct imx_port *sport = (struct imx_port *)port;
2003 
2004 	while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
2005 		barrier();
2006 
2007 	imx_uart_writel(sport, ch, URTX0);
2008 }
2009 
2010 /*
2011  * Interrupts are disabled on entering
2012  */
2013 static void
2014 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2015 {
2016 	struct imx_port *sport = imx_uart_ports[co->index];
2017 	struct imx_port_ucrs old_ucr;
2018 	unsigned long flags;
2019 	unsigned int ucr1, usr2;
2020 	int locked = 1;
2021 
2022 	if (sport->port.sysrq)
2023 		locked = 0;
2024 	else if (oops_in_progress)
2025 		locked = spin_trylock_irqsave(&sport->port.lock, flags);
2026 	else
2027 		spin_lock_irqsave(&sport->port.lock, flags);
2028 
2029 	/*
2030 	 *	First, save UCR1/2/3 and then disable interrupts
2031 	 */
2032 	imx_uart_ucrs_save(sport, &old_ucr);
2033 	ucr1 = old_ucr.ucr1;
2034 
2035 	if (imx_uart_is_imx1(sport))
2036 		ucr1 |= IMX1_UCR1_UARTCLKEN;
2037 	ucr1 |= UCR1_UARTEN;
2038 	ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2039 
2040 	imx_uart_writel(sport, ucr1, UCR1);
2041 
2042 	imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2043 
2044 	uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2045 
2046 	/*
2047 	 *	Finally, wait for transmitter to become empty
2048 	 *	and restore UCR1/2/3
2049 	 */
2050 	read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2051 				 0, USEC_PER_SEC, false, sport, USR2);
2052 	imx_uart_ucrs_restore(sport, &old_ucr);
2053 
2054 	if (locked)
2055 		spin_unlock_irqrestore(&sport->port.lock, flags);
2056 }
2057 
2058 /*
2059  * If the port was already initialised (eg, by a boot loader),
2060  * try to determine the current setup.
2061  */
2062 static void
2063 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2064 			     int *parity, int *bits)
2065 {
2066 
2067 	if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2068 		/* ok, the port was enabled */
2069 		unsigned int ucr2, ubir, ubmr, uartclk;
2070 		unsigned int baud_raw;
2071 		unsigned int ucfr_rfdiv;
2072 
2073 		ucr2 = imx_uart_readl(sport, UCR2);
2074 
2075 		*parity = 'n';
2076 		if (ucr2 & UCR2_PREN) {
2077 			if (ucr2 & UCR2_PROE)
2078 				*parity = 'o';
2079 			else
2080 				*parity = 'e';
2081 		}
2082 
2083 		if (ucr2 & UCR2_WS)
2084 			*bits = 8;
2085 		else
2086 			*bits = 7;
2087 
2088 		ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2089 		ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2090 
2091 		ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2092 		if (ucfr_rfdiv == 6)
2093 			ucfr_rfdiv = 7;
2094 		else
2095 			ucfr_rfdiv = 6 - ucfr_rfdiv;
2096 
2097 		uartclk = clk_get_rate(sport->clk_per);
2098 		uartclk /= ucfr_rfdiv;
2099 
2100 		{	/*
2101 			 * The next code provides exact computation of
2102 			 *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2103 			 * without need of float support or long long division,
2104 			 * which would be required to prevent 32bit arithmetic overflow
2105 			 */
2106 			unsigned int mul = ubir + 1;
2107 			unsigned int div = 16 * (ubmr + 1);
2108 			unsigned int rem = uartclk % div;
2109 
2110 			baud_raw = (uartclk / div) * mul;
2111 			baud_raw += (rem * mul + div / 2) / div;
2112 			*baud = (baud_raw + 50) / 100 * 100;
2113 		}
2114 
2115 		if (*baud != baud_raw)
2116 			dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2117 				baud_raw, *baud);
2118 	}
2119 }
2120 
2121 static int
2122 imx_uart_console_setup(struct console *co, char *options)
2123 {
2124 	struct imx_port *sport;
2125 	int baud = 9600;
2126 	int bits = 8;
2127 	int parity = 'n';
2128 	int flow = 'n';
2129 	int retval;
2130 
2131 	/*
2132 	 * Check whether an invalid uart number has been specified, and
2133 	 * if so, search for the first available port that does have
2134 	 * console support.
2135 	 */
2136 	if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2137 		co->index = 0;
2138 	sport = imx_uart_ports[co->index];
2139 	if (sport == NULL)
2140 		return -ENODEV;
2141 
2142 	/* For setting the registers, we only need to enable the ipg clock. */
2143 	retval = clk_prepare_enable(sport->clk_ipg);
2144 	if (retval)
2145 		goto error_console;
2146 
2147 	if (options)
2148 		uart_parse_options(options, &baud, &parity, &bits, &flow);
2149 	else
2150 		imx_uart_console_get_options(sport, &baud, &parity, &bits);
2151 
2152 	imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2153 
2154 	retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2155 
2156 	if (retval) {
2157 		clk_disable_unprepare(sport->clk_ipg);
2158 		goto error_console;
2159 	}
2160 
2161 	retval = clk_prepare_enable(sport->clk_per);
2162 	if (retval)
2163 		clk_disable_unprepare(sport->clk_ipg);
2164 
2165 error_console:
2166 	return retval;
2167 }
2168 
2169 static int
2170 imx_uart_console_exit(struct console *co)
2171 {
2172 	struct imx_port *sport = imx_uart_ports[co->index];
2173 
2174 	clk_disable_unprepare(sport->clk_per);
2175 	clk_disable_unprepare(sport->clk_ipg);
2176 
2177 	return 0;
2178 }
2179 
2180 static struct uart_driver imx_uart_uart_driver;
2181 static struct console imx_uart_console = {
2182 	.name		= DEV_NAME,
2183 	.write		= imx_uart_console_write,
2184 	.device		= uart_console_device,
2185 	.setup		= imx_uart_console_setup,
2186 	.exit		= imx_uart_console_exit,
2187 	.flags		= CON_PRINTBUFFER,
2188 	.index		= -1,
2189 	.data		= &imx_uart_uart_driver,
2190 };
2191 
2192 #define IMX_CONSOLE	&imx_uart_console
2193 
2194 #else
2195 #define IMX_CONSOLE	NULL
2196 #endif
2197 
2198 static struct uart_driver imx_uart_uart_driver = {
2199 	.owner          = THIS_MODULE,
2200 	.driver_name    = DRIVER_NAME,
2201 	.dev_name       = DEV_NAME,
2202 	.major          = SERIAL_IMX_MAJOR,
2203 	.minor          = MINOR_START,
2204 	.nr             = ARRAY_SIZE(imx_uart_ports),
2205 	.cons           = IMX_CONSOLE,
2206 };
2207 
2208 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2209 {
2210 	struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2211 	unsigned long flags;
2212 
2213 	spin_lock_irqsave(&sport->port.lock, flags);
2214 	if (sport->tx_state == WAIT_AFTER_RTS)
2215 		imx_uart_start_tx(&sport->port);
2216 	spin_unlock_irqrestore(&sport->port.lock, flags);
2217 
2218 	return HRTIMER_NORESTART;
2219 }
2220 
2221 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2222 {
2223 	struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2224 	unsigned long flags;
2225 
2226 	spin_lock_irqsave(&sport->port.lock, flags);
2227 	if (sport->tx_state == WAIT_AFTER_SEND)
2228 		imx_uart_stop_tx(&sport->port);
2229 	spin_unlock_irqrestore(&sport->port.lock, flags);
2230 
2231 	return HRTIMER_NORESTART;
2232 }
2233 
2234 static const struct serial_rs485 imx_rs485_supported = {
2235 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2236 		 SER_RS485_RX_DURING_TX,
2237 	.delay_rts_before_send = 1,
2238 	.delay_rts_after_send = 1,
2239 };
2240 
2241 /* Default RX DMA buffer configuration */
2242 #define RX_DMA_PERIODS		16
2243 #define RX_DMA_PERIOD_LEN	(PAGE_SIZE / 4)
2244 
2245 static int imx_uart_probe(struct platform_device *pdev)
2246 {
2247 	struct device_node *np = pdev->dev.of_node;
2248 	struct imx_port *sport;
2249 	void __iomem *base;
2250 	u32 dma_buf_conf[2];
2251 	int ret = 0;
2252 	u32 ucr1, ucr2, uts;
2253 	struct resource *res;
2254 	int txirq, rxirq, rtsirq;
2255 
2256 	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2257 	if (!sport)
2258 		return -ENOMEM;
2259 
2260 	sport->devdata = of_device_get_match_data(&pdev->dev);
2261 
2262 	ret = of_alias_get_id(np, "serial");
2263 	if (ret < 0) {
2264 		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2265 		return ret;
2266 	}
2267 	sport->port.line = ret;
2268 
2269 	sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2270 		of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2271 
2272 	sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2273 
2274 	sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2275 
2276 	sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2277 
2278 	sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2279 
2280 	if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2281 		sport->rx_period_length = dma_buf_conf[0];
2282 		sport->rx_periods = dma_buf_conf[1];
2283 	} else {
2284 		sport->rx_period_length = RX_DMA_PERIOD_LEN;
2285 		sport->rx_periods = RX_DMA_PERIODS;
2286 	}
2287 
2288 	if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2289 		dev_err(&pdev->dev, "serial%d out of range\n",
2290 			sport->port.line);
2291 		return -EINVAL;
2292 	}
2293 
2294 	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2295 	if (IS_ERR(base))
2296 		return PTR_ERR(base);
2297 
2298 	rxirq = platform_get_irq(pdev, 0);
2299 	if (rxirq < 0)
2300 		return rxirq;
2301 	txirq = platform_get_irq_optional(pdev, 1);
2302 	rtsirq = platform_get_irq_optional(pdev, 2);
2303 
2304 	sport->port.dev = &pdev->dev;
2305 	sport->port.mapbase = res->start;
2306 	sport->port.membase = base;
2307 	sport->port.type = PORT_IMX;
2308 	sport->port.iotype = UPIO_MEM;
2309 	sport->port.irq = rxirq;
2310 	sport->port.fifosize = 32;
2311 	sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2312 	sport->port.ops = &imx_uart_pops;
2313 	sport->port.rs485_config = imx_uart_rs485_config;
2314 	/* RTS is required to control the RS485 transmitter */
2315 	if (sport->have_rtscts || sport->have_rtsgpio)
2316 		sport->port.rs485_supported = imx_rs485_supported;
2317 	sport->port.flags = UPF_BOOT_AUTOCONF;
2318 	timer_setup(&sport->timer, imx_uart_timeout, 0);
2319 
2320 	sport->gpios = mctrl_gpio_init(&sport->port, 0);
2321 	if (IS_ERR(sport->gpios))
2322 		return PTR_ERR(sport->gpios);
2323 
2324 	sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2325 	if (IS_ERR(sport->clk_ipg)) {
2326 		ret = PTR_ERR(sport->clk_ipg);
2327 		dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2328 		return ret;
2329 	}
2330 
2331 	sport->clk_per = devm_clk_get(&pdev->dev, "per");
2332 	if (IS_ERR(sport->clk_per)) {
2333 		ret = PTR_ERR(sport->clk_per);
2334 		dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2335 		return ret;
2336 	}
2337 
2338 	sport->port.uartclk = clk_get_rate(sport->clk_per);
2339 
2340 	/* For register access, we only need to enable the ipg clock. */
2341 	ret = clk_prepare_enable(sport->clk_ipg);
2342 	if (ret) {
2343 		dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2344 		return ret;
2345 	}
2346 
2347 	ret = uart_get_rs485_mode(&sport->port);
2348 	if (ret)
2349 		goto err_clk;
2350 
2351 	/*
2352 	 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2353 	 * signal cannot be set low during transmission in case the
2354 	 * receiver is off (limitation of the i.MX UART IP).
2355 	 */
2356 	if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2357 	    sport->have_rtscts && !sport->have_rtsgpio &&
2358 	    (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2359 	     !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2360 		dev_err(&pdev->dev,
2361 			"low-active RTS not possible when receiver is off, enabling receiver\n");
2362 
2363 	/* Disable interrupts before requesting them */
2364 	ucr1 = imx_uart_readl(sport, UCR1);
2365 	ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2366 	imx_uart_writel(sport, ucr1, UCR1);
2367 
2368 	/* Disable Ageing Timer interrupt */
2369 	ucr2 = imx_uart_readl(sport, UCR2);
2370 	ucr2 &= ~UCR2_ATEN;
2371 	imx_uart_writel(sport, ucr2, UCR2);
2372 
2373 	/*
2374 	 * In case RS485 is enabled without GPIO RTS control, the UART IP
2375 	 * is used to control CTS signal. Keep both the UART and Receiver
2376 	 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2377 	 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2378 	 * data from being fed into the RX FIFO, enable loopback mode in
2379 	 * UTS register, which disconnects the RX path from external RXD
2380 	 * pin and connects it to the Transceiver, which is disabled, so
2381 	 * no data can be fed to the RX FIFO that way.
2382 	 */
2383 	if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2384 	    sport->have_rtscts && !sport->have_rtsgpio) {
2385 		uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2386 		uts |= UTS_LOOP;
2387 		imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2388 
2389 		ucr1 = imx_uart_readl(sport, UCR1);
2390 		ucr1 |= UCR1_UARTEN;
2391 		imx_uart_writel(sport, ucr1, UCR1);
2392 
2393 		ucr2 = imx_uart_readl(sport, UCR2);
2394 		ucr2 |= UCR2_RXEN;
2395 		imx_uart_writel(sport, ucr2, UCR2);
2396 	}
2397 
2398 	if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2399 		/*
2400 		 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2401 		 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2402 		 * and DCD (when they are outputs) or enables the respective
2403 		 * irqs. So set this bit early, i.e. before requesting irqs.
2404 		 */
2405 		u32 ufcr = imx_uart_readl(sport, UFCR);
2406 		if (!(ufcr & UFCR_DCEDTE))
2407 			imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2408 
2409 		/*
2410 		 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2411 		 * enabled later because they cannot be cleared
2412 		 * (confirmed on i.MX25) which makes them unusable.
2413 		 */
2414 		imx_uart_writel(sport,
2415 				IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2416 				UCR3);
2417 
2418 	} else {
2419 		u32 ucr3 = UCR3_DSR;
2420 		u32 ufcr = imx_uart_readl(sport, UFCR);
2421 		if (ufcr & UFCR_DCEDTE)
2422 			imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2423 
2424 		if (!imx_uart_is_imx1(sport))
2425 			ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2426 		imx_uart_writel(sport, ucr3, UCR3);
2427 	}
2428 
2429 	hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2430 	hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2431 	sport->trigger_start_tx.function = imx_trigger_start_tx;
2432 	sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2433 
2434 	/*
2435 	 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2436 	 * chips only have one interrupt.
2437 	 */
2438 	if (txirq > 0) {
2439 		ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2440 				       dev_name(&pdev->dev), sport);
2441 		if (ret) {
2442 			dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2443 				ret);
2444 			goto err_clk;
2445 		}
2446 
2447 		ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2448 				       dev_name(&pdev->dev), sport);
2449 		if (ret) {
2450 			dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2451 				ret);
2452 			goto err_clk;
2453 		}
2454 
2455 		ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2456 				       dev_name(&pdev->dev), sport);
2457 		if (ret) {
2458 			dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2459 				ret);
2460 			goto err_clk;
2461 		}
2462 	} else {
2463 		ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2464 				       dev_name(&pdev->dev), sport);
2465 		if (ret) {
2466 			dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2467 			goto err_clk;
2468 		}
2469 	}
2470 
2471 	imx_uart_ports[sport->port.line] = sport;
2472 
2473 	platform_set_drvdata(pdev, sport);
2474 
2475 	ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2476 
2477 err_clk:
2478 	clk_disable_unprepare(sport->clk_ipg);
2479 
2480 	return ret;
2481 }
2482 
2483 static int imx_uart_remove(struct platform_device *pdev)
2484 {
2485 	struct imx_port *sport = platform_get_drvdata(pdev);
2486 
2487 	uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2488 
2489 	return 0;
2490 }
2491 
2492 static void imx_uart_restore_context(struct imx_port *sport)
2493 {
2494 	unsigned long flags;
2495 
2496 	spin_lock_irqsave(&sport->port.lock, flags);
2497 	if (!sport->context_saved) {
2498 		spin_unlock_irqrestore(&sport->port.lock, flags);
2499 		return;
2500 	}
2501 
2502 	imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2503 	imx_uart_writel(sport, sport->saved_reg[5], UESC);
2504 	imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2505 	imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2506 	imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2507 	imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2508 	imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2509 	imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2510 	imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2511 	imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2512 	sport->context_saved = false;
2513 	spin_unlock_irqrestore(&sport->port.lock, flags);
2514 }
2515 
2516 static void imx_uart_save_context(struct imx_port *sport)
2517 {
2518 	unsigned long flags;
2519 
2520 	/* Save necessary regs */
2521 	spin_lock_irqsave(&sport->port.lock, flags);
2522 	sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2523 	sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2524 	sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2525 	sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2526 	sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2527 	sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2528 	sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2529 	sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2530 	sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2531 	sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2532 	sport->context_saved = true;
2533 	spin_unlock_irqrestore(&sport->port.lock, flags);
2534 }
2535 
2536 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2537 {
2538 	u32 ucr3;
2539 
2540 	ucr3 = imx_uart_readl(sport, UCR3);
2541 	if (on) {
2542 		imx_uart_writel(sport, USR1_AWAKE, USR1);
2543 		ucr3 |= UCR3_AWAKEN;
2544 	} else {
2545 		ucr3 &= ~UCR3_AWAKEN;
2546 	}
2547 	imx_uart_writel(sport, ucr3, UCR3);
2548 
2549 	if (sport->have_rtscts) {
2550 		u32 ucr1 = imx_uart_readl(sport, UCR1);
2551 		if (on) {
2552 			imx_uart_writel(sport, USR1_RTSD, USR1);
2553 			ucr1 |= UCR1_RTSDEN;
2554 		} else {
2555 			ucr1 &= ~UCR1_RTSDEN;
2556 		}
2557 		imx_uart_writel(sport, ucr1, UCR1);
2558 	}
2559 }
2560 
2561 static int imx_uart_suspend_noirq(struct device *dev)
2562 {
2563 	struct imx_port *sport = dev_get_drvdata(dev);
2564 
2565 	imx_uart_save_context(sport);
2566 
2567 	clk_disable(sport->clk_ipg);
2568 
2569 	pinctrl_pm_select_sleep_state(dev);
2570 
2571 	return 0;
2572 }
2573 
2574 static int imx_uart_resume_noirq(struct device *dev)
2575 {
2576 	struct imx_port *sport = dev_get_drvdata(dev);
2577 	int ret;
2578 
2579 	pinctrl_pm_select_default_state(dev);
2580 
2581 	ret = clk_enable(sport->clk_ipg);
2582 	if (ret)
2583 		return ret;
2584 
2585 	imx_uart_restore_context(sport);
2586 
2587 	return 0;
2588 }
2589 
2590 static int imx_uart_suspend(struct device *dev)
2591 {
2592 	struct imx_port *sport = dev_get_drvdata(dev);
2593 	int ret;
2594 
2595 	uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2596 	disable_irq(sport->port.irq);
2597 
2598 	ret = clk_prepare_enable(sport->clk_ipg);
2599 	if (ret)
2600 		return ret;
2601 
2602 	/* enable wakeup from i.MX UART */
2603 	imx_uart_enable_wakeup(sport, true);
2604 
2605 	return 0;
2606 }
2607 
2608 static int imx_uart_resume(struct device *dev)
2609 {
2610 	struct imx_port *sport = dev_get_drvdata(dev);
2611 
2612 	/* disable wakeup from i.MX UART */
2613 	imx_uart_enable_wakeup(sport, false);
2614 
2615 	uart_resume_port(&imx_uart_uart_driver, &sport->port);
2616 	enable_irq(sport->port.irq);
2617 
2618 	clk_disable_unprepare(sport->clk_ipg);
2619 
2620 	return 0;
2621 }
2622 
2623 static int imx_uart_freeze(struct device *dev)
2624 {
2625 	struct imx_port *sport = dev_get_drvdata(dev);
2626 
2627 	uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2628 
2629 	return clk_prepare_enable(sport->clk_ipg);
2630 }
2631 
2632 static int imx_uart_thaw(struct device *dev)
2633 {
2634 	struct imx_port *sport = dev_get_drvdata(dev);
2635 
2636 	uart_resume_port(&imx_uart_uart_driver, &sport->port);
2637 
2638 	clk_disable_unprepare(sport->clk_ipg);
2639 
2640 	return 0;
2641 }
2642 
2643 static const struct dev_pm_ops imx_uart_pm_ops = {
2644 	.suspend_noirq = imx_uart_suspend_noirq,
2645 	.resume_noirq = imx_uart_resume_noirq,
2646 	.freeze_noirq = imx_uart_suspend_noirq,
2647 	.thaw_noirq = imx_uart_resume_noirq,
2648 	.restore_noirq = imx_uart_resume_noirq,
2649 	.suspend = imx_uart_suspend,
2650 	.resume = imx_uart_resume,
2651 	.freeze = imx_uart_freeze,
2652 	.thaw = imx_uart_thaw,
2653 	.restore = imx_uart_thaw,
2654 };
2655 
2656 static struct platform_driver imx_uart_platform_driver = {
2657 	.probe = imx_uart_probe,
2658 	.remove = imx_uart_remove,
2659 
2660 	.driver = {
2661 		.name = "imx-uart",
2662 		.of_match_table = imx_uart_dt_ids,
2663 		.pm = &imx_uart_pm_ops,
2664 	},
2665 };
2666 
2667 static int __init imx_uart_init(void)
2668 {
2669 	int ret = uart_register_driver(&imx_uart_uart_driver);
2670 
2671 	if (ret)
2672 		return ret;
2673 
2674 	ret = platform_driver_register(&imx_uart_platform_driver);
2675 	if (ret != 0)
2676 		uart_unregister_driver(&imx_uart_uart_driver);
2677 
2678 	return ret;
2679 }
2680 
2681 static void __exit imx_uart_exit(void)
2682 {
2683 	platform_driver_unregister(&imx_uart_platform_driver);
2684 	uart_unregister_driver(&imx_uart_uart_driver);
2685 }
2686 
2687 module_init(imx_uart_init);
2688 module_exit(imx_uart_exit);
2689 
2690 MODULE_AUTHOR("Sascha Hauer");
2691 MODULE_DESCRIPTION("IMX generic serial port driver");
2692 MODULE_LICENSE("GPL");
2693 MODULE_ALIAS("platform:imx-uart");
2694