1ab4382d2SGreg Kroah-Hartman /* 2f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 7ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 8ab4382d2SGreg Kroah-Hartman * 9ab4382d2SGreg Kroah-Hartman * Author: Fabian Godehardt (added IrDA support for iMX) 10f890cef2SUwe Kleine-König * Copyright (C) 2009 emlix GmbH 11ab4382d2SGreg Kroah-Hartman * 12ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 13ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 14ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2 of the License, or 15ab4382d2SGreg Kroah-Hartman * (at your option) any later version. 16ab4382d2SGreg Kroah-Hartman * 17ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 18ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY; without even the implied warranty of 19ab4382d2SGreg Kroah-Hartman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20ab4382d2SGreg Kroah-Hartman * GNU General Public License for more details. 21ab4382d2SGreg Kroah-Hartman */ 22ab4382d2SGreg Kroah-Hartman 23ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 25ab4382d2SGreg Kroah-Hartman #endif 26ab4382d2SGreg Kroah-Hartman 27ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 29ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 30ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 31ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 32ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 33ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 34ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 35ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 36ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 37ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 38ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 39ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 40ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 4122698aa2SShawn Guo #include <linux/of.h> 4222698aa2SShawn Guo #include <linux/of_device.h> 43e32a9f8fSSachin Kamat #include <linux/io.h> 44b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 45ab4382d2SGreg Kroah-Hartman 46ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 4782906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 48b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 49ab4382d2SGreg Kroah-Hartman 50ab4382d2SGreg Kroah-Hartman /* Register definitions */ 51ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 52ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 53ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 54ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 55ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 56ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 57ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 58ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 59ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 60ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 61ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 62ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 63ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 64ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 65fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 66fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 67fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 68ab4382d2SGreg Kroah-Hartman 69ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 7055d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 71ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 72ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 73ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 74ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 75ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 76ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 7726c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 7825985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 81ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 82b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 84ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 88ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 89ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 90fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 91b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 93ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 98ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 101ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 102ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 103ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 10401f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 105ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 106ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 107ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 112ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 113ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 114b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 115ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 118fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 119ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 120ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 124ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 125ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 126ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 127b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 128ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 129ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 130ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 131ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 132ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 133ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1347be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 135ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 136ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 137ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 138ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 140ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 141ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 142ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 143ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 145ab4382d2SGreg Kroah-Hartman #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 146ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 147ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 150ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 151ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 152ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 153ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 154ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 155ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 156ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 157ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 158ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 159ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 160ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 161ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 162ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 163ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 164ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 165ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 166ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 167ab4382d2SGreg Kroah-Hartman 168ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 169ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 170ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 171ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 172ab4382d2SGreg Kroah-Hartman 173ab4382d2SGreg Kroah-Hartman /* 174ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 175ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 176ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 177ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 178ab4382d2SGreg Kroah-Hartman */ 179ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 180ab4382d2SGreg Kroah-Hartman 181ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 182ab4382d2SGreg Kroah-Hartman 183ab4382d2SGreg Kroah-Hartman #define UART_NR 8 184ab4382d2SGreg Kroah-Hartman 185fe6b540aSShawn Guo /* i.mx21 type uart runs on all i.mx except i.mx1 */ 186fe6b540aSShawn Guo enum imx_uart_type { 187fe6b540aSShawn Guo IMX1_UART, 188fe6b540aSShawn Guo IMX21_UART, 189a496e628SHuang Shijie IMX6Q_UART, 190fe6b540aSShawn Guo }; 191fe6b540aSShawn Guo 192fe6b540aSShawn Guo /* device type dependent stuff */ 193fe6b540aSShawn Guo struct imx_uart_data { 194fe6b540aSShawn Guo unsigned uts_reg; 195fe6b540aSShawn Guo enum imx_uart_type devtype; 196fe6b540aSShawn Guo }; 197fe6b540aSShawn Guo 198ab4382d2SGreg Kroah-Hartman struct imx_port { 199ab4382d2SGreg Kroah-Hartman struct uart_port port; 200ab4382d2SGreg Kroah-Hartman struct timer_list timer; 201ab4382d2SGreg Kroah-Hartman unsigned int old_status; 202ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 20320ff2fe6SHuang Shijie unsigned int dte_mode:1; 204ab4382d2SGreg Kroah-Hartman unsigned int use_irda:1; 205ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_rx:1; 206ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_tx:1; 207ab4382d2SGreg Kroah-Hartman unsigned short trcv_delay; /* transceiver delay */ 2083a9465faSSascha Hauer struct clk *clk_ipg; 2093a9465faSSascha Hauer struct clk *clk_per; 2107d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 211b4cdc8f6SHuang Shijie 212b4cdc8f6SHuang Shijie /* DMA fields */ 213b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 214b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 215b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 216b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 217b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 218b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 219b4cdc8f6SHuang Shijie void *rx_buf; 2207cb92fd2SHuang Shijie unsigned int tx_bytes; 221b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 2229ce4f8f3SGreg Kroah-Hartman wait_queue_head_t dma_wait; 223ab4382d2SGreg Kroah-Hartman }; 224ab4382d2SGreg Kroah-Hartman 2250ad5a814SDirk Behme struct imx_port_ucrs { 2260ad5a814SDirk Behme unsigned int ucr1; 2270ad5a814SDirk Behme unsigned int ucr2; 2280ad5a814SDirk Behme unsigned int ucr3; 2290ad5a814SDirk Behme }; 2300ad5a814SDirk Behme 231ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_IRDA 232ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) ((sport)->use_irda) 233ab4382d2SGreg Kroah-Hartman #else 234ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) (0) 235ab4382d2SGreg Kroah-Hartman #endif 236ab4382d2SGreg Kroah-Hartman 237fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 238fe6b540aSShawn Guo [IMX1_UART] = { 239fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 240fe6b540aSShawn Guo .devtype = IMX1_UART, 241fe6b540aSShawn Guo }, 242fe6b540aSShawn Guo [IMX21_UART] = { 243fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 244fe6b540aSShawn Guo .devtype = IMX21_UART, 245fe6b540aSShawn Guo }, 246a496e628SHuang Shijie [IMX6Q_UART] = { 247a496e628SHuang Shijie .uts_reg = IMX21_UTS, 248a496e628SHuang Shijie .devtype = IMX6Q_UART, 249a496e628SHuang Shijie }, 250fe6b540aSShawn Guo }; 251fe6b540aSShawn Guo 252fe6b540aSShawn Guo static struct platform_device_id imx_uart_devtype[] = { 253fe6b540aSShawn Guo { 254fe6b540aSShawn Guo .name = "imx1-uart", 255fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 256fe6b540aSShawn Guo }, { 257fe6b540aSShawn Guo .name = "imx21-uart", 258fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 259fe6b540aSShawn Guo }, { 260a496e628SHuang Shijie .name = "imx6q-uart", 261a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 262a496e628SHuang Shijie }, { 263fe6b540aSShawn Guo /* sentinel */ 264fe6b540aSShawn Guo } 265fe6b540aSShawn Guo }; 266fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 267fe6b540aSShawn Guo 268ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 269a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 27022698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27122698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27222698aa2SShawn Guo { /* sentinel */ } 27322698aa2SShawn Guo }; 27422698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27522698aa2SShawn Guo 276fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 277fe6b540aSShawn Guo { 278fe6b540aSShawn Guo return sport->devdata->uts_reg; 279fe6b540aSShawn Guo } 280fe6b540aSShawn Guo 281fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 282fe6b540aSShawn Guo { 283fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 284fe6b540aSShawn Guo } 285fe6b540aSShawn Guo 286fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 287fe6b540aSShawn Guo { 288fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 289fe6b540aSShawn Guo } 290fe6b540aSShawn Guo 291a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 292a496e628SHuang Shijie { 293a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 294a496e628SHuang Shijie } 295ab4382d2SGreg Kroah-Hartman /* 29644a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 29744a75411Sfabio.estevam@freescale.com */ 29893d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 29944a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 30044a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30144a75411Sfabio.estevam@freescale.com { 30244a75411Sfabio.estevam@freescale.com /* save control registers */ 30344a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 30444a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 30544a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 30644a75411Sfabio.estevam@freescale.com } 30744a75411Sfabio.estevam@freescale.com 30844a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 30944a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 31044a75411Sfabio.estevam@freescale.com { 31144a75411Sfabio.estevam@freescale.com /* restore control registers */ 31244a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 31344a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 31444a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 31544a75411Sfabio.estevam@freescale.com } 316e8bfa760SFabio Estevam #endif 31744a75411Sfabio.estevam@freescale.com 31844a75411Sfabio.estevam@freescale.com /* 319ab4382d2SGreg Kroah-Hartman * Handle any change of modem status signal since we were last called. 320ab4382d2SGreg Kroah-Hartman */ 321ab4382d2SGreg Kroah-Hartman static void imx_mctrl_check(struct imx_port *sport) 322ab4382d2SGreg Kroah-Hartman { 323ab4382d2SGreg Kroah-Hartman unsigned int status, changed; 324ab4382d2SGreg Kroah-Hartman 325ab4382d2SGreg Kroah-Hartman status = sport->port.ops->get_mctrl(&sport->port); 326ab4382d2SGreg Kroah-Hartman changed = status ^ sport->old_status; 327ab4382d2SGreg Kroah-Hartman 328ab4382d2SGreg Kroah-Hartman if (changed == 0) 329ab4382d2SGreg Kroah-Hartman return; 330ab4382d2SGreg Kroah-Hartman 331ab4382d2SGreg Kroah-Hartman sport->old_status = status; 332ab4382d2SGreg Kroah-Hartman 333ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_RI) 334ab4382d2SGreg Kroah-Hartman sport->port.icount.rng++; 335ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_DSR) 336ab4382d2SGreg Kroah-Hartman sport->port.icount.dsr++; 337ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CAR) 338ab4382d2SGreg Kroah-Hartman uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 339ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CTS) 340ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 341ab4382d2SGreg Kroah-Hartman 342ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 343ab4382d2SGreg Kroah-Hartman } 344ab4382d2SGreg Kroah-Hartman 345ab4382d2SGreg Kroah-Hartman /* 346ab4382d2SGreg Kroah-Hartman * This is our per-port timeout handler, for checking the 347ab4382d2SGreg Kroah-Hartman * modem status signals. 348ab4382d2SGreg Kroah-Hartman */ 349ab4382d2SGreg Kroah-Hartman static void imx_timeout(unsigned long data) 350ab4382d2SGreg Kroah-Hartman { 351ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)data; 352ab4382d2SGreg Kroah-Hartman unsigned long flags; 353ab4382d2SGreg Kroah-Hartman 354ab4382d2SGreg Kroah-Hartman if (sport->port.state) { 355ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 356ab4382d2SGreg Kroah-Hartman imx_mctrl_check(sport); 357ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 358ab4382d2SGreg Kroah-Hartman 359ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 360ab4382d2SGreg Kroah-Hartman } 361ab4382d2SGreg Kroah-Hartman } 362ab4382d2SGreg Kroah-Hartman 363ab4382d2SGreg Kroah-Hartman /* 364ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 365ab4382d2SGreg Kroah-Hartman */ 366ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 367ab4382d2SGreg Kroah-Hartman { 368ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 369ab4382d2SGreg Kroah-Hartman unsigned long temp; 370ab4382d2SGreg Kroah-Hartman 371ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 372ab4382d2SGreg Kroah-Hartman /* half duplex - wait for end of transmission */ 373ab4382d2SGreg Kroah-Hartman int n = 256; 374ab4382d2SGreg Kroah-Hartman while ((--n > 0) && 375ab4382d2SGreg Kroah-Hartman !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 376ab4382d2SGreg Kroah-Hartman udelay(5); 377ab4382d2SGreg Kroah-Hartman barrier(); 378ab4382d2SGreg Kroah-Hartman } 379ab4382d2SGreg Kroah-Hartman /* 380ab4382d2SGreg Kroah-Hartman * irda transceiver - wait a bit more to avoid 381ab4382d2SGreg Kroah-Hartman * cutoff, hardware dependent 382ab4382d2SGreg Kroah-Hartman */ 383ab4382d2SGreg Kroah-Hartman udelay(sport->trcv_delay); 384ab4382d2SGreg Kroah-Hartman 385ab4382d2SGreg Kroah-Hartman /* 386ab4382d2SGreg Kroah-Hartman * half duplex - reactivate receive mode, 387ab4382d2SGreg Kroah-Hartman * flush receive pipe echo crap 388ab4382d2SGreg Kroah-Hartman */ 389ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR2) & USR2_TXDC) { 390ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 391ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 392ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 393ab4382d2SGreg Kroah-Hartman 394ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 395ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_TCEN); 396ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 397ab4382d2SGreg Kroah-Hartman 398ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + URXD0) & 399ab4382d2SGreg Kroah-Hartman URXD_CHARRDY) 400ab4382d2SGreg Kroah-Hartman barrier(); 401ab4382d2SGreg Kroah-Hartman 402ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 403ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN; 404ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 405ab4382d2SGreg Kroah-Hartman 406ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 407ab4382d2SGreg Kroah-Hartman temp |= UCR4_DREN; 408ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 409ab4382d2SGreg Kroah-Hartman } 410ab4382d2SGreg Kroah-Hartman return; 411ab4382d2SGreg Kroah-Hartman } 412ab4382d2SGreg Kroah-Hartman 4139ce4f8f3SGreg Kroah-Hartman /* 4149ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4159ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4169ce4f8f3SGreg Kroah-Hartman */ 4179ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 4189ce4f8f3SGreg Kroah-Hartman return; 419b4cdc8f6SHuang Shijie 420ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 421ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 422ab4382d2SGreg Kroah-Hartman } 423ab4382d2SGreg Kroah-Hartman 424ab4382d2SGreg Kroah-Hartman /* 425ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 426ab4382d2SGreg Kroah-Hartman */ 427ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 428ab4382d2SGreg Kroah-Hartman { 429ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 430ab4382d2SGreg Kroah-Hartman unsigned long temp; 431ab4382d2SGreg Kroah-Hartman 43245564a66SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) { 43345564a66SHuang Shijie if (sport->port.suspended) { 43445564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 43545564a66SHuang Shijie sport->dma_is_rxing = 0; 43645564a66SHuang Shijie } else { 4379ce4f8f3SGreg Kroah-Hartman return; 43845564a66SHuang Shijie } 43945564a66SHuang Shijie } 440b4cdc8f6SHuang Shijie 441ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 442ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 44385878399SHuang Shijie 44485878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 44585878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 44685878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 447ab4382d2SGreg Kroah-Hartman } 448ab4382d2SGreg Kroah-Hartman 449ab4382d2SGreg Kroah-Hartman /* 450ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 451ab4382d2SGreg Kroah-Hartman */ 452ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 453ab4382d2SGreg Kroah-Hartman { 454ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 455ab4382d2SGreg Kroah-Hartman 456ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 457ab4382d2SGreg Kroah-Hartman } 458ab4382d2SGreg Kroah-Hartman 45991a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 460ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 461ab4382d2SGreg Kroah-Hartman { 462ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 46391a1a909SJiada Wang unsigned long temp; 464ab4382d2SGreg Kroah-Hartman 4655e42e9a3SPeter Hurley if (sport->port.x_char) { 4665e42e9a3SPeter Hurley /* Send next char */ 4675e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4687e2fb5aaSJiada Wang sport->port.icount.tx++; 4697e2fb5aaSJiada Wang sport->port.x_char = 0; 4705e42e9a3SPeter Hurley return; 4715e42e9a3SPeter Hurley } 4725e42e9a3SPeter Hurley 4735e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4745e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4755e42e9a3SPeter Hurley return; 4765e42e9a3SPeter Hurley } 4775e42e9a3SPeter Hurley 47891a1a909SJiada Wang if (sport->dma_is_enabled) { 47991a1a909SJiada Wang /* 48091a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 48191a1a909SJiada Wang * and the TX IRQ is disabled. 48291a1a909SJiada Wang **/ 48391a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 48491a1a909SJiada Wang temp &= ~UCR1_TXMPTYEN; 48591a1a909SJiada Wang if (sport->dma_is_txing) { 48691a1a909SJiada Wang temp |= UCR1_TDMAEN; 48791a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 48891a1a909SJiada Wang } else { 48991a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 49091a1a909SJiada Wang imx_dma_tx(sport); 49191a1a909SJiada Wang } 49291a1a909SJiada Wang } 49391a1a909SJiada Wang 494ab4382d2SGreg Kroah-Hartman while (!uart_circ_empty(xmit) && 4955e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 496ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 497ab4382d2SGreg Kroah-Hartman * out the port here */ 498ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 499ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 500ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 501ab4382d2SGreg Kroah-Hartman } 502ab4382d2SGreg Kroah-Hartman 503ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 504ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 505ab4382d2SGreg Kroah-Hartman 506ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 507ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 508ab4382d2SGreg Kroah-Hartman } 509ab4382d2SGreg Kroah-Hartman 510b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 511b4cdc8f6SHuang Shijie { 512b4cdc8f6SHuang Shijie struct imx_port *sport = data; 513b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 514b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 515b4cdc8f6SHuang Shijie unsigned long flags; 516a2c718ceSDirk Behme unsigned long temp; 517b4cdc8f6SHuang Shijie 51842f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 51942f752b3SDirk Behme 520b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 521b4cdc8f6SHuang Shijie 522a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 523a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 524a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 525a2c718ceSDirk Behme 52642f752b3SDirk Behme /* update the stat */ 52742f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 52842f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 52942f752b3SDirk Behme 53042f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 53142f752b3SDirk Behme 532b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 533b4cdc8f6SHuang Shijie 534b4cdc8f6SHuang Shijie spin_unlock_irqrestore(&sport->port.lock, flags); 535b4cdc8f6SHuang Shijie 536d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 537b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5389ce4f8f3SGreg Kroah-Hartman 5399ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) { 5409ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 5419ce4f8f3SGreg Kroah-Hartman dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 5429ce4f8f3SGreg Kroah-Hartman return; 5439ce4f8f3SGreg Kroah-Hartman } 5440bbc9b81SJiada Wang 5450bbc9b81SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 5460bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5470bbc9b81SJiada Wang imx_dma_tx(sport); 5480bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 549b4cdc8f6SHuang Shijie } 550b4cdc8f6SHuang Shijie 5517cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 552b4cdc8f6SHuang Shijie { 553b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 554b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 555b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 556b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 557b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 558a2c718ceSDirk Behme unsigned long temp; 559b4cdc8f6SHuang Shijie int ret; 560b4cdc8f6SHuang Shijie 56142f752b3SDirk Behme if (sport->dma_is_txing) 562b4cdc8f6SHuang Shijie return; 563b4cdc8f6SHuang Shijie 564b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 565b4cdc8f6SHuang Shijie 5667942f857SDirk Behme if (xmit->tail < xmit->head) { 5677942f857SDirk Behme sport->dma_tx_nents = 1; 5687942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5697942f857SDirk Behme } else { 570b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 571b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 572b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 573b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 574b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 575b4cdc8f6SHuang Shijie } 576b4cdc8f6SHuang Shijie 577b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 578b4cdc8f6SHuang Shijie if (ret == 0) { 579b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 580b4cdc8f6SHuang Shijie return; 581b4cdc8f6SHuang Shijie } 582b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 583b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 584b4cdc8f6SHuang Shijie if (!desc) { 58524649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 58624649821SDirk Behme DMA_TO_DEVICE); 587b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 588b4cdc8f6SHuang Shijie return; 589b4cdc8f6SHuang Shijie } 590b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 591b4cdc8f6SHuang Shijie desc->callback_param = sport; 592b4cdc8f6SHuang Shijie 593b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 594b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 595a2c718ceSDirk Behme 596a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 597a2c718ceSDirk Behme temp |= UCR1_TDMAEN; 598a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 599a2c718ceSDirk Behme 600b4cdc8f6SHuang Shijie /* fire it */ 601b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 602b4cdc8f6SHuang Shijie dmaengine_submit(desc); 603b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 604b4cdc8f6SHuang Shijie return; 605b4cdc8f6SHuang Shijie } 606b4cdc8f6SHuang Shijie 607ab4382d2SGreg Kroah-Hartman /* 608ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 609ab4382d2SGreg Kroah-Hartman */ 610ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 611ab4382d2SGreg Kroah-Hartman { 612ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 613ab4382d2SGreg Kroah-Hartman unsigned long temp; 614ab4382d2SGreg Kroah-Hartman 615ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 616ab4382d2SGreg Kroah-Hartman /* half duplex in IrDA mode; have to disable receive mode */ 617ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 618ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_DREN); 619ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 620ab4382d2SGreg Kroah-Hartman 621ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 622ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RRDYEN); 623ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 624ab4382d2SGreg Kroah-Hartman } 625ab4382d2SGreg Kroah-Hartman 626b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 627ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 628ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 629b4cdc8f6SHuang Shijie } 630ab4382d2SGreg Kroah-Hartman 631ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 632ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 633ab4382d2SGreg Kroah-Hartman temp |= UCR1_TRDYEN; 634ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 635ab4382d2SGreg Kroah-Hartman 636ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 637ab4382d2SGreg Kroah-Hartman temp |= UCR4_TCEN; 638ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 639ab4382d2SGreg Kroah-Hartman } 640ab4382d2SGreg Kroah-Hartman 641b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 64291a1a909SJiada Wang if (sport->port.x_char) { 64391a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 64491a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 64591a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 64691a1a909SJiada Wang temp &= ~UCR1_TDMAEN; 64791a1a909SJiada Wang temp |= UCR1_TXMPTYEN; 64891a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 64991a1a909SJiada Wang return; 65091a1a909SJiada Wang } 65191a1a909SJiada Wang 6525e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6535e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6547cb92fd2SHuang Shijie imx_dma_tx(sport); 655b4cdc8f6SHuang Shijie return; 656b4cdc8f6SHuang Shijie } 657ab4382d2SGreg Kroah-Hartman } 658ab4382d2SGreg Kroah-Hartman 659ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 660ab4382d2SGreg Kroah-Hartman { 661ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6625680e941SUwe Kleine-König unsigned int val; 663ab4382d2SGreg Kroah-Hartman unsigned long flags; 664ab4382d2SGreg Kroah-Hartman 665ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 666ab4382d2SGreg Kroah-Hartman 667ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6685680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 669ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 670ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 671ab4382d2SGreg Kroah-Hartman 672ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 673ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 674ab4382d2SGreg Kroah-Hartman } 675ab4382d2SGreg Kroah-Hartman 676ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 677ab4382d2SGreg Kroah-Hartman { 678ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 679ab4382d2SGreg Kroah-Hartman unsigned long flags; 680ab4382d2SGreg Kroah-Hartman 681ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 682ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 683ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 684ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 685ab4382d2SGreg Kroah-Hartman } 686ab4382d2SGreg Kroah-Hartman 687ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 688ab4382d2SGreg Kroah-Hartman { 689ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 690ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 69192a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 692ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 693ab4382d2SGreg Kroah-Hartman 694ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 695ab4382d2SGreg Kroah-Hartman 696ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 697ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 698ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 699ab4382d2SGreg Kroah-Hartman 700ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 701ab4382d2SGreg Kroah-Hartman 702ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 703ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 704ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 705ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 706ab4382d2SGreg Kroah-Hartman continue; 707ab4382d2SGreg Kroah-Hartman } 708ab4382d2SGreg Kroah-Hartman 709ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 710ab4382d2SGreg Kroah-Hartman continue; 711ab4382d2SGreg Kroah-Hartman 712019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 713019dc9eaSHui Wang if (rx & URXD_BRK) 714019dc9eaSHui Wang sport->port.icount.brk++; 715019dc9eaSHui Wang else if (rx & URXD_PRERR) 716ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 717ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 718ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 719ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 720ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 721ab4382d2SGreg Kroah-Hartman 722ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 723ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 724ab4382d2SGreg Kroah-Hartman goto out; 725ab4382d2SGreg Kroah-Hartman continue; 726ab4382d2SGreg Kroah-Hartman } 727ab4382d2SGreg Kroah-Hartman 7288d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 729ab4382d2SGreg Kroah-Hartman 730019dc9eaSHui Wang if (rx & URXD_BRK) 731019dc9eaSHui Wang flg = TTY_BREAK; 732019dc9eaSHui Wang else if (rx & URXD_PRERR) 733ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 734ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 735ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 736ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 737ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 738ab4382d2SGreg Kroah-Hartman 739ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 740ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 741ab4382d2SGreg Kroah-Hartman #endif 742ab4382d2SGreg Kroah-Hartman } 743ab4382d2SGreg Kroah-Hartman 74455d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 74555d8693aSJiada Wang goto out; 74655d8693aSJiada Wang 74792a19f9cSJiri Slaby tty_insert_flip_char(port, rx, flg); 748ab4382d2SGreg Kroah-Hartman } 749ab4382d2SGreg Kroah-Hartman 750ab4382d2SGreg Kroah-Hartman out: 751ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7522e124b4aSJiri Slaby tty_flip_buffer_push(port); 753ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 754ab4382d2SGreg Kroah-Hartman } 755ab4382d2SGreg Kroah-Hartman 7567cb92fd2SHuang Shijie static int start_rx_dma(struct imx_port *sport); 757b4cdc8f6SHuang Shijie /* 758b4cdc8f6SHuang Shijie * If the RXFIFO is filled with some data, and then we 759b4cdc8f6SHuang Shijie * arise a DMA operation to receive them. 760b4cdc8f6SHuang Shijie */ 761b4cdc8f6SHuang Shijie static void imx_dma_rxint(struct imx_port *sport) 762b4cdc8f6SHuang Shijie { 763b4cdc8f6SHuang Shijie unsigned long temp; 76473631813SJiada Wang unsigned long flags; 76573631813SJiada Wang 76673631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 767b4cdc8f6SHuang Shijie 768b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + USR2); 769b4cdc8f6SHuang Shijie if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 770b4cdc8f6SHuang Shijie sport->dma_is_rxing = 1; 771b4cdc8f6SHuang Shijie 772b4cdc8f6SHuang Shijie /* disable the `Recerver Ready Interrrupt` */ 773b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 774b4cdc8f6SHuang Shijie temp &= ~(UCR1_RRDYEN); 775b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 776b4cdc8f6SHuang Shijie 777b4cdc8f6SHuang Shijie /* tell the DMA to receive the data. */ 7787cb92fd2SHuang Shijie start_rx_dma(sport); 779b4cdc8f6SHuang Shijie } 78073631813SJiada Wang 78173631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 782b4cdc8f6SHuang Shijie } 783b4cdc8f6SHuang Shijie 784ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 785ab4382d2SGreg Kroah-Hartman { 786ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 787ab4382d2SGreg Kroah-Hartman unsigned int sts; 788f1f836e4SAlexander Stein unsigned int sts2; 789ab4382d2SGreg Kroah-Hartman 790ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 791ab4382d2SGreg Kroah-Hartman 792b4cdc8f6SHuang Shijie if (sts & USR1_RRDY) { 793b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) 794b4cdc8f6SHuang Shijie imx_dma_rxint(sport); 795b4cdc8f6SHuang Shijie else 796ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 797b4cdc8f6SHuang Shijie } 798ab4382d2SGreg Kroah-Hartman 799ab4382d2SGreg Kroah-Hartman if (sts & USR1_TRDY && 800ab4382d2SGreg Kroah-Hartman readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 801ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 802ab4382d2SGreg Kroah-Hartman 803ab4382d2SGreg Kroah-Hartman if (sts & USR1_RTSD) 804ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 805ab4382d2SGreg Kroah-Hartman 806db1a9b55SFabio Estevam if (sts & USR1_AWAKE) 807db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 808db1a9b55SFabio Estevam 809f1f836e4SAlexander Stein sts2 = readl(sport->port.membase + USR2); 810f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 811f1f836e4SAlexander Stein dev_err(sport->port.dev, "Rx FIFO overrun\n"); 812f1f836e4SAlexander Stein sport->port.icount.overrun++; 81391555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 814f1f836e4SAlexander Stein } 815f1f836e4SAlexander Stein 816ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 817ab4382d2SGreg Kroah-Hartman } 818ab4382d2SGreg Kroah-Hartman 819ab4382d2SGreg Kroah-Hartman /* 820ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 821ab4382d2SGreg Kroah-Hartman */ 822ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 823ab4382d2SGreg Kroah-Hartman { 824ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 8251ce43e58SHuang Shijie unsigned int ret; 826ab4382d2SGreg Kroah-Hartman 8271ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 8281ce43e58SHuang Shijie 8291ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 8301ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 8311ce43e58SHuang Shijie ret = 0; 8321ce43e58SHuang Shijie 8331ce43e58SHuang Shijie return ret; 834ab4382d2SGreg Kroah-Hartman } 835ab4382d2SGreg Kroah-Hartman 836ab4382d2SGreg Kroah-Hartman /* 837ab4382d2SGreg Kroah-Hartman * We have a modem side uart, so the meanings of RTS and CTS are inverted. 838ab4382d2SGreg Kroah-Hartman */ 839ab4382d2SGreg Kroah-Hartman static unsigned int imx_get_mctrl(struct uart_port *port) 840ab4382d2SGreg Kroah-Hartman { 841ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 842ab4382d2SGreg Kroah-Hartman unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 843ab4382d2SGreg Kroah-Hartman 844ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR1) & USR1_RTSS) 845ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_CTS; 846ab4382d2SGreg Kroah-Hartman 847ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR2) & UCR2_CTS) 848ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_RTS; 849ab4382d2SGreg Kroah-Hartman 8506b471a98SHuang Shijie if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 8516b471a98SHuang Shijie tmp |= TIOCM_LOOP; 8526b471a98SHuang Shijie 853ab4382d2SGreg Kroah-Hartman return tmp; 854ab4382d2SGreg Kroah-Hartman } 855ab4382d2SGreg Kroah-Hartman 856ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 857ab4382d2SGreg Kroah-Hartman { 858ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 859ab4382d2SGreg Kroah-Hartman unsigned long temp; 860ab4382d2SGreg Kroah-Hartman 861bb2f861aSFugang Duan temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC); 862ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 863bb2f861aSFugang Duan temp |= UCR2_CTS | UCR2_CTSC; 864ab4382d2SGreg Kroah-Hartman 865ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 8666b471a98SHuang Shijie 8676b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8686b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8696b471a98SHuang Shijie temp |= UTS_LOOP; 8706b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 871ab4382d2SGreg Kroah-Hartman } 872ab4382d2SGreg Kroah-Hartman 873ab4382d2SGreg Kroah-Hartman /* 874ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 875ab4382d2SGreg Kroah-Hartman */ 876ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 877ab4382d2SGreg Kroah-Hartman { 878ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 879ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 880ab4382d2SGreg Kroah-Hartman 881ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 882ab4382d2SGreg Kroah-Hartman 883ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 884ab4382d2SGreg Kroah-Hartman 885ab4382d2SGreg Kroah-Hartman if (break_state != 0) 886ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 887ab4382d2SGreg Kroah-Hartman 888ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 889ab4382d2SGreg Kroah-Hartman 890ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 891ab4382d2SGreg Kroah-Hartman } 892ab4382d2SGreg Kroah-Hartman 893ab4382d2SGreg Kroah-Hartman #define TXTL 2 /* reset default */ 894ab4382d2SGreg Kroah-Hartman #define RXTL 1 /* reset default */ 895ab4382d2SGreg Kroah-Hartman 896ab4382d2SGreg Kroah-Hartman static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 897ab4382d2SGreg Kroah-Hartman { 898ab4382d2SGreg Kroah-Hartman unsigned int val; 899ab4382d2SGreg Kroah-Hartman 9007be0670fSDirk Behme /* set receiver / transmitter trigger level */ 9017be0670fSDirk Behme val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 9027be0670fSDirk Behme val |= TXTL << UFCR_TXTL_SHF | RXTL; 903ab4382d2SGreg Kroah-Hartman writel(val, sport->port.membase + UFCR); 904ab4382d2SGreg Kroah-Hartman return 0; 905ab4382d2SGreg Kroah-Hartman } 906ab4382d2SGreg Kroah-Hartman 907b4cdc8f6SHuang Shijie #define RX_BUF_SIZE (PAGE_SIZE) 908b4cdc8f6SHuang Shijie static void imx_rx_dma_done(struct imx_port *sport) 909b4cdc8f6SHuang Shijie { 910b4cdc8f6SHuang Shijie unsigned long temp; 91173631813SJiada Wang unsigned long flags; 91273631813SJiada Wang 91373631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 914b4cdc8f6SHuang Shijie 915b4cdc8f6SHuang Shijie /* Enable this interrupt when the RXFIFO is empty. */ 916b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 917b4cdc8f6SHuang Shijie temp |= UCR1_RRDYEN; 918b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 919b4cdc8f6SHuang Shijie 920b4cdc8f6SHuang Shijie sport->dma_is_rxing = 0; 9219ce4f8f3SGreg Kroah-Hartman 9229ce4f8f3SGreg Kroah-Hartman /* Is the shutdown waiting for us? */ 9239ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) 9249ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 92573631813SJiada Wang 92673631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 927b4cdc8f6SHuang Shijie } 928b4cdc8f6SHuang Shijie 929b4cdc8f6SHuang Shijie /* 930b4cdc8f6SHuang Shijie * There are three kinds of RX DMA interrupts(such as in the MX6Q): 931b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 932b4cdc8f6SHuang Shijie * [2] the Aging timer expires(wait for 8 bytes long) 933b4cdc8f6SHuang Shijie * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 934b4cdc8f6SHuang Shijie * 935b4cdc8f6SHuang Shijie * The [2] is trigger when a character was been sitting in the FIFO 936b4cdc8f6SHuang Shijie * meanwhile [3] can wait for 32 bytes long when the RX line is 937b4cdc8f6SHuang Shijie * on IDLE state and RxFIFO is empty. 938b4cdc8f6SHuang Shijie */ 939b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 940b4cdc8f6SHuang Shijie { 941b4cdc8f6SHuang Shijie struct imx_port *sport = data; 942b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 943b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9447cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 945b4cdc8f6SHuang Shijie struct dma_tx_state state; 946b4cdc8f6SHuang Shijie enum dma_status status; 947b4cdc8f6SHuang Shijie unsigned int count; 948b4cdc8f6SHuang Shijie 949b4cdc8f6SHuang Shijie /* unmap it first */ 950b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 951b4cdc8f6SHuang Shijie 952f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 953b4cdc8f6SHuang Shijie count = RX_BUF_SIZE - state.residue; 954b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 955b4cdc8f6SHuang Shijie 956b4cdc8f6SHuang Shijie if (count) { 95755d8693aSJiada Wang if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) 9587cb92fd2SHuang Shijie tty_insert_flip_string(port, sport->rx_buf, count); 9597cb92fd2SHuang Shijie tty_flip_buffer_push(port); 9607cb92fd2SHuang Shijie 9617cb92fd2SHuang Shijie start_rx_dma(sport); 962ee5e7c10SRobin Gong } else if (readl(sport->port.membase + USR2) & USR2_RDR) { 963ee5e7c10SRobin Gong /* 964ee5e7c10SRobin Gong * start rx_dma directly once data in RXFIFO, more efficient 965ee5e7c10SRobin Gong * than before: 966ee5e7c10SRobin Gong * 1. call imx_rx_dma_done to stop dma if no data received 967ee5e7c10SRobin Gong * 2. wait next RDR interrupt to start dma transfer. 968ee5e7c10SRobin Gong */ 969ee5e7c10SRobin Gong start_rx_dma(sport); 970ee5e7c10SRobin Gong } else { 971ee5e7c10SRobin Gong /* 972ee5e7c10SRobin Gong * stop dma to prevent too many IDLE event trigged if no data 973ee5e7c10SRobin Gong * in RXFIFO 974ee5e7c10SRobin Gong */ 975b4cdc8f6SHuang Shijie imx_rx_dma_done(sport); 976b4cdc8f6SHuang Shijie } 977ee5e7c10SRobin Gong } 978b4cdc8f6SHuang Shijie 979b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 980b4cdc8f6SHuang Shijie { 981b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 982b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 983b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 984b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 985b4cdc8f6SHuang Shijie int ret; 986b4cdc8f6SHuang Shijie 987b4cdc8f6SHuang Shijie sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 988b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 989b4cdc8f6SHuang Shijie if (ret == 0) { 990b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 991b4cdc8f6SHuang Shijie return -EINVAL; 992b4cdc8f6SHuang Shijie } 993b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 994b4cdc8f6SHuang Shijie DMA_PREP_INTERRUPT); 995b4cdc8f6SHuang Shijie if (!desc) { 99624649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 997b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 998b4cdc8f6SHuang Shijie return -EINVAL; 999b4cdc8f6SHuang Shijie } 1000b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 1001b4cdc8f6SHuang Shijie desc->callback_param = sport; 1002b4cdc8f6SHuang Shijie 1003b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 1004b4cdc8f6SHuang Shijie dmaengine_submit(desc); 1005b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1006b4cdc8f6SHuang Shijie return 0; 1007b4cdc8f6SHuang Shijie } 1008b4cdc8f6SHuang Shijie 1009b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1010b4cdc8f6SHuang Shijie { 1011b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1012b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1013b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 1014b4cdc8f6SHuang Shijie 1015b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1016b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1017b4cdc8f6SHuang Shijie } 1018b4cdc8f6SHuang Shijie 1019b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1020b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1021b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1022b4cdc8f6SHuang Shijie } 1023b4cdc8f6SHuang Shijie 1024b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 1025b4cdc8f6SHuang Shijie } 1026b4cdc8f6SHuang Shijie 1027b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1028b4cdc8f6SHuang Shijie { 1029b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1030b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1031b4cdc8f6SHuang Shijie int ret; 1032b4cdc8f6SHuang Shijie 1033b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1034b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1035b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1036b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1037b4cdc8f6SHuang Shijie ret = -EINVAL; 1038b4cdc8f6SHuang Shijie goto err; 1039b4cdc8f6SHuang Shijie } 1040b4cdc8f6SHuang Shijie 1041b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1042b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1043b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1044b4cdc8f6SHuang Shijie slave_config.src_maxburst = RXTL; 1045b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1046b4cdc8f6SHuang Shijie if (ret) { 1047b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1048b4cdc8f6SHuang Shijie goto err; 1049b4cdc8f6SHuang Shijie } 1050b4cdc8f6SHuang Shijie 1051b4cdc8f6SHuang Shijie sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1052b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1053b4cdc8f6SHuang Shijie ret = -ENOMEM; 1054b4cdc8f6SHuang Shijie goto err; 1055b4cdc8f6SHuang Shijie } 1056b4cdc8f6SHuang Shijie 1057b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1058b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1059b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1060b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1061b4cdc8f6SHuang Shijie ret = -EINVAL; 1062b4cdc8f6SHuang Shijie goto err; 1063b4cdc8f6SHuang Shijie } 1064b4cdc8f6SHuang Shijie 1065b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1066b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1067b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1068b4cdc8f6SHuang Shijie slave_config.dst_maxburst = TXTL; 1069b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1070b4cdc8f6SHuang Shijie if (ret) { 1071b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1072b4cdc8f6SHuang Shijie goto err; 1073b4cdc8f6SHuang Shijie } 1074b4cdc8f6SHuang Shijie 1075b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1076b4cdc8f6SHuang Shijie 1077b4cdc8f6SHuang Shijie return 0; 1078b4cdc8f6SHuang Shijie err: 1079b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1080b4cdc8f6SHuang Shijie return ret; 1081b4cdc8f6SHuang Shijie } 1082b4cdc8f6SHuang Shijie 1083b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1084b4cdc8f6SHuang Shijie { 1085b4cdc8f6SHuang Shijie unsigned long temp; 1086b4cdc8f6SHuang Shijie 10879ce4f8f3SGreg Kroah-Hartman init_waitqueue_head(&sport->dma_wait); 10889ce4f8f3SGreg Kroah-Hartman 1089b4cdc8f6SHuang Shijie /* set UCR1 */ 1090b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1091b4cdc8f6SHuang Shijie temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1092b4cdc8f6SHuang Shijie /* wait for 32 idle frames for IDDMA interrupt */ 1093b4cdc8f6SHuang Shijie UCR1_ICD_REG(3); 1094b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1095b4cdc8f6SHuang Shijie 1096b4cdc8f6SHuang Shijie /* set UCR4 */ 1097b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1098b4cdc8f6SHuang Shijie temp |= UCR4_IDDMAEN; 1099b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1100b4cdc8f6SHuang Shijie 1101b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1102b4cdc8f6SHuang Shijie } 1103b4cdc8f6SHuang Shijie 1104b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1105b4cdc8f6SHuang Shijie { 1106b4cdc8f6SHuang Shijie unsigned long temp; 1107b4cdc8f6SHuang Shijie 1108b4cdc8f6SHuang Shijie /* clear UCR1 */ 1109b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1110b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1111b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1112b4cdc8f6SHuang Shijie 1113b4cdc8f6SHuang Shijie /* clear UCR2 */ 1114b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 1115b4cdc8f6SHuang Shijie temp &= ~(UCR2_CTSC | UCR2_CTS); 1116b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1117b4cdc8f6SHuang Shijie 1118b4cdc8f6SHuang Shijie /* clear UCR4 */ 1119b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1120b4cdc8f6SHuang Shijie temp &= ~UCR4_IDDMAEN; 1121b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1122b4cdc8f6SHuang Shijie 1123b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1124b4cdc8f6SHuang Shijie } 1125b4cdc8f6SHuang Shijie 1126ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1127ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1128ab4382d2SGreg Kroah-Hartman 1129ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1130ab4382d2SGreg Kroah-Hartman { 1131ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1132772f8991SHuang Shijie int retval, i; 1133ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1134ab4382d2SGreg Kroah-Hartman 113528eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 113628eb4274SHuang Shijie if (retval) 1137cb0f0a5fSFabio Estevam return retval; 113828eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 11390c375501SHuang Shijie if (retval) { 11400c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1141cb0f0a5fSFabio Estevam return retval; 11420c375501SHuang Shijie } 114328eb4274SHuang Shijie 1144ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1145ab4382d2SGreg Kroah-Hartman 1146ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1147ab4382d2SGreg Kroah-Hartman * requesting IRQs 1148ab4382d2SGreg Kroah-Hartman */ 1149ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1150ab4382d2SGreg Kroah-Hartman 1151ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1152ab4382d2SGreg Kroah-Hartman temp |= UCR4_IRSC; 1153ab4382d2SGreg Kroah-Hartman 1154ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1155ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1156ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1157ab4382d2SGreg Kroah-Hartman 1158ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1159ab4382d2SGreg Kroah-Hartman 1160772f8991SHuang Shijie /* Reset fifo's and state machines */ 1161772f8991SHuang Shijie i = 100; 1162772f8991SHuang Shijie 1163ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1164ab4382d2SGreg Kroah-Hartman temp &= ~UCR2_SRST; 1165ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1166772f8991SHuang Shijie 1167772f8991SHuang Shijie while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1168ab4382d2SGreg Kroah-Hartman udelay(1); 1169ab4382d2SGreg Kroah-Hartman 1170068500e0SAnton Bondarenko /* Can we enable the DMA support? */ 1171068500e0SAnton Bondarenko if (is_imx6q_uart(sport) && !uart_console(port) && 1172068500e0SAnton Bondarenko !sport->dma_is_inited) 1173068500e0SAnton Bondarenko imx_uart_dma_init(sport); 1174068500e0SAnton Bondarenko 11759ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 117691555ce9SUwe Kleine-König 1177ab4382d2SGreg Kroah-Hartman /* 1178ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1179ab4382d2SGreg Kroah-Hartman */ 1180ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 118191555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 1182ab4382d2SGreg Kroah-Hartman 1183068500e0SAnton Bondarenko if (sport->dma_is_inited && !sport->dma_is_enabled) 1184068500e0SAnton Bondarenko imx_enable_dma(sport); 1185068500e0SAnton Bondarenko 1186ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1187ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1188ab4382d2SGreg Kroah-Hartman 1189ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1190ab4382d2SGreg Kroah-Hartman temp |= UCR1_IREN; 1191ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RTSDEN); 1192ab4382d2SGreg Kroah-Hartman } 1193ab4382d2SGreg Kroah-Hartman 1194ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1195ab4382d2SGreg Kroah-Hartman 11966f026d6bSJiada Wang temp = readl(sport->port.membase + UCR4); 11976f026d6bSJiada Wang temp |= UCR4_OREN; 11986f026d6bSJiada Wang writel(temp, sport->port.membase + UCR4); 11996f026d6bSJiada Wang 1200ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1201ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1202bff09b09SLucas Stach if (!sport->have_rtscts) 1203bff09b09SLucas Stach temp |= UCR2_IRTS; 1204ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1205ab4382d2SGreg Kroah-Hartman 1206a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1207ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1208b38cb7d2SFabio Estevam temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1209ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1210ab4382d2SGreg Kroah-Hartman } 1211ab4382d2SGreg Kroah-Hartman 1212ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1213ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1214ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_rx) 1215ab4382d2SGreg Kroah-Hartman temp |= UCR4_INVR; 1216ab4382d2SGreg Kroah-Hartman else 1217ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_INVR); 1218ab4382d2SGreg Kroah-Hartman writel(temp | UCR4_DREN, sport->port.membase + UCR4); 1219ab4382d2SGreg Kroah-Hartman 1220ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1221ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_tx) 1222ab4382d2SGreg Kroah-Hartman temp |= UCR3_INVT; 1223ab4382d2SGreg Kroah-Hartman else 1224ab4382d2SGreg Kroah-Hartman temp &= ~(UCR3_INVT); 1225ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1226ab4382d2SGreg Kroah-Hartman } 1227ab4382d2SGreg Kroah-Hartman 1228ab4382d2SGreg Kroah-Hartman /* 1229ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1230ab4382d2SGreg Kroah-Hartman */ 1231ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1232ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1233ab4382d2SGreg Kroah-Hartman 1234ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1235ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1236574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1237ab4382d2SGreg Kroah-Hartman sport->irda_inv_rx = pdata->irda_inv_rx; 1238ab4382d2SGreg Kroah-Hartman sport->irda_inv_tx = pdata->irda_inv_tx; 1239ab4382d2SGreg Kroah-Hartman sport->trcv_delay = pdata->transceiver_delay; 1240ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1241ab4382d2SGreg Kroah-Hartman pdata->irda_enable(1); 1242ab4382d2SGreg Kroah-Hartman } 1243ab4382d2SGreg Kroah-Hartman 1244ab4382d2SGreg Kroah-Hartman return 0; 1245ab4382d2SGreg Kroah-Hartman } 1246ab4382d2SGreg Kroah-Hartman 1247ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1248ab4382d2SGreg Kroah-Hartman { 1249ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1250ab4382d2SGreg Kroah-Hartman unsigned long temp; 12519ec1882dSXinyu Chen unsigned long flags; 1252ab4382d2SGreg Kroah-Hartman 1253b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1254a4688bcdSHuang Shijie int ret; 1255a4688bcdSHuang Shijie 12569ce4f8f3SGreg Kroah-Hartman /* We have to wait for the DMA to finish. */ 1257a4688bcdSHuang Shijie ret = wait_event_interruptible(sport->dma_wait, 12589ce4f8f3SGreg Kroah-Hartman !sport->dma_is_rxing && !sport->dma_is_txing); 1259a4688bcdSHuang Shijie if (ret != 0) { 1260a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1261a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1262a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 1263a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 1264a4688bcdSHuang Shijie } 126573631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1266a4688bcdSHuang Shijie imx_stop_tx(port); 1267b4cdc8f6SHuang Shijie imx_stop_rx(port); 1268b4cdc8f6SHuang Shijie imx_disable_dma(sport); 126973631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1270b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1271b4cdc8f6SHuang Shijie } 1272b4cdc8f6SHuang Shijie 12739ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1274ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1275ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1276ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 12779ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1278ab4382d2SGreg Kroah-Hartman 1279ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1280ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1281574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1282ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1283ab4382d2SGreg Kroah-Hartman pdata->irda_enable(0); 1284ab4382d2SGreg Kroah-Hartman } 1285ab4382d2SGreg Kroah-Hartman 1286ab4382d2SGreg Kroah-Hartman /* 1287ab4382d2SGreg Kroah-Hartman * Stop our timer. 1288ab4382d2SGreg Kroah-Hartman */ 1289ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1290ab4382d2SGreg Kroah-Hartman 1291ab4382d2SGreg Kroah-Hartman /* 1292ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1293ab4382d2SGreg Kroah-Hartman */ 1294ab4382d2SGreg Kroah-Hartman 12959ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1296ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1297ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1298ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1299ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_IREN); 1300ab4382d2SGreg Kroah-Hartman 1301ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 13029ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 130328eb4274SHuang Shijie 130428eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 130528eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1306ab4382d2SGreg Kroah-Hartman } 1307ab4382d2SGreg Kroah-Hartman 1308eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1309eb56b7edSHuang Shijie { 1310eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 131182e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1312a2c718ceSDirk Behme unsigned long temp; 13134f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1314eb56b7edSHuang Shijie 131582e86ae9SDirk Behme if (!sport->dma_chan_tx) 131682e86ae9SDirk Behme return; 131782e86ae9SDirk Behme 1318eb56b7edSHuang Shijie sport->tx_bytes = 0; 1319eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 132082e86ae9SDirk Behme if (sport->dma_is_txing) { 132182e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 132282e86ae9SDirk Behme DMA_TO_DEVICE); 1323a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 1324a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 1325a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 132682e86ae9SDirk Behme sport->dma_is_txing = false; 1327eb56b7edSHuang Shijie } 1328934084a9SFabio Estevam 1329934084a9SFabio Estevam /* 1330934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1331934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1332934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1333934084a9SFabio Estevam * and UTS[6-3]". As we don't need to restore the old values from 1334934084a9SFabio Estevam * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1335934084a9SFabio Estevam */ 1336934084a9SFabio Estevam ubir = readl(sport->port.membase + UBIR); 1337934084a9SFabio Estevam ubmr = readl(sport->port.membase + UBMR); 1338934084a9SFabio Estevam uts = readl(sport->port.membase + IMX21_UTS); 1339934084a9SFabio Estevam 1340934084a9SFabio Estevam temp = readl(sport->port.membase + UCR2); 1341934084a9SFabio Estevam temp &= ~UCR2_SRST; 1342934084a9SFabio Estevam writel(temp, sport->port.membase + UCR2); 1343934084a9SFabio Estevam 1344934084a9SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1345934084a9SFabio Estevam udelay(1); 1346934084a9SFabio Estevam 1347934084a9SFabio Estevam /* Restore the registers */ 1348934084a9SFabio Estevam writel(ubir, sport->port.membase + UBIR); 1349934084a9SFabio Estevam writel(ubmr, sport->port.membase + UBMR); 1350934084a9SFabio Estevam writel(uts, sport->port.membase + IMX21_UTS); 1351eb56b7edSHuang Shijie } 1352eb56b7edSHuang Shijie 1353ab4382d2SGreg Kroah-Hartman static void 1354ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1355ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1356ab4382d2SGreg Kroah-Hartman { 1357ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1358ab4382d2SGreg Kroah-Hartman unsigned long flags; 1359ab4382d2SGreg Kroah-Hartman unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1360ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1361ab4382d2SGreg Kroah-Hartman unsigned int div, ufcr; 1362ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1363ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1364ab4382d2SGreg Kroah-Hartman 1365ab4382d2SGreg Kroah-Hartman /* 1366ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1367ab4382d2SGreg Kroah-Hartman */ 1368ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1369ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1370ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1371ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1372ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1373ab4382d2SGreg Kroah-Hartman } 1374ab4382d2SGreg Kroah-Hartman 1375ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1376ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1377ab4382d2SGreg Kroah-Hartman else 1378ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1379ab4382d2SGreg Kroah-Hartman 1380ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1381ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1382ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 1383ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_CTSC; 1384ab4382d2SGreg Kroah-Hartman } else { 1385ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1386ab4382d2SGreg Kroah-Hartman } 1387ab4382d2SGreg Kroah-Hartman } 1388ab4382d2SGreg Kroah-Hartman 1389ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1390ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1391ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1392ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1393ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1394ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1395ab4382d2SGreg Kroah-Hartman } 1396ab4382d2SGreg Kroah-Hartman 1397995234daSEric Miao del_timer_sync(&sport->timer); 1398995234daSEric Miao 1399ab4382d2SGreg Kroah-Hartman /* 1400ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1401ab4382d2SGreg Kroah-Hartman */ 1402ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1403ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1404ab4382d2SGreg Kroah-Hartman 1405ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1406ab4382d2SGreg Kroah-Hartman 1407ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1408ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1409ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1410ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1411ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1412ab4382d2SGreg Kroah-Hartman 1413ab4382d2SGreg Kroah-Hartman /* 1414ab4382d2SGreg Kroah-Hartman * Characters to ignore 1415ab4382d2SGreg Kroah-Hartman */ 1416ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1417ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1418865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1419ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1420ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1421ab4382d2SGreg Kroah-Hartman /* 1422ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1423ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1424ab4382d2SGreg Kroah-Hartman */ 1425ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1426ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1427ab4382d2SGreg Kroah-Hartman } 1428ab4382d2SGreg Kroah-Hartman 142955d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 143055d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 143155d8693aSJiada Wang 1432ab4382d2SGreg Kroah-Hartman /* 1433ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1434ab4382d2SGreg Kroah-Hartman */ 1435ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1436ab4382d2SGreg Kroah-Hartman 1437ab4382d2SGreg Kroah-Hartman /* 1438ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1439ab4382d2SGreg Kroah-Hartman */ 1440ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1441ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1442ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1443ab4382d2SGreg Kroah-Hartman 1444ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1445ab4382d2SGreg Kroah-Hartman barrier(); 1446ab4382d2SGreg Kroah-Hartman 1447ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 1448ab4382d2SGreg Kroah-Hartman old_txrxen = readl(sport->port.membase + UCR2); 1449ab4382d2SGreg Kroah-Hartman writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1450ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 1451ab4382d2SGreg Kroah-Hartman old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1452ab4382d2SGreg Kroah-Hartman 1453ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1454ab4382d2SGreg Kroah-Hartman /* 1455ab4382d2SGreg Kroah-Hartman * use maximum available submodule frequency to 1456ab4382d2SGreg Kroah-Hartman * avoid missing short pulses due to low sampling rate 1457ab4382d2SGreg Kroah-Hartman */ 1458ab4382d2SGreg Kroah-Hartman div = 1; 1459ab4382d2SGreg Kroah-Hartman } else { 146009bd00f6SHubert Feurstein /* custom-baudrate handling */ 146109bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 146209bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 146309bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 146409bd00f6SHubert Feurstein 1465ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1466ab4382d2SGreg Kroah-Hartman if (div > 7) 1467ab4382d2SGreg Kroah-Hartman div = 7; 1468ab4382d2SGreg Kroah-Hartman if (!div) 1469ab4382d2SGreg Kroah-Hartman div = 1; 1470ab4382d2SGreg Kroah-Hartman } 1471ab4382d2SGreg Kroah-Hartman 1472ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1473ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1474ab4382d2SGreg Kroah-Hartman 1475ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1476ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1477ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1478ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1479ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1480ab4382d2SGreg Kroah-Hartman 1481ab4382d2SGreg Kroah-Hartman num -= 1; 1482ab4382d2SGreg Kroah-Hartman denom -= 1; 1483ab4382d2SGreg Kroah-Hartman 1484ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1485ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 148620ff2fe6SHuang Shijie if (sport->dte_mode) 148720ff2fe6SHuang Shijie ufcr |= UFCR_DCEDTE; 1488ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1489ab4382d2SGreg Kroah-Hartman 1490ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1491ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1492ab4382d2SGreg Kroah-Hartman 1493a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1494ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1495fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1496ab4382d2SGreg Kroah-Hartman 1497ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1498ab4382d2SGreg Kroah-Hartman 1499ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 1500ab4382d2SGreg Kroah-Hartman writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1501ab4382d2SGreg Kroah-Hartman 1502ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1503ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1504ab4382d2SGreg Kroah-Hartman 1505ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1506ab4382d2SGreg Kroah-Hartman } 1507ab4382d2SGreg Kroah-Hartman 1508ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1509ab4382d2SGreg Kroah-Hartman { 1510ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1511ab4382d2SGreg Kroah-Hartman 1512ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1513ab4382d2SGreg Kroah-Hartman } 1514ab4382d2SGreg Kroah-Hartman 1515ab4382d2SGreg Kroah-Hartman /* 1516ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1517ab4382d2SGreg Kroah-Hartman */ 1518ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1519ab4382d2SGreg Kroah-Hartman { 1520ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1521ab4382d2SGreg Kroah-Hartman 1522da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1523ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1524ab4382d2SGreg Kroah-Hartman } 1525ab4382d2SGreg Kroah-Hartman 1526ab4382d2SGreg Kroah-Hartman /* 1527ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1528ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1529ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1530ab4382d2SGreg Kroah-Hartman */ 1531ab4382d2SGreg Kroah-Hartman static int 1532ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1533ab4382d2SGreg Kroah-Hartman { 1534ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1535ab4382d2SGreg Kroah-Hartman int ret = 0; 1536ab4382d2SGreg Kroah-Hartman 1537ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1538ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1539ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1540ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1541ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1542ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1543ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1544ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1545a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1546ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1547ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1548ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1549ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1550ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1551ab4382d2SGreg Kroah-Hartman return ret; 1552ab4382d2SGreg Kroah-Hartman } 1553ab4382d2SGreg Kroah-Hartman 155401f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 15556b8bdad9SDaniel Thompson 15566b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 15576b8bdad9SDaniel Thompson { 15586b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 15596b8bdad9SDaniel Thompson unsigned long flags; 15606b8bdad9SDaniel Thompson unsigned long temp; 15616b8bdad9SDaniel Thompson int retval; 15626b8bdad9SDaniel Thompson 15636b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 15646b8bdad9SDaniel Thompson if (retval) 15656b8bdad9SDaniel Thompson return retval; 15666b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 15676b8bdad9SDaniel Thompson if (retval) 15686b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 15696b8bdad9SDaniel Thompson 15706b8bdad9SDaniel Thompson imx_setup_ufcr(sport, 0); 15716b8bdad9SDaniel Thompson 15726b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 15736b8bdad9SDaniel Thompson 15746b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR1); 15756b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 15766b8bdad9SDaniel Thompson temp |= IMX1_UCR1_UARTCLKEN; 15776b8bdad9SDaniel Thompson temp |= UCR1_UARTEN | UCR1_RRDYEN; 15786b8bdad9SDaniel Thompson temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 15796b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR1); 15806b8bdad9SDaniel Thompson 15816b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR2); 15826b8bdad9SDaniel Thompson temp |= UCR2_RXEN; 15836b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR2); 15846b8bdad9SDaniel Thompson 15856b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 15866b8bdad9SDaniel Thompson 15876b8bdad9SDaniel Thompson return 0; 15886b8bdad9SDaniel Thompson } 15896b8bdad9SDaniel Thompson 159001f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 159101f56abdSSaleem Abdulrasool { 1592f968ef34SDaniel Thompson if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 159326c47412SDirk Behme return NO_POLL_CHAR; 159401f56abdSSaleem Abdulrasool 1595f968ef34SDaniel Thompson return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 159601f56abdSSaleem Abdulrasool } 159701f56abdSSaleem Abdulrasool 159801f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 159901f56abdSSaleem Abdulrasool { 160001f56abdSSaleem Abdulrasool unsigned int status; 160101f56abdSSaleem Abdulrasool 160201f56abdSSaleem Abdulrasool /* drain */ 160301f56abdSSaleem Abdulrasool do { 1604f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR1); 160501f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 160601f56abdSSaleem Abdulrasool 160701f56abdSSaleem Abdulrasool /* write */ 1608f968ef34SDaniel Thompson writel_relaxed(c, port->membase + URTX0); 160901f56abdSSaleem Abdulrasool 161001f56abdSSaleem Abdulrasool /* flush */ 161101f56abdSSaleem Abdulrasool do { 1612f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR2); 161301f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 161401f56abdSSaleem Abdulrasool } 161501f56abdSSaleem Abdulrasool #endif 161601f56abdSSaleem Abdulrasool 1617ab4382d2SGreg Kroah-Hartman static struct uart_ops imx_pops = { 1618ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1619ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1620ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1621ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1622ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1623ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1624ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1625ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1626ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1627ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1628eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1629ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1630ab4382d2SGreg Kroah-Hartman .type = imx_type, 1631ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1632ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 163301f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 16346b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 163501f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 163601f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 163701f56abdSSaleem Abdulrasool #endif 1638ab4382d2SGreg Kroah-Hartman }; 1639ab4382d2SGreg Kroah-Hartman 1640ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1641ab4382d2SGreg Kroah-Hartman 1642ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1643ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1644ab4382d2SGreg Kroah-Hartman { 1645ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1646ab4382d2SGreg Kroah-Hartman 1647fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1648ab4382d2SGreg Kroah-Hartman barrier(); 1649ab4382d2SGreg Kroah-Hartman 1650ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1651ab4382d2SGreg Kroah-Hartman } 1652ab4382d2SGreg Kroah-Hartman 1653ab4382d2SGreg Kroah-Hartman /* 1654ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1655ab4382d2SGreg Kroah-Hartman */ 1656ab4382d2SGreg Kroah-Hartman static void 1657ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1658ab4382d2SGreg Kroah-Hartman { 1659ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 16600ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 16610ad5a814SDirk Behme unsigned int ucr1; 1662f30e8260SShawn Guo unsigned long flags = 0; 1663677fe555SThomas Gleixner int locked = 1; 16641cf93e0dSHuang Shijie int retval; 16651cf93e0dSHuang Shijie 16661cf93e0dSHuang Shijie retval = clk_enable(sport->clk_per); 16671cf93e0dSHuang Shijie if (retval) 16681cf93e0dSHuang Shijie return; 16691cf93e0dSHuang Shijie retval = clk_enable(sport->clk_ipg); 16701cf93e0dSHuang Shijie if (retval) { 16711cf93e0dSHuang Shijie clk_disable(sport->clk_per); 16721cf93e0dSHuang Shijie return; 16731cf93e0dSHuang Shijie } 16749ec1882dSXinyu Chen 1675677fe555SThomas Gleixner if (sport->port.sysrq) 1676677fe555SThomas Gleixner locked = 0; 1677677fe555SThomas Gleixner else if (oops_in_progress) 1678677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1679677fe555SThomas Gleixner else 16809ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1681ab4382d2SGreg Kroah-Hartman 1682ab4382d2SGreg Kroah-Hartman /* 16830ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1684ab4382d2SGreg Kroah-Hartman */ 16850ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 16860ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1687ab4382d2SGreg Kroah-Hartman 1688fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1689fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1690ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1691ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1692ab4382d2SGreg Kroah-Hartman 1693ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1694ab4382d2SGreg Kroah-Hartman 16950ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1696ab4382d2SGreg Kroah-Hartman 1697ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1698ab4382d2SGreg Kroah-Hartman 1699ab4382d2SGreg Kroah-Hartman /* 1700ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 17010ad5a814SDirk Behme * and restore UCR1/2/3 1702ab4382d2SGreg Kroah-Hartman */ 1703ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1704ab4382d2SGreg Kroah-Hartman 17050ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 17069ec1882dSXinyu Chen 1707677fe555SThomas Gleixner if (locked) 17089ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 17091cf93e0dSHuang Shijie 17101cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 17111cf93e0dSHuang Shijie clk_disable(sport->clk_per); 1712ab4382d2SGreg Kroah-Hartman } 1713ab4382d2SGreg Kroah-Hartman 1714ab4382d2SGreg Kroah-Hartman /* 1715ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1716ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1717ab4382d2SGreg Kroah-Hartman */ 1718ab4382d2SGreg Kroah-Hartman static void __init 1719ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1720ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1721ab4382d2SGreg Kroah-Hartman { 1722ab4382d2SGreg Kroah-Hartman 1723ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1724ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1725ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1726ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1727ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1728ab4382d2SGreg Kroah-Hartman 1729ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1730ab4382d2SGreg Kroah-Hartman 1731ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1732ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1733ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1734ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1735ab4382d2SGreg Kroah-Hartman else 1736ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1737ab4382d2SGreg Kroah-Hartman } 1738ab4382d2SGreg Kroah-Hartman 1739ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1740ab4382d2SGreg Kroah-Hartman *bits = 8; 1741ab4382d2SGreg Kroah-Hartman else 1742ab4382d2SGreg Kroah-Hartman *bits = 7; 1743ab4382d2SGreg Kroah-Hartman 1744ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1745ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1746ab4382d2SGreg Kroah-Hartman 1747ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1748ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1749ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1750ab4382d2SGreg Kroah-Hartman else 1751ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1752ab4382d2SGreg Kroah-Hartman 17533a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1754ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1755ab4382d2SGreg Kroah-Hartman 1756ab4382d2SGreg Kroah-Hartman { /* 1757ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1758ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1759ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1760ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1761ab4382d2SGreg Kroah-Hartman */ 1762ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1763ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1764ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1765ab4382d2SGreg Kroah-Hartman 1766ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1767ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1768ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1769ab4382d2SGreg Kroah-Hartman } 1770ab4382d2SGreg Kroah-Hartman 1771ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 177250bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1773ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1774ab4382d2SGreg Kroah-Hartman } 1775ab4382d2SGreg Kroah-Hartman } 1776ab4382d2SGreg Kroah-Hartman 1777ab4382d2SGreg Kroah-Hartman static int __init 1778ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1779ab4382d2SGreg Kroah-Hartman { 1780ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1781ab4382d2SGreg Kroah-Hartman int baud = 9600; 1782ab4382d2SGreg Kroah-Hartman int bits = 8; 1783ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1784ab4382d2SGreg Kroah-Hartman int flow = 'n'; 17851cf93e0dSHuang Shijie int retval; 1786ab4382d2SGreg Kroah-Hartman 1787ab4382d2SGreg Kroah-Hartman /* 1788ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1789ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1790ab4382d2SGreg Kroah-Hartman * console support. 1791ab4382d2SGreg Kroah-Hartman */ 1792ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1793ab4382d2SGreg Kroah-Hartman co->index = 0; 1794ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1795ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1796ab4382d2SGreg Kroah-Hartman return -ENODEV; 1797ab4382d2SGreg Kroah-Hartman 17981cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 17991cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 18001cf93e0dSHuang Shijie if (retval) 18011cf93e0dSHuang Shijie goto error_console; 18021cf93e0dSHuang Shijie 1803ab4382d2SGreg Kroah-Hartman if (options) 1804ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1805ab4382d2SGreg Kroah-Hartman else 1806ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1807ab4382d2SGreg Kroah-Hartman 1808ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1809ab4382d2SGreg Kroah-Hartman 18101cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 18111cf93e0dSHuang Shijie 18121cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 18131cf93e0dSHuang Shijie if (retval) { 18141cf93e0dSHuang Shijie clk_unprepare(sport->clk_ipg); 18151cf93e0dSHuang Shijie goto error_console; 18161cf93e0dSHuang Shijie } 18171cf93e0dSHuang Shijie 18181cf93e0dSHuang Shijie retval = clk_prepare(sport->clk_per); 18191cf93e0dSHuang Shijie if (retval) 18201cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 18211cf93e0dSHuang Shijie 18221cf93e0dSHuang Shijie error_console: 18231cf93e0dSHuang Shijie return retval; 1824ab4382d2SGreg Kroah-Hartman } 1825ab4382d2SGreg Kroah-Hartman 1826ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1827ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1828ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1829ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1830ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1831ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1832ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1833ab4382d2SGreg Kroah-Hartman .index = -1, 1834ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1835ab4382d2SGreg Kroah-Hartman }; 1836ab4382d2SGreg Kroah-Hartman 1837ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1838ab4382d2SGreg Kroah-Hartman #else 1839ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1840ab4382d2SGreg Kroah-Hartman #endif 1841ab4382d2SGreg Kroah-Hartman 1842ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1843ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1844ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 1845ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 1846ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 1847ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 1848ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 1849ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 1850ab4382d2SGreg Kroah-Hartman }; 1851ab4382d2SGreg Kroah-Hartman 1852ab4382d2SGreg Kroah-Hartman static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1853ab4382d2SGreg Kroah-Hartman { 1854ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1855db1a9b55SFabio Estevam unsigned int val; 1856db1a9b55SFabio Estevam 1857db1a9b55SFabio Estevam /* enable wakeup from i.MX UART */ 1858db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1859db1a9b55SFabio Estevam val |= UCR3_AWAKEN; 1860db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1861ab4382d2SGreg Kroah-Hartman 1862ab4382d2SGreg Kroah-Hartman uart_suspend_port(&imx_reg, &sport->port); 1863ab4382d2SGreg Kroah-Hartman 1864ab4382d2SGreg Kroah-Hartman return 0; 1865ab4382d2SGreg Kroah-Hartman } 1866ab4382d2SGreg Kroah-Hartman 1867ab4382d2SGreg Kroah-Hartman static int serial_imx_resume(struct platform_device *dev) 1868ab4382d2SGreg Kroah-Hartman { 1869ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1870db1a9b55SFabio Estevam unsigned int val; 1871db1a9b55SFabio Estevam 1872db1a9b55SFabio Estevam /* disable wakeup from i.MX UART */ 1873db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1874db1a9b55SFabio Estevam val &= ~UCR3_AWAKEN; 1875db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1876ab4382d2SGreg Kroah-Hartman 1877ab4382d2SGreg Kroah-Hartman uart_resume_port(&imx_reg, &sport->port); 1878ab4382d2SGreg Kroah-Hartman 1879ab4382d2SGreg Kroah-Hartman return 0; 1880ab4382d2SGreg Kroah-Hartman } 1881ab4382d2SGreg Kroah-Hartman 188222698aa2SShawn Guo #ifdef CONFIG_OF 188320bb8095SUwe Kleine-König /* 188420bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 188520bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 188620bb8095SUwe Kleine-König */ 188722698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 188822698aa2SShawn Guo struct platform_device *pdev) 188922698aa2SShawn Guo { 189022698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 189122698aa2SShawn Guo const struct of_device_id *of_id = 189222698aa2SShawn Guo of_match_device(imx_uart_dt_ids, &pdev->dev); 1893ff05967aSShawn Guo int ret; 189422698aa2SShawn Guo 189522698aa2SShawn Guo if (!np) 189620bb8095SUwe Kleine-König /* no device tree device */ 189720bb8095SUwe Kleine-König return 1; 189822698aa2SShawn Guo 1899ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 1900ff05967aSShawn Guo if (ret < 0) { 1901ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1902a197a191SUwe Kleine-König return ret; 1903ff05967aSShawn Guo } 1904ff05967aSShawn Guo sport->port.line = ret; 190522698aa2SShawn Guo 190622698aa2SShawn Guo if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 190722698aa2SShawn Guo sport->have_rtscts = 1; 190822698aa2SShawn Guo 190922698aa2SShawn Guo if (of_get_property(np, "fsl,irda-mode", NULL)) 191022698aa2SShawn Guo sport->use_irda = 1; 191122698aa2SShawn Guo 191220ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 191320ff2fe6SHuang Shijie sport->dte_mode = 1; 191420ff2fe6SHuang Shijie 191522698aa2SShawn Guo sport->devdata = of_id->data; 191622698aa2SShawn Guo 191722698aa2SShawn Guo return 0; 191822698aa2SShawn Guo } 191922698aa2SShawn Guo #else 192022698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 192122698aa2SShawn Guo struct platform_device *pdev) 192222698aa2SShawn Guo { 192320bb8095SUwe Kleine-König return 1; 192422698aa2SShawn Guo } 192522698aa2SShawn Guo #endif 192622698aa2SShawn Guo 192722698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 192822698aa2SShawn Guo struct platform_device *pdev) 192922698aa2SShawn Guo { 1930574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 193122698aa2SShawn Guo 193222698aa2SShawn Guo sport->port.line = pdev->id; 193322698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 193422698aa2SShawn Guo 193522698aa2SShawn Guo if (!pdata) 193622698aa2SShawn Guo return; 193722698aa2SShawn Guo 193822698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 193922698aa2SShawn Guo sport->have_rtscts = 1; 194022698aa2SShawn Guo 194122698aa2SShawn Guo if (pdata->flags & IMXUART_IRDA) 194222698aa2SShawn Guo sport->use_irda = 1; 194322698aa2SShawn Guo } 194422698aa2SShawn Guo 1945ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 1946ab4382d2SGreg Kroah-Hartman { 1947ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1948ab4382d2SGreg Kroah-Hartman void __iomem *base; 1949ab4382d2SGreg Kroah-Hartman int ret = 0; 1950ab4382d2SGreg Kroah-Hartman struct resource *res; 1951842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 1952ab4382d2SGreg Kroah-Hartman 195342d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1954ab4382d2SGreg Kroah-Hartman if (!sport) 1955ab4382d2SGreg Kroah-Hartman return -ENOMEM; 1956ab4382d2SGreg Kroah-Hartman 195722698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 195820bb8095SUwe Kleine-König if (ret > 0) 195922698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 196020bb8095SUwe Kleine-König else if (ret < 0) 196142d34191SSachin Kamat return ret; 196222698aa2SShawn Guo 1963ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1964da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 1965da82f997SAlexander Shiyan if (IS_ERR(base)) 1966da82f997SAlexander Shiyan return PTR_ERR(base); 1967ab4382d2SGreg Kroah-Hartman 1968842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 1969842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 1970842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 1971842633bdSUwe Kleine-König 1972ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 1973ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 1974ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 1975ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 1976ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 1977842633bdSUwe Kleine-König sport->port.irq = rxirq; 1978ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 1979ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 1980ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 1981ab4382d2SGreg Kroah-Hartman init_timer(&sport->timer); 1982ab4382d2SGreg Kroah-Hartman sport->timer.function = imx_timeout; 1983ab4382d2SGreg Kroah-Hartman sport->timer.data = (unsigned long)sport; 1984ab4382d2SGreg Kroah-Hartman 19853a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 19863a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 19873a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 1988833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 198942d34191SSachin Kamat return ret; 1990ab4382d2SGreg Kroah-Hartman } 1991ab4382d2SGreg Kroah-Hartman 19923a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 19933a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 19943a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 1995833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 199642d34191SSachin Kamat return ret; 19973a9465faSSascha Hauer } 19983a9465faSSascha Hauer 19993a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2000ab4382d2SGreg Kroah-Hartman 2001c0d1c6b0SFabio Estevam /* 2002c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2003c0d1c6b0SFabio Estevam * chips only have one interrupt. 2004c0d1c6b0SFabio Estevam */ 2005842633bdSUwe Kleine-König if (txirq > 0) { 2006842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2007c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2008c0d1c6b0SFabio Estevam if (ret) 2009c0d1c6b0SFabio Estevam return ret; 2010c0d1c6b0SFabio Estevam 2011842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2012c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2013c0d1c6b0SFabio Estevam if (ret) 2014c0d1c6b0SFabio Estevam return ret; 2015c0d1c6b0SFabio Estevam 2016c0d1c6b0SFabio Estevam /* do not use RTS IRQ on IrDA */ 2017c0d1c6b0SFabio Estevam if (!USE_IRDA(sport)) { 2018842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, 2019c0d1c6b0SFabio Estevam imx_rtsint, 0, 2020c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2021c0d1c6b0SFabio Estevam if (ret) 2022c0d1c6b0SFabio Estevam return ret; 2023c0d1c6b0SFabio Estevam } 2024c0d1c6b0SFabio Estevam } else { 2025842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2026c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2027c0d1c6b0SFabio Estevam if (ret) 2028c0d1c6b0SFabio Estevam return ret; 2029c0d1c6b0SFabio Estevam } 2030c0d1c6b0SFabio Estevam 203122698aa2SShawn Guo imx_ports[sport->port.line] = sport; 2032ab4382d2SGreg Kroah-Hartman 20330a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2034ab4382d2SGreg Kroah-Hartman 203545af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2036ab4382d2SGreg Kroah-Hartman } 2037ab4382d2SGreg Kroah-Hartman 2038ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2039ab4382d2SGreg Kroah-Hartman { 2040ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2041ab4382d2SGreg Kroah-Hartman 204245af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2043ab4382d2SGreg Kroah-Hartman } 2044ab4382d2SGreg Kroah-Hartman 2045ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2046ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2047ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2048ab4382d2SGreg Kroah-Hartman 2049ab4382d2SGreg Kroah-Hartman .suspend = serial_imx_suspend, 2050ab4382d2SGreg Kroah-Hartman .resume = serial_imx_resume, 2051fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2052ab4382d2SGreg Kroah-Hartman .driver = { 2053ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 205422698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 2055ab4382d2SGreg Kroah-Hartman }, 2056ab4382d2SGreg Kroah-Hartman }; 2057ab4382d2SGreg Kroah-Hartman 2058ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2059ab4382d2SGreg Kroah-Hartman { 2060f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2061ab4382d2SGreg Kroah-Hartman 2062ab4382d2SGreg Kroah-Hartman if (ret) 2063ab4382d2SGreg Kroah-Hartman return ret; 2064ab4382d2SGreg Kroah-Hartman 2065ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2066ab4382d2SGreg Kroah-Hartman if (ret != 0) 2067ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2068ab4382d2SGreg Kroah-Hartman 2069f227824eSUwe Kleine-König return ret; 2070ab4382d2SGreg Kroah-Hartman } 2071ab4382d2SGreg Kroah-Hartman 2072ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2073ab4382d2SGreg Kroah-Hartman { 2074ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2075ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2076ab4382d2SGreg Kroah-Hartman } 2077ab4382d2SGreg Kroah-Hartman 2078ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2079ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2080ab4382d2SGreg Kroah-Hartman 2081ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2082ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2083ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2084ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2085