1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 12ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 13ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 14ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 15ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 23bd78ecd6SAhmad Fatoum #include <linux/ktime.h> 24fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2722698aa2SShawn Guo #include <linux/of.h> 2822698aa2SShawn Guo #include <linux/of_device.h> 29e32a9f8fSSachin Kamat #include <linux/io.h> 30b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 31ab4382d2SGreg Kroah-Hartman 32ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 3382906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 34b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 35ab4382d2SGreg Kroah-Hartman 3658362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3758362d5bSUwe Kleine-König 38ab4382d2SGreg Kroah-Hartman /* Register definitions */ 39ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 40ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 41ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 42ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 43ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 44ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 45ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 46ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 47ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 48ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 49ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 50ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 51ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 52ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 53fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 54fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 55fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 56ab4382d2SGreg Kroah-Hartman 57ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 5855d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 59ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 60ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 61ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 62ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 63ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 64ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6526c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6625985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 67ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 68ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 69ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 70b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 71ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 72302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 77302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 78fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 79b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 81ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 82ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 83ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9201f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 96ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 97ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 101ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 102b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 105ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10627e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 107fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 109ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 110ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 111ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 115ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 116b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1237be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 125ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 126ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 127ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 128ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 129ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 130ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 131ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 133ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13486a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13527e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 136ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 137ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 138ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 140ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 141ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 142ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14390ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14490ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 145ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 146ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14790ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 148ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 150ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 151ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 152ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 153ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 154ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 155ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 156ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 157ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 158ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 159ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 160ab4382d2SGreg Kroah-Hartman 161ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 162ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 163ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 164ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 165ab4382d2SGreg Kroah-Hartman 166ab4382d2SGreg Kroah-Hartman /* 167ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 168ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 169ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 170ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 171ab4382d2SGreg Kroah-Hartman */ 172ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 173ab4382d2SGreg Kroah-Hartman 174ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 175ab4382d2SGreg Kroah-Hartman 176ab4382d2SGreg Kroah-Hartman #define UART_NR 8 177ab4382d2SGreg Kroah-Hartman 178f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 179fe6b540aSShawn Guo enum imx_uart_type { 180fe6b540aSShawn Guo IMX1_UART, 181fe6b540aSShawn Guo IMX21_UART, 1821c06bde6SMartyn Welch IMX53_UART, 183a496e628SHuang Shijie IMX6Q_UART, 184fe6b540aSShawn Guo }; 185fe6b540aSShawn Guo 186fe6b540aSShawn Guo /* device type dependent stuff */ 187fe6b540aSShawn Guo struct imx_uart_data { 188fe6b540aSShawn Guo unsigned uts_reg; 189fe6b540aSShawn Guo enum imx_uart_type devtype; 190fe6b540aSShawn Guo }; 191fe6b540aSShawn Guo 192cb1a6092SUwe Kleine-König enum imx_tx_state { 193cb1a6092SUwe Kleine-König OFF, 194cb1a6092SUwe Kleine-König WAIT_AFTER_RTS, 195cb1a6092SUwe Kleine-König SEND, 196cb1a6092SUwe Kleine-König WAIT_AFTER_SEND, 197cb1a6092SUwe Kleine-König }; 198cb1a6092SUwe Kleine-König 199ab4382d2SGreg Kroah-Hartman struct imx_port { 200ab4382d2SGreg Kroah-Hartman struct uart_port port; 201ab4382d2SGreg Kroah-Hartman struct timer_list timer; 202ab4382d2SGreg Kroah-Hartman unsigned int old_status; 203ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2047b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20520ff2fe6SHuang Shijie unsigned int dte_mode:1; 2065a08a487SGeorge Hilliard unsigned int inverted_tx:1; 2075a08a487SGeorge Hilliard unsigned int inverted_rx:1; 2083a9465faSSascha Hauer struct clk *clk_ipg; 2093a9465faSSascha Hauer struct clk *clk_per; 2107d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 211b4cdc8f6SHuang Shijie 21258362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21358362d5bSUwe Kleine-König 2143a0ab62fSUwe Kleine-König /* shadow registers */ 2153a0ab62fSUwe Kleine-König unsigned int ucr1; 2163a0ab62fSUwe Kleine-König unsigned int ucr2; 2173a0ab62fSUwe Kleine-König unsigned int ucr3; 2183a0ab62fSUwe Kleine-König unsigned int ucr4; 2193a0ab62fSUwe Kleine-König unsigned int ufcr; 2203a0ab62fSUwe Kleine-König 221b4cdc8f6SHuang Shijie /* DMA fields */ 222b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 224b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 225b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 226b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 227b4cdc8f6SHuang Shijie void *rx_buf; 2289d297239SNandor Han struct circ_buf rx_ring; 2299d297239SNandor Han unsigned int rx_periods; 2309d297239SNandor Han dma_cookie_t rx_cookie; 2317cb92fd2SHuang Shijie unsigned int tx_bytes; 232b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 23390bb6bd3SShenwei Wang unsigned int saved_reg[10]; 234c868cbb7SEduardo Valentin bool context_saved; 235cb1a6092SUwe Kleine-König 236cb1a6092SUwe Kleine-König enum imx_tx_state tx_state; 237bd78ecd6SAhmad Fatoum struct hrtimer trigger_start_tx; 238bd78ecd6SAhmad Fatoum struct hrtimer trigger_stop_tx; 239ab4382d2SGreg Kroah-Hartman }; 240ab4382d2SGreg Kroah-Hartman 2410ad5a814SDirk Behme struct imx_port_ucrs { 2420ad5a814SDirk Behme unsigned int ucr1; 2430ad5a814SDirk Behme unsigned int ucr2; 2440ad5a814SDirk Behme unsigned int ucr3; 2450ad5a814SDirk Behme }; 2460ad5a814SDirk Behme 247fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 248fe6b540aSShawn Guo [IMX1_UART] = { 249fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 250fe6b540aSShawn Guo .devtype = IMX1_UART, 251fe6b540aSShawn Guo }, 252fe6b540aSShawn Guo [IMX21_UART] = { 253fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 254fe6b540aSShawn Guo .devtype = IMX21_UART, 255fe6b540aSShawn Guo }, 2561c06bde6SMartyn Welch [IMX53_UART] = { 2571c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2581c06bde6SMartyn Welch .devtype = IMX53_UART, 2591c06bde6SMartyn Welch }, 260a496e628SHuang Shijie [IMX6Q_UART] = { 261a496e628SHuang Shijie .uts_reg = IMX21_UTS, 262a496e628SHuang Shijie .devtype = IMX6Q_UART, 263a496e628SHuang Shijie }, 264fe6b540aSShawn Guo }; 265fe6b540aSShawn Guo 26631ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 267fe6b540aSShawn Guo { 268fe6b540aSShawn Guo .name = "imx1-uart", 269fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 270fe6b540aSShawn Guo }, { 271fe6b540aSShawn Guo .name = "imx21-uart", 272fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 273fe6b540aSShawn Guo }, { 2741c06bde6SMartyn Welch .name = "imx53-uart", 2751c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2761c06bde6SMartyn Welch }, { 277a496e628SHuang Shijie .name = "imx6q-uart", 278a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 279a496e628SHuang Shijie }, { 280fe6b540aSShawn Guo /* sentinel */ 281fe6b540aSShawn Guo } 282fe6b540aSShawn Guo }; 283fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 284fe6b540aSShawn Guo 285ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 286a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2871c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 28822698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 28922698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 29022698aa2SShawn Guo { /* sentinel */ } 29122698aa2SShawn Guo }; 29222698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 29322698aa2SShawn Guo 29427c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 29527c84426SUwe Kleine-König { 2963a0ab62fSUwe Kleine-König switch (offset) { 2973a0ab62fSUwe Kleine-König case UCR1: 2983a0ab62fSUwe Kleine-König sport->ucr1 = val; 2993a0ab62fSUwe Kleine-König break; 3003a0ab62fSUwe Kleine-König case UCR2: 3013a0ab62fSUwe Kleine-König sport->ucr2 = val; 3023a0ab62fSUwe Kleine-König break; 3033a0ab62fSUwe Kleine-König case UCR3: 3043a0ab62fSUwe Kleine-König sport->ucr3 = val; 3053a0ab62fSUwe Kleine-König break; 3063a0ab62fSUwe Kleine-König case UCR4: 3073a0ab62fSUwe Kleine-König sport->ucr4 = val; 3083a0ab62fSUwe Kleine-König break; 3093a0ab62fSUwe Kleine-König case UFCR: 3103a0ab62fSUwe Kleine-König sport->ufcr = val; 3113a0ab62fSUwe Kleine-König break; 3123a0ab62fSUwe Kleine-König default: 3133a0ab62fSUwe Kleine-König break; 3143a0ab62fSUwe Kleine-König } 31527c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 31627c84426SUwe Kleine-König } 31727c84426SUwe Kleine-König 31827c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 31927c84426SUwe Kleine-König { 3203a0ab62fSUwe Kleine-König switch (offset) { 3213a0ab62fSUwe Kleine-König case UCR1: 3223a0ab62fSUwe Kleine-König return sport->ucr1; 3233a0ab62fSUwe Kleine-König break; 3243a0ab62fSUwe Kleine-König case UCR2: 3253a0ab62fSUwe Kleine-König /* 3263a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3273a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 328728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 329728e74a4SUwe Kleine-König * conditionally. 3303a0ab62fSUwe Kleine-König */ 3310aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3323a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3333a0ab62fSUwe Kleine-König return sport->ucr2; 3343a0ab62fSUwe Kleine-König break; 3353a0ab62fSUwe Kleine-König case UCR3: 3363a0ab62fSUwe Kleine-König return sport->ucr3; 3373a0ab62fSUwe Kleine-König break; 3383a0ab62fSUwe Kleine-König case UCR4: 3393a0ab62fSUwe Kleine-König return sport->ucr4; 3403a0ab62fSUwe Kleine-König break; 3413a0ab62fSUwe Kleine-König case UFCR: 3423a0ab62fSUwe Kleine-König return sport->ufcr; 3433a0ab62fSUwe Kleine-König break; 3443a0ab62fSUwe Kleine-König default: 34527c84426SUwe Kleine-König return readl(sport->port.membase + offset); 34627c84426SUwe Kleine-König } 3473a0ab62fSUwe Kleine-König } 34827c84426SUwe Kleine-König 3499d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 350fe6b540aSShawn Guo { 351fe6b540aSShawn Guo return sport->devdata->uts_reg; 352fe6b540aSShawn Guo } 353fe6b540aSShawn Guo 3549d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 355fe6b540aSShawn Guo { 356fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 357fe6b540aSShawn Guo } 358fe6b540aSShawn Guo 3599d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 360fe6b540aSShawn Guo { 361fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 362fe6b540aSShawn Guo } 363fe6b540aSShawn Guo 3649d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3651c06bde6SMartyn Welch { 3661c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3671c06bde6SMartyn Welch } 3681c06bde6SMartyn Welch 3699d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 370a496e628SHuang Shijie { 371a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 372a496e628SHuang Shijie } 373ab4382d2SGreg Kroah-Hartman /* 37444a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 37544a75411Sfabio.estevam@freescale.com */ 3760db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 3779d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 37844a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37944a75411Sfabio.estevam@freescale.com { 38044a75411Sfabio.estevam@freescale.com /* save control registers */ 38127c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 38227c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 38327c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 38444a75411Sfabio.estevam@freescale.com } 38544a75411Sfabio.estevam@freescale.com 3869d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 38744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 38844a75411Sfabio.estevam@freescale.com { 38944a75411Sfabio.estevam@freescale.com /* restore control registers */ 39027c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 39127c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 39227c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 39344a75411Sfabio.estevam@freescale.com } 394e8bfa760SFabio Estevam #endif 39544a75411Sfabio.estevam@freescale.com 3964e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3979d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 39858362d5bSUwe Kleine-König { 399bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 40058362d5bSUwe Kleine-König 401a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 402a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 40358362d5bSUwe Kleine-König } 40458362d5bSUwe Kleine-König 4054e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 4069d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 40758362d5bSUwe Kleine-König { 408bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 409bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 41058362d5bSUwe Kleine-König 411a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 412a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 41358362d5bSUwe Kleine-König } 41458362d5bSUwe Kleine-König 415bd78ecd6SAhmad Fatoum static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 416bd78ecd6SAhmad Fatoum { 417bd78ecd6SAhmad Fatoum long sec = msec / MSEC_PER_SEC; 418bd78ecd6SAhmad Fatoum long nsec = (msec % MSEC_PER_SEC) * 1000000; 419bd78ecd6SAhmad Fatoum ktime_t t = ktime_set(sec, nsec); 420bd78ecd6SAhmad Fatoum 421bd78ecd6SAhmad Fatoum hrtimer_start(hrt, t, HRTIMER_MODE_REL); 422bd78ecd6SAhmad Fatoum } 423bd78ecd6SAhmad Fatoum 4246aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4259d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 42676821e22SUwe Kleine-König { 42776821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 42876821e22SUwe Kleine-König unsigned int ucr1, ucr2; 42976821e22SUwe Kleine-König 43076821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 43176821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 43276821e22SUwe Kleine-König 43376821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 43476821e22SUwe Kleine-König 43576821e22SUwe Kleine-König if (sport->dma_is_enabled) { 43676821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 43776821e22SUwe Kleine-König } else { 43876821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 43981ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 44076821e22SUwe Kleine-König } 44176821e22SUwe Kleine-König 44276821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 44376821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 44476821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 44576821e22SUwe Kleine-König } 44676821e22SUwe Kleine-König 44776821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4489d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 449ab4382d2SGreg Kroah-Hartman { 450ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 451cb1a6092SUwe Kleine-König u32 ucr1, ucr4, usr2; 452cb1a6092SUwe Kleine-König 453cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) 454cb1a6092SUwe Kleine-König return; 455ab4382d2SGreg Kroah-Hartman 4569ce4f8f3SGreg Kroah-Hartman /* 4579ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4589ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4599ce4f8f3SGreg Kroah-Hartman */ 460686351f3SUwe Kleine-König if (sport->dma_is_txing) 4619ce4f8f3SGreg Kroah-Hartman return; 462b4cdc8f6SHuang Shijie 4634444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 464c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 46517b8f2a3SUwe Kleine-König 466cb1a6092SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 467cb1a6092SUwe Kleine-König if (!(usr2 & USR2_TXDC)) { 468cb1a6092SUwe Kleine-König /* The shifter is still busy, so retry once TC triggers */ 469cb1a6092SUwe Kleine-König return; 470cb1a6092SUwe Kleine-König } 471cb1a6092SUwe Kleine-König 472cb1a6092SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 473cb1a6092SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 474cb1a6092SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 475cb1a6092SUwe Kleine-König 476cb1a6092SUwe Kleine-König /* in rs485 mode disable transmitter */ 477cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 478cb1a6092SUwe Kleine-König if (sport->tx_state == SEND) { 479cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_SEND; 480bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_stop_tx, 481bd78ecd6SAhmad Fatoum port->rs485.delay_rts_after_send); 482bd78ecd6SAhmad Fatoum return; 483cb1a6092SUwe Kleine-König } 484cb1a6092SUwe Kleine-König 485cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS || 486bd78ecd6SAhmad Fatoum sport->tx_state == WAIT_AFTER_SEND) { 487cb1a6092SUwe Kleine-König u32 ucr2; 488cb1a6092SUwe Kleine-König 489bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_start_tx); 490cb1a6092SUwe Kleine-König 491cb1a6092SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 49217b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4939d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4941a613626SFabio Estevam else 4959d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4964444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 49717b8f2a3SUwe Kleine-König 4989d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 49976821e22SUwe Kleine-König 500cb1a6092SUwe Kleine-König sport->tx_state = OFF; 501cb1a6092SUwe Kleine-König } 502cb1a6092SUwe Kleine-König } else { 503cb1a6092SUwe Kleine-König sport->tx_state = OFF; 50417b8f2a3SUwe Kleine-König } 505ab4382d2SGreg Kroah-Hartman } 506ab4382d2SGreg Kroah-Hartman 5076aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5089d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 509ab4382d2SGreg Kroah-Hartman { 510ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 5114444dcf1SUwe Kleine-König u32 ucr1, ucr2; 512ab4382d2SGreg Kroah-Hartman 5134444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 51476821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 51576821e22SUwe Kleine-König 51676821e22SUwe Kleine-König if (sport->dma_is_enabled) { 51776821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 51876821e22SUwe Kleine-König } else { 51976821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 52081ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 52176821e22SUwe Kleine-König } 52276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 52376821e22SUwe Kleine-König 52476821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 52576821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 526ab4382d2SGreg Kroah-Hartman } 527ab4382d2SGreg Kroah-Hartman 5286aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5299d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 530ab4382d2SGreg Kroah-Hartman { 531ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 532ab4382d2SGreg Kroah-Hartman 533ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 53458362d5bSUwe Kleine-König 53558362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 536ab4382d2SGreg Kroah-Hartman } 537ab4382d2SGreg Kroah-Hartman 5389d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 5396aed2a88SUwe Kleine-König 5406aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5419d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 542ab4382d2SGreg Kroah-Hartman { 543ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 544ab4382d2SGreg Kroah-Hartman 5455e42e9a3SPeter Hurley if (sport->port.x_char) { 5465e42e9a3SPeter Hurley /* Send next char */ 54727c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5487e2fb5aaSJiada Wang sport->port.icount.tx++; 5497e2fb5aaSJiada Wang sport->port.x_char = 0; 5505e42e9a3SPeter Hurley return; 5515e42e9a3SPeter Hurley } 5525e42e9a3SPeter Hurley 5535e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5549d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5555e42e9a3SPeter Hurley return; 5565e42e9a3SPeter Hurley } 5575e42e9a3SPeter Hurley 55891a1a909SJiada Wang if (sport->dma_is_enabled) { 5594444dcf1SUwe Kleine-König u32 ucr1; 56091a1a909SJiada Wang /* 56191a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 56291a1a909SJiada Wang * and the TX IRQ is disabled. 56391a1a909SJiada Wang **/ 5644444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 565c514a6f8SSergey Organov ucr1 &= ~UCR1_TRDYEN; 56691a1a909SJiada Wang if (sport->dma_is_txing) { 5674444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5684444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 56991a1a909SJiada Wang } else { 5704444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5719d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 57291a1a909SJiada Wang } 57391a1a909SJiada Wang 5745aabd3b0SIan Jamison return; 5750c549223SUwe Kleine-König } 5765aabd3b0SIan Jamison 5775aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5789d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 579ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 580ab4382d2SGreg Kroah-Hartman * out the port here */ 58127c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 582ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 583ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 584ab4382d2SGreg Kroah-Hartman } 585ab4382d2SGreg Kroah-Hartman 586ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 587ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 588ab4382d2SGreg Kroah-Hartman 589ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5909d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 591ab4382d2SGreg Kroah-Hartman } 592ab4382d2SGreg Kroah-Hartman 5939d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 594b4cdc8f6SHuang Shijie { 595b4cdc8f6SHuang Shijie struct imx_port *sport = data; 596b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 597b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 598b4cdc8f6SHuang Shijie unsigned long flags; 5994444dcf1SUwe Kleine-König u32 ucr1; 600b4cdc8f6SHuang Shijie 60142f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 60242f752b3SDirk Behme 603b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 604b4cdc8f6SHuang Shijie 6054444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6064444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 6074444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 608a2c718ceSDirk Behme 60942f752b3SDirk Behme /* update the stat */ 61042f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 61142f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 61242f752b3SDirk Behme 61342f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 61442f752b3SDirk Behme 615b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 616b4cdc8f6SHuang Shijie 617d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 618b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 6199ce4f8f3SGreg Kroah-Hartman 6200bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 6219d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 62218665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 62318665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 62418665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 62518665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 62618665414SUwe Kleine-König } 62764432a85SUwe Kleine-König 6280bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 629b4cdc8f6SHuang Shijie } 630b4cdc8f6SHuang Shijie 6316aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6329d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 633b4cdc8f6SHuang Shijie { 634b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 635b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 636b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 637b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 638b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 63918665414SUwe Kleine-König u32 ucr1, ucr4; 640b4cdc8f6SHuang Shijie int ret; 641b4cdc8f6SHuang Shijie 64242f752b3SDirk Behme if (sport->dma_is_txing) 643b4cdc8f6SHuang Shijie return; 644b4cdc8f6SHuang Shijie 64518665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 64618665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 64718665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 64818665414SUwe Kleine-König 649b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 650b4cdc8f6SHuang Shijie 651f7670783SFugang Duan if (xmit->tail < xmit->head || xmit->head == 0) { 6527942f857SDirk Behme sport->dma_tx_nents = 1; 6537942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6547942f857SDirk Behme } else { 655b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 656b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 657b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 658b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 659b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 660b4cdc8f6SHuang Shijie } 661b4cdc8f6SHuang Shijie 662b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 663b4cdc8f6SHuang Shijie if (ret == 0) { 664b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 665b4cdc8f6SHuang Shijie return; 666b4cdc8f6SHuang Shijie } 667596fd8dfSPeng Fan desc = dmaengine_prep_slave_sg(chan, sgl, ret, 668b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 669b4cdc8f6SHuang Shijie if (!desc) { 67024649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 67124649821SDirk Behme DMA_TO_DEVICE); 672b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 673b4cdc8f6SHuang Shijie return; 674b4cdc8f6SHuang Shijie } 6759d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 676b4cdc8f6SHuang Shijie desc->callback_param = sport; 677b4cdc8f6SHuang Shijie 678b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 679b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 680a2c718ceSDirk Behme 6814444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6824444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 684a2c718ceSDirk Behme 685b4cdc8f6SHuang Shijie /* fire it */ 686b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 687b4cdc8f6SHuang Shijie dmaengine_submit(desc); 688b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 689b4cdc8f6SHuang Shijie return; 690b4cdc8f6SHuang Shijie } 691b4cdc8f6SHuang Shijie 6926aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6939d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 694ab4382d2SGreg Kroah-Hartman { 695ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6964444dcf1SUwe Kleine-König u32 ucr1; 697ab4382d2SGreg Kroah-Hartman 69848669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 69948669b69SUwe Kleine-König return; 70048669b69SUwe Kleine-König 701cb1a6092SUwe Kleine-König /* 702cb1a6092SUwe Kleine-König * We cannot simply do nothing here if sport->tx_state == SEND already 703cb1a6092SUwe Kleine-König * because UCR1_TXMPTYEN might already have been cleared in 704cb1a6092SUwe Kleine-König * imx_uart_stop_tx(), but tx_state is still SEND. 705cb1a6092SUwe Kleine-König */ 7064444dcf1SUwe Kleine-König 707cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 708cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) { 709cb1a6092SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2); 71017b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 7119d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 7121a613626SFabio Estevam else 7139d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 7144444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 71517b8f2a3SUwe Kleine-König 71676821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 7179d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 71876821e22SUwe Kleine-König 719cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_RTS; 720bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_start_tx, 721bd78ecd6SAhmad Fatoum port->rs485.delay_rts_before_send); 722bd78ecd6SAhmad Fatoum return; 723cb1a6092SUwe Kleine-König } 724cb1a6092SUwe Kleine-König 725bd78ecd6SAhmad Fatoum if (sport->tx_state == WAIT_AFTER_SEND 726bd78ecd6SAhmad Fatoum || sport->tx_state == WAIT_AFTER_RTS) { 727cb1a6092SUwe Kleine-König 728bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_stop_tx); 729bd78ecd6SAhmad Fatoum 73018665414SUwe Kleine-König /* 731cb1a6092SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA 732cb1a6092SUwe Kleine-König * is off. In the DMA case this is done in the 733cb1a6092SUwe Kleine-König * tx-callback. 73418665414SUwe Kleine-König */ 73518665414SUwe Kleine-König if (!sport->dma_is_enabled) { 73618665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 7374444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 7384444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 73917b8f2a3SUwe Kleine-König } 740cb1a6092SUwe Kleine-König 741cb1a6092SUwe Kleine-König sport->tx_state = SEND; 742cb1a6092SUwe Kleine-König } 743cb1a6092SUwe Kleine-König } else { 744cb1a6092SUwe Kleine-König sport->tx_state = SEND; 74518665414SUwe Kleine-König } 74617b8f2a3SUwe Kleine-König 747b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 7484444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 749c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 750b4cdc8f6SHuang Shijie } 751ab4382d2SGreg Kroah-Hartman 752b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 75391a1a909SJiada Wang if (sport->port.x_char) { 75491a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 75591a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 7564444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 7574444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 758c514a6f8SSergey Organov ucr1 |= UCR1_TRDYEN; 7594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 76091a1a909SJiada Wang return; 76191a1a909SJiada Wang } 76291a1a909SJiada Wang 7635e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 7645e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7659d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 766b4cdc8f6SHuang Shijie return; 767b4cdc8f6SHuang Shijie } 768ab4382d2SGreg Kroah-Hartman } 769ab4382d2SGreg Kroah-Hartman 770101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 771ab4382d2SGreg Kroah-Hartman { 772ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7734444dcf1SUwe Kleine-König u32 usr1; 774ab4382d2SGreg Kroah-Hartman 77527c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7764444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7774444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 778ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 779ab4382d2SGreg Kroah-Hartman 780ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 781ab4382d2SGreg Kroah-Hartman } 782ab4382d2SGreg Kroah-Hartman 783101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 784101aa46bSUwe Kleine-König { 785101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 786101aa46bSUwe Kleine-König irqreturn_t ret; 787101aa46bSUwe Kleine-König 788101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 789101aa46bSUwe Kleine-König 790101aa46bSUwe Kleine-König ret = __imx_uart_rtsint(irq, dev_id); 791101aa46bSUwe Kleine-König 792101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 793101aa46bSUwe Kleine-König 794101aa46bSUwe Kleine-König return ret; 795101aa46bSUwe Kleine-König } 796101aa46bSUwe Kleine-König 7979d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 798ab4382d2SGreg Kroah-Hartman { 799ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 800ab4382d2SGreg Kroah-Hartman 801c974991dSjun qian spin_lock(&sport->port.lock); 8029d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 803c974991dSjun qian spin_unlock(&sport->port.lock); 804ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 805ab4382d2SGreg Kroah-Hartman } 806ab4382d2SGreg Kroah-Hartman 807101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 808ab4382d2SGreg Kroah-Hartman { 809ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 810ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 81192a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 812ab4382d2SGreg Kroah-Hartman 81327c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 8144444dcf1SUwe Kleine-König u32 usr2; 8154444dcf1SUwe Kleine-König 816ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 817ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 818ab4382d2SGreg Kroah-Hartman 81927c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 820ab4382d2SGreg Kroah-Hartman 8214444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 8224444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 82327c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 824ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 825ab4382d2SGreg Kroah-Hartman continue; 826ab4382d2SGreg Kroah-Hartman } 827ab4382d2SGreg Kroah-Hartman 828ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 829ab4382d2SGreg Kroah-Hartman continue; 830ab4382d2SGreg Kroah-Hartman 831019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 832019dc9eaSHui Wang if (rx & URXD_BRK) 833019dc9eaSHui Wang sport->port.icount.brk++; 834019dc9eaSHui Wang else if (rx & URXD_PRERR) 835ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 836ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 837ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 838ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 839ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 840ab4382d2SGreg Kroah-Hartman 841ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 842ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 843ab4382d2SGreg Kroah-Hartman goto out; 844ab4382d2SGreg Kroah-Hartman continue; 845ab4382d2SGreg Kroah-Hartman } 846ab4382d2SGreg Kroah-Hartman 8478d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 848ab4382d2SGreg Kroah-Hartman 849019dc9eaSHui Wang if (rx & URXD_BRK) 850019dc9eaSHui Wang flg = TTY_BREAK; 851019dc9eaSHui Wang else if (rx & URXD_PRERR) 852ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 853ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 854ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 855ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 856ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 857ab4382d2SGreg Kroah-Hartman 858ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 859ab4382d2SGreg Kroah-Hartman } 860ab4382d2SGreg Kroah-Hartman 86155d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 86255d8693aSJiada Wang goto out; 86355d8693aSJiada Wang 8649b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 8659b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 866ab4382d2SGreg Kroah-Hartman } 867ab4382d2SGreg Kroah-Hartman 868ab4382d2SGreg Kroah-Hartman out: 8692e124b4aSJiri Slaby tty_flip_buffer_push(port); 870101aa46bSUwe Kleine-König 871ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 872ab4382d2SGreg Kroah-Hartman } 873ab4382d2SGreg Kroah-Hartman 874101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 875101aa46bSUwe Kleine-König { 876101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 877101aa46bSUwe Kleine-König irqreturn_t ret; 878101aa46bSUwe Kleine-König 879101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 880101aa46bSUwe Kleine-König 881101aa46bSUwe Kleine-König ret = __imx_uart_rxint(irq, dev_id); 882101aa46bSUwe Kleine-König 883101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 884101aa46bSUwe Kleine-König 885101aa46bSUwe Kleine-König return ret; 886101aa46bSUwe Kleine-König } 887101aa46bSUwe Kleine-König 8889d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 889b4cdc8f6SHuang Shijie 89066f95884SUwe Kleine-König /* 89166f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 89266f95884SUwe Kleine-König */ 8939d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 89466f95884SUwe Kleine-König { 89566f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 89627c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 89727c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 89866f95884SUwe Kleine-König 89966f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 90066f95884SUwe Kleine-König tmp |= TIOCM_CTS; 90166f95884SUwe Kleine-König 90266f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 9034b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 90466f95884SUwe Kleine-König tmp |= TIOCM_CAR; 90566f95884SUwe Kleine-König 90666f95884SUwe Kleine-König if (sport->dte_mode) 90727c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 90866f95884SUwe Kleine-König tmp |= TIOCM_RI; 90966f95884SUwe Kleine-König 91066f95884SUwe Kleine-König return tmp; 91166f95884SUwe Kleine-König } 91266f95884SUwe Kleine-König 91366f95884SUwe Kleine-König /* 91466f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 91566f95884SUwe Kleine-König */ 9169d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 91766f95884SUwe Kleine-König { 91866f95884SUwe Kleine-König unsigned int status, changed; 91966f95884SUwe Kleine-König 9209d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 92166f95884SUwe Kleine-König changed = status ^ sport->old_status; 92266f95884SUwe Kleine-König 92366f95884SUwe Kleine-König if (changed == 0) 92466f95884SUwe Kleine-König return; 92566f95884SUwe Kleine-König 92666f95884SUwe Kleine-König sport->old_status = status; 92766f95884SUwe Kleine-König 92866f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 92966f95884SUwe Kleine-König sport->port.icount.rng++; 93066f95884SUwe Kleine-König if (changed & TIOCM_DSR) 93166f95884SUwe Kleine-König sport->port.icount.dsr++; 93266f95884SUwe Kleine-König if (changed & TIOCM_CAR) 93366f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 93466f95884SUwe Kleine-König if (changed & TIOCM_CTS) 93566f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 93666f95884SUwe Kleine-König 93766f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 93866f95884SUwe Kleine-König } 93966f95884SUwe Kleine-König 9409d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 941ab4382d2SGreg Kroah-Hartman { 942ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 94343776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 9444d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 945ab4382d2SGreg Kroah-Hartman 946101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 947101aa46bSUwe Kleine-König 94827c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 94927c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 95027c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 95127c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 95227c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 95327c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 954ab4382d2SGreg Kroah-Hartman 95543776896SUwe Kleine-König /* 95643776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 95743776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 95843776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 95943776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 96043776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 96143776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 96243776896SUwe Kleine-König */ 96343776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 96443776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 96543776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 96643776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 967c514a6f8SSergey Organov if ((ucr1 & UCR1_TRDYEN) == 0) 96843776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 96943776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 97043776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 97143776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 97243776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 97343776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 97443776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 97543776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 97643776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 97743776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 97843776896SUwe Kleine-König usr2 &= ~USR2_ORE; 97943776896SUwe Kleine-König 98043776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 981d1d996afSMatthias Schiffer imx_uart_writel(sport, USR1_AGTIM, USR1); 982d1d996afSMatthias Schiffer 983101aa46bSUwe Kleine-König __imx_uart_rxint(irq, dev_id); 9844d845a62SUwe Kleine-König ret = IRQ_HANDLED; 985b4cdc8f6SHuang Shijie } 986ab4382d2SGreg Kroah-Hartman 98743776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 988101aa46bSUwe Kleine-König imx_uart_transmit_buffer(sport); 9894d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9904d845a62SUwe Kleine-König } 991ab4382d2SGreg Kroah-Hartman 9920399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 99327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 99427e16501SUwe Kleine-König 9959d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 99627e16501SUwe Kleine-König 99727e16501SUwe Kleine-König ret = IRQ_HANDLED; 99827e16501SUwe Kleine-König } 99927e16501SUwe Kleine-König 10000399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 1001101aa46bSUwe Kleine-König __imx_uart_rtsint(irq, dev_id); 10024d845a62SUwe Kleine-König ret = IRQ_HANDLED; 10034d845a62SUwe Kleine-König } 1004ab4382d2SGreg Kroah-Hartman 10050399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 100627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 10074d845a62SUwe Kleine-König ret = IRQ_HANDLED; 10084d845a62SUwe Kleine-König } 1009db1a9b55SFabio Estevam 10100399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 1011f1f836e4SAlexander Stein sport->port.icount.overrun++; 101227c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 10134d845a62SUwe Kleine-König ret = IRQ_HANDLED; 1014f1f836e4SAlexander Stein } 1015f1f836e4SAlexander Stein 1016101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 1017101aa46bSUwe Kleine-König 10184d845a62SUwe Kleine-König return ret; 1019ab4382d2SGreg Kroah-Hartman } 1020ab4382d2SGreg Kroah-Hartman 1021ab4382d2SGreg Kroah-Hartman /* 1022ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 1023ab4382d2SGreg Kroah-Hartman */ 10249d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 1025ab4382d2SGreg Kroah-Hartman { 1026ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10271ce43e58SHuang Shijie unsigned int ret; 1028ab4382d2SGreg Kroah-Hartman 102927c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 10301ce43e58SHuang Shijie 10311ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 1032686351f3SUwe Kleine-König if (sport->dma_is_txing) 10331ce43e58SHuang Shijie ret = 0; 10341ce43e58SHuang Shijie 10351ce43e58SHuang Shijie return ret; 1036ab4382d2SGreg Kroah-Hartman } 1037ab4382d2SGreg Kroah-Hartman 10386aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10399d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 104058362d5bSUwe Kleine-König { 104158362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 10429d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 104358362d5bSUwe Kleine-König 104458362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 104558362d5bSUwe Kleine-König 104658362d5bSUwe Kleine-König return ret; 104758362d5bSUwe Kleine-König } 104858362d5bSUwe Kleine-König 10496aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10509d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1051ab4382d2SGreg Kroah-Hartman { 1052ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10534444dcf1SUwe Kleine-König u32 ucr3, uts; 1054ab4382d2SGreg Kroah-Hartman 105517b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 10564444dcf1SUwe Kleine-König u32 ucr2; 10574444dcf1SUwe Kleine-König 1058197540dcSSergey Organov /* 1059197540dcSSergey Organov * Turn off autoRTS if RTS is lowered and restore autoRTS 1060197540dcSSergey Organov * setting if RTS is raised. 1061197540dcSSergey Organov */ 10624444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 10634444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1064197540dcSSergey Organov if (mctrl & TIOCM_RTS) { 1065197540dcSSergey Organov ucr2 |= UCR2_CTS; 1066197540dcSSergey Organov /* 1067197540dcSSergey Organov * UCR2_IRTS is unset if and only if the port is 1068197540dcSSergey Organov * configured for CRTSCTS, so we use inverted UCR2_IRTS 1069197540dcSSergey Organov * to get the state to restore to. 1070197540dcSSergey Organov */ 1071197540dcSSergey Organov if (!(ucr2 & UCR2_IRTS)) 1072197540dcSSergey Organov ucr2 |= UCR2_CTSC; 1073197540dcSSergey Organov } 10744444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 107517b8f2a3SUwe Kleine-König } 10766b471a98SHuang Shijie 10774444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 107890ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 10794444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 10804444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 108190ebc483SUwe Kleine-König 10829d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 10836b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 10844444dcf1SUwe Kleine-König uts |= UTS_LOOP; 10859d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 108658362d5bSUwe Kleine-König 108758362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 1088ab4382d2SGreg Kroah-Hartman } 1089ab4382d2SGreg Kroah-Hartman 1090ab4382d2SGreg Kroah-Hartman /* 1091ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 1092ab4382d2SGreg Kroah-Hartman */ 10939d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1094ab4382d2SGreg Kroah-Hartman { 1095ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10964444dcf1SUwe Kleine-König unsigned long flags; 10974444dcf1SUwe Kleine-König u32 ucr1; 1098ab4382d2SGreg Kroah-Hartman 1099ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1100ab4382d2SGreg Kroah-Hartman 11014444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1102ab4382d2SGreg Kroah-Hartman 1103ab4382d2SGreg Kroah-Hartman if (break_state != 0) 11044444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1105ab4382d2SGreg Kroah-Hartman 11064444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1107ab4382d2SGreg Kroah-Hartman 1108ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1109ab4382d2SGreg Kroah-Hartman } 1110ab4382d2SGreg Kroah-Hartman 1111cc568849SUwe Kleine-König /* 1112cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1113cc568849SUwe Kleine-König * modem status signals. 1114cc568849SUwe Kleine-König */ 11159d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1116cc568849SUwe Kleine-König { 1117e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1118cc568849SUwe Kleine-König unsigned long flags; 1119cc568849SUwe Kleine-König 1120cc568849SUwe Kleine-König if (sport->port.state) { 1121cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 11229d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1123cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1124cc568849SUwe Kleine-König 1125cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1126cc568849SUwe Kleine-König } 1127cc568849SUwe Kleine-König } 1128cc568849SUwe Kleine-König 1129b4cdc8f6SHuang Shijie /* 1130905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1131b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1132905c0decSLucas Stach * [2] the aging timer expires 1133b4cdc8f6SHuang Shijie * 1134905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1135905c0decSLucas Stach * for at least 8 byte durations. 1136b4cdc8f6SHuang Shijie */ 11379d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1138b4cdc8f6SHuang Shijie { 1139b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1140b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1141b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 11427cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1143b4cdc8f6SHuang Shijie struct dma_tx_state state; 11449d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1145b4cdc8f6SHuang Shijie enum dma_status status; 11469d297239SNandor Han unsigned int w_bytes = 0; 11479d297239SNandor Han unsigned int r_bytes; 11489d297239SNandor Han unsigned int bd_size; 1149b4cdc8f6SHuang Shijie 1150fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1151392bceedSPhilipp Zabel 11529d297239SNandor Han if (status == DMA_ERROR) { 11539d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 11549d297239SNandor Han return; 11559d297239SNandor Han } 1156b4cdc8f6SHuang Shijie 11579b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1158976b39cdSLucas Stach 1159976b39cdSLucas Stach /* 11609d297239SNandor Han * The state-residue variable represents the empty space 11619d297239SNandor Han * relative to the entire buffer. Taking this in consideration 11629d297239SNandor Han * the head is always calculated base on the buffer total 11639d297239SNandor Han * length - DMA transaction residue. The UART script from the 11649d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 11659d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 11669d297239SNandor Han * Taking this in consideration the tail is always at the 11679d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1168976b39cdSLucas Stach */ 11699d297239SNandor Han 11709d297239SNandor Han /* Calculate the head */ 11719d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 11729d297239SNandor Han 11739d297239SNandor Han /* Calculate the tail. */ 11749d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 11759d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 11769d297239SNandor Han 11779d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 11789d297239SNandor Han rx_ring->head > rx_ring->tail) { 11799d297239SNandor Han 11809d297239SNandor Han /* Move data from tail to head */ 11819d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 11829d297239SNandor Han 11839d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 11849d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 11859d297239SNandor Han DMA_FROM_DEVICE); 11869d297239SNandor Han 11879d297239SNandor Han w_bytes = tty_insert_flip_string(port, 11889d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 11899d297239SNandor Han 11909d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 11919d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 11929d297239SNandor Han DMA_FROM_DEVICE); 11939d297239SNandor Han 11949d297239SNandor Han if (w_bytes != r_bytes) 11959d297239SNandor Han sport->port.icount.buf_overrun++; 11969d297239SNandor Han 11979d297239SNandor Han sport->port.icount.rx += w_bytes; 11989d297239SNandor Han } else { 11999d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 12009d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1201ee5e7c10SRobin Gong } 12029d297239SNandor Han } 12039d297239SNandor Han 12049d297239SNandor Han if (w_bytes) { 12059d297239SNandor Han tty_flip_buffer_push(port); 12069d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 12079d297239SNandor Han } 12089d297239SNandor Han } 12099d297239SNandor Han 1210351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 121176c38d30SPhilipp Puschmann #define RX_DMA_PERIODS 16 121276c38d30SPhilipp Puschmann #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4) 1213351ea50dSGreg Kroah-Hartman 12149d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1215b4cdc8f6SHuang Shijie { 1216b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1217b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1218b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1219b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1220b4cdc8f6SHuang Shijie int ret; 1221b4cdc8f6SHuang Shijie 12229d297239SNandor Han sport->rx_ring.head = 0; 12239d297239SNandor Han sport->rx_ring.tail = 0; 1224351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 12259d297239SNandor Han 1226351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1227b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1228b4cdc8f6SHuang Shijie if (ret == 0) { 1229b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1230b4cdc8f6SHuang Shijie return -EINVAL; 1231b4cdc8f6SHuang Shijie } 12329d297239SNandor Han 12339d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 12349d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 12359d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 12369d297239SNandor Han 1237b4cdc8f6SHuang Shijie if (!desc) { 123824649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1239b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1240b4cdc8f6SHuang Shijie return -EINVAL; 1241b4cdc8f6SHuang Shijie } 12429d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1243b4cdc8f6SHuang Shijie desc->callback_param = sport; 1244b4cdc8f6SHuang Shijie 1245b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 12464139fd76SRomain Perier sport->dma_is_rxing = 1; 12479d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1248b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1249b4cdc8f6SHuang Shijie return 0; 1250b4cdc8f6SHuang Shijie } 1251b4cdc8f6SHuang Shijie 12529d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 125341d98b5dSNandor Han { 125445ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 12554444dcf1SUwe Kleine-König u32 usr1, usr2; 125641d98b5dSNandor Han 12574444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 12584444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 125941d98b5dSNandor Han 12604444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 126141d98b5dSNandor Han sport->port.icount.brk++; 126227c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 126345ca673eSTroy Kisky uart_handle_break(&sport->port); 126445ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 126545ca673eSTroy Kisky sport->port.icount.buf_overrun++; 126645ca673eSTroy Kisky tty_flip_buffer_push(port); 126745ca673eSTroy Kisky } else { 12684444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 126941d98b5dSNandor Han sport->port.icount.frame++; 127027c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 12714444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 127241d98b5dSNandor Han sport->port.icount.parity++; 127327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 127441d98b5dSNandor Han } 127545ca673eSTroy Kisky } 127641d98b5dSNandor Han 12774444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 127841d98b5dSNandor Han sport->port.icount.overrun++; 127927c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 128041d98b5dSNandor Han } 128141d98b5dSNandor Han 128241d98b5dSNandor Han } 128341d98b5dSNandor Han 1284cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1285cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1286184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1287184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1288cc32382dSLucas Stach 12899d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1290cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1291cc32382dSLucas Stach { 1292cc32382dSLucas Stach unsigned int val; 1293cc32382dSLucas Stach 1294cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 129527c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1296cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 129727c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1298cc32382dSLucas Stach } 1299cc32382dSLucas Stach 1300b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1301b4cdc8f6SHuang Shijie { 1302b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1303e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1304b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1305b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 13069d297239SNandor Han sport->rx_cookie = -EINVAL; 1307b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1308b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1309b4cdc8f6SHuang Shijie } 1310b4cdc8f6SHuang Shijie 1311b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1312e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1313b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1314b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1315b4cdc8f6SHuang Shijie } 1316b4cdc8f6SHuang Shijie } 1317b4cdc8f6SHuang Shijie 1318b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1319b4cdc8f6SHuang Shijie { 1320b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1321b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1322b4cdc8f6SHuang Shijie int ret; 1323b4cdc8f6SHuang Shijie 1324b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1325b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1326b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1327b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1328b4cdc8f6SHuang Shijie ret = -EINVAL; 1329b4cdc8f6SHuang Shijie goto err; 1330b4cdc8f6SHuang Shijie } 1331b4cdc8f6SHuang Shijie 1332b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1333b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1334b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1335184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1336184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1337b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1338b4cdc8f6SHuang Shijie if (ret) { 1339b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1340b4cdc8f6SHuang Shijie goto err; 1341b4cdc8f6SHuang Shijie } 1342b4cdc8f6SHuang Shijie 1343f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1344b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1345b4cdc8f6SHuang Shijie ret = -ENOMEM; 1346b4cdc8f6SHuang Shijie goto err; 1347b4cdc8f6SHuang Shijie } 13489d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1349b4cdc8f6SHuang Shijie 1350b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1351b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1352b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1353b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1354b4cdc8f6SHuang Shijie ret = -EINVAL; 1355b4cdc8f6SHuang Shijie goto err; 1356b4cdc8f6SHuang Shijie } 1357b4cdc8f6SHuang Shijie 1358b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1359b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1360b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1361184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1362b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1363b4cdc8f6SHuang Shijie if (ret) { 1364b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1365b4cdc8f6SHuang Shijie goto err; 1366b4cdc8f6SHuang Shijie } 1367b4cdc8f6SHuang Shijie 1368b4cdc8f6SHuang Shijie return 0; 1369b4cdc8f6SHuang Shijie err: 1370b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1371b4cdc8f6SHuang Shijie return ret; 1372b4cdc8f6SHuang Shijie } 1373b4cdc8f6SHuang Shijie 13749d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1375b4cdc8f6SHuang Shijie { 13764444dcf1SUwe Kleine-König u32 ucr1; 1377b4cdc8f6SHuang Shijie 13789d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 137902b0abd3SUwe Kleine-König 1380b4cdc8f6SHuang Shijie /* set UCR1 */ 13814444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13824444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 13834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1384b4cdc8f6SHuang Shijie 1385b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1386b4cdc8f6SHuang Shijie } 1387b4cdc8f6SHuang Shijie 13889d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1389b4cdc8f6SHuang Shijie { 1390676a31d8SSebastian Reichel u32 ucr1; 1391b4cdc8f6SHuang Shijie 1392b4cdc8f6SHuang Shijie /* clear UCR1 */ 13934444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13944444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 13954444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1396b4cdc8f6SHuang Shijie 13979d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1398184bd70bSLucas Stach 1399b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1400b4cdc8f6SHuang Shijie } 1401b4cdc8f6SHuang Shijie 1402ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1403ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1404ab4382d2SGreg Kroah-Hartman 14059d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1406ab4382d2SGreg Kroah-Hartman { 1407ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1408458e2c82SFabio Estevam int retval, i; 14094444dcf1SUwe Kleine-König unsigned long flags; 14104238c00bSUwe Kleine-König int dma_is_inited = 0; 14115a08a487SGeorge Hilliard u32 ucr1, ucr2, ucr3, ucr4; 1412ab4382d2SGreg Kroah-Hartman 141328eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 141428eb4274SHuang Shijie if (retval) 1415cb0f0a5fSFabio Estevam return retval; 141628eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 14170c375501SHuang Shijie if (retval) { 14180c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1419cb0f0a5fSFabio Estevam return retval; 14200c375501SHuang Shijie } 142128eb4274SHuang Shijie 14229d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1423ab4382d2SGreg Kroah-Hartman 1424ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1425ab4382d2SGreg Kroah-Hartman * requesting IRQs 1426ab4382d2SGreg Kroah-Hartman */ 14274444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1428ab4382d2SGreg Kroah-Hartman 1429ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 14304444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 14314444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1432ab4382d2SGreg Kroah-Hartman 14334444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1434ab4382d2SGreg Kroah-Hartman 14357e11577eSLucas Stach /* Can we enable the DMA support? */ 14364238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 14374238c00bSUwe Kleine-König dma_is_inited = 1; 14387e11577eSLucas Stach 143953794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1440772f8991SHuang Shijie /* Reset fifo's and state machines */ 1441458e2c82SFabio Estevam i = 100; 1442458e2c82SFabio Estevam 14434444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14444444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 14454444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1446458e2c82SFabio Estevam 144727c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1448458e2c82SFabio Estevam udelay(1); 1449ab4382d2SGreg Kroah-Hartman 1450ab4382d2SGreg Kroah-Hartman /* 1451ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1452ab4382d2SGreg Kroah-Hartman */ 145327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 145427c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1455ab4382d2SGreg Kroah-Hartman 14564444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 14574444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 14586376cd39SNandor Han if (sport->have_rtscts) 14594444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1460ab4382d2SGreg Kroah-Hartman 14614444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1462ab4382d2SGreg Kroah-Hartman 14635a08a487SGeorge Hilliard ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 14641f043572STroy Kisky if (!sport->dma_is_enabled) 14654444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 14665a08a487SGeorge Hilliard if (sport->inverted_rx) 14675a08a487SGeorge Hilliard ucr4 |= UCR4_INVR; 14684444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 14696f026d6bSJiada Wang 14705a08a487SGeorge Hilliard ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 14715a08a487SGeorge Hilliard /* 14725a08a487SGeorge Hilliard * configure tx polarity before enabling tx 14735a08a487SGeorge Hilliard */ 14745a08a487SGeorge Hilliard if (sport->inverted_tx) 14755a08a487SGeorge Hilliard ucr3 |= UCR3_INVT; 14765a08a487SGeorge Hilliard 14775a08a487SGeorge Hilliard if (!imx_uart_is_imx1(sport)) { 14785a08a487SGeorge Hilliard ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 14795a08a487SGeorge Hilliard 14805a08a487SGeorge Hilliard if (sport->dte_mode) 14815a08a487SGeorge Hilliard /* disable broken interrupts */ 14825a08a487SGeorge Hilliard ucr3 &= ~(UCR3_RI | UCR3_DCD); 14835a08a487SGeorge Hilliard } 14845a08a487SGeorge Hilliard imx_uart_writel(sport, ucr3, UCR3); 14855a08a487SGeorge Hilliard 14864444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 14874444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1488bff09b09SLucas Stach if (!sport->have_rtscts) 14894444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 149016804d68SUwe Kleine-König /* 149116804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 149216804d68SUwe Kleine-König * we're using RTSD instead. 149316804d68SUwe Kleine-König */ 14949d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 14954444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 14964444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1497ab4382d2SGreg Kroah-Hartman 1498ab4382d2SGreg Kroah-Hartman /* 1499ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1500ab4382d2SGreg Kroah-Hartman */ 15019d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 150218a42088SPeter Senna Tschudin 150376821e22SUwe Kleine-König if (dma_is_inited) { 15049d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 15059d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 150676821e22SUwe Kleine-König } else { 150776821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 150876821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 150976821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 151081ca8e82SUwe Kleine-König 151181ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 151281ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 151381ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 151476821e22SUwe Kleine-König } 151518a42088SPeter Senna Tschudin 1516ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1517ab4382d2SGreg Kroah-Hartman 1518ab4382d2SGreg Kroah-Hartman return 0; 1519ab4382d2SGreg Kroah-Hartman } 1520ab4382d2SGreg Kroah-Hartman 15219d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1522ab4382d2SGreg Kroah-Hartman { 1523ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 15249ec1882dSXinyu Chen unsigned long flags; 1525339c7a87SSebastian Reichel u32 ucr1, ucr2, ucr4; 1526ab4382d2SGreg Kroah-Hartman 1527b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1528e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 15297722c240SSebastian Reichel if (sport->dma_is_txing) { 15307722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 15317722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 15327722c240SSebastian Reichel sport->dma_is_txing = 0; 15337722c240SSebastian Reichel } 1534e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 15357722c240SSebastian Reichel if (sport->dma_is_rxing) { 15367722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 15377722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 15387722c240SSebastian Reichel sport->dma_is_rxing = 0; 15397722c240SSebastian Reichel } 15409d297239SNandor Han 154173631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 15429d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 15439d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 15449d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 154573631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1546b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1547b4cdc8f6SHuang Shijie } 1548b4cdc8f6SHuang Shijie 154958362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 155058362d5bSUwe Kleine-König 15519ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 15524444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15530fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 15544444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 15559ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1556ab4382d2SGreg Kroah-Hartman 1557ab4382d2SGreg Kroah-Hartman /* 1558ab4382d2SGreg Kroah-Hartman * Stop our timer. 1559ab4382d2SGreg Kroah-Hartman */ 1560ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1561ab4382d2SGreg Kroah-Hartman 1562ab4382d2SGreg Kroah-Hartman /* 1563ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1564ab4382d2SGreg Kroah-Hartman */ 1565ab4382d2SGreg Kroah-Hartman 15669ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1567*edd64f30SMatthias Schiffer 15684444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 1569c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 15704444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1571*edd64f30SMatthias Schiffer 1572*edd64f30SMatthias Schiffer ucr4 = imx_uart_readl(sport, UCR4); 1573*edd64f30SMatthias Schiffer ucr4 &= ~(UCR4_OREN | UCR4_TCEN); 1574*edd64f30SMatthias Schiffer imx_uart_writel(sport, ucr4, UCR4); 1575*edd64f30SMatthias Schiffer 15769ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 157728eb4274SHuang Shijie 157828eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 157928eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1580ab4382d2SGreg Kroah-Hartman } 1581ab4382d2SGreg Kroah-Hartman 15826aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 15839d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1584eb56b7edSHuang Shijie { 1585eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 158682e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 15874444dcf1SUwe Kleine-König u32 ucr2; 15884f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1589eb56b7edSHuang Shijie 159082e86ae9SDirk Behme if (!sport->dma_chan_tx) 159182e86ae9SDirk Behme return; 159282e86ae9SDirk Behme 1593eb56b7edSHuang Shijie sport->tx_bytes = 0; 1594eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 159582e86ae9SDirk Behme if (sport->dma_is_txing) { 15964444dcf1SUwe Kleine-König u32 ucr1; 15974444dcf1SUwe Kleine-König 159882e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 159982e86ae9SDirk Behme DMA_TO_DEVICE); 16004444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 16014444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 16024444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 16030f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1604eb56b7edSHuang Shijie } 1605934084a9SFabio Estevam 1606934084a9SFabio Estevam /* 1607934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1608263763c1SMartyn Welch * 1609934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1610934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1611263763c1SMartyn Welch * and UTS[6-3]". 1612263763c1SMartyn Welch * 1613263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1614263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1615263763c1SMartyn Welch * registers. 1616934084a9SFabio Estevam */ 161727c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 161827c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 161927c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1620934084a9SFabio Estevam 16214444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 16224444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 16234444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1624934084a9SFabio Estevam 162527c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1626934084a9SFabio Estevam udelay(1); 1627934084a9SFabio Estevam 1628934084a9SFabio Estevam /* Restore the registers */ 162927c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 163027c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 163127c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1632eb56b7edSHuang Shijie } 1633eb56b7edSHuang Shijie 1634ab4382d2SGreg Kroah-Hartman static void 16359d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1636ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1637ab4382d2SGreg Kroah-Hartman { 1638ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1639ab4382d2SGreg Kroah-Hartman unsigned long flags; 164085f30fbfSSergey Organov u32 ucr2, old_ucr2, ufcr; 164158362d5bSUwe Kleine-König unsigned int baud, quot; 1642ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 16434444dcf1SUwe Kleine-König unsigned long div; 1644d47bcb4aSSergey Organov unsigned long num, denom, old_ubir, old_ubmr; 1645ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1646ab4382d2SGreg Kroah-Hartman 1647ab4382d2SGreg Kroah-Hartman /* 1648ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1649ab4382d2SGreg Kroah-Hartman */ 1650ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1651ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1652ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1653ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1654ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1655ab4382d2SGreg Kroah-Hartman } 1656ab4382d2SGreg Kroah-Hartman 16574e828c3eSSergey Organov del_timer_sync(&sport->timer); 16584e828c3eSSergey Organov 16594e828c3eSSergey Organov /* 16604e828c3eSSergey Organov * Ask the core to calculate the divisor for us. 16614e828c3eSSergey Organov */ 16624e828c3eSSergey Organov baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 16634e828c3eSSergey Organov quot = uart_get_divisor(port, baud); 16644e828c3eSSergey Organov 16654e828c3eSSergey Organov spin_lock_irqsave(&sport->port.lock, flags); 16664e828c3eSSergey Organov 1667011bd05dSSergey Organov /* 1668011bd05dSSergey Organov * Read current UCR2 and save it for future use, then clear all the bits 1669011bd05dSSergey Organov * except those we will or may need to preserve. 1670011bd05dSSergey Organov */ 1671011bd05dSSergey Organov old_ucr2 = imx_uart_readl(sport, UCR2); 1672011bd05dSSergey Organov ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1673011bd05dSSergey Organov 1674011bd05dSSergey Organov ucr2 |= UCR2_SRST | UCR2_IRTS; 167541ffa48eSSergey Organov if ((termios->c_cflag & CSIZE) == CS8) 167641ffa48eSSergey Organov ucr2 |= UCR2_WS; 1677ab4382d2SGreg Kroah-Hartman 1678ddf89e75SSergey Organov if (!sport->have_rtscts) 1679ddf89e75SSergey Organov termios->c_cflag &= ~CRTSCTS; 168017b8f2a3SUwe Kleine-König 168112fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 168217b8f2a3SUwe Kleine-König /* 168317b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 168417b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 168517b8f2a3SUwe Kleine-König * disabled. 168617b8f2a3SUwe Kleine-König */ 168758362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 16889d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 16891a613626SFabio Estevam else 16909d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 169158362d5bSUwe Kleine-König 1692b777b5deSSergey Organov } else if (termios->c_cflag & CRTSCTS) { 1693b777b5deSSergey Organov /* 1694b777b5deSSergey Organov * Only let receiver control RTS output if we were not requested 1695b777b5deSSergey Organov * to have RTS inactive (which then should take precedence). 1696b777b5deSSergey Organov */ 1697b777b5deSSergey Organov if (ucr2 & UCR2_CTS) 1698b777b5deSSergey Organov ucr2 |= UCR2_CTSC; 1699b777b5deSSergey Organov } 1700ddf89e75SSergey Organov 1701ddf89e75SSergey Organov if (termios->c_cflag & CRTSCTS) 1702ddf89e75SSergey Organov ucr2 &= ~UCR2_IRTS; 1703ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1704ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1705ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1706ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1707ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1708ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1709ab4382d2SGreg Kroah-Hartman } 1710ab4382d2SGreg Kroah-Hartman 1711ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1712ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1713ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1714ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1715ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1716ab4382d2SGreg Kroah-Hartman 1717ab4382d2SGreg Kroah-Hartman /* 1718ab4382d2SGreg Kroah-Hartman * Characters to ignore 1719ab4382d2SGreg Kroah-Hartman */ 1720ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1721ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1722865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1723ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1724ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1725ab4382d2SGreg Kroah-Hartman /* 1726ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1727ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1728ab4382d2SGreg Kroah-Hartman */ 1729ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1730ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1731ab4382d2SGreg Kroah-Hartman } 1732ab4382d2SGreg Kroah-Hartman 173355d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 173455d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 173555d8693aSJiada Wang 1736ab4382d2SGreg Kroah-Hartman /* 1737ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1738ab4382d2SGreg Kroah-Hartman */ 1739ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1740ab4382d2SGreg Kroah-Hartman 174109bd00f6SHubert Feurstein /* custom-baudrate handling */ 174209bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 174309bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 174409bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 174509bd00f6SHubert Feurstein 1746ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1747ab4382d2SGreg Kroah-Hartman if (div > 7) 1748ab4382d2SGreg Kroah-Hartman div = 7; 1749ab4382d2SGreg Kroah-Hartman if (!div) 1750ab4382d2SGreg Kroah-Hartman div = 1; 1751ab4382d2SGreg Kroah-Hartman 1752ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1753ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1754ab4382d2SGreg Kroah-Hartman 1755ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1756ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1757ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1758ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1759ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1760ab4382d2SGreg Kroah-Hartman 1761ab4382d2SGreg Kroah-Hartman num -= 1; 1762ab4382d2SGreg Kroah-Hartman denom -= 1; 1763ab4382d2SGreg Kroah-Hartman 176427c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1765ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 176627c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1767ab4382d2SGreg Kroah-Hartman 1768d47bcb4aSSergey Organov /* 1769d47bcb4aSSergey Organov * Two registers below should always be written both and in this 1770d47bcb4aSSergey Organov * particular order. One consequence is that we need to check if any of 1771d47bcb4aSSergey Organov * them changes and then update both. We do need the check for change 1772d47bcb4aSSergey Organov * as even writing the same values seem to "restart" 1773d47bcb4aSSergey Organov * transmission/receiving logic in the hardware, that leads to data 1774d47bcb4aSSergey Organov * breakage even when rate doesn't in fact change. E.g., user switches 1775d47bcb4aSSergey Organov * RTS/CTS handshake and suddenly gets broken bytes. 1776d47bcb4aSSergey Organov */ 1777d47bcb4aSSergey Organov old_ubir = imx_uart_readl(sport, UBIR); 1778d47bcb4aSSergey Organov old_ubmr = imx_uart_readl(sport, UBMR); 1779d47bcb4aSSergey Organov if (old_ubir != num || old_ubmr != denom) { 178027c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 178127c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1782d47bcb4aSSergey Organov } 1783ab4382d2SGreg Kroah-Hartman 17849d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 178527c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 178627c84426SUwe Kleine-König IMX21_ONEMS); 1787ab4382d2SGreg Kroah-Hartman 1788011bd05dSSergey Organov imx_uart_writel(sport, ucr2, UCR2); 1789ab4382d2SGreg Kroah-Hartman 1790ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 17919d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1792ab4382d2SGreg Kroah-Hartman 1793ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1794ab4382d2SGreg Kroah-Hartman } 1795ab4382d2SGreg Kroah-Hartman 17969d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1797ab4382d2SGreg Kroah-Hartman { 1798ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1799ab4382d2SGreg Kroah-Hartman 1800ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1801ab4382d2SGreg Kroah-Hartman } 1802ab4382d2SGreg Kroah-Hartman 1803ab4382d2SGreg Kroah-Hartman /* 1804ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1805ab4382d2SGreg Kroah-Hartman */ 18069d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1807ab4382d2SGreg Kroah-Hartman { 1808ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1809ab4382d2SGreg Kroah-Hartman 1810da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1811ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1812ab4382d2SGreg Kroah-Hartman } 1813ab4382d2SGreg Kroah-Hartman 1814ab4382d2SGreg Kroah-Hartman /* 1815ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1816ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1817ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1818ab4382d2SGreg Kroah-Hartman */ 1819ab4382d2SGreg Kroah-Hartman static int 18209d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1821ab4382d2SGreg Kroah-Hartman { 1822ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1823ab4382d2SGreg Kroah-Hartman int ret = 0; 1824ab4382d2SGreg Kroah-Hartman 1825ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1826ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1827ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1828ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1829ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1830ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1831ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1832ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1833a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1834ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1835ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1836ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1837ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1838ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1839ab4382d2SGreg Kroah-Hartman return ret; 1840ab4382d2SGreg Kroah-Hartman } 1841ab4382d2SGreg Kroah-Hartman 184201f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18436b8bdad9SDaniel Thompson 18449d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 18456b8bdad9SDaniel Thompson { 18466b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 18476b8bdad9SDaniel Thompson unsigned long flags; 18484444dcf1SUwe Kleine-König u32 ucr1, ucr2; 18496b8bdad9SDaniel Thompson int retval; 18506b8bdad9SDaniel Thompson 18516b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 18526b8bdad9SDaniel Thompson if (retval) 18536b8bdad9SDaniel Thompson return retval; 18546b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 18556b8bdad9SDaniel Thompson if (retval) 18566b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 18576b8bdad9SDaniel Thompson 18589d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 18596b8bdad9SDaniel Thompson 18606b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 18616b8bdad9SDaniel Thompson 186276821e22SUwe Kleine-König /* 186376821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 186476821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 186576821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 186676821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 186776821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 186876821e22SUwe Kleine-König */ 18694444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 187076821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 187176821e22SUwe Kleine-König 18729d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 18734444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 18746b8bdad9SDaniel Thompson 187576821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 1876c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 187776821e22SUwe Kleine-König 18784444dcf1SUwe Kleine-König ucr2 |= UCR2_RXEN; 187981ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 188076821e22SUwe Kleine-König 188176821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 18824444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 18836b8bdad9SDaniel Thompson 188476821e22SUwe Kleine-König /* now enable irqs */ 188576821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 188681ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 188776821e22SUwe Kleine-König 18886b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 18896b8bdad9SDaniel Thompson 18906b8bdad9SDaniel Thompson return 0; 18916b8bdad9SDaniel Thompson } 18926b8bdad9SDaniel Thompson 18939d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 189401f56abdSSaleem Abdulrasool { 189527c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 189627c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 189726c47412SDirk Behme return NO_POLL_CHAR; 189801f56abdSSaleem Abdulrasool 189927c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 190001f56abdSSaleem Abdulrasool } 190101f56abdSSaleem Abdulrasool 19029d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 190301f56abdSSaleem Abdulrasool { 190427c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 190501f56abdSSaleem Abdulrasool unsigned int status; 190601f56abdSSaleem Abdulrasool 190701f56abdSSaleem Abdulrasool /* drain */ 190801f56abdSSaleem Abdulrasool do { 190927c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 191001f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 191101f56abdSSaleem Abdulrasool 191201f56abdSSaleem Abdulrasool /* write */ 191327c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 191401f56abdSSaleem Abdulrasool 191501f56abdSSaleem Abdulrasool /* flush */ 191601f56abdSSaleem Abdulrasool do { 191727c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 191801f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 191901f56abdSSaleem Abdulrasool } 192001f56abdSSaleem Abdulrasool #endif 192101f56abdSSaleem Abdulrasool 19226aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 19239d1a50a2SUwe Kleine-König static int imx_uart_rs485_config(struct uart_port *port, 192417b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 192517b8f2a3SUwe Kleine-König { 192617b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 19274444dcf1SUwe Kleine-König u32 ucr2; 192817b8f2a3SUwe Kleine-König 192917b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 19307b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 193117b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 193217b8f2a3SUwe Kleine-König 193317b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 19346d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 19356d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 19366d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 19376d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 19386d215f83SStefan Agner 193917b8f2a3SUwe Kleine-König /* disable transmitter */ 19404444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 194117b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 19429d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 19431a613626SFabio Estevam else 19449d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 19454444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 194617b8f2a3SUwe Kleine-König } 194717b8f2a3SUwe Kleine-König 19487d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 19497d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 195076821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 19519d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 19527d1cadcaSBaruch Siach 195317b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 195417b8f2a3SUwe Kleine-König 195517b8f2a3SUwe Kleine-König return 0; 195617b8f2a3SUwe Kleine-König } 195717b8f2a3SUwe Kleine-König 19589d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 19599d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 19609d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 19619d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 19629d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 19639d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 19649d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 19659d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 19669d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 19679d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 19689d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 19699d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 19709d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 19719d1a50a2SUwe Kleine-König .type = imx_uart_type, 19729d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 19739d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 197401f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 19759d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 19769d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 19779d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 197801f56abdSSaleem Abdulrasool #endif 1979ab4382d2SGreg Kroah-Hartman }; 1980ab4382d2SGreg Kroah-Hartman 19819d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1982ab4382d2SGreg Kroah-Hartman 19830db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 19849d1a50a2SUwe Kleine-König static void imx_uart_console_putchar(struct uart_port *port, int ch) 1985ab4382d2SGreg Kroah-Hartman { 1986ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1987ab4382d2SGreg Kroah-Hartman 19889d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1989ab4382d2SGreg Kroah-Hartman barrier(); 1990ab4382d2SGreg Kroah-Hartman 199127c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1992ab4382d2SGreg Kroah-Hartman } 1993ab4382d2SGreg Kroah-Hartman 1994ab4382d2SGreg Kroah-Hartman /* 1995ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1996ab4382d2SGreg Kroah-Hartman */ 1997ab4382d2SGreg Kroah-Hartman static void 19989d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1999ab4382d2SGreg Kroah-Hartman { 20009d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 20010ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 20020ad5a814SDirk Behme unsigned int ucr1; 2003f30e8260SShawn Guo unsigned long flags = 0; 2004677fe555SThomas Gleixner int locked = 1; 20051cf93e0dSHuang Shijie int retval; 20061cf93e0dSHuang Shijie 20070c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 20081cf93e0dSHuang Shijie if (retval) 20091cf93e0dSHuang Shijie return; 20100c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 20111cf93e0dSHuang Shijie if (retval) { 20120c727a42SFabio Estevam clk_disable(sport->clk_per); 20131cf93e0dSHuang Shijie return; 20141cf93e0dSHuang Shijie } 20159ec1882dSXinyu Chen 2016677fe555SThomas Gleixner if (sport->port.sysrq) 2017677fe555SThomas Gleixner locked = 0; 2018677fe555SThomas Gleixner else if (oops_in_progress) 2019677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 2020677fe555SThomas Gleixner else 20219ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 2022ab4382d2SGreg Kroah-Hartman 2023ab4382d2SGreg Kroah-Hartman /* 20240ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 2025ab4382d2SGreg Kroah-Hartman */ 20269d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 20270ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 2028ab4382d2SGreg Kroah-Hartman 20299d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 2030fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 2031ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 2032c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 2033ab4382d2SGreg Kroah-Hartman 203427c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2035ab4382d2SGreg Kroah-Hartman 203627c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2037ab4382d2SGreg Kroah-Hartman 20389d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2039ab4382d2SGreg Kroah-Hartman 2040ab4382d2SGreg Kroah-Hartman /* 2041ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 20420ad5a814SDirk Behme * and restore UCR1/2/3 2043ab4382d2SGreg Kroah-Hartman */ 204427c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2045ab4382d2SGreg Kroah-Hartman 20469d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 20479ec1882dSXinyu Chen 2048677fe555SThomas Gleixner if (locked) 20499ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 20501cf93e0dSHuang Shijie 20510c727a42SFabio Estevam clk_disable(sport->clk_ipg); 20520c727a42SFabio Estevam clk_disable(sport->clk_per); 2053ab4382d2SGreg Kroah-Hartman } 2054ab4382d2SGreg Kroah-Hartman 2055ab4382d2SGreg Kroah-Hartman /* 2056ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 2057ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 2058ab4382d2SGreg Kroah-Hartman */ 2059ab4382d2SGreg Kroah-Hartman static void __init 20609d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 2061ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 2062ab4382d2SGreg Kroah-Hartman { 2063ab4382d2SGreg Kroah-Hartman 206427c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2065ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 2066ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 2067ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 2068ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 2069ab4382d2SGreg Kroah-Hartman 207027c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 2071ab4382d2SGreg Kroah-Hartman 2072ab4382d2SGreg Kroah-Hartman *parity = 'n'; 2073ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 2074ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 2075ab4382d2SGreg Kroah-Hartman *parity = 'o'; 2076ab4382d2SGreg Kroah-Hartman else 2077ab4382d2SGreg Kroah-Hartman *parity = 'e'; 2078ab4382d2SGreg Kroah-Hartman } 2079ab4382d2SGreg Kroah-Hartman 2080ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 2081ab4382d2SGreg Kroah-Hartman *bits = 8; 2082ab4382d2SGreg Kroah-Hartman else 2083ab4382d2SGreg Kroah-Hartman *bits = 7; 2084ab4382d2SGreg Kroah-Hartman 208527c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 208627c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2087ab4382d2SGreg Kroah-Hartman 208827c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2089ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 2090ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 2091ab4382d2SGreg Kroah-Hartman else 2092ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 2093ab4382d2SGreg Kroah-Hartman 20943a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2095ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2096ab4382d2SGreg Kroah-Hartman 2097ab4382d2SGreg Kroah-Hartman { /* 2098ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2099ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2100ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2101ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2102ab4382d2SGreg Kroah-Hartman */ 2103ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2104ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2105ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2106ab4382d2SGreg Kroah-Hartman 2107ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2108ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2109ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2110ab4382d2SGreg Kroah-Hartman } 2111ab4382d2SGreg Kroah-Hartman 2112ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 2113f5a9e5f7SFabio Estevam dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2114ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2115ab4382d2SGreg Kroah-Hartman } 2116ab4382d2SGreg Kroah-Hartman } 2117ab4382d2SGreg Kroah-Hartman 2118ab4382d2SGreg Kroah-Hartman static int __init 21199d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2120ab4382d2SGreg Kroah-Hartman { 2121ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2122ab4382d2SGreg Kroah-Hartman int baud = 9600; 2123ab4382d2SGreg Kroah-Hartman int bits = 8; 2124ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2125ab4382d2SGreg Kroah-Hartman int flow = 'n'; 21261cf93e0dSHuang Shijie int retval; 2127ab4382d2SGreg Kroah-Hartman 2128ab4382d2SGreg Kroah-Hartman /* 2129ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2130ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2131ab4382d2SGreg Kroah-Hartman * console support. 2132ab4382d2SGreg Kroah-Hartman */ 21339d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2134ab4382d2SGreg Kroah-Hartman co->index = 0; 21359d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2136ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2137ab4382d2SGreg Kroah-Hartman return -ENODEV; 2138ab4382d2SGreg Kroah-Hartman 21391cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 21401cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 21411cf93e0dSHuang Shijie if (retval) 21421cf93e0dSHuang Shijie goto error_console; 21431cf93e0dSHuang Shijie 2144ab4382d2SGreg Kroah-Hartman if (options) 2145ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2146ab4382d2SGreg Kroah-Hartman else 21479d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2148ab4382d2SGreg Kroah-Hartman 21499d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2150ab4382d2SGreg Kroah-Hartman 21511cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 21521cf93e0dSHuang Shijie 21530c727a42SFabio Estevam clk_disable(sport->clk_ipg); 21540c727a42SFabio Estevam if (retval) { 21550c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 21560c727a42SFabio Estevam goto error_console; 21570c727a42SFabio Estevam } 21580c727a42SFabio Estevam 21590c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 21600c727a42SFabio Estevam if (retval) 216163fd4b94SStefan Agner clk_unprepare(sport->clk_ipg); 21621cf93e0dSHuang Shijie 21631cf93e0dSHuang Shijie error_console: 21641cf93e0dSHuang Shijie return retval; 2165ab4382d2SGreg Kroah-Hartman } 2166ab4382d2SGreg Kroah-Hartman 21679d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 21689d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2169ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 21709d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2171ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 21729d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 2173ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2174ab4382d2SGreg Kroah-Hartman .index = -1, 21759d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2176ab4382d2SGreg Kroah-Hartman }; 2177ab4382d2SGreg Kroah-Hartman 21789d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2179913c6c0eSLucas Stach 2180ab4382d2SGreg Kroah-Hartman #else 2181ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2182ab4382d2SGreg Kroah-Hartman #endif 2183ab4382d2SGreg Kroah-Hartman 21849d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2185ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2186ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2187ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2188ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2189ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21909d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2191ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2192ab4382d2SGreg Kroah-Hartman }; 2193ab4382d2SGreg Kroah-Hartman 219422698aa2SShawn Guo #ifdef CONFIG_OF 219520bb8095SUwe Kleine-König /* 219620bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 219720bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 219820bb8095SUwe Kleine-König */ 21999d1a50a2SUwe Kleine-König static int imx_uart_probe_dt(struct imx_port *sport, 220022698aa2SShawn Guo struct platform_device *pdev) 220122698aa2SShawn Guo { 220222698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2203ff05967aSShawn Guo int ret; 220422698aa2SShawn Guo 22055f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 22065f8b9043SLABBE Corentin if (!sport->devdata) 220720bb8095SUwe Kleine-König /* no device tree device */ 220820bb8095SUwe Kleine-König return 1; 220922698aa2SShawn Guo 2210ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2211ff05967aSShawn Guo if (ret < 0) { 2212ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2213a197a191SUwe Kleine-König return ret; 2214ff05967aSShawn Guo } 2215ff05967aSShawn Guo sport->port.line = ret; 221622698aa2SShawn Guo 22171006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 22181006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 221922698aa2SShawn Guo sport->have_rtscts = 1; 222022698aa2SShawn Guo 222120ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 222220ff2fe6SHuang Shijie sport->dte_mode = 1; 222320ff2fe6SHuang Shijie 22247b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 22257b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 22267b7e8e8eSFabio Estevam 22275a08a487SGeorge Hilliard if (of_get_property(np, "fsl,inverted-tx", NULL)) 22285a08a487SGeorge Hilliard sport->inverted_tx = 1; 22295a08a487SGeorge Hilliard 22305a08a487SGeorge Hilliard if (of_get_property(np, "fsl,inverted-rx", NULL)) 22315a08a487SGeorge Hilliard sport->inverted_rx = 1; 22325a08a487SGeorge Hilliard 223322698aa2SShawn Guo return 0; 223422698aa2SShawn Guo } 223522698aa2SShawn Guo #else 22369d1a50a2SUwe Kleine-König static inline int imx_uart_probe_dt(struct imx_port *sport, 223722698aa2SShawn Guo struct platform_device *pdev) 223822698aa2SShawn Guo { 223920bb8095SUwe Kleine-König return 1; 224022698aa2SShawn Guo } 224122698aa2SShawn Guo #endif 224222698aa2SShawn Guo 22439d1a50a2SUwe Kleine-König static void imx_uart_probe_pdata(struct imx_port *sport, 224422698aa2SShawn Guo struct platform_device *pdev) 224522698aa2SShawn Guo { 2246574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 224722698aa2SShawn Guo 224822698aa2SShawn Guo sport->port.line = pdev->id; 224922698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 225022698aa2SShawn Guo 225122698aa2SShawn Guo if (!pdata) 225222698aa2SShawn Guo return; 225322698aa2SShawn Guo 225422698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 225522698aa2SShawn Guo sport->have_rtscts = 1; 225622698aa2SShawn Guo } 225722698aa2SShawn Guo 2258bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2259cb1a6092SUwe Kleine-König { 2260bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2261cb1a6092SUwe Kleine-König unsigned long flags; 2262cb1a6092SUwe Kleine-König 2263cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2264cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS) 2265cb1a6092SUwe Kleine-König imx_uart_start_tx(&sport->port); 2266cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2267bd78ecd6SAhmad Fatoum 2268bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2269cb1a6092SUwe Kleine-König } 2270cb1a6092SUwe Kleine-König 2271bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2272cb1a6092SUwe Kleine-König { 2273bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2274cb1a6092SUwe Kleine-König unsigned long flags; 2275cb1a6092SUwe Kleine-König 2276cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2277cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_SEND) 2278cb1a6092SUwe Kleine-König imx_uart_stop_tx(&sport->port); 2279cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2280bd78ecd6SAhmad Fatoum 2281bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2282cb1a6092SUwe Kleine-König } 2283cb1a6092SUwe Kleine-König 22849d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2285ab4382d2SGreg Kroah-Hartman { 2286ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2287ab4382d2SGreg Kroah-Hartman void __iomem *base; 22884444dcf1SUwe Kleine-König int ret = 0; 22894444dcf1SUwe Kleine-König u32 ucr1; 2290ab4382d2SGreg Kroah-Hartman struct resource *res; 2291842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2292ab4382d2SGreg Kroah-Hartman 229342d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2294ab4382d2SGreg Kroah-Hartman if (!sport) 2295ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2296ab4382d2SGreg Kroah-Hartman 22979d1a50a2SUwe Kleine-König ret = imx_uart_probe_dt(sport, pdev); 229820bb8095SUwe Kleine-König if (ret > 0) 22999d1a50a2SUwe Kleine-König imx_uart_probe_pdata(sport, pdev); 230020bb8095SUwe Kleine-König else if (ret < 0) 230142d34191SSachin Kamat return ret; 230222698aa2SShawn Guo 23039d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 230456734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 230556734448SGeert Uytterhoeven sport->port.line); 230656734448SGeert Uytterhoeven return -EINVAL; 230756734448SGeert Uytterhoeven } 230856734448SGeert Uytterhoeven 2309ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2310da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2311da82f997SAlexander Shiyan if (IS_ERR(base)) 2312da82f997SAlexander Shiyan return PTR_ERR(base); 2313ab4382d2SGreg Kroah-Hartman 2314842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2315aa49d8e8SAnson Huang if (rxirq < 0) 2316aa49d8e8SAnson Huang return rxirq; 231731a8d8faSAnson Huang txirq = platform_get_irq_optional(pdev, 1); 231831a8d8faSAnson Huang rtsirq = platform_get_irq_optional(pdev, 2); 2319842633bdSUwe Kleine-König 2320ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2321ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2322ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2323ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2324ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2325842633bdSUwe Kleine-König sport->port.irq = rxirq; 2326ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2327aa3479d2SDmitry Safonov sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 23289d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 23299d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 2330ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 23319d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2332ab4382d2SGreg Kroah-Hartman 233358362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 233458362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 233558362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 233658362d5bSUwe Kleine-König 23373a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 23383a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 23393a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2340833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 234142d34191SSachin Kamat return ret; 2342ab4382d2SGreg Kroah-Hartman } 2343ab4382d2SGreg Kroah-Hartman 23443a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 23453a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 23463a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2347833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 234842d34191SSachin Kamat return ret; 23493a9465faSSascha Hauer } 23503a9465faSSascha Hauer 23513a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2352ab4382d2SGreg Kroah-Hartman 23538a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 23548a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 23551e512d45SUwe Kleine-König if (ret) { 23561e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 23578a61f0c7SFabio Estevam return ret; 23581e512d45SUwe Kleine-König } 23598a61f0c7SFabio Estevam 23603a0ab62fSUwe Kleine-König /* initialize shadow register values */ 23613a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 23623a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 23633a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 23643a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 23653a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 23663a0ab62fSUwe Kleine-König 2367c150c0f3SLukas Wunner ret = uart_get_rs485_mode(&sport->port); 2368c150c0f3SLukas Wunner if (ret) { 2369c150c0f3SLukas Wunner clk_disable_unprepare(sport->clk_ipg); 2370c150c0f3SLukas Wunner return ret; 2371c150c0f3SLukas Wunner } 2372743f93f8SLukas Wunner 2373b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23745d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2375b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2376b8f3bff0SLukas Wunner 23776d215f83SStefan Agner /* 23786d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 23796d215f83SStefan Agner * signal cannot be set low during transmission in case the 23806d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 23816d215f83SStefan Agner */ 23826d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23836d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 23846d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 23856d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 23866d215f83SStefan Agner dev_err(&pdev->dev, 23876d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 23886d215f83SStefan Agner 23899d1a50a2SUwe Kleine-König imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2390b8f3bff0SLukas Wunner 23918a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 23924444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 23935f0e708cSYe Bin ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 23944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 23958a61f0c7SFabio Estevam 23969d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2397e61c38d8SUwe Kleine-König /* 2398e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2399e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2400e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2401e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2402e61c38d8SUwe Kleine-König */ 24034444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 24044444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 24054444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2406e61c38d8SUwe Kleine-König 2407e61c38d8SUwe Kleine-König /* 2408e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2409e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2410e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2411e61c38d8SUwe Kleine-König */ 241227c84426SUwe Kleine-König imx_uart_writel(sport, 241327c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 241427c84426SUwe Kleine-König UCR3); 2415e61c38d8SUwe Kleine-König 2416e61c38d8SUwe Kleine-König } else { 24174444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 24184444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 24194444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 24204444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 24216df765dcSUwe Kleine-König 24229d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 24236df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 242427c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2425e61c38d8SUwe Kleine-König } 2426e61c38d8SUwe Kleine-König 24278a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 24288a61f0c7SFabio Estevam 2429bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2430bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2431bd78ecd6SAhmad Fatoum sport->trigger_start_tx.function = imx_trigger_start_tx; 2432bd78ecd6SAhmad Fatoum sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2433cb1a6092SUwe Kleine-König 2434c0d1c6b0SFabio Estevam /* 2435c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2436c0d1c6b0SFabio Estevam * chips only have one interrupt. 2437c0d1c6b0SFabio Estevam */ 2438842633bdSUwe Kleine-König if (txirq > 0) { 24399d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2440c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24411e512d45SUwe Kleine-König if (ret) { 24421e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 24431e512d45SUwe Kleine-König ret); 2444c0d1c6b0SFabio Estevam return ret; 24451e512d45SUwe Kleine-König } 2446c0d1c6b0SFabio Estevam 24479d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2448c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24491e512d45SUwe Kleine-König if (ret) { 24501e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 24511e512d45SUwe Kleine-König ret); 2452c0d1c6b0SFabio Estevam return ret; 24531e512d45SUwe Kleine-König } 24547e620984SUwe Kleine-König 24557e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 24567e620984SUwe Kleine-König dev_name(&pdev->dev), sport); 24577e620984SUwe Kleine-König if (ret) { 24587e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n", 24597e620984SUwe Kleine-König ret); 24607e620984SUwe Kleine-König return ret; 24617e620984SUwe Kleine-König } 2462c0d1c6b0SFabio Estevam } else { 24639d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2464c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24651e512d45SUwe Kleine-König if (ret) { 24661e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2467c0d1c6b0SFabio Estevam return ret; 2468c0d1c6b0SFabio Estevam } 24691e512d45SUwe Kleine-König } 2470c0d1c6b0SFabio Estevam 24719d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2472ab4382d2SGreg Kroah-Hartman 24730a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2474ab4382d2SGreg Kroah-Hartman 24759d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2476ab4382d2SGreg Kroah-Hartman } 2477ab4382d2SGreg Kroah-Hartman 24789d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2479ab4382d2SGreg Kroah-Hartman { 2480ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2481ab4382d2SGreg Kroah-Hartman 24829d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2483ab4382d2SGreg Kroah-Hartman } 2484ab4382d2SGreg Kroah-Hartman 24859d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2486c868cbb7SEduardo Valentin { 248707b5e16eSAnson Huang unsigned long flags; 248807b5e16eSAnson Huang 248907b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 249007b5e16eSAnson Huang if (!sport->context_saved) { 249107b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2492c868cbb7SEduardo Valentin return; 249307b5e16eSAnson Huang } 2494c868cbb7SEduardo Valentin 249527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 249627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 249727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 249827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 249927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 250027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 250127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 250227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 250327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 250427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2505c868cbb7SEduardo Valentin sport->context_saved = false; 250607b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2507c868cbb7SEduardo Valentin } 2508c868cbb7SEduardo Valentin 25099d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2510c868cbb7SEduardo Valentin { 251107b5e16eSAnson Huang unsigned long flags; 251207b5e16eSAnson Huang 2513c868cbb7SEduardo Valentin /* Save necessary regs */ 251407b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 251527c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 251627c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 251727c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 251827c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 251927c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 252027c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 252127c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 252227c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 252327c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 252427c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2525c868cbb7SEduardo Valentin sport->context_saved = true; 252607b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2527c868cbb7SEduardo Valentin } 2528c868cbb7SEduardo Valentin 25299d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2530189550b8SEduardo Valentin { 25314444dcf1SUwe Kleine-König u32 ucr3; 2532189550b8SEduardo Valentin 25334444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 253409df0b34SMartin Kaiser if (on) { 253527c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 25364444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 25374444dcf1SUwe Kleine-König } else { 25384444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 253909df0b34SMartin Kaiser } 25404444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2541bc85734bSEduardo Valentin 254238b1f0fbSFabio Estevam if (sport->have_rtscts) { 25434444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2544bc85734bSEduardo Valentin if (on) 25454444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2546bc85734bSEduardo Valentin else 25474444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 25484444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2549189550b8SEduardo Valentin } 255038b1f0fbSFabio Estevam } 2551189550b8SEduardo Valentin 25529d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 255390bb6bd3SShenwei Wang { 2554a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 255590bb6bd3SShenwei Wang 25569d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 255790bb6bd3SShenwei Wang 255890bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 255990bb6bd3SShenwei Wang 2560fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev); 2561fcfed1beSAnson Huang 256290bb6bd3SShenwei Wang return 0; 256390bb6bd3SShenwei Wang } 256490bb6bd3SShenwei Wang 25659d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 256690bb6bd3SShenwei Wang { 2567a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 256890bb6bd3SShenwei Wang int ret; 256990bb6bd3SShenwei Wang 2570fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev); 2571fcfed1beSAnson Huang 257290bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 257390bb6bd3SShenwei Wang if (ret) 257490bb6bd3SShenwei Wang return ret; 257590bb6bd3SShenwei Wang 25769d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 257790bb6bd3SShenwei Wang 257890bb6bd3SShenwei Wang return 0; 257990bb6bd3SShenwei Wang } 258090bb6bd3SShenwei Wang 25819d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 258290bb6bd3SShenwei Wang { 2583a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 258409df0b34SMartin Kaiser int ret; 258590bb6bd3SShenwei Wang 25869d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 258781b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 258890bb6bd3SShenwei Wang 258909df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 259009df0b34SMartin Kaiser if (ret) 259109df0b34SMartin Kaiser return ret; 259209df0b34SMartin Kaiser 259309df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 25949d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 259509df0b34SMartin Kaiser 259609df0b34SMartin Kaiser return 0; 259790bb6bd3SShenwei Wang } 259890bb6bd3SShenwei Wang 25999d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 260090bb6bd3SShenwei Wang { 2601a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 260290bb6bd3SShenwei Wang 260390bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 26049d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 260590bb6bd3SShenwei Wang 26069d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 260781b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 260890bb6bd3SShenwei Wang 260909df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 261029add68dSMartin Fuzzey 261190bb6bd3SShenwei Wang return 0; 261290bb6bd3SShenwei Wang } 261390bb6bd3SShenwei Wang 26149d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 261594be6d74SPhilipp Zabel { 2616a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 261794be6d74SPhilipp Zabel 26189d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 261994be6d74SPhilipp Zabel 262009df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 262194be6d74SPhilipp Zabel } 262294be6d74SPhilipp Zabel 26239d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 262494be6d74SPhilipp Zabel { 2625a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 262694be6d74SPhilipp Zabel 26279d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 262894be6d74SPhilipp Zabel 262909df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 263094be6d74SPhilipp Zabel 263194be6d74SPhilipp Zabel return 0; 263294be6d74SPhilipp Zabel } 263394be6d74SPhilipp Zabel 26349d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 26359d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 26369d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 26379d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 26389d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 26399d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 26409d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 26419d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 26429d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 26439d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 264490bb6bd3SShenwei Wang }; 264590bb6bd3SShenwei Wang 26469d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 26479d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 26489d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2649ab4382d2SGreg Kroah-Hartman 2650fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2651ab4382d2SGreg Kroah-Hartman .driver = { 2652ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 265322698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 26549d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2655ab4382d2SGreg Kroah-Hartman }, 2656ab4382d2SGreg Kroah-Hartman }; 2657ab4382d2SGreg Kroah-Hartman 26589d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2659ab4382d2SGreg Kroah-Hartman { 26609d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2661ab4382d2SGreg Kroah-Hartman 2662ab4382d2SGreg Kroah-Hartman if (ret) 2663ab4382d2SGreg Kroah-Hartman return ret; 2664ab4382d2SGreg Kroah-Hartman 26659d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2666ab4382d2SGreg Kroah-Hartman if (ret != 0) 26679d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2668ab4382d2SGreg Kroah-Hartman 2669f227824eSUwe Kleine-König return ret; 2670ab4382d2SGreg Kroah-Hartman } 2671ab4382d2SGreg Kroah-Hartman 26729d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2673ab4382d2SGreg Kroah-Hartman { 26749d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 26759d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2676ab4382d2SGreg Kroah-Hartman } 2677ab4382d2SGreg Kroah-Hartman 26789d1a50a2SUwe Kleine-König module_init(imx_uart_init); 26799d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2680ab4382d2SGreg Kroah-Hartman 2681ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2682ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2683ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2684ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2685