1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 12ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 13ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 14ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 15ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 23bd78ecd6SAhmad Fatoum #include <linux/ktime.h> 24fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2722698aa2SShawn Guo #include <linux/of.h> 2822698aa2SShawn Guo #include <linux/of_device.h> 29e32a9f8fSSachin Kamat #include <linux/io.h> 30b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 31ab4382d2SGreg Kroah-Hartman 32ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 33b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 34ab4382d2SGreg Kroah-Hartman 3558362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3658362d5bSUwe Kleine-König 37ab4382d2SGreg Kroah-Hartman /* Register definitions */ 38ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 39ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 40ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 41ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 42ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 43ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 44ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 45ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 46ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 47ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 48ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 49ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 50ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 51ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 52fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 53fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 54fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 55ab4382d2SGreg Kroah-Hartman 56ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 5755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 58ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 59ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 60ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 61ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 62ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 63ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 66ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 67ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 68ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 69b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 71302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 72ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 76302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 77fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 78b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 81ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 83ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 95ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 96ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 97ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 101b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10527e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 106fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 110ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 111ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 115b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1227be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 123ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 125ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 126ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 127ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 128ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 129ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 130ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 131ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13386a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13427e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 136ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 137ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 138ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 139ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 140ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14290ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14390ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14690ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 149ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 150ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 151ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 152ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 153ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 154ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 155ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 156ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 157ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 158ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 159ab4382d2SGreg Kroah-Hartman 160ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 161ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 162ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 163ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 164ab4382d2SGreg Kroah-Hartman 165ab4382d2SGreg Kroah-Hartman /* 166ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 167ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 168ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 169ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 170ab4382d2SGreg Kroah-Hartman */ 171ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 172ab4382d2SGreg Kroah-Hartman 173ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 174ab4382d2SGreg Kroah-Hartman 175ab4382d2SGreg Kroah-Hartman #define UART_NR 8 176ab4382d2SGreg Kroah-Hartman 177f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 178fe6b540aSShawn Guo enum imx_uart_type { 179fe6b540aSShawn Guo IMX1_UART, 180fe6b540aSShawn Guo IMX21_UART, 1811c06bde6SMartyn Welch IMX53_UART, 182a496e628SHuang Shijie IMX6Q_UART, 183fe6b540aSShawn Guo }; 184fe6b540aSShawn Guo 185fe6b540aSShawn Guo /* device type dependent stuff */ 186fe6b540aSShawn Guo struct imx_uart_data { 187fe6b540aSShawn Guo unsigned uts_reg; 188fe6b540aSShawn Guo enum imx_uart_type devtype; 189fe6b540aSShawn Guo }; 190fe6b540aSShawn Guo 191cb1a6092SUwe Kleine-König enum imx_tx_state { 192cb1a6092SUwe Kleine-König OFF, 193cb1a6092SUwe Kleine-König WAIT_AFTER_RTS, 194cb1a6092SUwe Kleine-König SEND, 195cb1a6092SUwe Kleine-König WAIT_AFTER_SEND, 196cb1a6092SUwe Kleine-König }; 197cb1a6092SUwe Kleine-König 198ab4382d2SGreg Kroah-Hartman struct imx_port { 199ab4382d2SGreg Kroah-Hartman struct uart_port port; 200ab4382d2SGreg Kroah-Hartman struct timer_list timer; 201ab4382d2SGreg Kroah-Hartman unsigned int old_status; 202ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2037b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20420ff2fe6SHuang Shijie unsigned int dte_mode:1; 2055a08a487SGeorge Hilliard unsigned int inverted_tx:1; 2065a08a487SGeorge Hilliard unsigned int inverted_rx:1; 2073a9465faSSascha Hauer struct clk *clk_ipg; 2083a9465faSSascha Hauer struct clk *clk_per; 2097d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 210b4cdc8f6SHuang Shijie 21158362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21258362d5bSUwe Kleine-König 2133a0ab62fSUwe Kleine-König /* shadow registers */ 2143a0ab62fSUwe Kleine-König unsigned int ucr1; 2153a0ab62fSUwe Kleine-König unsigned int ucr2; 2163a0ab62fSUwe Kleine-König unsigned int ucr3; 2173a0ab62fSUwe Kleine-König unsigned int ucr4; 2183a0ab62fSUwe Kleine-König unsigned int ufcr; 2193a0ab62fSUwe Kleine-König 220b4cdc8f6SHuang Shijie /* DMA fields */ 221b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 224b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 225b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 226b4cdc8f6SHuang Shijie void *rx_buf; 2279d297239SNandor Han struct circ_buf rx_ring; 228*db0a196bSFabien Lahoudere unsigned int rx_buf_size; 229*db0a196bSFabien Lahoudere unsigned int rx_period_length; 2309d297239SNandor Han unsigned int rx_periods; 2319d297239SNandor Han dma_cookie_t rx_cookie; 2327cb92fd2SHuang Shijie unsigned int tx_bytes; 233b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 23490bb6bd3SShenwei Wang unsigned int saved_reg[10]; 235c868cbb7SEduardo Valentin bool context_saved; 236cb1a6092SUwe Kleine-König 237cb1a6092SUwe Kleine-König enum imx_tx_state tx_state; 238bd78ecd6SAhmad Fatoum struct hrtimer trigger_start_tx; 239bd78ecd6SAhmad Fatoum struct hrtimer trigger_stop_tx; 240ab4382d2SGreg Kroah-Hartman }; 241ab4382d2SGreg Kroah-Hartman 2420ad5a814SDirk Behme struct imx_port_ucrs { 2430ad5a814SDirk Behme unsigned int ucr1; 2440ad5a814SDirk Behme unsigned int ucr2; 2450ad5a814SDirk Behme unsigned int ucr3; 2460ad5a814SDirk Behme }; 2470ad5a814SDirk Behme 248fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 249fe6b540aSShawn Guo [IMX1_UART] = { 250fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 251fe6b540aSShawn Guo .devtype = IMX1_UART, 252fe6b540aSShawn Guo }, 253fe6b540aSShawn Guo [IMX21_UART] = { 254fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 255fe6b540aSShawn Guo .devtype = IMX21_UART, 256fe6b540aSShawn Guo }, 2571c06bde6SMartyn Welch [IMX53_UART] = { 2581c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2591c06bde6SMartyn Welch .devtype = IMX53_UART, 2601c06bde6SMartyn Welch }, 261a496e628SHuang Shijie [IMX6Q_UART] = { 262a496e628SHuang Shijie .uts_reg = IMX21_UTS, 263a496e628SHuang Shijie .devtype = IMX6Q_UART, 264a496e628SHuang Shijie }, 265fe6b540aSShawn Guo }; 266fe6b540aSShawn Guo 267ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 268a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2691c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27022698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27122698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27222698aa2SShawn Guo { /* sentinel */ } 27322698aa2SShawn Guo }; 27422698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27522698aa2SShawn Guo 27627c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 27727c84426SUwe Kleine-König { 2783a0ab62fSUwe Kleine-König switch (offset) { 2793a0ab62fSUwe Kleine-König case UCR1: 2803a0ab62fSUwe Kleine-König sport->ucr1 = val; 2813a0ab62fSUwe Kleine-König break; 2823a0ab62fSUwe Kleine-König case UCR2: 2833a0ab62fSUwe Kleine-König sport->ucr2 = val; 2843a0ab62fSUwe Kleine-König break; 2853a0ab62fSUwe Kleine-König case UCR3: 2863a0ab62fSUwe Kleine-König sport->ucr3 = val; 2873a0ab62fSUwe Kleine-König break; 2883a0ab62fSUwe Kleine-König case UCR4: 2893a0ab62fSUwe Kleine-König sport->ucr4 = val; 2903a0ab62fSUwe Kleine-König break; 2913a0ab62fSUwe Kleine-König case UFCR: 2923a0ab62fSUwe Kleine-König sport->ufcr = val; 2933a0ab62fSUwe Kleine-König break; 2943a0ab62fSUwe Kleine-König default: 2953a0ab62fSUwe Kleine-König break; 2963a0ab62fSUwe Kleine-König } 29727c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 29827c84426SUwe Kleine-König } 29927c84426SUwe Kleine-König 30027c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30127c84426SUwe Kleine-König { 3023a0ab62fSUwe Kleine-König switch (offset) { 3033a0ab62fSUwe Kleine-König case UCR1: 3043a0ab62fSUwe Kleine-König return sport->ucr1; 3053a0ab62fSUwe Kleine-König break; 3063a0ab62fSUwe Kleine-König case UCR2: 3073a0ab62fSUwe Kleine-König /* 3083a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3093a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 310728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 311728e74a4SUwe Kleine-König * conditionally. 3123a0ab62fSUwe Kleine-König */ 3130aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3143a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3153a0ab62fSUwe Kleine-König return sport->ucr2; 3163a0ab62fSUwe Kleine-König break; 3173a0ab62fSUwe Kleine-König case UCR3: 3183a0ab62fSUwe Kleine-König return sport->ucr3; 3193a0ab62fSUwe Kleine-König break; 3203a0ab62fSUwe Kleine-König case UCR4: 3213a0ab62fSUwe Kleine-König return sport->ucr4; 3223a0ab62fSUwe Kleine-König break; 3233a0ab62fSUwe Kleine-König case UFCR: 3243a0ab62fSUwe Kleine-König return sport->ufcr; 3253a0ab62fSUwe Kleine-König break; 3263a0ab62fSUwe Kleine-König default: 32727c84426SUwe Kleine-König return readl(sport->port.membase + offset); 32827c84426SUwe Kleine-König } 3293a0ab62fSUwe Kleine-König } 33027c84426SUwe Kleine-König 3319d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 332fe6b540aSShawn Guo { 333fe6b540aSShawn Guo return sport->devdata->uts_reg; 334fe6b540aSShawn Guo } 335fe6b540aSShawn Guo 3369d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 337fe6b540aSShawn Guo { 338fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 339fe6b540aSShawn Guo } 340fe6b540aSShawn Guo 3419d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 342fe6b540aSShawn Guo { 343fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 344fe6b540aSShawn Guo } 345fe6b540aSShawn Guo 3469d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3471c06bde6SMartyn Welch { 3481c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3491c06bde6SMartyn Welch } 3501c06bde6SMartyn Welch 3519d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 352a496e628SHuang Shijie { 353a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 354a496e628SHuang Shijie } 355ab4382d2SGreg Kroah-Hartman /* 35644a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 35744a75411Sfabio.estevam@freescale.com */ 3580db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 3599d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 36044a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36144a75411Sfabio.estevam@freescale.com { 36244a75411Sfabio.estevam@freescale.com /* save control registers */ 36327c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 36427c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 36527c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 36644a75411Sfabio.estevam@freescale.com } 36744a75411Sfabio.estevam@freescale.com 3689d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 36944a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37044a75411Sfabio.estevam@freescale.com { 37144a75411Sfabio.estevam@freescale.com /* restore control registers */ 37227c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 37327c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 37427c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 37544a75411Sfabio.estevam@freescale.com } 376e8bfa760SFabio Estevam #endif 37744a75411Sfabio.estevam@freescale.com 3784e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3799d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 38058362d5bSUwe Kleine-König { 381bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38258362d5bSUwe Kleine-König 383a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 384a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 38558362d5bSUwe Kleine-König } 38658362d5bSUwe Kleine-König 3874e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3889d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 38958362d5bSUwe Kleine-König { 390bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 391bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39258362d5bSUwe Kleine-König 393a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 394a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39558362d5bSUwe Kleine-König } 39658362d5bSUwe Kleine-König 397bd78ecd6SAhmad Fatoum static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 398bd78ecd6SAhmad Fatoum { 399f751ae1cSJiri Slaby hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 400bd78ecd6SAhmad Fatoum } 401bd78ecd6SAhmad Fatoum 4026aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4039d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 40476821e22SUwe Kleine-König { 40576821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 40676821e22SUwe Kleine-König unsigned int ucr1, ucr2; 40776821e22SUwe Kleine-König 40876821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 40976821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 41076821e22SUwe Kleine-König 41176821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41276821e22SUwe Kleine-König 41376821e22SUwe Kleine-König if (sport->dma_is_enabled) { 41476821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 41576821e22SUwe Kleine-König } else { 41676821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 41781ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 41876821e22SUwe Kleine-König } 41976821e22SUwe Kleine-König 42076821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 42176821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42376821e22SUwe Kleine-König } 42476821e22SUwe Kleine-König 42576821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4269d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 427ab4382d2SGreg Kroah-Hartman { 428ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 429cb1a6092SUwe Kleine-König u32 ucr1, ucr4, usr2; 430cb1a6092SUwe Kleine-König 431cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) 432cb1a6092SUwe Kleine-König return; 433ab4382d2SGreg Kroah-Hartman 4349ce4f8f3SGreg Kroah-Hartman /* 4359ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4369ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4379ce4f8f3SGreg Kroah-Hartman */ 438686351f3SUwe Kleine-König if (sport->dma_is_txing) 4399ce4f8f3SGreg Kroah-Hartman return; 440b4cdc8f6SHuang Shijie 4414444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 442c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 44317b8f2a3SUwe Kleine-König 444cb1a6092SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 445cb1a6092SUwe Kleine-König if (!(usr2 & USR2_TXDC)) { 446cb1a6092SUwe Kleine-König /* The shifter is still busy, so retry once TC triggers */ 447cb1a6092SUwe Kleine-König return; 448cb1a6092SUwe Kleine-König } 449cb1a6092SUwe Kleine-König 450cb1a6092SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 451cb1a6092SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 452cb1a6092SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 453cb1a6092SUwe Kleine-König 454cb1a6092SUwe Kleine-König /* in rs485 mode disable transmitter */ 455cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 456cb1a6092SUwe Kleine-König if (sport->tx_state == SEND) { 457cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_SEND; 458bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_stop_tx, 459bd78ecd6SAhmad Fatoum port->rs485.delay_rts_after_send); 460bd78ecd6SAhmad Fatoum return; 461cb1a6092SUwe Kleine-König } 462cb1a6092SUwe Kleine-König 463cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS || 464bd78ecd6SAhmad Fatoum sport->tx_state == WAIT_AFTER_SEND) { 465cb1a6092SUwe Kleine-König u32 ucr2; 466cb1a6092SUwe Kleine-König 467bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_start_tx); 468cb1a6092SUwe Kleine-König 469cb1a6092SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 47017b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4719d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4721a613626SFabio Estevam else 4739d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4744444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 47517b8f2a3SUwe Kleine-König 4769d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 47776821e22SUwe Kleine-König 478cb1a6092SUwe Kleine-König sport->tx_state = OFF; 479cb1a6092SUwe Kleine-König } 480cb1a6092SUwe Kleine-König } else { 481cb1a6092SUwe Kleine-König sport->tx_state = OFF; 48217b8f2a3SUwe Kleine-König } 483ab4382d2SGreg Kroah-Hartman } 484ab4382d2SGreg Kroah-Hartman 4856aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4869d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 487ab4382d2SGreg Kroah-Hartman { 488ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4894444dcf1SUwe Kleine-König u32 ucr1, ucr2; 490ab4382d2SGreg Kroah-Hartman 4914444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 49276821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 49376821e22SUwe Kleine-König 49476821e22SUwe Kleine-König if (sport->dma_is_enabled) { 49576821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 49676821e22SUwe Kleine-König } else { 49776821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 49881ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 49976821e22SUwe Kleine-König } 50076821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 50176821e22SUwe Kleine-König 50276821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 50376821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 504ab4382d2SGreg Kroah-Hartman } 505ab4382d2SGreg Kroah-Hartman 5066aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5079d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 508ab4382d2SGreg Kroah-Hartman { 509ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 510ab4382d2SGreg Kroah-Hartman 511ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 51258362d5bSUwe Kleine-König 51358362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 514ab4382d2SGreg Kroah-Hartman } 515ab4382d2SGreg Kroah-Hartman 5169d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 5176aed2a88SUwe Kleine-König 5186aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5199d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 520ab4382d2SGreg Kroah-Hartman { 521ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 522ab4382d2SGreg Kroah-Hartman 5235e42e9a3SPeter Hurley if (sport->port.x_char) { 5245e42e9a3SPeter Hurley /* Send next char */ 52527c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5267e2fb5aaSJiada Wang sport->port.icount.tx++; 5277e2fb5aaSJiada Wang sport->port.x_char = 0; 5285e42e9a3SPeter Hurley return; 5295e42e9a3SPeter Hurley } 5305e42e9a3SPeter Hurley 5315e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5329d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5335e42e9a3SPeter Hurley return; 5345e42e9a3SPeter Hurley } 5355e42e9a3SPeter Hurley 53691a1a909SJiada Wang if (sport->dma_is_enabled) { 5374444dcf1SUwe Kleine-König u32 ucr1; 53891a1a909SJiada Wang /* 53991a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 54091a1a909SJiada Wang * and the TX IRQ is disabled. 54191a1a909SJiada Wang **/ 5424444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 543c514a6f8SSergey Organov ucr1 &= ~UCR1_TRDYEN; 54491a1a909SJiada Wang if (sport->dma_is_txing) { 5454444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5464444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 54791a1a909SJiada Wang } else { 5484444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5499d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 55091a1a909SJiada Wang } 55191a1a909SJiada Wang 5525aabd3b0SIan Jamison return; 5530c549223SUwe Kleine-König } 5545aabd3b0SIan Jamison 5555aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5569d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 557ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 558ab4382d2SGreg Kroah-Hartman * out the port here */ 55927c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 560ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 561ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 562ab4382d2SGreg Kroah-Hartman } 563ab4382d2SGreg Kroah-Hartman 564ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 565ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 566ab4382d2SGreg Kroah-Hartman 567ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5689d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 569ab4382d2SGreg Kroah-Hartman } 570ab4382d2SGreg Kroah-Hartman 5719d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 572b4cdc8f6SHuang Shijie { 573b4cdc8f6SHuang Shijie struct imx_port *sport = data; 574b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 575b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 576b4cdc8f6SHuang Shijie unsigned long flags; 5774444dcf1SUwe Kleine-König u32 ucr1; 578b4cdc8f6SHuang Shijie 57942f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 58042f752b3SDirk Behme 581b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 582b4cdc8f6SHuang Shijie 5834444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5844444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5854444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 586a2c718ceSDirk Behme 58742f752b3SDirk Behme /* update the stat */ 58842f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 58942f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 59042f752b3SDirk Behme 59142f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 59242f752b3SDirk Behme 593b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 594b4cdc8f6SHuang Shijie 595d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 596b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5979ce4f8f3SGreg Kroah-Hartman 5980bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5999d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 60018665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 60118665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 60218665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 60318665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 60418665414SUwe Kleine-König } 60564432a85SUwe Kleine-König 6060bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 607b4cdc8f6SHuang Shijie } 608b4cdc8f6SHuang Shijie 6096aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6109d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 611b4cdc8f6SHuang Shijie { 612b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 613b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 614b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 615b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 616b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 61718665414SUwe Kleine-König u32 ucr1, ucr4; 618b4cdc8f6SHuang Shijie int ret; 619b4cdc8f6SHuang Shijie 62042f752b3SDirk Behme if (sport->dma_is_txing) 621b4cdc8f6SHuang Shijie return; 622b4cdc8f6SHuang Shijie 62318665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 62418665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 62518665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 62618665414SUwe Kleine-König 627b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 628b4cdc8f6SHuang Shijie 629f7670783SFugang Duan if (xmit->tail < xmit->head || xmit->head == 0) { 6307942f857SDirk Behme sport->dma_tx_nents = 1; 6317942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6327942f857SDirk Behme } else { 633b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 634b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 635b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 636b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 637b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 638b4cdc8f6SHuang Shijie } 639b4cdc8f6SHuang Shijie 640b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 641b4cdc8f6SHuang Shijie if (ret == 0) { 642b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 643b4cdc8f6SHuang Shijie return; 644b4cdc8f6SHuang Shijie } 645596fd8dfSPeng Fan desc = dmaengine_prep_slave_sg(chan, sgl, ret, 646b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 647b4cdc8f6SHuang Shijie if (!desc) { 64824649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 64924649821SDirk Behme DMA_TO_DEVICE); 650b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 651b4cdc8f6SHuang Shijie return; 652b4cdc8f6SHuang Shijie } 6539d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 654b4cdc8f6SHuang Shijie desc->callback_param = sport; 655b4cdc8f6SHuang Shijie 656b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 657b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 658a2c718ceSDirk Behme 6594444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6604444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6614444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 662a2c718ceSDirk Behme 663b4cdc8f6SHuang Shijie /* fire it */ 664b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 665b4cdc8f6SHuang Shijie dmaengine_submit(desc); 666b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 667b4cdc8f6SHuang Shijie return; 668b4cdc8f6SHuang Shijie } 669b4cdc8f6SHuang Shijie 6706aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6719d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 672ab4382d2SGreg Kroah-Hartman { 673ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6744444dcf1SUwe Kleine-König u32 ucr1; 675ab4382d2SGreg Kroah-Hartman 67648669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 67748669b69SUwe Kleine-König return; 67848669b69SUwe Kleine-König 679cb1a6092SUwe Kleine-König /* 680cb1a6092SUwe Kleine-König * We cannot simply do nothing here if sport->tx_state == SEND already 681cb1a6092SUwe Kleine-König * because UCR1_TXMPTYEN might already have been cleared in 682cb1a6092SUwe Kleine-König * imx_uart_stop_tx(), but tx_state is still SEND. 683cb1a6092SUwe Kleine-König */ 6844444dcf1SUwe Kleine-König 685cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 686cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) { 687cb1a6092SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2); 68817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6899d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 6901a613626SFabio Estevam else 6919d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 6924444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 69317b8f2a3SUwe Kleine-König 69476821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 6959d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 69676821e22SUwe Kleine-König 697cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_RTS; 698bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_start_tx, 699bd78ecd6SAhmad Fatoum port->rs485.delay_rts_before_send); 700bd78ecd6SAhmad Fatoum return; 701cb1a6092SUwe Kleine-König } 702cb1a6092SUwe Kleine-König 703bd78ecd6SAhmad Fatoum if (sport->tx_state == WAIT_AFTER_SEND 704bd78ecd6SAhmad Fatoum || sport->tx_state == WAIT_AFTER_RTS) { 705cb1a6092SUwe Kleine-König 706bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_stop_tx); 707bd78ecd6SAhmad Fatoum 70818665414SUwe Kleine-König /* 709cb1a6092SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA 710cb1a6092SUwe Kleine-König * is off. In the DMA case this is done in the 711cb1a6092SUwe Kleine-König * tx-callback. 71218665414SUwe Kleine-König */ 71318665414SUwe Kleine-König if (!sport->dma_is_enabled) { 71418665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 7154444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 7164444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 71717b8f2a3SUwe Kleine-König } 718cb1a6092SUwe Kleine-König 719cb1a6092SUwe Kleine-König sport->tx_state = SEND; 720cb1a6092SUwe Kleine-König } 721cb1a6092SUwe Kleine-König } else { 722cb1a6092SUwe Kleine-König sport->tx_state = SEND; 72318665414SUwe Kleine-König } 72417b8f2a3SUwe Kleine-König 725b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 7264444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 727c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 728b4cdc8f6SHuang Shijie } 729ab4382d2SGreg Kroah-Hartman 730b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 73191a1a909SJiada Wang if (sport->port.x_char) { 73291a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 73391a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 7344444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 7354444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 736c514a6f8SSergey Organov ucr1 |= UCR1_TRDYEN; 7374444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 73891a1a909SJiada Wang return; 73991a1a909SJiada Wang } 74091a1a909SJiada Wang 7415e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 7425e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7439d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 744b4cdc8f6SHuang Shijie return; 745b4cdc8f6SHuang Shijie } 746ab4382d2SGreg Kroah-Hartman } 747ab4382d2SGreg Kroah-Hartman 748101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 749ab4382d2SGreg Kroah-Hartman { 750ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7514444dcf1SUwe Kleine-König u32 usr1; 752ab4382d2SGreg Kroah-Hartman 75327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7544444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7554444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 756ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 757ab4382d2SGreg Kroah-Hartman 758ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 759ab4382d2SGreg Kroah-Hartman } 760ab4382d2SGreg Kroah-Hartman 761101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 762101aa46bSUwe Kleine-König { 763101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 764101aa46bSUwe Kleine-König irqreturn_t ret; 765101aa46bSUwe Kleine-König 766101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 767101aa46bSUwe Kleine-König 768101aa46bSUwe Kleine-König ret = __imx_uart_rtsint(irq, dev_id); 769101aa46bSUwe Kleine-König 770101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 771101aa46bSUwe Kleine-König 772101aa46bSUwe Kleine-König return ret; 773101aa46bSUwe Kleine-König } 774101aa46bSUwe Kleine-König 7759d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 776ab4382d2SGreg Kroah-Hartman { 777ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 778ab4382d2SGreg Kroah-Hartman 779c974991dSjun qian spin_lock(&sport->port.lock); 7809d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 781c974991dSjun qian spin_unlock(&sport->port.lock); 782ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 783ab4382d2SGreg Kroah-Hartman } 784ab4382d2SGreg Kroah-Hartman 785101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 786ab4382d2SGreg Kroah-Hartman { 787ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 788ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 78992a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 790ab4382d2SGreg Kroah-Hartman 79127c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 7924444dcf1SUwe Kleine-König u32 usr2; 7934444dcf1SUwe Kleine-König 794ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 795ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 796ab4382d2SGreg Kroah-Hartman 79727c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 798ab4382d2SGreg Kroah-Hartman 7994444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 8004444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 80127c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 802ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 803ab4382d2SGreg Kroah-Hartman continue; 804ab4382d2SGreg Kroah-Hartman } 805ab4382d2SGreg Kroah-Hartman 806ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 807ab4382d2SGreg Kroah-Hartman continue; 808ab4382d2SGreg Kroah-Hartman 809019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 810019dc9eaSHui Wang if (rx & URXD_BRK) 811019dc9eaSHui Wang sport->port.icount.brk++; 812019dc9eaSHui Wang else if (rx & URXD_PRERR) 813ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 814ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 815ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 816ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 817ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 818ab4382d2SGreg Kroah-Hartman 819ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 820ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 821ab4382d2SGreg Kroah-Hartman goto out; 822ab4382d2SGreg Kroah-Hartman continue; 823ab4382d2SGreg Kroah-Hartman } 824ab4382d2SGreg Kroah-Hartman 8258d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 826ab4382d2SGreg Kroah-Hartman 827019dc9eaSHui Wang if (rx & URXD_BRK) 828019dc9eaSHui Wang flg = TTY_BREAK; 829019dc9eaSHui Wang else if (rx & URXD_PRERR) 830ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 831ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 832ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 833ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 834ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 835ab4382d2SGreg Kroah-Hartman 836ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 837ab4382d2SGreg Kroah-Hartman } 838ab4382d2SGreg Kroah-Hartman 83955d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 84055d8693aSJiada Wang goto out; 84155d8693aSJiada Wang 8429b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 8439b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 844ab4382d2SGreg Kroah-Hartman } 845ab4382d2SGreg Kroah-Hartman 846ab4382d2SGreg Kroah-Hartman out: 8472e124b4aSJiri Slaby tty_flip_buffer_push(port); 848101aa46bSUwe Kleine-König 849ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 850ab4382d2SGreg Kroah-Hartman } 851ab4382d2SGreg Kroah-Hartman 852101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 853101aa46bSUwe Kleine-König { 854101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 855101aa46bSUwe Kleine-König irqreturn_t ret; 856101aa46bSUwe Kleine-König 857101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 858101aa46bSUwe Kleine-König 859101aa46bSUwe Kleine-König ret = __imx_uart_rxint(irq, dev_id); 860101aa46bSUwe Kleine-König 861101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 862101aa46bSUwe Kleine-König 863101aa46bSUwe Kleine-König return ret; 864101aa46bSUwe Kleine-König } 865101aa46bSUwe Kleine-König 8669d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 867b4cdc8f6SHuang Shijie 86866f95884SUwe Kleine-König /* 86966f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 87066f95884SUwe Kleine-König */ 8719d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 87266f95884SUwe Kleine-König { 87366f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 87427c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 87527c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 87666f95884SUwe Kleine-König 87766f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 87866f95884SUwe Kleine-König tmp |= TIOCM_CTS; 87966f95884SUwe Kleine-König 88066f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 8814b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 88266f95884SUwe Kleine-König tmp |= TIOCM_CAR; 88366f95884SUwe Kleine-König 88466f95884SUwe Kleine-König if (sport->dte_mode) 88527c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 88666f95884SUwe Kleine-König tmp |= TIOCM_RI; 88766f95884SUwe Kleine-König 88866f95884SUwe Kleine-König return tmp; 88966f95884SUwe Kleine-König } 89066f95884SUwe Kleine-König 89166f95884SUwe Kleine-König /* 89266f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 89366f95884SUwe Kleine-König */ 8949d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 89566f95884SUwe Kleine-König { 89666f95884SUwe Kleine-König unsigned int status, changed; 89766f95884SUwe Kleine-König 8989d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 89966f95884SUwe Kleine-König changed = status ^ sport->old_status; 90066f95884SUwe Kleine-König 90166f95884SUwe Kleine-König if (changed == 0) 90266f95884SUwe Kleine-König return; 90366f95884SUwe Kleine-König 90466f95884SUwe Kleine-König sport->old_status = status; 90566f95884SUwe Kleine-König 90666f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 90766f95884SUwe Kleine-König sport->port.icount.rng++; 90866f95884SUwe Kleine-König if (changed & TIOCM_DSR) 90966f95884SUwe Kleine-König sport->port.icount.dsr++; 91066f95884SUwe Kleine-König if (changed & TIOCM_CAR) 91166f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 91266f95884SUwe Kleine-König if (changed & TIOCM_CTS) 91366f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 91466f95884SUwe Kleine-König 91566f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 91666f95884SUwe Kleine-König } 91766f95884SUwe Kleine-König 9189d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 919ab4382d2SGreg Kroah-Hartman { 920ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 92143776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 9224d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 923ab4382d2SGreg Kroah-Hartman 9249baedb7bSJohan Hovold spin_lock(&sport->port.lock); 925101aa46bSUwe Kleine-König 92627c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 92727c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 92827c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 92927c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 93027c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 93127c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 932ab4382d2SGreg Kroah-Hartman 93343776896SUwe Kleine-König /* 93443776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 93543776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 93643776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 93743776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 93843776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 93943776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 94043776896SUwe Kleine-König */ 94143776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 94243776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 94343776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 94443776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 945c514a6f8SSergey Organov if ((ucr1 & UCR1_TRDYEN) == 0) 94643776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 94743776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 94843776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 94943776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 95043776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 95143776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 95243776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 95343776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 95443776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 95543776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 95643776896SUwe Kleine-König usr2 &= ~USR2_ORE; 95743776896SUwe Kleine-König 95843776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 959d1d996afSMatthias Schiffer imx_uart_writel(sport, USR1_AGTIM, USR1); 960d1d996afSMatthias Schiffer 961101aa46bSUwe Kleine-König __imx_uart_rxint(irq, dev_id); 9624d845a62SUwe Kleine-König ret = IRQ_HANDLED; 963b4cdc8f6SHuang Shijie } 964ab4382d2SGreg Kroah-Hartman 96543776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 966101aa46bSUwe Kleine-König imx_uart_transmit_buffer(sport); 9674d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9684d845a62SUwe Kleine-König } 969ab4382d2SGreg Kroah-Hartman 9700399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 97127c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 97227e16501SUwe Kleine-König 9739d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 97427e16501SUwe Kleine-König 97527e16501SUwe Kleine-König ret = IRQ_HANDLED; 97627e16501SUwe Kleine-König } 97727e16501SUwe Kleine-König 9780399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 979101aa46bSUwe Kleine-König __imx_uart_rtsint(irq, dev_id); 9804d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9814d845a62SUwe Kleine-König } 982ab4382d2SGreg Kroah-Hartman 9830399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 98427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 9854d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9864d845a62SUwe Kleine-König } 987db1a9b55SFabio Estevam 9880399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 989f1f836e4SAlexander Stein sport->port.icount.overrun++; 99027c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 9914d845a62SUwe Kleine-König ret = IRQ_HANDLED; 992f1f836e4SAlexander Stein } 993f1f836e4SAlexander Stein 9949baedb7bSJohan Hovold spin_unlock(&sport->port.lock); 995101aa46bSUwe Kleine-König 9964d845a62SUwe Kleine-König return ret; 997ab4382d2SGreg Kroah-Hartman } 998ab4382d2SGreg Kroah-Hartman 999ab4382d2SGreg Kroah-Hartman /* 1000ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 1001ab4382d2SGreg Kroah-Hartman */ 10029d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 1003ab4382d2SGreg Kroah-Hartman { 1004ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10051ce43e58SHuang Shijie unsigned int ret; 1006ab4382d2SGreg Kroah-Hartman 100727c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 10081ce43e58SHuang Shijie 10091ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 1010686351f3SUwe Kleine-König if (sport->dma_is_txing) 10111ce43e58SHuang Shijie ret = 0; 10121ce43e58SHuang Shijie 10131ce43e58SHuang Shijie return ret; 1014ab4382d2SGreg Kroah-Hartman } 1015ab4382d2SGreg Kroah-Hartman 10166aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10179d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 101858362d5bSUwe Kleine-König { 101958362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 10209d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 102158362d5bSUwe Kleine-König 102258362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 102358362d5bSUwe Kleine-König 102458362d5bSUwe Kleine-König return ret; 102558362d5bSUwe Kleine-König } 102658362d5bSUwe Kleine-König 10276aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10289d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1029ab4382d2SGreg Kroah-Hartman { 1030ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10314444dcf1SUwe Kleine-König u32 ucr3, uts; 1032ab4382d2SGreg Kroah-Hartman 103317b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 10344444dcf1SUwe Kleine-König u32 ucr2; 10354444dcf1SUwe Kleine-König 1036197540dcSSergey Organov /* 1037197540dcSSergey Organov * Turn off autoRTS if RTS is lowered and restore autoRTS 1038197540dcSSergey Organov * setting if RTS is raised. 1039197540dcSSergey Organov */ 10404444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 10414444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1042197540dcSSergey Organov if (mctrl & TIOCM_RTS) { 1043197540dcSSergey Organov ucr2 |= UCR2_CTS; 1044197540dcSSergey Organov /* 1045197540dcSSergey Organov * UCR2_IRTS is unset if and only if the port is 1046197540dcSSergey Organov * configured for CRTSCTS, so we use inverted UCR2_IRTS 1047197540dcSSergey Organov * to get the state to restore to. 1048197540dcSSergey Organov */ 1049197540dcSSergey Organov if (!(ucr2 & UCR2_IRTS)) 1050197540dcSSergey Organov ucr2 |= UCR2_CTSC; 1051197540dcSSergey Organov } 10524444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 105317b8f2a3SUwe Kleine-König } 10546b471a98SHuang Shijie 10554444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 105690ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 10574444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 10584444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 105990ebc483SUwe Kleine-König 10609d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 10616b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 10624444dcf1SUwe Kleine-König uts |= UTS_LOOP; 10639d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 106458362d5bSUwe Kleine-König 106558362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 1066ab4382d2SGreg Kroah-Hartman } 1067ab4382d2SGreg Kroah-Hartman 1068ab4382d2SGreg Kroah-Hartman /* 1069ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 1070ab4382d2SGreg Kroah-Hartman */ 10719d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1072ab4382d2SGreg Kroah-Hartman { 1073ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10744444dcf1SUwe Kleine-König unsigned long flags; 10754444dcf1SUwe Kleine-König u32 ucr1; 1076ab4382d2SGreg Kroah-Hartman 1077ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1078ab4382d2SGreg Kroah-Hartman 10794444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1080ab4382d2SGreg Kroah-Hartman 1081ab4382d2SGreg Kroah-Hartman if (break_state != 0) 10824444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1083ab4382d2SGreg Kroah-Hartman 10844444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1085ab4382d2SGreg Kroah-Hartman 1086ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1087ab4382d2SGreg Kroah-Hartman } 1088ab4382d2SGreg Kroah-Hartman 1089cc568849SUwe Kleine-König /* 1090cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1091cc568849SUwe Kleine-König * modem status signals. 1092cc568849SUwe Kleine-König */ 10939d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1094cc568849SUwe Kleine-König { 1095e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1096cc568849SUwe Kleine-König unsigned long flags; 1097cc568849SUwe Kleine-König 1098cc568849SUwe Kleine-König if (sport->port.state) { 1099cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 11009d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1101cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1102cc568849SUwe Kleine-König 1103cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1104cc568849SUwe Kleine-König } 1105cc568849SUwe Kleine-König } 1106cc568849SUwe Kleine-König 1107b4cdc8f6SHuang Shijie /* 1108905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1109b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1110905c0decSLucas Stach * [2] the aging timer expires 1111b4cdc8f6SHuang Shijie * 1112905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1113905c0decSLucas Stach * for at least 8 byte durations. 1114b4cdc8f6SHuang Shijie */ 11159d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1116b4cdc8f6SHuang Shijie { 1117b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1118b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1119b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 11207cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1121b4cdc8f6SHuang Shijie struct dma_tx_state state; 11229d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1123b4cdc8f6SHuang Shijie enum dma_status status; 11249d297239SNandor Han unsigned int w_bytes = 0; 11259d297239SNandor Han unsigned int r_bytes; 11269d297239SNandor Han unsigned int bd_size; 1127b4cdc8f6SHuang Shijie 1128fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1129392bceedSPhilipp Zabel 11309d297239SNandor Han if (status == DMA_ERROR) { 11319d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 11329d297239SNandor Han return; 11339d297239SNandor Han } 1134b4cdc8f6SHuang Shijie 11359b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1136976b39cdSLucas Stach 1137976b39cdSLucas Stach /* 11389d297239SNandor Han * The state-residue variable represents the empty space 11399d297239SNandor Han * relative to the entire buffer. Taking this in consideration 11409d297239SNandor Han * the head is always calculated base on the buffer total 11419d297239SNandor Han * length - DMA transaction residue. The UART script from the 11429d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 11439d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 11449d297239SNandor Han * Taking this in consideration the tail is always at the 11459d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1146976b39cdSLucas Stach */ 11479d297239SNandor Han 11489d297239SNandor Han /* Calculate the head */ 11499d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 11509d297239SNandor Han 11519d297239SNandor Han /* Calculate the tail. */ 11529d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 11539d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 11549d297239SNandor Han 11559d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 11569d297239SNandor Han rx_ring->head > rx_ring->tail) { 11579d297239SNandor Han 11589d297239SNandor Han /* Move data from tail to head */ 11599d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 11609d297239SNandor Han 11619d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 11629d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 11639d297239SNandor Han DMA_FROM_DEVICE); 11649d297239SNandor Han 11659d297239SNandor Han w_bytes = tty_insert_flip_string(port, 11669d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 11679d297239SNandor Han 11689d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 11699d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 11709d297239SNandor Han DMA_FROM_DEVICE); 11719d297239SNandor Han 11729d297239SNandor Han if (w_bytes != r_bytes) 11739d297239SNandor Han sport->port.icount.buf_overrun++; 11749d297239SNandor Han 11759d297239SNandor Han sport->port.icount.rx += w_bytes; 11769d297239SNandor Han } else { 11779d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11789d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1179ee5e7c10SRobin Gong } 11809d297239SNandor Han } 11819d297239SNandor Han 11829d297239SNandor Han if (w_bytes) { 11839d297239SNandor Han tty_flip_buffer_push(port); 11849d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 11859d297239SNandor Han } 11869d297239SNandor Han } 11879d297239SNandor Han 11889d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1189b4cdc8f6SHuang Shijie { 1190b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1191b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1192b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1193b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1194b4cdc8f6SHuang Shijie int ret; 1195b4cdc8f6SHuang Shijie 11969d297239SNandor Han sport->rx_ring.head = 0; 11979d297239SNandor Han sport->rx_ring.tail = 0; 11989d297239SNandor Han 1199*db0a196bSFabien Lahoudere sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); 1200b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1201b4cdc8f6SHuang Shijie if (ret == 0) { 1202b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1203b4cdc8f6SHuang Shijie return -EINVAL; 1204b4cdc8f6SHuang Shijie } 12059d297239SNandor Han 12069d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 12079d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 12089d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 12099d297239SNandor Han 1210b4cdc8f6SHuang Shijie if (!desc) { 121124649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1212b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1213b4cdc8f6SHuang Shijie return -EINVAL; 1214b4cdc8f6SHuang Shijie } 12159d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1216b4cdc8f6SHuang Shijie desc->callback_param = sport; 1217b4cdc8f6SHuang Shijie 1218b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 12194139fd76SRomain Perier sport->dma_is_rxing = 1; 12209d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1221b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1222b4cdc8f6SHuang Shijie return 0; 1223b4cdc8f6SHuang Shijie } 1224b4cdc8f6SHuang Shijie 12259d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 122641d98b5dSNandor Han { 122745ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 12284444dcf1SUwe Kleine-König u32 usr1, usr2; 122941d98b5dSNandor Han 12304444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 12314444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 123241d98b5dSNandor Han 12334444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 123441d98b5dSNandor Han sport->port.icount.brk++; 123527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 123645ca673eSTroy Kisky uart_handle_break(&sport->port); 123745ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 123845ca673eSTroy Kisky sport->port.icount.buf_overrun++; 123945ca673eSTroy Kisky tty_flip_buffer_push(port); 124045ca673eSTroy Kisky } else { 12414444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 124241d98b5dSNandor Han sport->port.icount.frame++; 124327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 12444444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 124541d98b5dSNandor Han sport->port.icount.parity++; 124627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 124741d98b5dSNandor Han } 124845ca673eSTroy Kisky } 124941d98b5dSNandor Han 12504444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 125141d98b5dSNandor Han sport->port.icount.overrun++; 125227c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 125341d98b5dSNandor Han } 125441d98b5dSNandor Han 125541d98b5dSNandor Han } 125641d98b5dSNandor Han 1257cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1258cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1259184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1260184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1261cc32382dSLucas Stach 12629d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1263cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1264cc32382dSLucas Stach { 1265cc32382dSLucas Stach unsigned int val; 1266cc32382dSLucas Stach 1267cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 126827c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1269cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 127027c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1271cc32382dSLucas Stach } 1272cc32382dSLucas Stach 1273b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1274b4cdc8f6SHuang Shijie { 1275b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1276e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1277b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1278b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 12799d297239SNandor Han sport->rx_cookie = -EINVAL; 1280b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1281b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1282b4cdc8f6SHuang Shijie } 1283b4cdc8f6SHuang Shijie 1284b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1285e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1286b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1287b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1288b4cdc8f6SHuang Shijie } 1289b4cdc8f6SHuang Shijie } 1290b4cdc8f6SHuang Shijie 1291b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1292b4cdc8f6SHuang Shijie { 1293b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1294b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1295b4cdc8f6SHuang Shijie int ret; 1296b4cdc8f6SHuang Shijie 1297b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1298b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1299b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1300b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1301b4cdc8f6SHuang Shijie ret = -EINVAL; 1302b4cdc8f6SHuang Shijie goto err; 1303b4cdc8f6SHuang Shijie } 1304b4cdc8f6SHuang Shijie 1305b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1306b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1307b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1308184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1309184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1310b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1311b4cdc8f6SHuang Shijie if (ret) { 1312b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1313b4cdc8f6SHuang Shijie goto err; 1314b4cdc8f6SHuang Shijie } 1315b4cdc8f6SHuang Shijie 1316*db0a196bSFabien Lahoudere sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; 1317*db0a196bSFabien Lahoudere sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); 1318b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1319b4cdc8f6SHuang Shijie ret = -ENOMEM; 1320b4cdc8f6SHuang Shijie goto err; 1321b4cdc8f6SHuang Shijie } 13229d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1323b4cdc8f6SHuang Shijie 1324b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1325b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1326b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1327b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1328b4cdc8f6SHuang Shijie ret = -EINVAL; 1329b4cdc8f6SHuang Shijie goto err; 1330b4cdc8f6SHuang Shijie } 1331b4cdc8f6SHuang Shijie 1332b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1333b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1334b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1335184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1336b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1337b4cdc8f6SHuang Shijie if (ret) { 1338b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1339b4cdc8f6SHuang Shijie goto err; 1340b4cdc8f6SHuang Shijie } 1341b4cdc8f6SHuang Shijie 1342b4cdc8f6SHuang Shijie return 0; 1343b4cdc8f6SHuang Shijie err: 1344b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1345b4cdc8f6SHuang Shijie return ret; 1346b4cdc8f6SHuang Shijie } 1347b4cdc8f6SHuang Shijie 13489d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1349b4cdc8f6SHuang Shijie { 13504444dcf1SUwe Kleine-König u32 ucr1; 1351b4cdc8f6SHuang Shijie 13529d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 135302b0abd3SUwe Kleine-König 1354b4cdc8f6SHuang Shijie /* set UCR1 */ 13554444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13564444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 13574444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1358b4cdc8f6SHuang Shijie 1359b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1360b4cdc8f6SHuang Shijie } 1361b4cdc8f6SHuang Shijie 13629d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1363b4cdc8f6SHuang Shijie { 1364676a31d8SSebastian Reichel u32 ucr1; 1365b4cdc8f6SHuang Shijie 1366b4cdc8f6SHuang Shijie /* clear UCR1 */ 13674444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13684444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 13694444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1370b4cdc8f6SHuang Shijie 13719d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1372184bd70bSLucas Stach 1373b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1374b4cdc8f6SHuang Shijie } 1375b4cdc8f6SHuang Shijie 1376ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1377ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1378ab4382d2SGreg Kroah-Hartman 13799d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1380ab4382d2SGreg Kroah-Hartman { 1381ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1382458e2c82SFabio Estevam int retval, i; 13834444dcf1SUwe Kleine-König unsigned long flags; 13844238c00bSUwe Kleine-König int dma_is_inited = 0; 13855a08a487SGeorge Hilliard u32 ucr1, ucr2, ucr3, ucr4; 1386ab4382d2SGreg Kroah-Hartman 138728eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 138828eb4274SHuang Shijie if (retval) 1389cb0f0a5fSFabio Estevam return retval; 139028eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 13910c375501SHuang Shijie if (retval) { 13920c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1393cb0f0a5fSFabio Estevam return retval; 13940c375501SHuang Shijie } 139528eb4274SHuang Shijie 13969d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1397ab4382d2SGreg Kroah-Hartman 1398ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1399ab4382d2SGreg Kroah-Hartman * requesting IRQs 1400ab4382d2SGreg Kroah-Hartman */ 14014444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1402ab4382d2SGreg Kroah-Hartman 1403ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 14044444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 14054444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1406ab4382d2SGreg Kroah-Hartman 14074444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1408ab4382d2SGreg Kroah-Hartman 14097e11577eSLucas Stach /* Can we enable the DMA support? */ 14104238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 14114238c00bSUwe Kleine-König dma_is_inited = 1; 14127e11577eSLucas Stach 141353794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1414772f8991SHuang Shijie /* Reset fifo's and state machines */ 1415458e2c82SFabio Estevam i = 100; 1416458e2c82SFabio Estevam 14174444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14184444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 14194444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1420458e2c82SFabio Estevam 142127c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1422458e2c82SFabio Estevam udelay(1); 1423ab4382d2SGreg Kroah-Hartman 1424ab4382d2SGreg Kroah-Hartman /* 1425ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1426ab4382d2SGreg Kroah-Hartman */ 142727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 142827c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1429ab4382d2SGreg Kroah-Hartman 14304444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 14314444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 14326376cd39SNandor Han if (sport->have_rtscts) 14334444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1434ab4382d2SGreg Kroah-Hartman 14354444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1436ab4382d2SGreg Kroah-Hartman 14375a08a487SGeorge Hilliard ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 14381f043572STroy Kisky if (!sport->dma_is_enabled) 14394444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 14405a08a487SGeorge Hilliard if (sport->inverted_rx) 14415a08a487SGeorge Hilliard ucr4 |= UCR4_INVR; 14424444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 14436f026d6bSJiada Wang 14445a08a487SGeorge Hilliard ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 14455a08a487SGeorge Hilliard /* 14465a08a487SGeorge Hilliard * configure tx polarity before enabling tx 14475a08a487SGeorge Hilliard */ 14485a08a487SGeorge Hilliard if (sport->inverted_tx) 14495a08a487SGeorge Hilliard ucr3 |= UCR3_INVT; 14505a08a487SGeorge Hilliard 14515a08a487SGeorge Hilliard if (!imx_uart_is_imx1(sport)) { 14525a08a487SGeorge Hilliard ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 14535a08a487SGeorge Hilliard 14545a08a487SGeorge Hilliard if (sport->dte_mode) 14555a08a487SGeorge Hilliard /* disable broken interrupts */ 14565a08a487SGeorge Hilliard ucr3 &= ~(UCR3_RI | UCR3_DCD); 14575a08a487SGeorge Hilliard } 14585a08a487SGeorge Hilliard imx_uart_writel(sport, ucr3, UCR3); 14595a08a487SGeorge Hilliard 14604444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 14614444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1462bff09b09SLucas Stach if (!sport->have_rtscts) 14634444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 146416804d68SUwe Kleine-König /* 146516804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 146616804d68SUwe Kleine-König * we're using RTSD instead. 146716804d68SUwe Kleine-König */ 14689d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 14694444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 14704444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1471ab4382d2SGreg Kroah-Hartman 1472ab4382d2SGreg Kroah-Hartman /* 1473ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1474ab4382d2SGreg Kroah-Hartman */ 14759d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 147618a42088SPeter Senna Tschudin 147776821e22SUwe Kleine-König if (dma_is_inited) { 14789d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 14799d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 148076821e22SUwe Kleine-König } else { 148176821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 148276821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 148376821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 148481ca8e82SUwe Kleine-König 148581ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 148681ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 148781ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 148876821e22SUwe Kleine-König } 148918a42088SPeter Senna Tschudin 1490ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1491ab4382d2SGreg Kroah-Hartman 1492ab4382d2SGreg Kroah-Hartman return 0; 1493ab4382d2SGreg Kroah-Hartman } 1494ab4382d2SGreg Kroah-Hartman 14959d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1496ab4382d2SGreg Kroah-Hartman { 1497ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 14989ec1882dSXinyu Chen unsigned long flags; 1499339c7a87SSebastian Reichel u32 ucr1, ucr2, ucr4; 1500ab4382d2SGreg Kroah-Hartman 1501b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1502e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 15037722c240SSebastian Reichel if (sport->dma_is_txing) { 15047722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 15057722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 15067722c240SSebastian Reichel sport->dma_is_txing = 0; 15077722c240SSebastian Reichel } 1508e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 15097722c240SSebastian Reichel if (sport->dma_is_rxing) { 15107722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 15117722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 15127722c240SSebastian Reichel sport->dma_is_rxing = 0; 15137722c240SSebastian Reichel } 15149d297239SNandor Han 151573631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 15169d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 15179d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 15189d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 151973631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1520b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1521b4cdc8f6SHuang Shijie } 1522b4cdc8f6SHuang Shijie 152358362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 152458362d5bSUwe Kleine-König 15259ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 15264444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15270fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 15284444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 15299ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1530ab4382d2SGreg Kroah-Hartman 1531ab4382d2SGreg Kroah-Hartman /* 1532ab4382d2SGreg Kroah-Hartman * Stop our timer. 1533ab4382d2SGreg Kroah-Hartman */ 1534ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1535ab4382d2SGreg Kroah-Hartman 1536ab4382d2SGreg Kroah-Hartman /* 1537ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1538ab4382d2SGreg Kroah-Hartman */ 1539ab4382d2SGreg Kroah-Hartman 15409ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1541edd64f30SMatthias Schiffer 15424444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 1543c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 15444444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1545edd64f30SMatthias Schiffer 1546edd64f30SMatthias Schiffer ucr4 = imx_uart_readl(sport, UCR4); 1547edd64f30SMatthias Schiffer ucr4 &= ~(UCR4_OREN | UCR4_TCEN); 1548edd64f30SMatthias Schiffer imx_uart_writel(sport, ucr4, UCR4); 1549edd64f30SMatthias Schiffer 15509ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 155128eb4274SHuang Shijie 155228eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 155328eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1554ab4382d2SGreg Kroah-Hartman } 1555ab4382d2SGreg Kroah-Hartman 15566aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 15579d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1558eb56b7edSHuang Shijie { 1559eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 156082e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 15614444dcf1SUwe Kleine-König u32 ucr2; 15624f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1563eb56b7edSHuang Shijie 156482e86ae9SDirk Behme if (!sport->dma_chan_tx) 156582e86ae9SDirk Behme return; 156682e86ae9SDirk Behme 1567eb56b7edSHuang Shijie sport->tx_bytes = 0; 1568eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 156982e86ae9SDirk Behme if (sport->dma_is_txing) { 15704444dcf1SUwe Kleine-König u32 ucr1; 15714444dcf1SUwe Kleine-König 157282e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 157382e86ae9SDirk Behme DMA_TO_DEVICE); 15744444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 15754444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 15764444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 15770f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1578eb56b7edSHuang Shijie } 1579934084a9SFabio Estevam 1580934084a9SFabio Estevam /* 1581934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1582263763c1SMartyn Welch * 1583934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1584934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1585263763c1SMartyn Welch * and UTS[6-3]". 1586263763c1SMartyn Welch * 1587263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1588263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1589263763c1SMartyn Welch * registers. 1590934084a9SFabio Estevam */ 159127c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 159227c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 159327c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1594934084a9SFabio Estevam 15954444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15964444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 15974444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1598934084a9SFabio Estevam 159927c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1600934084a9SFabio Estevam udelay(1); 1601934084a9SFabio Estevam 1602934084a9SFabio Estevam /* Restore the registers */ 160327c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 160427c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 160527c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1606eb56b7edSHuang Shijie } 1607eb56b7edSHuang Shijie 1608ab4382d2SGreg Kroah-Hartman static void 16099d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1610ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1611ab4382d2SGreg Kroah-Hartman { 1612ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1613ab4382d2SGreg Kroah-Hartman unsigned long flags; 161485f30fbfSSergey Organov u32 ucr2, old_ucr2, ufcr; 161558362d5bSUwe Kleine-König unsigned int baud, quot; 1616ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 16174444dcf1SUwe Kleine-König unsigned long div; 1618d47bcb4aSSergey Organov unsigned long num, denom, old_ubir, old_ubmr; 1619ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1620ab4382d2SGreg Kroah-Hartman 1621ab4382d2SGreg Kroah-Hartman /* 1622ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1623ab4382d2SGreg Kroah-Hartman */ 1624ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1625ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1626ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1627ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1628ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1629ab4382d2SGreg Kroah-Hartman } 1630ab4382d2SGreg Kroah-Hartman 16314e828c3eSSergey Organov del_timer_sync(&sport->timer); 16324e828c3eSSergey Organov 16334e828c3eSSergey Organov /* 16344e828c3eSSergey Organov * Ask the core to calculate the divisor for us. 16354e828c3eSSergey Organov */ 16364e828c3eSSergey Organov baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 16374e828c3eSSergey Organov quot = uart_get_divisor(port, baud); 16384e828c3eSSergey Organov 16394e828c3eSSergey Organov spin_lock_irqsave(&sport->port.lock, flags); 16404e828c3eSSergey Organov 1641011bd05dSSergey Organov /* 1642011bd05dSSergey Organov * Read current UCR2 and save it for future use, then clear all the bits 1643011bd05dSSergey Organov * except those we will or may need to preserve. 1644011bd05dSSergey Organov */ 1645011bd05dSSergey Organov old_ucr2 = imx_uart_readl(sport, UCR2); 1646011bd05dSSergey Organov ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1647011bd05dSSergey Organov 1648011bd05dSSergey Organov ucr2 |= UCR2_SRST | UCR2_IRTS; 164941ffa48eSSergey Organov if ((termios->c_cflag & CSIZE) == CS8) 165041ffa48eSSergey Organov ucr2 |= UCR2_WS; 1651ab4382d2SGreg Kroah-Hartman 1652ddf89e75SSergey Organov if (!sport->have_rtscts) 1653ddf89e75SSergey Organov termios->c_cflag &= ~CRTSCTS; 165417b8f2a3SUwe Kleine-König 165512fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 165617b8f2a3SUwe Kleine-König /* 165717b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 165817b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 165917b8f2a3SUwe Kleine-König * disabled. 166017b8f2a3SUwe Kleine-König */ 166158362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 16629d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 16631a613626SFabio Estevam else 16649d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 166558362d5bSUwe Kleine-König 1666b777b5deSSergey Organov } else if (termios->c_cflag & CRTSCTS) { 1667b777b5deSSergey Organov /* 1668b777b5deSSergey Organov * Only let receiver control RTS output if we were not requested 1669b777b5deSSergey Organov * to have RTS inactive (which then should take precedence). 1670b777b5deSSergey Organov */ 1671b777b5deSSergey Organov if (ucr2 & UCR2_CTS) 1672b777b5deSSergey Organov ucr2 |= UCR2_CTSC; 1673b777b5deSSergey Organov } 1674ddf89e75SSergey Organov 1675ddf89e75SSergey Organov if (termios->c_cflag & CRTSCTS) 1676ddf89e75SSergey Organov ucr2 &= ~UCR2_IRTS; 1677ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1678ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1679ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1680ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1681ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1682ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1683ab4382d2SGreg Kroah-Hartman } 1684ab4382d2SGreg Kroah-Hartman 1685ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1686ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1687ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1688ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1689ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1690ab4382d2SGreg Kroah-Hartman 1691ab4382d2SGreg Kroah-Hartman /* 1692ab4382d2SGreg Kroah-Hartman * Characters to ignore 1693ab4382d2SGreg Kroah-Hartman */ 1694ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1695ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1696865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1697ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1698ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1699ab4382d2SGreg Kroah-Hartman /* 1700ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1701ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1702ab4382d2SGreg Kroah-Hartman */ 1703ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1704ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1705ab4382d2SGreg Kroah-Hartman } 1706ab4382d2SGreg Kroah-Hartman 170755d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 170855d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 170955d8693aSJiada Wang 1710ab4382d2SGreg Kroah-Hartman /* 1711ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1712ab4382d2SGreg Kroah-Hartman */ 1713ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1714ab4382d2SGreg Kroah-Hartman 171509bd00f6SHubert Feurstein /* custom-baudrate handling */ 171609bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 171709bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 171809bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 171909bd00f6SHubert Feurstein 1720ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1721ab4382d2SGreg Kroah-Hartman if (div > 7) 1722ab4382d2SGreg Kroah-Hartman div = 7; 1723ab4382d2SGreg Kroah-Hartman if (!div) 1724ab4382d2SGreg Kroah-Hartman div = 1; 1725ab4382d2SGreg Kroah-Hartman 1726ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1727ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1728ab4382d2SGreg Kroah-Hartman 1729ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1730ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1731ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1732ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1733ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1734ab4382d2SGreg Kroah-Hartman 1735ab4382d2SGreg Kroah-Hartman num -= 1; 1736ab4382d2SGreg Kroah-Hartman denom -= 1; 1737ab4382d2SGreg Kroah-Hartman 173827c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1739ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 174027c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1741ab4382d2SGreg Kroah-Hartman 1742d47bcb4aSSergey Organov /* 1743d47bcb4aSSergey Organov * Two registers below should always be written both and in this 1744d47bcb4aSSergey Organov * particular order. One consequence is that we need to check if any of 1745d47bcb4aSSergey Organov * them changes and then update both. We do need the check for change 1746d47bcb4aSSergey Organov * as even writing the same values seem to "restart" 1747d47bcb4aSSergey Organov * transmission/receiving logic in the hardware, that leads to data 1748d47bcb4aSSergey Organov * breakage even when rate doesn't in fact change. E.g., user switches 1749d47bcb4aSSergey Organov * RTS/CTS handshake and suddenly gets broken bytes. 1750d47bcb4aSSergey Organov */ 1751d47bcb4aSSergey Organov old_ubir = imx_uart_readl(sport, UBIR); 1752d47bcb4aSSergey Organov old_ubmr = imx_uart_readl(sport, UBMR); 1753d47bcb4aSSergey Organov if (old_ubir != num || old_ubmr != denom) { 175427c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 175527c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1756d47bcb4aSSergey Organov } 1757ab4382d2SGreg Kroah-Hartman 17589d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 175927c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 176027c84426SUwe Kleine-König IMX21_ONEMS); 1761ab4382d2SGreg Kroah-Hartman 1762011bd05dSSergey Organov imx_uart_writel(sport, ucr2, UCR2); 1763ab4382d2SGreg Kroah-Hartman 1764ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 17659d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1766ab4382d2SGreg Kroah-Hartman 1767ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1768ab4382d2SGreg Kroah-Hartman } 1769ab4382d2SGreg Kroah-Hartman 17709d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1771ab4382d2SGreg Kroah-Hartman { 1772ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1773ab4382d2SGreg Kroah-Hartman 1774ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1775ab4382d2SGreg Kroah-Hartman } 1776ab4382d2SGreg Kroah-Hartman 1777ab4382d2SGreg Kroah-Hartman /* 1778ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1779ab4382d2SGreg Kroah-Hartman */ 17809d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1781ab4382d2SGreg Kroah-Hartman { 1782ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1783ab4382d2SGreg Kroah-Hartman 1784da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1785ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1786ab4382d2SGreg Kroah-Hartman } 1787ab4382d2SGreg Kroah-Hartman 1788ab4382d2SGreg Kroah-Hartman /* 1789ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1790ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1791ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1792ab4382d2SGreg Kroah-Hartman */ 1793ab4382d2SGreg Kroah-Hartman static int 17949d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1795ab4382d2SGreg Kroah-Hartman { 1796ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1797ab4382d2SGreg Kroah-Hartman int ret = 0; 1798ab4382d2SGreg Kroah-Hartman 1799ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1800ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1801ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1802ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1803ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1804ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1805ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1806ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1807a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1808ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1809ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1810ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1811ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1812ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1813ab4382d2SGreg Kroah-Hartman return ret; 1814ab4382d2SGreg Kroah-Hartman } 1815ab4382d2SGreg Kroah-Hartman 181601f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18176b8bdad9SDaniel Thompson 18189d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 18196b8bdad9SDaniel Thompson { 18206b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 18216b8bdad9SDaniel Thompson unsigned long flags; 18224444dcf1SUwe Kleine-König u32 ucr1, ucr2; 18236b8bdad9SDaniel Thompson int retval; 18246b8bdad9SDaniel Thompson 18256b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 18266b8bdad9SDaniel Thompson if (retval) 18276b8bdad9SDaniel Thompson return retval; 18286b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 18296b8bdad9SDaniel Thompson if (retval) 18306b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 18316b8bdad9SDaniel Thompson 18329d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 18336b8bdad9SDaniel Thompson 18346b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 18356b8bdad9SDaniel Thompson 183676821e22SUwe Kleine-König /* 183776821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 183876821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 183976821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 184076821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 184176821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 184276821e22SUwe Kleine-König */ 18434444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 184476821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 184576821e22SUwe Kleine-König 18469d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 18474444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 18486b8bdad9SDaniel Thompson 184976821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 1850c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 185176821e22SUwe Kleine-König 1852aef1b6a2SMingrui Ren ucr2 |= UCR2_RXEN | UCR2_TXEN; 185381ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 185476821e22SUwe Kleine-König 185576821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 18564444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 18576b8bdad9SDaniel Thompson 185876821e22SUwe Kleine-König /* now enable irqs */ 185976821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 186081ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 186176821e22SUwe Kleine-König 18626b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 18636b8bdad9SDaniel Thompson 18646b8bdad9SDaniel Thompson return 0; 18656b8bdad9SDaniel Thompson } 18666b8bdad9SDaniel Thompson 18679d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 186801f56abdSSaleem Abdulrasool { 186927c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 187027c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 187126c47412SDirk Behme return NO_POLL_CHAR; 187201f56abdSSaleem Abdulrasool 187327c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 187401f56abdSSaleem Abdulrasool } 187501f56abdSSaleem Abdulrasool 18769d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 187701f56abdSSaleem Abdulrasool { 187827c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 187901f56abdSSaleem Abdulrasool unsigned int status; 188001f56abdSSaleem Abdulrasool 188101f56abdSSaleem Abdulrasool /* drain */ 188201f56abdSSaleem Abdulrasool do { 188327c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 188401f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 188501f56abdSSaleem Abdulrasool 188601f56abdSSaleem Abdulrasool /* write */ 188727c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 188801f56abdSSaleem Abdulrasool 188901f56abdSSaleem Abdulrasool /* flush */ 189001f56abdSSaleem Abdulrasool do { 189127c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 189201f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 189301f56abdSSaleem Abdulrasool } 189401f56abdSSaleem Abdulrasool #endif 189501f56abdSSaleem Abdulrasool 18966aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 18979d1a50a2SUwe Kleine-König static int imx_uart_rs485_config(struct uart_port *port, 189817b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 189917b8f2a3SUwe Kleine-König { 190017b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 19014444dcf1SUwe Kleine-König u32 ucr2; 190217b8f2a3SUwe Kleine-König 190317b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 19047b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 190517b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 190617b8f2a3SUwe Kleine-König 190717b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 19086d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 19096d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 19106d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 19116d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 19126d215f83SStefan Agner 191317b8f2a3SUwe Kleine-König /* disable transmitter */ 19144444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 191517b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 19169d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 19171a613626SFabio Estevam else 19189d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 19194444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 192017b8f2a3SUwe Kleine-König } 192117b8f2a3SUwe Kleine-König 19227d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 19237d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 192476821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 19259d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 19267d1cadcaSBaruch Siach 192717b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 192817b8f2a3SUwe Kleine-König 192917b8f2a3SUwe Kleine-König return 0; 193017b8f2a3SUwe Kleine-König } 193117b8f2a3SUwe Kleine-König 19329d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 19339d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 19349d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 19359d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 19369d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 19379d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 19389d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 19399d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 19409d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 19419d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 19429d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 19439d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 19449d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 19459d1a50a2SUwe Kleine-König .type = imx_uart_type, 19469d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 19479d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 194801f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 19499d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 19509d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 19519d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 195201f56abdSSaleem Abdulrasool #endif 1953ab4382d2SGreg Kroah-Hartman }; 1954ab4382d2SGreg Kroah-Hartman 19559d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1956ab4382d2SGreg Kroah-Hartman 19570db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 19589d1a50a2SUwe Kleine-König static void imx_uart_console_putchar(struct uart_port *port, int ch) 1959ab4382d2SGreg Kroah-Hartman { 1960ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1961ab4382d2SGreg Kroah-Hartman 19629d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1963ab4382d2SGreg Kroah-Hartman barrier(); 1964ab4382d2SGreg Kroah-Hartman 196527c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1966ab4382d2SGreg Kroah-Hartman } 1967ab4382d2SGreg Kroah-Hartman 1968ab4382d2SGreg Kroah-Hartman /* 1969ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1970ab4382d2SGreg Kroah-Hartman */ 1971ab4382d2SGreg Kroah-Hartman static void 19729d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1973ab4382d2SGreg Kroah-Hartman { 19749d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 19750ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 197618ee37e1SJohan Hovold unsigned long flags; 19770ad5a814SDirk Behme unsigned int ucr1; 1978677fe555SThomas Gleixner int locked = 1; 19799ec1882dSXinyu Chen 1980677fe555SThomas Gleixner if (sport->port.sysrq) 1981677fe555SThomas Gleixner locked = 0; 1982677fe555SThomas Gleixner else if (oops_in_progress) 1983677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1984677fe555SThomas Gleixner else 19859ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1986ab4382d2SGreg Kroah-Hartman 1987ab4382d2SGreg Kroah-Hartman /* 19880ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1989ab4382d2SGreg Kroah-Hartman */ 19909d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 19910ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1992ab4382d2SGreg Kroah-Hartman 19939d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 1994fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1995ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1996c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1997ab4382d2SGreg Kroah-Hartman 199827c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1999ab4382d2SGreg Kroah-Hartman 200027c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2001ab4382d2SGreg Kroah-Hartman 20029d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2003ab4382d2SGreg Kroah-Hartman 2004ab4382d2SGreg Kroah-Hartman /* 2005ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 20060ad5a814SDirk Behme * and restore UCR1/2/3 2007ab4382d2SGreg Kroah-Hartman */ 200827c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2009ab4382d2SGreg Kroah-Hartman 20109d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 20119ec1882dSXinyu Chen 2012677fe555SThomas Gleixner if (locked) 20139ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 2014ab4382d2SGreg Kroah-Hartman } 2015ab4382d2SGreg Kroah-Hartman 2016ab4382d2SGreg Kroah-Hartman /* 2017ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 2018ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 2019ab4382d2SGreg Kroah-Hartman */ 2020ab4382d2SGreg Kroah-Hartman static void __init 20219d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 2022ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 2023ab4382d2SGreg Kroah-Hartman { 2024ab4382d2SGreg Kroah-Hartman 202527c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2026ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 2027ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 2028ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 2029ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 2030ab4382d2SGreg Kroah-Hartman 203127c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 2032ab4382d2SGreg Kroah-Hartman 2033ab4382d2SGreg Kroah-Hartman *parity = 'n'; 2034ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 2035ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 2036ab4382d2SGreg Kroah-Hartman *parity = 'o'; 2037ab4382d2SGreg Kroah-Hartman else 2038ab4382d2SGreg Kroah-Hartman *parity = 'e'; 2039ab4382d2SGreg Kroah-Hartman } 2040ab4382d2SGreg Kroah-Hartman 2041ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 2042ab4382d2SGreg Kroah-Hartman *bits = 8; 2043ab4382d2SGreg Kroah-Hartman else 2044ab4382d2SGreg Kroah-Hartman *bits = 7; 2045ab4382d2SGreg Kroah-Hartman 204627c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 204727c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2048ab4382d2SGreg Kroah-Hartman 204927c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2050ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 2051ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 2052ab4382d2SGreg Kroah-Hartman else 2053ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 2054ab4382d2SGreg Kroah-Hartman 20553a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2056ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2057ab4382d2SGreg Kroah-Hartman 2058ab4382d2SGreg Kroah-Hartman { /* 2059ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2060ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2061ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2062ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2063ab4382d2SGreg Kroah-Hartman */ 2064ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2065ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2066ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2067ab4382d2SGreg Kroah-Hartman 2068ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2069ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2070ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2071ab4382d2SGreg Kroah-Hartman } 2072ab4382d2SGreg Kroah-Hartman 2073ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 2074f5a9e5f7SFabio Estevam dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2075ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2076ab4382d2SGreg Kroah-Hartman } 2077ab4382d2SGreg Kroah-Hartman } 2078ab4382d2SGreg Kroah-Hartman 2079ab4382d2SGreg Kroah-Hartman static int __init 20809d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2081ab4382d2SGreg Kroah-Hartman { 2082ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2083ab4382d2SGreg Kroah-Hartman int baud = 9600; 2084ab4382d2SGreg Kroah-Hartman int bits = 8; 2085ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2086ab4382d2SGreg Kroah-Hartman int flow = 'n'; 20871cf93e0dSHuang Shijie int retval; 2088ab4382d2SGreg Kroah-Hartman 2089ab4382d2SGreg Kroah-Hartman /* 2090ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2091ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2092ab4382d2SGreg Kroah-Hartman * console support. 2093ab4382d2SGreg Kroah-Hartman */ 20949d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2095ab4382d2SGreg Kroah-Hartman co->index = 0; 20969d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2097ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2098ab4382d2SGreg Kroah-Hartman return -ENODEV; 2099ab4382d2SGreg Kroah-Hartman 21001cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 21011cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 21021cf93e0dSHuang Shijie if (retval) 21031cf93e0dSHuang Shijie goto error_console; 21041cf93e0dSHuang Shijie 2105ab4382d2SGreg Kroah-Hartman if (options) 2106ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2107ab4382d2SGreg Kroah-Hartman else 21089d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2109ab4382d2SGreg Kroah-Hartman 21109d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2111ab4382d2SGreg Kroah-Hartman 21121cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 21131cf93e0dSHuang Shijie 21140c727a42SFabio Estevam if (retval) { 2115e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21160c727a42SFabio Estevam goto error_console; 21170c727a42SFabio Estevam } 21180c727a42SFabio Estevam 2119e67c139cSFugang Duan retval = clk_prepare_enable(sport->clk_per); 21200c727a42SFabio Estevam if (retval) 2121e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21221cf93e0dSHuang Shijie 21231cf93e0dSHuang Shijie error_console: 21241cf93e0dSHuang Shijie return retval; 2125ab4382d2SGreg Kroah-Hartman } 2126ab4382d2SGreg Kroah-Hartman 21279d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 21289d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2129ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 21309d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2131ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 21329d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 2133ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2134ab4382d2SGreg Kroah-Hartman .index = -1, 21359d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2136ab4382d2SGreg Kroah-Hartman }; 2137ab4382d2SGreg Kroah-Hartman 21389d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2139913c6c0eSLucas Stach 2140ab4382d2SGreg Kroah-Hartman #else 2141ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2142ab4382d2SGreg Kroah-Hartman #endif 2143ab4382d2SGreg Kroah-Hartman 21449d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2145ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2146ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2147ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2148ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2149ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21509d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2151ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2152ab4382d2SGreg Kroah-Hartman }; 2153ab4382d2SGreg Kroah-Hartman 2154bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2155cb1a6092SUwe Kleine-König { 2156bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2157cb1a6092SUwe Kleine-König unsigned long flags; 2158cb1a6092SUwe Kleine-König 2159cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2160cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS) 2161cb1a6092SUwe Kleine-König imx_uart_start_tx(&sport->port); 2162cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2163bd78ecd6SAhmad Fatoum 2164bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2165cb1a6092SUwe Kleine-König } 2166cb1a6092SUwe Kleine-König 2167bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2168cb1a6092SUwe Kleine-König { 2169bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2170cb1a6092SUwe Kleine-König unsigned long flags; 2171cb1a6092SUwe Kleine-König 2172cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2173cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_SEND) 2174cb1a6092SUwe Kleine-König imx_uart_stop_tx(&sport->port); 2175cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2176bd78ecd6SAhmad Fatoum 2177bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2178cb1a6092SUwe Kleine-König } 2179cb1a6092SUwe Kleine-König 2180*db0a196bSFabien Lahoudere /* Default RX DMA buffer configuration */ 2181*db0a196bSFabien Lahoudere #define RX_DMA_PERIODS 16 2182*db0a196bSFabien Lahoudere #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4) 2183*db0a196bSFabien Lahoudere 21849d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2185ab4382d2SGreg Kroah-Hartman { 21864661f46eSFabio Estevam struct device_node *np = pdev->dev.of_node; 2187ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2188ab4382d2SGreg Kroah-Hartman void __iomem *base; 2189*db0a196bSFabien Lahoudere u32 dma_buf_conf[2]; 21904444dcf1SUwe Kleine-König int ret = 0; 21914444dcf1SUwe Kleine-König u32 ucr1; 2192ab4382d2SGreg Kroah-Hartman struct resource *res; 2193842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2194ab4382d2SGreg Kroah-Hartman 219542d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2196ab4382d2SGreg Kroah-Hartman if (!sport) 2197ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2198ab4382d2SGreg Kroah-Hartman 21994661f46eSFabio Estevam sport->devdata = of_device_get_match_data(&pdev->dev); 22004661f46eSFabio Estevam 22014661f46eSFabio Estevam ret = of_alias_get_id(np, "serial"); 22024661f46eSFabio Estevam if (ret < 0) { 22034661f46eSFabio Estevam dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 220442d34191SSachin Kamat return ret; 22054661f46eSFabio Estevam } 22064661f46eSFabio Estevam sport->port.line = ret; 22074661f46eSFabio Estevam 22084661f46eSFabio Estevam if (of_get_property(np, "uart-has-rtscts", NULL) || 22094661f46eSFabio Estevam of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 22104661f46eSFabio Estevam sport->have_rtscts = 1; 22114661f46eSFabio Estevam 22124661f46eSFabio Estevam if (of_get_property(np, "fsl,dte-mode", NULL)) 22134661f46eSFabio Estevam sport->dte_mode = 1; 22144661f46eSFabio Estevam 22154661f46eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 22164661f46eSFabio Estevam sport->have_rtsgpio = 1; 22174661f46eSFabio Estevam 22184661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-tx", NULL)) 22194661f46eSFabio Estevam sport->inverted_tx = 1; 22204661f46eSFabio Estevam 22214661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-rx", NULL)) 22224661f46eSFabio Estevam sport->inverted_rx = 1; 222322698aa2SShawn Guo 2224*db0a196bSFabien Lahoudere if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { 2225*db0a196bSFabien Lahoudere sport->rx_period_length = dma_buf_conf[0]; 2226*db0a196bSFabien Lahoudere sport->rx_periods = dma_buf_conf[1]; 2227*db0a196bSFabien Lahoudere } else { 2228*db0a196bSFabien Lahoudere sport->rx_period_length = RX_DMA_PERIOD_LEN; 2229*db0a196bSFabien Lahoudere sport->rx_periods = RX_DMA_PERIODS; 2230*db0a196bSFabien Lahoudere } 2231*db0a196bSFabien Lahoudere 22329d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 223356734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 223456734448SGeert Uytterhoeven sport->port.line); 223556734448SGeert Uytterhoeven return -EINVAL; 223656734448SGeert Uytterhoeven } 223756734448SGeert Uytterhoeven 2238ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2239da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2240da82f997SAlexander Shiyan if (IS_ERR(base)) 2241da82f997SAlexander Shiyan return PTR_ERR(base); 2242ab4382d2SGreg Kroah-Hartman 2243842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2244aa49d8e8SAnson Huang if (rxirq < 0) 2245aa49d8e8SAnson Huang return rxirq; 224631a8d8faSAnson Huang txirq = platform_get_irq_optional(pdev, 1); 224731a8d8faSAnson Huang rtsirq = platform_get_irq_optional(pdev, 2); 2248842633bdSUwe Kleine-König 2249ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2250ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2251ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 22525b109564SZheng Yongjun sport->port.type = PORT_IMX; 2253ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2254842633bdSUwe Kleine-König sport->port.irq = rxirq; 2255ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2256aa3479d2SDmitry Safonov sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 22579d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 22589d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 2259ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 22609d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2261ab4382d2SGreg Kroah-Hartman 226258362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 226358362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 226458362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 226558362d5bSUwe Kleine-König 22663a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 22673a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 22683a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2269833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 227042d34191SSachin Kamat return ret; 2271ab4382d2SGreg Kroah-Hartman } 2272ab4382d2SGreg Kroah-Hartman 22733a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 22743a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 22753a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2276833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 227742d34191SSachin Kamat return ret; 22783a9465faSSascha Hauer } 22793a9465faSSascha Hauer 22803a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2281ab4382d2SGreg Kroah-Hartman 22828a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 22838a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 22841e512d45SUwe Kleine-König if (ret) { 22851e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 22868a61f0c7SFabio Estevam return ret; 22871e512d45SUwe Kleine-König } 22888a61f0c7SFabio Estevam 22893a0ab62fSUwe Kleine-König /* initialize shadow register values */ 22903a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 22913a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 22923a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 22933a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 22943a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 22953a0ab62fSUwe Kleine-König 2296c150c0f3SLukas Wunner ret = uart_get_rs485_mode(&sport->port); 2297c150c0f3SLukas Wunner if (ret) { 2298c150c0f3SLukas Wunner clk_disable_unprepare(sport->clk_ipg); 2299c150c0f3SLukas Wunner return ret; 2300c150c0f3SLukas Wunner } 2301743f93f8SLukas Wunner 2302b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23035d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2304b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2305b8f3bff0SLukas Wunner 23066d215f83SStefan Agner /* 23076d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 23086d215f83SStefan Agner * signal cannot be set low during transmission in case the 23096d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 23106d215f83SStefan Agner */ 23116d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23126d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 23136d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 23146d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 23156d215f83SStefan Agner dev_err(&pdev->dev, 23166d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 23176d215f83SStefan Agner 23189d1a50a2SUwe Kleine-König imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2319b8f3bff0SLukas Wunner 23208a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 23214444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 23225f0e708cSYe Bin ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 23234444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 23248a61f0c7SFabio Estevam 23259d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2326e61c38d8SUwe Kleine-König /* 2327e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2328e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2329e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2330e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2331e61c38d8SUwe Kleine-König */ 23324444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23334444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 23344444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2335e61c38d8SUwe Kleine-König 2336e61c38d8SUwe Kleine-König /* 2337e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2338e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2339e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2340e61c38d8SUwe Kleine-König */ 234127c84426SUwe Kleine-König imx_uart_writel(sport, 234227c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 234327c84426SUwe Kleine-König UCR3); 2344e61c38d8SUwe Kleine-König 2345e61c38d8SUwe Kleine-König } else { 23464444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 23474444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23484444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 23494444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 23506df765dcSUwe Kleine-König 23519d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 23526df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 235327c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2354e61c38d8SUwe Kleine-König } 2355e61c38d8SUwe Kleine-König 23568a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 23578a61f0c7SFabio Estevam 2358bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2359bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2360bd78ecd6SAhmad Fatoum sport->trigger_start_tx.function = imx_trigger_start_tx; 2361bd78ecd6SAhmad Fatoum sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2362cb1a6092SUwe Kleine-König 2363c0d1c6b0SFabio Estevam /* 2364c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2365c0d1c6b0SFabio Estevam * chips only have one interrupt. 2366c0d1c6b0SFabio Estevam */ 2367842633bdSUwe Kleine-König if (txirq > 0) { 23689d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2369c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23701e512d45SUwe Kleine-König if (ret) { 23711e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 23721e512d45SUwe Kleine-König ret); 2373c0d1c6b0SFabio Estevam return ret; 23741e512d45SUwe Kleine-König } 2375c0d1c6b0SFabio Estevam 23769d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2377c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23781e512d45SUwe Kleine-König if (ret) { 23791e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 23801e512d45SUwe Kleine-König ret); 2381c0d1c6b0SFabio Estevam return ret; 23821e512d45SUwe Kleine-König } 23837e620984SUwe Kleine-König 23847e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 23857e620984SUwe Kleine-König dev_name(&pdev->dev), sport); 23867e620984SUwe Kleine-König if (ret) { 23877e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n", 23887e620984SUwe Kleine-König ret); 23897e620984SUwe Kleine-König return ret; 23907e620984SUwe Kleine-König } 2391c0d1c6b0SFabio Estevam } else { 23929d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2393c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23941e512d45SUwe Kleine-König if (ret) { 23951e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2396c0d1c6b0SFabio Estevam return ret; 2397c0d1c6b0SFabio Estevam } 23981e512d45SUwe Kleine-König } 2399c0d1c6b0SFabio Estevam 24009d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2401ab4382d2SGreg Kroah-Hartman 24020a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2403ab4382d2SGreg Kroah-Hartman 24049d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2405ab4382d2SGreg Kroah-Hartman } 2406ab4382d2SGreg Kroah-Hartman 24079d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2408ab4382d2SGreg Kroah-Hartman { 2409ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2410ab4382d2SGreg Kroah-Hartman 24119d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2412ab4382d2SGreg Kroah-Hartman } 2413ab4382d2SGreg Kroah-Hartman 24149d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2415c868cbb7SEduardo Valentin { 241607b5e16eSAnson Huang unsigned long flags; 241707b5e16eSAnson Huang 241807b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 241907b5e16eSAnson Huang if (!sport->context_saved) { 242007b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2421c868cbb7SEduardo Valentin return; 242207b5e16eSAnson Huang } 2423c868cbb7SEduardo Valentin 242427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 242527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 242627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 242727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 242827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 242927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 243027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 243127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 243227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 243327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2434c868cbb7SEduardo Valentin sport->context_saved = false; 243507b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2436c868cbb7SEduardo Valentin } 2437c868cbb7SEduardo Valentin 24389d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2439c868cbb7SEduardo Valentin { 244007b5e16eSAnson Huang unsigned long flags; 244107b5e16eSAnson Huang 2442c868cbb7SEduardo Valentin /* Save necessary regs */ 244307b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 244427c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 244527c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 244627c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 244727c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 244827c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 244927c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 245027c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 245127c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 245227c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 245327c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2454c868cbb7SEduardo Valentin sport->context_saved = true; 245507b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2456c868cbb7SEduardo Valentin } 2457c868cbb7SEduardo Valentin 24589d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2459189550b8SEduardo Valentin { 24604444dcf1SUwe Kleine-König u32 ucr3; 2461189550b8SEduardo Valentin 24624444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 246309df0b34SMartin Kaiser if (on) { 246427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 24654444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 24664444dcf1SUwe Kleine-König } else { 24674444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 246809df0b34SMartin Kaiser } 24694444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2470bc85734bSEduardo Valentin 247138b1f0fbSFabio Estevam if (sport->have_rtscts) { 24724444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2473bc85734bSEduardo Valentin if (on) 24744444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2475bc85734bSEduardo Valentin else 24764444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 24774444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2478189550b8SEduardo Valentin } 247938b1f0fbSFabio Estevam } 2480189550b8SEduardo Valentin 24819d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 248290bb6bd3SShenwei Wang { 2483a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 248490bb6bd3SShenwei Wang 24859d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 248690bb6bd3SShenwei Wang 248790bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 248890bb6bd3SShenwei Wang 2489fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev); 2490fcfed1beSAnson Huang 249190bb6bd3SShenwei Wang return 0; 249290bb6bd3SShenwei Wang } 249390bb6bd3SShenwei Wang 24949d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 249590bb6bd3SShenwei Wang { 2496a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 249790bb6bd3SShenwei Wang int ret; 249890bb6bd3SShenwei Wang 2499fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev); 2500fcfed1beSAnson Huang 250190bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 250290bb6bd3SShenwei Wang if (ret) 250390bb6bd3SShenwei Wang return ret; 250490bb6bd3SShenwei Wang 25059d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 250690bb6bd3SShenwei Wang 250790bb6bd3SShenwei Wang return 0; 250890bb6bd3SShenwei Wang } 250990bb6bd3SShenwei Wang 25109d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 251190bb6bd3SShenwei Wang { 2512a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 251309df0b34SMartin Kaiser int ret; 251490bb6bd3SShenwei Wang 25159d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 251681b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 251790bb6bd3SShenwei Wang 251809df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 251909df0b34SMartin Kaiser if (ret) 252009df0b34SMartin Kaiser return ret; 252109df0b34SMartin Kaiser 252209df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 25239d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 252409df0b34SMartin Kaiser 252509df0b34SMartin Kaiser return 0; 252690bb6bd3SShenwei Wang } 252790bb6bd3SShenwei Wang 25289d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 252990bb6bd3SShenwei Wang { 2530a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 253190bb6bd3SShenwei Wang 253290bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 25339d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 253490bb6bd3SShenwei Wang 25359d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 253681b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 253790bb6bd3SShenwei Wang 253809df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 253929add68dSMartin Fuzzey 254090bb6bd3SShenwei Wang return 0; 254190bb6bd3SShenwei Wang } 254290bb6bd3SShenwei Wang 25439d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 254494be6d74SPhilipp Zabel { 2545a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 254694be6d74SPhilipp Zabel 25479d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 254894be6d74SPhilipp Zabel 254909df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 255094be6d74SPhilipp Zabel } 255194be6d74SPhilipp Zabel 25529d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 255394be6d74SPhilipp Zabel { 2554a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 255594be6d74SPhilipp Zabel 25569d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 255794be6d74SPhilipp Zabel 255809df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 255994be6d74SPhilipp Zabel 256094be6d74SPhilipp Zabel return 0; 256194be6d74SPhilipp Zabel } 256294be6d74SPhilipp Zabel 25639d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 25649d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 25659d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 25669d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 25679d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 25689d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 25699d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 25709d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 25719d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 25729d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 257390bb6bd3SShenwei Wang }; 257490bb6bd3SShenwei Wang 25759d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 25769d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 25779d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2578ab4382d2SGreg Kroah-Hartman 2579ab4382d2SGreg Kroah-Hartman .driver = { 2580ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 258122698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 25829d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2583ab4382d2SGreg Kroah-Hartman }, 2584ab4382d2SGreg Kroah-Hartman }; 2585ab4382d2SGreg Kroah-Hartman 25869d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2587ab4382d2SGreg Kroah-Hartman { 25889d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2589ab4382d2SGreg Kroah-Hartman 2590ab4382d2SGreg Kroah-Hartman if (ret) 2591ab4382d2SGreg Kroah-Hartman return ret; 2592ab4382d2SGreg Kroah-Hartman 25939d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2594ab4382d2SGreg Kroah-Hartman if (ret != 0) 25959d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2596ab4382d2SGreg Kroah-Hartman 2597f227824eSUwe Kleine-König return ret; 2598ab4382d2SGreg Kroah-Hartman } 2599ab4382d2SGreg Kroah-Hartman 26009d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2601ab4382d2SGreg Kroah-Hartman { 26029d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 26039d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2604ab4382d2SGreg Kroah-Hartman } 2605ab4382d2SGreg Kroah-Hartman 26069d1a50a2SUwe Kleine-König module_init(imx_uart_init); 26079d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2608ab4382d2SGreg Kroah-Hartman 2609ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2610ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2611ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2612ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2613