1ab4382d2SGreg Kroah-Hartman /* 2ab4382d2SGreg Kroah-Hartman * Driver for Motorola IMX serial ports 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 7ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 8ab4382d2SGreg Kroah-Hartman * 9ab4382d2SGreg Kroah-Hartman * Copyright (C) 2009 emlix GmbH 10ab4382d2SGreg Kroah-Hartman * Author: Fabian Godehardt (added IrDA support for iMX) 11ab4382d2SGreg Kroah-Hartman * 12ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 13ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 14ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2 of the License, or 15ab4382d2SGreg Kroah-Hartman * (at your option) any later version. 16ab4382d2SGreg Kroah-Hartman * 17ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 18ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY; without even the implied warranty of 19ab4382d2SGreg Kroah-Hartman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20ab4382d2SGreg Kroah-Hartman * GNU General Public License for more details. 21ab4382d2SGreg Kroah-Hartman * 22ab4382d2SGreg Kroah-Hartman * You should have received a copy of the GNU General Public License 23ab4382d2SGreg Kroah-Hartman * along with this program; if not, write to the Free Software 24ab4382d2SGreg Kroah-Hartman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25ab4382d2SGreg Kroah-Hartman * 26ab4382d2SGreg Kroah-Hartman * [29-Mar-2005] Mike Lee 27ab4382d2SGreg Kroah-Hartman * Added hardware handshake 28ab4382d2SGreg Kroah-Hartman */ 29ab4382d2SGreg Kroah-Hartman 30ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 32ab4382d2SGreg Kroah-Hartman #endif 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 35ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 36ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 37ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 38ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 39ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 40ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 41ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 42ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 43ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 44ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 45ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 46ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 47ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 4822698aa2SShawn Guo #include <linux/of.h> 4922698aa2SShawn Guo #include <linux/of_device.h> 50e32a9f8fSSachin Kamat #include <linux/io.h> 51b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 52ab4382d2SGreg Kroah-Hartman 53ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 5482906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 55b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 56ab4382d2SGreg Kroah-Hartman 57ab4382d2SGreg Kroah-Hartman /* Register definitions */ 58ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 59ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 60ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 61ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 62ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 63ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 64ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 65ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 66ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 67ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 68ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 69ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 70ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 71ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 72fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 73fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 74fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 75ab4382d2SGreg Kroah-Hartman 76ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 7755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 78ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 79ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 80ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 81ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 82ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 83ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 8426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 8525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 86ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 87ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 88ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 89b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 90ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 91ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 93ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 94ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 95ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 96ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 97fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 98b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 100ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 101ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 102ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 103ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 104ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 105ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 108ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 109ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 110ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 11101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 112ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 113ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 114ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 115ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 119ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 120ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 121b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 122ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 125fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 126ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 127ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 128ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 129ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 130ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 131ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 132ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 133ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 134b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 135ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 136ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 137ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 138ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 139ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 140ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1417be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 142ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 143ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 144ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 145ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 146ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 147ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 148ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 149ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 150ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 151ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 152ab4382d2SGreg Kroah-Hartman #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 153ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 154ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 155ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 156ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 157ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 158ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 159ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 160ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 161ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 162ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 163ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 164ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 165ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 166ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 167ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 168ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 169ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 170ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 171ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 172ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 173ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 174ab4382d2SGreg Kroah-Hartman 175ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 176ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 177ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 178ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 179ab4382d2SGreg Kroah-Hartman 180ab4382d2SGreg Kroah-Hartman /* 181ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 182ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 183ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 184ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 185ab4382d2SGreg Kroah-Hartman */ 186ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 187ab4382d2SGreg Kroah-Hartman 188ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 189ab4382d2SGreg Kroah-Hartman 190ab4382d2SGreg Kroah-Hartman #define UART_NR 8 191ab4382d2SGreg Kroah-Hartman 192fe6b540aSShawn Guo /* i.mx21 type uart runs on all i.mx except i.mx1 */ 193fe6b540aSShawn Guo enum imx_uart_type { 194fe6b540aSShawn Guo IMX1_UART, 195fe6b540aSShawn Guo IMX21_UART, 196a496e628SHuang Shijie IMX6Q_UART, 197fe6b540aSShawn Guo }; 198fe6b540aSShawn Guo 199fe6b540aSShawn Guo /* device type dependent stuff */ 200fe6b540aSShawn Guo struct imx_uart_data { 201fe6b540aSShawn Guo unsigned uts_reg; 202fe6b540aSShawn Guo enum imx_uart_type devtype; 203fe6b540aSShawn Guo }; 204fe6b540aSShawn Guo 205ab4382d2SGreg Kroah-Hartman struct imx_port { 206ab4382d2SGreg Kroah-Hartman struct uart_port port; 207ab4382d2SGreg Kroah-Hartman struct timer_list timer; 208ab4382d2SGreg Kroah-Hartman unsigned int old_status; 209ab4382d2SGreg Kroah-Hartman int txirq, rxirq, rtsirq; 210ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 21120ff2fe6SHuang Shijie unsigned int dte_mode:1; 212ab4382d2SGreg Kroah-Hartman unsigned int use_irda:1; 213ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_rx:1; 214ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_tx:1; 215ab4382d2SGreg Kroah-Hartman unsigned short trcv_delay; /* transceiver delay */ 2163a9465faSSascha Hauer struct clk *clk_ipg; 2173a9465faSSascha Hauer struct clk *clk_per; 2187d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 219b4cdc8f6SHuang Shijie 220b4cdc8f6SHuang Shijie /* DMA fields */ 221b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 224b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 225b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 226b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 227b4cdc8f6SHuang Shijie void *rx_buf; 2287cb92fd2SHuang Shijie unsigned int tx_bytes; 229b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 2309ce4f8f3SGreg Kroah-Hartman wait_queue_head_t dma_wait; 231ab4382d2SGreg Kroah-Hartman }; 232ab4382d2SGreg Kroah-Hartman 2330ad5a814SDirk Behme struct imx_port_ucrs { 2340ad5a814SDirk Behme unsigned int ucr1; 2350ad5a814SDirk Behme unsigned int ucr2; 2360ad5a814SDirk Behme unsigned int ucr3; 2370ad5a814SDirk Behme }; 2380ad5a814SDirk Behme 239ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_IRDA 240ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) ((sport)->use_irda) 241ab4382d2SGreg Kroah-Hartman #else 242ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) (0) 243ab4382d2SGreg Kroah-Hartman #endif 244ab4382d2SGreg Kroah-Hartman 245fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 246fe6b540aSShawn Guo [IMX1_UART] = { 247fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 248fe6b540aSShawn Guo .devtype = IMX1_UART, 249fe6b540aSShawn Guo }, 250fe6b540aSShawn Guo [IMX21_UART] = { 251fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 252fe6b540aSShawn Guo .devtype = IMX21_UART, 253fe6b540aSShawn Guo }, 254a496e628SHuang Shijie [IMX6Q_UART] = { 255a496e628SHuang Shijie .uts_reg = IMX21_UTS, 256a496e628SHuang Shijie .devtype = IMX6Q_UART, 257a496e628SHuang Shijie }, 258fe6b540aSShawn Guo }; 259fe6b540aSShawn Guo 260fe6b540aSShawn Guo static struct platform_device_id imx_uart_devtype[] = { 261fe6b540aSShawn Guo { 262fe6b540aSShawn Guo .name = "imx1-uart", 263fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 264fe6b540aSShawn Guo }, { 265fe6b540aSShawn Guo .name = "imx21-uart", 266fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 267fe6b540aSShawn Guo }, { 268a496e628SHuang Shijie .name = "imx6q-uart", 269a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 270a496e628SHuang Shijie }, { 271fe6b540aSShawn Guo /* sentinel */ 272fe6b540aSShawn Guo } 273fe6b540aSShawn Guo }; 274fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 275fe6b540aSShawn Guo 27622698aa2SShawn Guo static struct of_device_id imx_uart_dt_ids[] = { 277a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 27822698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27922698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 28022698aa2SShawn Guo { /* sentinel */ } 28122698aa2SShawn Guo }; 28222698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28322698aa2SShawn Guo 284fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 285fe6b540aSShawn Guo { 286fe6b540aSShawn Guo return sport->devdata->uts_reg; 287fe6b540aSShawn Guo } 288fe6b540aSShawn Guo 289fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 290fe6b540aSShawn Guo { 291fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 292fe6b540aSShawn Guo } 293fe6b540aSShawn Guo 294fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 295fe6b540aSShawn Guo { 296fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 297fe6b540aSShawn Guo } 298fe6b540aSShawn Guo 299a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 300a496e628SHuang Shijie { 301a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 302a496e628SHuang Shijie } 303ab4382d2SGreg Kroah-Hartman /* 30444a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 30544a75411Sfabio.estevam@freescale.com */ 30693d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 30744a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 30844a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30944a75411Sfabio.estevam@freescale.com { 31044a75411Sfabio.estevam@freescale.com /* save control registers */ 31144a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 31244a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 31344a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 31444a75411Sfabio.estevam@freescale.com } 31544a75411Sfabio.estevam@freescale.com 31644a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 31744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 31844a75411Sfabio.estevam@freescale.com { 31944a75411Sfabio.estevam@freescale.com /* restore control registers */ 32044a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 32144a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 32244a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 32344a75411Sfabio.estevam@freescale.com } 324e8bfa760SFabio Estevam #endif 32544a75411Sfabio.estevam@freescale.com 32644a75411Sfabio.estevam@freescale.com /* 327ab4382d2SGreg Kroah-Hartman * Handle any change of modem status signal since we were last called. 328ab4382d2SGreg Kroah-Hartman */ 329ab4382d2SGreg Kroah-Hartman static void imx_mctrl_check(struct imx_port *sport) 330ab4382d2SGreg Kroah-Hartman { 331ab4382d2SGreg Kroah-Hartman unsigned int status, changed; 332ab4382d2SGreg Kroah-Hartman 333ab4382d2SGreg Kroah-Hartman status = sport->port.ops->get_mctrl(&sport->port); 334ab4382d2SGreg Kroah-Hartman changed = status ^ sport->old_status; 335ab4382d2SGreg Kroah-Hartman 336ab4382d2SGreg Kroah-Hartman if (changed == 0) 337ab4382d2SGreg Kroah-Hartman return; 338ab4382d2SGreg Kroah-Hartman 339ab4382d2SGreg Kroah-Hartman sport->old_status = status; 340ab4382d2SGreg Kroah-Hartman 341ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_RI) 342ab4382d2SGreg Kroah-Hartman sport->port.icount.rng++; 343ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_DSR) 344ab4382d2SGreg Kroah-Hartman sport->port.icount.dsr++; 345ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CAR) 346ab4382d2SGreg Kroah-Hartman uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 347ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CTS) 348ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 349ab4382d2SGreg Kroah-Hartman 350ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 351ab4382d2SGreg Kroah-Hartman } 352ab4382d2SGreg Kroah-Hartman 353ab4382d2SGreg Kroah-Hartman /* 354ab4382d2SGreg Kroah-Hartman * This is our per-port timeout handler, for checking the 355ab4382d2SGreg Kroah-Hartman * modem status signals. 356ab4382d2SGreg Kroah-Hartman */ 357ab4382d2SGreg Kroah-Hartman static void imx_timeout(unsigned long data) 358ab4382d2SGreg Kroah-Hartman { 359ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)data; 360ab4382d2SGreg Kroah-Hartman unsigned long flags; 361ab4382d2SGreg Kroah-Hartman 362ab4382d2SGreg Kroah-Hartman if (sport->port.state) { 363ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 364ab4382d2SGreg Kroah-Hartman imx_mctrl_check(sport); 365ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 366ab4382d2SGreg Kroah-Hartman 367ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 368ab4382d2SGreg Kroah-Hartman } 369ab4382d2SGreg Kroah-Hartman } 370ab4382d2SGreg Kroah-Hartman 371ab4382d2SGreg Kroah-Hartman /* 372ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 373ab4382d2SGreg Kroah-Hartman */ 374ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 375ab4382d2SGreg Kroah-Hartman { 376ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 377ab4382d2SGreg Kroah-Hartman unsigned long temp; 378ab4382d2SGreg Kroah-Hartman 379ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 380ab4382d2SGreg Kroah-Hartman /* half duplex - wait for end of transmission */ 381ab4382d2SGreg Kroah-Hartman int n = 256; 382ab4382d2SGreg Kroah-Hartman while ((--n > 0) && 383ab4382d2SGreg Kroah-Hartman !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 384ab4382d2SGreg Kroah-Hartman udelay(5); 385ab4382d2SGreg Kroah-Hartman barrier(); 386ab4382d2SGreg Kroah-Hartman } 387ab4382d2SGreg Kroah-Hartman /* 388ab4382d2SGreg Kroah-Hartman * irda transceiver - wait a bit more to avoid 389ab4382d2SGreg Kroah-Hartman * cutoff, hardware dependent 390ab4382d2SGreg Kroah-Hartman */ 391ab4382d2SGreg Kroah-Hartman udelay(sport->trcv_delay); 392ab4382d2SGreg Kroah-Hartman 393ab4382d2SGreg Kroah-Hartman /* 394ab4382d2SGreg Kroah-Hartman * half duplex - reactivate receive mode, 395ab4382d2SGreg Kroah-Hartman * flush receive pipe echo crap 396ab4382d2SGreg Kroah-Hartman */ 397ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR2) & USR2_TXDC) { 398ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 399ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 400ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 401ab4382d2SGreg Kroah-Hartman 402ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 403ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_TCEN); 404ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 405ab4382d2SGreg Kroah-Hartman 406ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + URXD0) & 407ab4382d2SGreg Kroah-Hartman URXD_CHARRDY) 408ab4382d2SGreg Kroah-Hartman barrier(); 409ab4382d2SGreg Kroah-Hartman 410ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 411ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN; 412ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 413ab4382d2SGreg Kroah-Hartman 414ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 415ab4382d2SGreg Kroah-Hartman temp |= UCR4_DREN; 416ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 417ab4382d2SGreg Kroah-Hartman } 418ab4382d2SGreg Kroah-Hartman return; 419ab4382d2SGreg Kroah-Hartman } 420ab4382d2SGreg Kroah-Hartman 4219ce4f8f3SGreg Kroah-Hartman /* 4229ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4239ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4249ce4f8f3SGreg Kroah-Hartman */ 4259ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 4269ce4f8f3SGreg Kroah-Hartman return; 427b4cdc8f6SHuang Shijie 428ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 429ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 430ab4382d2SGreg Kroah-Hartman } 431ab4382d2SGreg Kroah-Hartman 432ab4382d2SGreg Kroah-Hartman /* 433ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 434ab4382d2SGreg Kroah-Hartman */ 435ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 436ab4382d2SGreg Kroah-Hartman { 437ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 438ab4382d2SGreg Kroah-Hartman unsigned long temp; 439ab4382d2SGreg Kroah-Hartman 44045564a66SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) { 44145564a66SHuang Shijie if (sport->port.suspended) { 44245564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 44345564a66SHuang Shijie sport->dma_is_rxing = 0; 44445564a66SHuang Shijie } else { 4459ce4f8f3SGreg Kroah-Hartman return; 44645564a66SHuang Shijie } 44745564a66SHuang Shijie } 448b4cdc8f6SHuang Shijie 449ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 450ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 45185878399SHuang Shijie 45285878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 45385878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 45485878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 455ab4382d2SGreg Kroah-Hartman } 456ab4382d2SGreg Kroah-Hartman 457ab4382d2SGreg Kroah-Hartman /* 458ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 459ab4382d2SGreg Kroah-Hartman */ 460ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 461ab4382d2SGreg Kroah-Hartman { 462ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 463ab4382d2SGreg Kroah-Hartman 464ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 465ab4382d2SGreg Kroah-Hartman } 466ab4382d2SGreg Kroah-Hartman 467ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 468ab4382d2SGreg Kroah-Hartman { 469ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 470ab4382d2SGreg Kroah-Hartman 4715e42e9a3SPeter Hurley if (sport->port.x_char) { 4725e42e9a3SPeter Hurley /* Send next char */ 4735e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4745e42e9a3SPeter Hurley return; 4755e42e9a3SPeter Hurley } 4765e42e9a3SPeter Hurley 4775e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4785e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4795e42e9a3SPeter Hurley return; 4805e42e9a3SPeter Hurley } 4815e42e9a3SPeter Hurley 482ab4382d2SGreg Kroah-Hartman while (!uart_circ_empty(xmit) && 4835e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 484ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 485ab4382d2SGreg Kroah-Hartman * out the port here */ 486ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 487ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 488ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 489ab4382d2SGreg Kroah-Hartman } 490ab4382d2SGreg Kroah-Hartman 491ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 492ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 493ab4382d2SGreg Kroah-Hartman 494ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 495ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 496ab4382d2SGreg Kroah-Hartman } 497ab4382d2SGreg Kroah-Hartman 498b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 499b4cdc8f6SHuang Shijie { 500b4cdc8f6SHuang Shijie struct imx_port *sport = data; 501b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 502b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 503b4cdc8f6SHuang Shijie unsigned long flags; 504b4cdc8f6SHuang Shijie 50542f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 50642f752b3SDirk Behme 507b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 508b4cdc8f6SHuang Shijie 50942f752b3SDirk Behme /* update the stat */ 51042f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 51142f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 51242f752b3SDirk Behme 51342f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 51442f752b3SDirk Behme 515b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 516b4cdc8f6SHuang Shijie 517b4cdc8f6SHuang Shijie spin_unlock_irqrestore(&sport->port.lock, flags); 518b4cdc8f6SHuang Shijie 519d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 520b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5219ce4f8f3SGreg Kroah-Hartman 5229ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) { 5239ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 5249ce4f8f3SGreg Kroah-Hartman dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 5259ce4f8f3SGreg Kroah-Hartman return; 5269ce4f8f3SGreg Kroah-Hartman } 527b4cdc8f6SHuang Shijie } 528b4cdc8f6SHuang Shijie 5297cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 530b4cdc8f6SHuang Shijie { 531b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 532b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 533b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 534b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 535b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 536b4cdc8f6SHuang Shijie int ret; 537b4cdc8f6SHuang Shijie 53842f752b3SDirk Behme if (sport->dma_is_txing) 539b4cdc8f6SHuang Shijie return; 540b4cdc8f6SHuang Shijie 541b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 542b4cdc8f6SHuang Shijie 5437942f857SDirk Behme if (xmit->tail < xmit->head) { 5447942f857SDirk Behme sport->dma_tx_nents = 1; 5457942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5467942f857SDirk Behme } else { 547b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 548b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 549b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 550b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 551b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 552b4cdc8f6SHuang Shijie } 553b4cdc8f6SHuang Shijie 554b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 555b4cdc8f6SHuang Shijie if (ret == 0) { 556b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 557b4cdc8f6SHuang Shijie return; 558b4cdc8f6SHuang Shijie } 559b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 560b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 561b4cdc8f6SHuang Shijie if (!desc) { 56224649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 56324649821SDirk Behme DMA_TO_DEVICE); 564b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 565b4cdc8f6SHuang Shijie return; 566b4cdc8f6SHuang Shijie } 567b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 568b4cdc8f6SHuang Shijie desc->callback_param = sport; 569b4cdc8f6SHuang Shijie 570b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 571b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 572b4cdc8f6SHuang Shijie /* fire it */ 573b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 574b4cdc8f6SHuang Shijie dmaengine_submit(desc); 575b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 576b4cdc8f6SHuang Shijie return; 577b4cdc8f6SHuang Shijie } 578b4cdc8f6SHuang Shijie 579ab4382d2SGreg Kroah-Hartman /* 580ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 581ab4382d2SGreg Kroah-Hartman */ 582ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 583ab4382d2SGreg Kroah-Hartman { 584ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 585ab4382d2SGreg Kroah-Hartman unsigned long temp; 586ab4382d2SGreg Kroah-Hartman 587ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 588ab4382d2SGreg Kroah-Hartman /* half duplex in IrDA mode; have to disable receive mode */ 589ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 590ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_DREN); 591ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 592ab4382d2SGreg Kroah-Hartman 593ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 594ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RRDYEN); 595ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 596ab4382d2SGreg Kroah-Hartman } 597f1f836e4SAlexander Stein /* Clear any pending ORE flag before enabling interrupt */ 598f1f836e4SAlexander Stein temp = readl(sport->port.membase + USR2); 599f1f836e4SAlexander Stein writel(temp | USR2_ORE, sport->port.membase + USR2); 600f1f836e4SAlexander Stein 601f1f836e4SAlexander Stein temp = readl(sport->port.membase + UCR4); 602f1f836e4SAlexander Stein temp |= UCR4_OREN; 603f1f836e4SAlexander Stein writel(temp, sport->port.membase + UCR4); 604ab4382d2SGreg Kroah-Hartman 605b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 606ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 607ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 608b4cdc8f6SHuang Shijie } 609ab4382d2SGreg Kroah-Hartman 610ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 611ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 612ab4382d2SGreg Kroah-Hartman temp |= UCR1_TRDYEN; 613ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 614ab4382d2SGreg Kroah-Hartman 615ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 616ab4382d2SGreg Kroah-Hartman temp |= UCR4_TCEN; 617ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 618ab4382d2SGreg Kroah-Hartman } 619ab4382d2SGreg Kroah-Hartman 620b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 6215e42e9a3SPeter Hurley /* FIXME: port->x_char must be transmitted if != 0 */ 6225e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6235e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6247cb92fd2SHuang Shijie imx_dma_tx(sport); 625b4cdc8f6SHuang Shijie return; 626b4cdc8f6SHuang Shijie } 627ab4382d2SGreg Kroah-Hartman } 628ab4382d2SGreg Kroah-Hartman 629ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 630ab4382d2SGreg Kroah-Hartman { 631ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6325680e941SUwe Kleine-König unsigned int val; 633ab4382d2SGreg Kroah-Hartman unsigned long flags; 634ab4382d2SGreg Kroah-Hartman 635ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 636ab4382d2SGreg Kroah-Hartman 637ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6385680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 639ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 640ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 641ab4382d2SGreg Kroah-Hartman 642ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 643ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 644ab4382d2SGreg Kroah-Hartman } 645ab4382d2SGreg Kroah-Hartman 646ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 647ab4382d2SGreg Kroah-Hartman { 648ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 649ab4382d2SGreg Kroah-Hartman unsigned long flags; 650ab4382d2SGreg Kroah-Hartman 651ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 652ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 653ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 654ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 655ab4382d2SGreg Kroah-Hartman } 656ab4382d2SGreg Kroah-Hartman 657ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 658ab4382d2SGreg Kroah-Hartman { 659ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 660ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 66192a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 662ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 663ab4382d2SGreg Kroah-Hartman 664ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 665ab4382d2SGreg Kroah-Hartman 666ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 667ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 668ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 669ab4382d2SGreg Kroah-Hartman 670ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 671ab4382d2SGreg Kroah-Hartman 672ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 673ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 674ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 675ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 676ab4382d2SGreg Kroah-Hartman continue; 677ab4382d2SGreg Kroah-Hartman } 678ab4382d2SGreg Kroah-Hartman 679ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 680ab4382d2SGreg Kroah-Hartman continue; 681ab4382d2SGreg Kroah-Hartman 682019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 683019dc9eaSHui Wang if (rx & URXD_BRK) 684019dc9eaSHui Wang sport->port.icount.brk++; 685019dc9eaSHui Wang else if (rx & URXD_PRERR) 686ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 687ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 688ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 689ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 690ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 691ab4382d2SGreg Kroah-Hartman 692ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 693ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 694ab4382d2SGreg Kroah-Hartman goto out; 695ab4382d2SGreg Kroah-Hartman continue; 696ab4382d2SGreg Kroah-Hartman } 697ab4382d2SGreg Kroah-Hartman 698ab4382d2SGreg Kroah-Hartman rx &= sport->port.read_status_mask; 699ab4382d2SGreg Kroah-Hartman 700019dc9eaSHui Wang if (rx & URXD_BRK) 701019dc9eaSHui Wang flg = TTY_BREAK; 702019dc9eaSHui Wang else if (rx & URXD_PRERR) 703ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 704ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 705ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 706ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 707ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 708ab4382d2SGreg Kroah-Hartman 709ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 710ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 711ab4382d2SGreg Kroah-Hartman #endif 712ab4382d2SGreg Kroah-Hartman } 713ab4382d2SGreg Kroah-Hartman 71455d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 71555d8693aSJiada Wang goto out; 71655d8693aSJiada Wang 71792a19f9cSJiri Slaby tty_insert_flip_char(port, rx, flg); 718ab4382d2SGreg Kroah-Hartman } 719ab4382d2SGreg Kroah-Hartman 720ab4382d2SGreg Kroah-Hartman out: 721ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7222e124b4aSJiri Slaby tty_flip_buffer_push(port); 723ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 724ab4382d2SGreg Kroah-Hartman } 725ab4382d2SGreg Kroah-Hartman 7267cb92fd2SHuang Shijie static int start_rx_dma(struct imx_port *sport); 727b4cdc8f6SHuang Shijie /* 728b4cdc8f6SHuang Shijie * If the RXFIFO is filled with some data, and then we 729b4cdc8f6SHuang Shijie * arise a DMA operation to receive them. 730b4cdc8f6SHuang Shijie */ 731b4cdc8f6SHuang Shijie static void imx_dma_rxint(struct imx_port *sport) 732b4cdc8f6SHuang Shijie { 733b4cdc8f6SHuang Shijie unsigned long temp; 73473631813SJiada Wang unsigned long flags; 73573631813SJiada Wang 73673631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 737b4cdc8f6SHuang Shijie 738b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + USR2); 739b4cdc8f6SHuang Shijie if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 740b4cdc8f6SHuang Shijie sport->dma_is_rxing = 1; 741b4cdc8f6SHuang Shijie 742b4cdc8f6SHuang Shijie /* disable the `Recerver Ready Interrrupt` */ 743b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 744b4cdc8f6SHuang Shijie temp &= ~(UCR1_RRDYEN); 745b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 746b4cdc8f6SHuang Shijie 747b4cdc8f6SHuang Shijie /* tell the DMA to receive the data. */ 7487cb92fd2SHuang Shijie start_rx_dma(sport); 749b4cdc8f6SHuang Shijie } 75073631813SJiada Wang 75173631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 752b4cdc8f6SHuang Shijie } 753b4cdc8f6SHuang Shijie 754ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 755ab4382d2SGreg Kroah-Hartman { 756ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 757ab4382d2SGreg Kroah-Hartman unsigned int sts; 758f1f836e4SAlexander Stein unsigned int sts2; 759ab4382d2SGreg Kroah-Hartman 760ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 761ab4382d2SGreg Kroah-Hartman 762b4cdc8f6SHuang Shijie if (sts & USR1_RRDY) { 763b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) 764b4cdc8f6SHuang Shijie imx_dma_rxint(sport); 765b4cdc8f6SHuang Shijie else 766ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 767b4cdc8f6SHuang Shijie } 768ab4382d2SGreg Kroah-Hartman 769ab4382d2SGreg Kroah-Hartman if (sts & USR1_TRDY && 770ab4382d2SGreg Kroah-Hartman readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 771ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 772ab4382d2SGreg Kroah-Hartman 773ab4382d2SGreg Kroah-Hartman if (sts & USR1_RTSD) 774ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 775ab4382d2SGreg Kroah-Hartman 776db1a9b55SFabio Estevam if (sts & USR1_AWAKE) 777db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 778db1a9b55SFabio Estevam 779f1f836e4SAlexander Stein sts2 = readl(sport->port.membase + USR2); 780f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 781f1f836e4SAlexander Stein dev_err(sport->port.dev, "Rx FIFO overrun\n"); 782f1f836e4SAlexander Stein sport->port.icount.overrun++; 783f1f836e4SAlexander Stein writel(sts2 | USR2_ORE, sport->port.membase + USR2); 784f1f836e4SAlexander Stein } 785f1f836e4SAlexander Stein 786ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 787ab4382d2SGreg Kroah-Hartman } 788ab4382d2SGreg Kroah-Hartman 789ab4382d2SGreg Kroah-Hartman /* 790ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 791ab4382d2SGreg Kroah-Hartman */ 792ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 793ab4382d2SGreg Kroah-Hartman { 794ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 7951ce43e58SHuang Shijie unsigned int ret; 796ab4382d2SGreg Kroah-Hartman 7971ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 7981ce43e58SHuang Shijie 7991ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 8001ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 8011ce43e58SHuang Shijie ret = 0; 8021ce43e58SHuang Shijie 8031ce43e58SHuang Shijie return ret; 804ab4382d2SGreg Kroah-Hartman } 805ab4382d2SGreg Kroah-Hartman 806ab4382d2SGreg Kroah-Hartman /* 807ab4382d2SGreg Kroah-Hartman * We have a modem side uart, so the meanings of RTS and CTS are inverted. 808ab4382d2SGreg Kroah-Hartman */ 809ab4382d2SGreg Kroah-Hartman static unsigned int imx_get_mctrl(struct uart_port *port) 810ab4382d2SGreg Kroah-Hartman { 811ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 812ab4382d2SGreg Kroah-Hartman unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 813ab4382d2SGreg Kroah-Hartman 814ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR1) & USR1_RTSS) 815ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_CTS; 816ab4382d2SGreg Kroah-Hartman 817ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR2) & UCR2_CTS) 818ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_RTS; 819ab4382d2SGreg Kroah-Hartman 8206b471a98SHuang Shijie if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 8216b471a98SHuang Shijie tmp |= TIOCM_LOOP; 8226b471a98SHuang Shijie 823ab4382d2SGreg Kroah-Hartman return tmp; 824ab4382d2SGreg Kroah-Hartman } 825ab4382d2SGreg Kroah-Hartman 826ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 827ab4382d2SGreg Kroah-Hartman { 828ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 829ab4382d2SGreg Kroah-Hartman unsigned long temp; 830ab4382d2SGreg Kroah-Hartman 831bb2f861aSFugang Duan temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC); 832ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 833bb2f861aSFugang Duan temp |= UCR2_CTS | UCR2_CTSC; 834ab4382d2SGreg Kroah-Hartman 835ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 8366b471a98SHuang Shijie 8376b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8386b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8396b471a98SHuang Shijie temp |= UTS_LOOP; 8406b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 841ab4382d2SGreg Kroah-Hartman } 842ab4382d2SGreg Kroah-Hartman 843ab4382d2SGreg Kroah-Hartman /* 844ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 845ab4382d2SGreg Kroah-Hartman */ 846ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 847ab4382d2SGreg Kroah-Hartman { 848ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 849ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 850ab4382d2SGreg Kroah-Hartman 851ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 852ab4382d2SGreg Kroah-Hartman 853ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 854ab4382d2SGreg Kroah-Hartman 855ab4382d2SGreg Kroah-Hartman if (break_state != 0) 856ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 857ab4382d2SGreg Kroah-Hartman 858ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 859ab4382d2SGreg Kroah-Hartman 860ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 861ab4382d2SGreg Kroah-Hartman } 862ab4382d2SGreg Kroah-Hartman 863ab4382d2SGreg Kroah-Hartman #define TXTL 2 /* reset default */ 864ab4382d2SGreg Kroah-Hartman #define RXTL 1 /* reset default */ 865ab4382d2SGreg Kroah-Hartman 866ab4382d2SGreg Kroah-Hartman static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 867ab4382d2SGreg Kroah-Hartman { 868ab4382d2SGreg Kroah-Hartman unsigned int val; 869ab4382d2SGreg Kroah-Hartman 8707be0670fSDirk Behme /* set receiver / transmitter trigger level */ 8717be0670fSDirk Behme val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 8727be0670fSDirk Behme val |= TXTL << UFCR_TXTL_SHF | RXTL; 873ab4382d2SGreg Kroah-Hartman writel(val, sport->port.membase + UFCR); 874ab4382d2SGreg Kroah-Hartman return 0; 875ab4382d2SGreg Kroah-Hartman } 876ab4382d2SGreg Kroah-Hartman 877b4cdc8f6SHuang Shijie #define RX_BUF_SIZE (PAGE_SIZE) 878b4cdc8f6SHuang Shijie static void imx_rx_dma_done(struct imx_port *sport) 879b4cdc8f6SHuang Shijie { 880b4cdc8f6SHuang Shijie unsigned long temp; 88173631813SJiada Wang unsigned long flags; 88273631813SJiada Wang 88373631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 884b4cdc8f6SHuang Shijie 885b4cdc8f6SHuang Shijie /* Enable this interrupt when the RXFIFO is empty. */ 886b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 887b4cdc8f6SHuang Shijie temp |= UCR1_RRDYEN; 888b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 889b4cdc8f6SHuang Shijie 890b4cdc8f6SHuang Shijie sport->dma_is_rxing = 0; 8919ce4f8f3SGreg Kroah-Hartman 8929ce4f8f3SGreg Kroah-Hartman /* Is the shutdown waiting for us? */ 8939ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) 8949ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 89573631813SJiada Wang 89673631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 897b4cdc8f6SHuang Shijie } 898b4cdc8f6SHuang Shijie 899b4cdc8f6SHuang Shijie /* 900b4cdc8f6SHuang Shijie * There are three kinds of RX DMA interrupts(such as in the MX6Q): 901b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 902b4cdc8f6SHuang Shijie * [2] the Aging timer expires(wait for 8 bytes long) 903b4cdc8f6SHuang Shijie * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 904b4cdc8f6SHuang Shijie * 905b4cdc8f6SHuang Shijie * The [2] is trigger when a character was been sitting in the FIFO 906b4cdc8f6SHuang Shijie * meanwhile [3] can wait for 32 bytes long when the RX line is 907b4cdc8f6SHuang Shijie * on IDLE state and RxFIFO is empty. 908b4cdc8f6SHuang Shijie */ 909b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 910b4cdc8f6SHuang Shijie { 911b4cdc8f6SHuang Shijie struct imx_port *sport = data; 912b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 913b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9147cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 915b4cdc8f6SHuang Shijie struct dma_tx_state state; 916b4cdc8f6SHuang Shijie enum dma_status status; 917b4cdc8f6SHuang Shijie unsigned int count; 918b4cdc8f6SHuang Shijie 919b4cdc8f6SHuang Shijie /* unmap it first */ 920b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 921b4cdc8f6SHuang Shijie 922f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 923b4cdc8f6SHuang Shijie count = RX_BUF_SIZE - state.residue; 924b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 925b4cdc8f6SHuang Shijie 926b4cdc8f6SHuang Shijie if (count) { 92755d8693aSJiada Wang if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) 9287cb92fd2SHuang Shijie tty_insert_flip_string(port, sport->rx_buf, count); 9297cb92fd2SHuang Shijie tty_flip_buffer_push(port); 9307cb92fd2SHuang Shijie 9317cb92fd2SHuang Shijie start_rx_dma(sport); 932b4cdc8f6SHuang Shijie } else 933b4cdc8f6SHuang Shijie imx_rx_dma_done(sport); 934b4cdc8f6SHuang Shijie } 935b4cdc8f6SHuang Shijie 936b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 937b4cdc8f6SHuang Shijie { 938b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 939b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 940b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 941b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 942b4cdc8f6SHuang Shijie int ret; 943b4cdc8f6SHuang Shijie 944b4cdc8f6SHuang Shijie sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 945b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 946b4cdc8f6SHuang Shijie if (ret == 0) { 947b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 948b4cdc8f6SHuang Shijie return -EINVAL; 949b4cdc8f6SHuang Shijie } 950b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 951b4cdc8f6SHuang Shijie DMA_PREP_INTERRUPT); 952b4cdc8f6SHuang Shijie if (!desc) { 95324649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 954b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 955b4cdc8f6SHuang Shijie return -EINVAL; 956b4cdc8f6SHuang Shijie } 957b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 958b4cdc8f6SHuang Shijie desc->callback_param = sport; 959b4cdc8f6SHuang Shijie 960b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 961b4cdc8f6SHuang Shijie dmaengine_submit(desc); 962b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 963b4cdc8f6SHuang Shijie return 0; 964b4cdc8f6SHuang Shijie } 965b4cdc8f6SHuang Shijie 966b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 967b4cdc8f6SHuang Shijie { 968b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 969b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 970b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 971b4cdc8f6SHuang Shijie 972b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 973b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 974b4cdc8f6SHuang Shijie } 975b4cdc8f6SHuang Shijie 976b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 977b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 978b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 979b4cdc8f6SHuang Shijie } 980b4cdc8f6SHuang Shijie 981b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 982b4cdc8f6SHuang Shijie } 983b4cdc8f6SHuang Shijie 984b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 985b4cdc8f6SHuang Shijie { 986b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 987b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 988b4cdc8f6SHuang Shijie int ret; 989b4cdc8f6SHuang Shijie 990b4cdc8f6SHuang Shijie /* Prepare for RX : */ 991b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 992b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 993b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 994b4cdc8f6SHuang Shijie ret = -EINVAL; 995b4cdc8f6SHuang Shijie goto err; 996b4cdc8f6SHuang Shijie } 997b4cdc8f6SHuang Shijie 998b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 999b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1000b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1001b4cdc8f6SHuang Shijie slave_config.src_maxburst = RXTL; 1002b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1003b4cdc8f6SHuang Shijie if (ret) { 1004b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1005b4cdc8f6SHuang Shijie goto err; 1006b4cdc8f6SHuang Shijie } 1007b4cdc8f6SHuang Shijie 1008b4cdc8f6SHuang Shijie sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1009b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1010b4cdc8f6SHuang Shijie ret = -ENOMEM; 1011b4cdc8f6SHuang Shijie goto err; 1012b4cdc8f6SHuang Shijie } 1013b4cdc8f6SHuang Shijie 1014b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1015b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1016b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1017b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1018b4cdc8f6SHuang Shijie ret = -EINVAL; 1019b4cdc8f6SHuang Shijie goto err; 1020b4cdc8f6SHuang Shijie } 1021b4cdc8f6SHuang Shijie 1022b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1023b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1024b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1025b4cdc8f6SHuang Shijie slave_config.dst_maxburst = TXTL; 1026b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1027b4cdc8f6SHuang Shijie if (ret) { 1028b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1029b4cdc8f6SHuang Shijie goto err; 1030b4cdc8f6SHuang Shijie } 1031b4cdc8f6SHuang Shijie 1032b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1033b4cdc8f6SHuang Shijie 1034b4cdc8f6SHuang Shijie return 0; 1035b4cdc8f6SHuang Shijie err: 1036b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1037b4cdc8f6SHuang Shijie return ret; 1038b4cdc8f6SHuang Shijie } 1039b4cdc8f6SHuang Shijie 1040b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1041b4cdc8f6SHuang Shijie { 1042b4cdc8f6SHuang Shijie unsigned long temp; 1043b4cdc8f6SHuang Shijie 10449ce4f8f3SGreg Kroah-Hartman init_waitqueue_head(&sport->dma_wait); 10459ce4f8f3SGreg Kroah-Hartman 1046b4cdc8f6SHuang Shijie /* set UCR1 */ 1047b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1048b4cdc8f6SHuang Shijie temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1049b4cdc8f6SHuang Shijie /* wait for 32 idle frames for IDDMA interrupt */ 1050b4cdc8f6SHuang Shijie UCR1_ICD_REG(3); 1051b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1052b4cdc8f6SHuang Shijie 1053b4cdc8f6SHuang Shijie /* set UCR4 */ 1054b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1055b4cdc8f6SHuang Shijie temp |= UCR4_IDDMAEN; 1056b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1057b4cdc8f6SHuang Shijie 1058b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1059b4cdc8f6SHuang Shijie } 1060b4cdc8f6SHuang Shijie 1061b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1062b4cdc8f6SHuang Shijie { 1063b4cdc8f6SHuang Shijie unsigned long temp; 1064b4cdc8f6SHuang Shijie 1065b4cdc8f6SHuang Shijie /* clear UCR1 */ 1066b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1067b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1068b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1069b4cdc8f6SHuang Shijie 1070b4cdc8f6SHuang Shijie /* clear UCR2 */ 1071b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 1072b4cdc8f6SHuang Shijie temp &= ~(UCR2_CTSC | UCR2_CTS); 1073b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1074b4cdc8f6SHuang Shijie 1075b4cdc8f6SHuang Shijie /* clear UCR4 */ 1076b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1077b4cdc8f6SHuang Shijie temp &= ~UCR4_IDDMAEN; 1078b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1079b4cdc8f6SHuang Shijie 1080b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1081b4cdc8f6SHuang Shijie } 1082b4cdc8f6SHuang Shijie 1083ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1084ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1085ab4382d2SGreg Kroah-Hartman 1086ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1087ab4382d2SGreg Kroah-Hartman { 1088ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1089772f8991SHuang Shijie int retval, i; 1090ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1091ab4382d2SGreg Kroah-Hartman 109228eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 109328eb4274SHuang Shijie if (retval) 1094cb0f0a5fSFabio Estevam return retval; 109528eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 10960c375501SHuang Shijie if (retval) { 10970c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1098cb0f0a5fSFabio Estevam return retval; 10990c375501SHuang Shijie } 110028eb4274SHuang Shijie 1101ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1102ab4382d2SGreg Kroah-Hartman 1103ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1104ab4382d2SGreg Kroah-Hartman * requesting IRQs 1105ab4382d2SGreg Kroah-Hartman */ 1106ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1107ab4382d2SGreg Kroah-Hartman 1108ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1109ab4382d2SGreg Kroah-Hartman temp |= UCR4_IRSC; 1110ab4382d2SGreg Kroah-Hartman 1111ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1112ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1113ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1114ab4382d2SGreg Kroah-Hartman 1115ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1116ab4382d2SGreg Kroah-Hartman 1117772f8991SHuang Shijie /* Reset fifo's and state machines */ 1118772f8991SHuang Shijie i = 100; 1119772f8991SHuang Shijie 1120ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1121ab4382d2SGreg Kroah-Hartman temp &= ~UCR2_SRST; 1122ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1123772f8991SHuang Shijie 1124772f8991SHuang Shijie while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1125ab4382d2SGreg Kroah-Hartman udelay(1); 1126ab4382d2SGreg Kroah-Hartman 11279ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1128ab4382d2SGreg Kroah-Hartman /* 1129ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1130ab4382d2SGreg Kroah-Hartman */ 1131ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 1132ab4382d2SGreg Kroah-Hartman 1133ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1134ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1135ab4382d2SGreg Kroah-Hartman 1136ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1137ab4382d2SGreg Kroah-Hartman temp |= UCR1_IREN; 1138ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RTSDEN); 1139ab4382d2SGreg Kroah-Hartman } 1140ab4382d2SGreg Kroah-Hartman 1141ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1142ab4382d2SGreg Kroah-Hartman 1143ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1144ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1145bff09b09SLucas Stach if (!sport->have_rtscts) 1146bff09b09SLucas Stach temp |= UCR2_IRTS; 1147ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1148ab4382d2SGreg Kroah-Hartman 1149a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1150ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1151b38cb7d2SFabio Estevam temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1152ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1153ab4382d2SGreg Kroah-Hartman } 1154ab4382d2SGreg Kroah-Hartman 1155ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1156ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1157ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_rx) 1158ab4382d2SGreg Kroah-Hartman temp |= UCR4_INVR; 1159ab4382d2SGreg Kroah-Hartman else 1160ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_INVR); 1161ab4382d2SGreg Kroah-Hartman writel(temp | UCR4_DREN, sport->port.membase + UCR4); 1162ab4382d2SGreg Kroah-Hartman 1163ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1164ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_tx) 1165ab4382d2SGreg Kroah-Hartman temp |= UCR3_INVT; 1166ab4382d2SGreg Kroah-Hartman else 1167ab4382d2SGreg Kroah-Hartman temp &= ~(UCR3_INVT); 1168ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1169ab4382d2SGreg Kroah-Hartman } 1170ab4382d2SGreg Kroah-Hartman 1171ab4382d2SGreg Kroah-Hartman /* 1172ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1173ab4382d2SGreg Kroah-Hartman */ 1174ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1175ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1176ab4382d2SGreg Kroah-Hartman 1177ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1178ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1179574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1180ab4382d2SGreg Kroah-Hartman sport->irda_inv_rx = pdata->irda_inv_rx; 1181ab4382d2SGreg Kroah-Hartman sport->irda_inv_tx = pdata->irda_inv_tx; 1182ab4382d2SGreg Kroah-Hartman sport->trcv_delay = pdata->transceiver_delay; 1183ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1184ab4382d2SGreg Kroah-Hartman pdata->irda_enable(1); 1185ab4382d2SGreg Kroah-Hartman } 1186ab4382d2SGreg Kroah-Hartman 1187ab4382d2SGreg Kroah-Hartman return 0; 1188ab4382d2SGreg Kroah-Hartman } 1189ab4382d2SGreg Kroah-Hartman 1190ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1191ab4382d2SGreg Kroah-Hartman { 1192ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1193ab4382d2SGreg Kroah-Hartman unsigned long temp; 11949ec1882dSXinyu Chen unsigned long flags; 1195ab4382d2SGreg Kroah-Hartman 1196b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1197a4688bcdSHuang Shijie int ret; 1198a4688bcdSHuang Shijie 11999ce4f8f3SGreg Kroah-Hartman /* We have to wait for the DMA to finish. */ 1200a4688bcdSHuang Shijie ret = wait_event_interruptible(sport->dma_wait, 12019ce4f8f3SGreg Kroah-Hartman !sport->dma_is_rxing && !sport->dma_is_txing); 1202a4688bcdSHuang Shijie if (ret != 0) { 1203a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1204a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1205a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 1206a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 1207a4688bcdSHuang Shijie } 120873631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1209a4688bcdSHuang Shijie imx_stop_tx(port); 1210b4cdc8f6SHuang Shijie imx_stop_rx(port); 1211b4cdc8f6SHuang Shijie imx_disable_dma(sport); 121273631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1213b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1214b4cdc8f6SHuang Shijie } 1215b4cdc8f6SHuang Shijie 12169ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1217ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1218ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1219ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 12209ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1221ab4382d2SGreg Kroah-Hartman 1222ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1223ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1224574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1225ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1226ab4382d2SGreg Kroah-Hartman pdata->irda_enable(0); 1227ab4382d2SGreg Kroah-Hartman } 1228ab4382d2SGreg Kroah-Hartman 1229ab4382d2SGreg Kroah-Hartman /* 1230ab4382d2SGreg Kroah-Hartman * Stop our timer. 1231ab4382d2SGreg Kroah-Hartman */ 1232ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1233ab4382d2SGreg Kroah-Hartman 1234ab4382d2SGreg Kroah-Hartman /* 1235ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1236ab4382d2SGreg Kroah-Hartman */ 1237ab4382d2SGreg Kroah-Hartman 12389ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1239ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1240ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1241ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1242ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_IREN); 1243ab4382d2SGreg Kroah-Hartman 1244ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 12459ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 124628eb4274SHuang Shijie 124728eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 124828eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1249ab4382d2SGreg Kroah-Hartman } 1250ab4382d2SGreg Kroah-Hartman 1251eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1252eb56b7edSHuang Shijie { 1253eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 125482e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1255eb56b7edSHuang Shijie 125682e86ae9SDirk Behme if (!sport->dma_chan_tx) 125782e86ae9SDirk Behme return; 125882e86ae9SDirk Behme 1259eb56b7edSHuang Shijie sport->tx_bytes = 0; 1260eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 126182e86ae9SDirk Behme if (sport->dma_is_txing) { 126282e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 126382e86ae9SDirk Behme DMA_TO_DEVICE); 126482e86ae9SDirk Behme sport->dma_is_txing = false; 1265eb56b7edSHuang Shijie } 1266eb56b7edSHuang Shijie } 1267eb56b7edSHuang Shijie 1268ab4382d2SGreg Kroah-Hartman static void 1269ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1270ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1271ab4382d2SGreg Kroah-Hartman { 1272ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1273ab4382d2SGreg Kroah-Hartman unsigned long flags; 1274ab4382d2SGreg Kroah-Hartman unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1275ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1276ab4382d2SGreg Kroah-Hartman unsigned int div, ufcr; 1277ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1278ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1279ab4382d2SGreg Kroah-Hartman 1280ab4382d2SGreg Kroah-Hartman /* 1281ab4382d2SGreg Kroah-Hartman * If we don't support modem control lines, don't allow 1282ab4382d2SGreg Kroah-Hartman * these to be set. 1283ab4382d2SGreg Kroah-Hartman */ 1284ab4382d2SGreg Kroah-Hartman if (0) { 1285ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 1286ab4382d2SGreg Kroah-Hartman termios->c_cflag |= CLOCAL; 1287ab4382d2SGreg Kroah-Hartman } 1288ab4382d2SGreg Kroah-Hartman 1289ab4382d2SGreg Kroah-Hartman /* 1290ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1291ab4382d2SGreg Kroah-Hartman */ 1292ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1293ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1294ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1295ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1296ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1297ab4382d2SGreg Kroah-Hartman } 1298ab4382d2SGreg Kroah-Hartman 1299ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1300ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1301ab4382d2SGreg Kroah-Hartman else 1302ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1303ab4382d2SGreg Kroah-Hartman 1304ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1305ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1306ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 1307ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_CTSC; 1308b4cdc8f6SHuang Shijie 1309b4cdc8f6SHuang Shijie /* Can we enable the DMA support? */ 1310b4cdc8f6SHuang Shijie if (is_imx6q_uart(sport) && !uart_console(port) 1311b4cdc8f6SHuang Shijie && !sport->dma_is_inited) 1312b4cdc8f6SHuang Shijie imx_uart_dma_init(sport); 1313ab4382d2SGreg Kroah-Hartman } else { 1314ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1315ab4382d2SGreg Kroah-Hartman } 1316ab4382d2SGreg Kroah-Hartman } 1317ab4382d2SGreg Kroah-Hartman 1318ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1319ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1320ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1321ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1322ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1323ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1324ab4382d2SGreg Kroah-Hartman } 1325ab4382d2SGreg Kroah-Hartman 1326995234daSEric Miao del_timer_sync(&sport->timer); 1327995234daSEric Miao 1328ab4382d2SGreg Kroah-Hartman /* 1329ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1330ab4382d2SGreg Kroah-Hartman */ 1331ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1332ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1333ab4382d2SGreg Kroah-Hartman 1334ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1335ab4382d2SGreg Kroah-Hartman 1336ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1337ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1338ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1339ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1340ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1341ab4382d2SGreg Kroah-Hartman 1342ab4382d2SGreg Kroah-Hartman /* 1343ab4382d2SGreg Kroah-Hartman * Characters to ignore 1344ab4382d2SGreg Kroah-Hartman */ 1345ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1346ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1347ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_PRERR; 1348ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1349ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1350ab4382d2SGreg Kroah-Hartman /* 1351ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1352ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1353ab4382d2SGreg Kroah-Hartman */ 1354ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1355ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1356ab4382d2SGreg Kroah-Hartman } 1357ab4382d2SGreg Kroah-Hartman 135855d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 135955d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 136055d8693aSJiada Wang 1361ab4382d2SGreg Kroah-Hartman /* 1362ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1363ab4382d2SGreg Kroah-Hartman */ 1364ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1365ab4382d2SGreg Kroah-Hartman 1366ab4382d2SGreg Kroah-Hartman /* 1367ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1368ab4382d2SGreg Kroah-Hartman */ 1369ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1370ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1371ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1372ab4382d2SGreg Kroah-Hartman 1373ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1374ab4382d2SGreg Kroah-Hartman barrier(); 1375ab4382d2SGreg Kroah-Hartman 1376ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 1377ab4382d2SGreg Kroah-Hartman old_txrxen = readl(sport->port.membase + UCR2); 1378ab4382d2SGreg Kroah-Hartman writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1379ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 1380ab4382d2SGreg Kroah-Hartman old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1381ab4382d2SGreg Kroah-Hartman 1382ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1383ab4382d2SGreg Kroah-Hartman /* 1384ab4382d2SGreg Kroah-Hartman * use maximum available submodule frequency to 1385ab4382d2SGreg Kroah-Hartman * avoid missing short pulses due to low sampling rate 1386ab4382d2SGreg Kroah-Hartman */ 1387ab4382d2SGreg Kroah-Hartman div = 1; 1388ab4382d2SGreg Kroah-Hartman } else { 138909bd00f6SHubert Feurstein /* custom-baudrate handling */ 139009bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 139109bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 139209bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 139309bd00f6SHubert Feurstein 1394ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1395ab4382d2SGreg Kroah-Hartman if (div > 7) 1396ab4382d2SGreg Kroah-Hartman div = 7; 1397ab4382d2SGreg Kroah-Hartman if (!div) 1398ab4382d2SGreg Kroah-Hartman div = 1; 1399ab4382d2SGreg Kroah-Hartman } 1400ab4382d2SGreg Kroah-Hartman 1401ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1402ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1403ab4382d2SGreg Kroah-Hartman 1404ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1405ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1406ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1407ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1408ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1409ab4382d2SGreg Kroah-Hartman 1410ab4382d2SGreg Kroah-Hartman num -= 1; 1411ab4382d2SGreg Kroah-Hartman denom -= 1; 1412ab4382d2SGreg Kroah-Hartman 1413ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1414ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 141520ff2fe6SHuang Shijie if (sport->dte_mode) 141620ff2fe6SHuang Shijie ufcr |= UFCR_DCEDTE; 1417ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1418ab4382d2SGreg Kroah-Hartman 1419ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1420ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1421ab4382d2SGreg Kroah-Hartman 1422a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1423ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1424fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1425ab4382d2SGreg Kroah-Hartman 1426ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1427ab4382d2SGreg Kroah-Hartman 1428ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 1429ab4382d2SGreg Kroah-Hartman writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1430ab4382d2SGreg Kroah-Hartman 1431ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1432ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1433ab4382d2SGreg Kroah-Hartman 1434b4cdc8f6SHuang Shijie if (sport->dma_is_inited && !sport->dma_is_enabled) 1435b4cdc8f6SHuang Shijie imx_enable_dma(sport); 1436ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1437ab4382d2SGreg Kroah-Hartman } 1438ab4382d2SGreg Kroah-Hartman 1439ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1440ab4382d2SGreg Kroah-Hartman { 1441ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1442ab4382d2SGreg Kroah-Hartman 1443ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1444ab4382d2SGreg Kroah-Hartman } 1445ab4382d2SGreg Kroah-Hartman 1446ab4382d2SGreg Kroah-Hartman /* 1447ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1448ab4382d2SGreg Kroah-Hartman */ 1449ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1450ab4382d2SGreg Kroah-Hartman { 1451ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1452ab4382d2SGreg Kroah-Hartman 1453da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1454ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1455ab4382d2SGreg Kroah-Hartman } 1456ab4382d2SGreg Kroah-Hartman 1457ab4382d2SGreg Kroah-Hartman /* 1458ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1459ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1460ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1461ab4382d2SGreg Kroah-Hartman */ 1462ab4382d2SGreg Kroah-Hartman static int 1463ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1464ab4382d2SGreg Kroah-Hartman { 1465ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1466ab4382d2SGreg Kroah-Hartman int ret = 0; 1467ab4382d2SGreg Kroah-Hartman 1468ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1469ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1470ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1471ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1472ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1473ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1474ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1475ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1476a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1477ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1478ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1479ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1480ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1481ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1482ab4382d2SGreg Kroah-Hartman return ret; 1483ab4382d2SGreg Kroah-Hartman } 1484ab4382d2SGreg Kroah-Hartman 148501f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 14866b8bdad9SDaniel Thompson 14876b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 14886b8bdad9SDaniel Thompson { 14896b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 14906b8bdad9SDaniel Thompson unsigned long flags; 14916b8bdad9SDaniel Thompson unsigned long temp; 14926b8bdad9SDaniel Thompson int retval; 14936b8bdad9SDaniel Thompson 14946b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 14956b8bdad9SDaniel Thompson if (retval) 14966b8bdad9SDaniel Thompson return retval; 14976b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 14986b8bdad9SDaniel Thompson if (retval) 14996b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 15006b8bdad9SDaniel Thompson 15016b8bdad9SDaniel Thompson imx_setup_ufcr(sport, 0); 15026b8bdad9SDaniel Thompson 15036b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 15046b8bdad9SDaniel Thompson 15056b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR1); 15066b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 15076b8bdad9SDaniel Thompson temp |= IMX1_UCR1_UARTCLKEN; 15086b8bdad9SDaniel Thompson temp |= UCR1_UARTEN | UCR1_RRDYEN; 15096b8bdad9SDaniel Thompson temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 15106b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR1); 15116b8bdad9SDaniel Thompson 15126b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR2); 15136b8bdad9SDaniel Thompson temp |= UCR2_RXEN; 15146b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR2); 15156b8bdad9SDaniel Thompson 15166b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 15176b8bdad9SDaniel Thompson 15186b8bdad9SDaniel Thompson return 0; 15196b8bdad9SDaniel Thompson } 15206b8bdad9SDaniel Thompson 152101f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 152201f56abdSSaleem Abdulrasool { 1523f968ef34SDaniel Thompson if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 152426c47412SDirk Behme return NO_POLL_CHAR; 152501f56abdSSaleem Abdulrasool 1526f968ef34SDaniel Thompson return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 152701f56abdSSaleem Abdulrasool } 152801f56abdSSaleem Abdulrasool 152901f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 153001f56abdSSaleem Abdulrasool { 153101f56abdSSaleem Abdulrasool unsigned int status; 153201f56abdSSaleem Abdulrasool 153301f56abdSSaleem Abdulrasool /* drain */ 153401f56abdSSaleem Abdulrasool do { 1535f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR1); 153601f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 153701f56abdSSaleem Abdulrasool 153801f56abdSSaleem Abdulrasool /* write */ 1539f968ef34SDaniel Thompson writel_relaxed(c, port->membase + URTX0); 154001f56abdSSaleem Abdulrasool 154101f56abdSSaleem Abdulrasool /* flush */ 154201f56abdSSaleem Abdulrasool do { 1543f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR2); 154401f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 154501f56abdSSaleem Abdulrasool } 154601f56abdSSaleem Abdulrasool #endif 154701f56abdSSaleem Abdulrasool 1548ab4382d2SGreg Kroah-Hartman static struct uart_ops imx_pops = { 1549ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1550ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1551ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1552ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1553ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1554ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1555ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1556ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1557ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1558ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1559eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1560ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1561ab4382d2SGreg Kroah-Hartman .type = imx_type, 1562ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1563ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 156401f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 15656b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 156601f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 156701f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 156801f56abdSSaleem Abdulrasool #endif 1569ab4382d2SGreg Kroah-Hartman }; 1570ab4382d2SGreg Kroah-Hartman 1571ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1572ab4382d2SGreg Kroah-Hartman 1573ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1574ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1575ab4382d2SGreg Kroah-Hartman { 1576ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1577ab4382d2SGreg Kroah-Hartman 1578fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1579ab4382d2SGreg Kroah-Hartman barrier(); 1580ab4382d2SGreg Kroah-Hartman 1581ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1582ab4382d2SGreg Kroah-Hartman } 1583ab4382d2SGreg Kroah-Hartman 1584ab4382d2SGreg Kroah-Hartman /* 1585ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1586ab4382d2SGreg Kroah-Hartman */ 1587ab4382d2SGreg Kroah-Hartman static void 1588ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1589ab4382d2SGreg Kroah-Hartman { 1590ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 15910ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 15920ad5a814SDirk Behme unsigned int ucr1; 1593f30e8260SShawn Guo unsigned long flags = 0; 1594677fe555SThomas Gleixner int locked = 1; 15951cf93e0dSHuang Shijie int retval; 15961cf93e0dSHuang Shijie 15971cf93e0dSHuang Shijie retval = clk_enable(sport->clk_per); 15981cf93e0dSHuang Shijie if (retval) 15991cf93e0dSHuang Shijie return; 16001cf93e0dSHuang Shijie retval = clk_enable(sport->clk_ipg); 16011cf93e0dSHuang Shijie if (retval) { 16021cf93e0dSHuang Shijie clk_disable(sport->clk_per); 16031cf93e0dSHuang Shijie return; 16041cf93e0dSHuang Shijie } 16059ec1882dSXinyu Chen 1606677fe555SThomas Gleixner if (sport->port.sysrq) 1607677fe555SThomas Gleixner locked = 0; 1608677fe555SThomas Gleixner else if (oops_in_progress) 1609677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1610677fe555SThomas Gleixner else 16119ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1612ab4382d2SGreg Kroah-Hartman 1613ab4382d2SGreg Kroah-Hartman /* 16140ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1615ab4382d2SGreg Kroah-Hartman */ 16160ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 16170ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1618ab4382d2SGreg Kroah-Hartman 1619fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1620fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1621ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1622ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1623ab4382d2SGreg Kroah-Hartman 1624ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1625ab4382d2SGreg Kroah-Hartman 16260ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1627ab4382d2SGreg Kroah-Hartman 1628ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1629ab4382d2SGreg Kroah-Hartman 1630ab4382d2SGreg Kroah-Hartman /* 1631ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 16320ad5a814SDirk Behme * and restore UCR1/2/3 1633ab4382d2SGreg Kroah-Hartman */ 1634ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1635ab4382d2SGreg Kroah-Hartman 16360ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 16379ec1882dSXinyu Chen 1638677fe555SThomas Gleixner if (locked) 16399ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 16401cf93e0dSHuang Shijie 16411cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 16421cf93e0dSHuang Shijie clk_disable(sport->clk_per); 1643ab4382d2SGreg Kroah-Hartman } 1644ab4382d2SGreg Kroah-Hartman 1645ab4382d2SGreg Kroah-Hartman /* 1646ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1647ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1648ab4382d2SGreg Kroah-Hartman */ 1649ab4382d2SGreg Kroah-Hartman static void __init 1650ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1651ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1652ab4382d2SGreg Kroah-Hartman { 1653ab4382d2SGreg Kroah-Hartman 1654ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1655ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1656ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1657ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1658ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1659ab4382d2SGreg Kroah-Hartman 1660ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1661ab4382d2SGreg Kroah-Hartman 1662ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1663ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1664ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1665ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1666ab4382d2SGreg Kroah-Hartman else 1667ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1668ab4382d2SGreg Kroah-Hartman } 1669ab4382d2SGreg Kroah-Hartman 1670ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1671ab4382d2SGreg Kroah-Hartman *bits = 8; 1672ab4382d2SGreg Kroah-Hartman else 1673ab4382d2SGreg Kroah-Hartman *bits = 7; 1674ab4382d2SGreg Kroah-Hartman 1675ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1676ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1677ab4382d2SGreg Kroah-Hartman 1678ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1679ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1680ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1681ab4382d2SGreg Kroah-Hartman else 1682ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1683ab4382d2SGreg Kroah-Hartman 16843a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1685ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1686ab4382d2SGreg Kroah-Hartman 1687ab4382d2SGreg Kroah-Hartman { /* 1688ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1689ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1690ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1691ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1692ab4382d2SGreg Kroah-Hartman */ 1693ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1694ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1695ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1696ab4382d2SGreg Kroah-Hartman 1697ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1698ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1699ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1700ab4382d2SGreg Kroah-Hartman } 1701ab4382d2SGreg Kroah-Hartman 1702ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 170350bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1704ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1705ab4382d2SGreg Kroah-Hartman } 1706ab4382d2SGreg Kroah-Hartman } 1707ab4382d2SGreg Kroah-Hartman 1708ab4382d2SGreg Kroah-Hartman static int __init 1709ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1710ab4382d2SGreg Kroah-Hartman { 1711ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1712ab4382d2SGreg Kroah-Hartman int baud = 9600; 1713ab4382d2SGreg Kroah-Hartman int bits = 8; 1714ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1715ab4382d2SGreg Kroah-Hartman int flow = 'n'; 17161cf93e0dSHuang Shijie int retval; 1717ab4382d2SGreg Kroah-Hartman 1718ab4382d2SGreg Kroah-Hartman /* 1719ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1720ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1721ab4382d2SGreg Kroah-Hartman * console support. 1722ab4382d2SGreg Kroah-Hartman */ 1723ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1724ab4382d2SGreg Kroah-Hartman co->index = 0; 1725ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1726ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1727ab4382d2SGreg Kroah-Hartman return -ENODEV; 1728ab4382d2SGreg Kroah-Hartman 17291cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 17301cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 17311cf93e0dSHuang Shijie if (retval) 17321cf93e0dSHuang Shijie goto error_console; 17331cf93e0dSHuang Shijie 1734ab4382d2SGreg Kroah-Hartman if (options) 1735ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1736ab4382d2SGreg Kroah-Hartman else 1737ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1738ab4382d2SGreg Kroah-Hartman 1739ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1740ab4382d2SGreg Kroah-Hartman 17411cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 17421cf93e0dSHuang Shijie 17431cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 17441cf93e0dSHuang Shijie if (retval) { 17451cf93e0dSHuang Shijie clk_unprepare(sport->clk_ipg); 17461cf93e0dSHuang Shijie goto error_console; 17471cf93e0dSHuang Shijie } 17481cf93e0dSHuang Shijie 17491cf93e0dSHuang Shijie retval = clk_prepare(sport->clk_per); 17501cf93e0dSHuang Shijie if (retval) 17511cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 17521cf93e0dSHuang Shijie 17531cf93e0dSHuang Shijie error_console: 17541cf93e0dSHuang Shijie return retval; 1755ab4382d2SGreg Kroah-Hartman } 1756ab4382d2SGreg Kroah-Hartman 1757ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1758ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1759ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1760ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1761ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1762ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1763ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1764ab4382d2SGreg Kroah-Hartman .index = -1, 1765ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1766ab4382d2SGreg Kroah-Hartman }; 1767ab4382d2SGreg Kroah-Hartman 1768ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1769ab4382d2SGreg Kroah-Hartman #else 1770ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1771ab4382d2SGreg Kroah-Hartman #endif 1772ab4382d2SGreg Kroah-Hartman 1773ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1774ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1775ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 1776ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 1777ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 1778ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 1779ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 1780ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 1781ab4382d2SGreg Kroah-Hartman }; 1782ab4382d2SGreg Kroah-Hartman 1783ab4382d2SGreg Kroah-Hartman static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1784ab4382d2SGreg Kroah-Hartman { 1785ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1786db1a9b55SFabio Estevam unsigned int val; 1787db1a9b55SFabio Estevam 1788db1a9b55SFabio Estevam /* enable wakeup from i.MX UART */ 1789db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1790db1a9b55SFabio Estevam val |= UCR3_AWAKEN; 1791db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1792ab4382d2SGreg Kroah-Hartman 1793ab4382d2SGreg Kroah-Hartman uart_suspend_port(&imx_reg, &sport->port); 1794ab4382d2SGreg Kroah-Hartman 1795ab4382d2SGreg Kroah-Hartman return 0; 1796ab4382d2SGreg Kroah-Hartman } 1797ab4382d2SGreg Kroah-Hartman 1798ab4382d2SGreg Kroah-Hartman static int serial_imx_resume(struct platform_device *dev) 1799ab4382d2SGreg Kroah-Hartman { 1800ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1801db1a9b55SFabio Estevam unsigned int val; 1802db1a9b55SFabio Estevam 1803db1a9b55SFabio Estevam /* disable wakeup from i.MX UART */ 1804db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1805db1a9b55SFabio Estevam val &= ~UCR3_AWAKEN; 1806db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1807ab4382d2SGreg Kroah-Hartman 1808ab4382d2SGreg Kroah-Hartman uart_resume_port(&imx_reg, &sport->port); 1809ab4382d2SGreg Kroah-Hartman 1810ab4382d2SGreg Kroah-Hartman return 0; 1811ab4382d2SGreg Kroah-Hartman } 1812ab4382d2SGreg Kroah-Hartman 181322698aa2SShawn Guo #ifdef CONFIG_OF 181420bb8095SUwe Kleine-König /* 181520bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 181620bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 181720bb8095SUwe Kleine-König */ 181822698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 181922698aa2SShawn Guo struct platform_device *pdev) 182022698aa2SShawn Guo { 182122698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 182222698aa2SShawn Guo const struct of_device_id *of_id = 182322698aa2SShawn Guo of_match_device(imx_uart_dt_ids, &pdev->dev); 1824ff05967aSShawn Guo int ret; 182522698aa2SShawn Guo 182622698aa2SShawn Guo if (!np) 182720bb8095SUwe Kleine-König /* no device tree device */ 182820bb8095SUwe Kleine-König return 1; 182922698aa2SShawn Guo 1830ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 1831ff05967aSShawn Guo if (ret < 0) { 1832ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1833a197a191SUwe Kleine-König return ret; 1834ff05967aSShawn Guo } 1835ff05967aSShawn Guo sport->port.line = ret; 183622698aa2SShawn Guo 183722698aa2SShawn Guo if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 183822698aa2SShawn Guo sport->have_rtscts = 1; 183922698aa2SShawn Guo 184022698aa2SShawn Guo if (of_get_property(np, "fsl,irda-mode", NULL)) 184122698aa2SShawn Guo sport->use_irda = 1; 184222698aa2SShawn Guo 184320ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 184420ff2fe6SHuang Shijie sport->dte_mode = 1; 184520ff2fe6SHuang Shijie 184622698aa2SShawn Guo sport->devdata = of_id->data; 184722698aa2SShawn Guo 184822698aa2SShawn Guo return 0; 184922698aa2SShawn Guo } 185022698aa2SShawn Guo #else 185122698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 185222698aa2SShawn Guo struct platform_device *pdev) 185322698aa2SShawn Guo { 185420bb8095SUwe Kleine-König return 1; 185522698aa2SShawn Guo } 185622698aa2SShawn Guo #endif 185722698aa2SShawn Guo 185822698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 185922698aa2SShawn Guo struct platform_device *pdev) 186022698aa2SShawn Guo { 1861574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 186222698aa2SShawn Guo 186322698aa2SShawn Guo sport->port.line = pdev->id; 186422698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 186522698aa2SShawn Guo 186622698aa2SShawn Guo if (!pdata) 186722698aa2SShawn Guo return; 186822698aa2SShawn Guo 186922698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 187022698aa2SShawn Guo sport->have_rtscts = 1; 187122698aa2SShawn Guo 187222698aa2SShawn Guo if (pdata->flags & IMXUART_IRDA) 187322698aa2SShawn Guo sport->use_irda = 1; 187422698aa2SShawn Guo } 187522698aa2SShawn Guo 1876ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 1877ab4382d2SGreg Kroah-Hartman { 1878ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1879ab4382d2SGreg Kroah-Hartman void __iomem *base; 1880ab4382d2SGreg Kroah-Hartman int ret = 0; 1881ab4382d2SGreg Kroah-Hartman struct resource *res; 1882ab4382d2SGreg Kroah-Hartman 188342d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1884ab4382d2SGreg Kroah-Hartman if (!sport) 1885ab4382d2SGreg Kroah-Hartman return -ENOMEM; 1886ab4382d2SGreg Kroah-Hartman 188722698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 188820bb8095SUwe Kleine-König if (ret > 0) 188922698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 189020bb8095SUwe Kleine-König else if (ret < 0) 189142d34191SSachin Kamat return ret; 189222698aa2SShawn Guo 1893ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1894da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 1895da82f997SAlexander Shiyan if (IS_ERR(base)) 1896da82f997SAlexander Shiyan return PTR_ERR(base); 1897ab4382d2SGreg Kroah-Hartman 1898ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 1899ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 1900ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 1901ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 1902ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 1903ab4382d2SGreg Kroah-Hartman sport->port.irq = platform_get_irq(pdev, 0); 1904ab4382d2SGreg Kroah-Hartman sport->rxirq = platform_get_irq(pdev, 0); 1905ab4382d2SGreg Kroah-Hartman sport->txirq = platform_get_irq(pdev, 1); 1906ab4382d2SGreg Kroah-Hartman sport->rtsirq = platform_get_irq(pdev, 2); 1907ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 1908ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 1909ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 1910ab4382d2SGreg Kroah-Hartman init_timer(&sport->timer); 1911ab4382d2SGreg Kroah-Hartman sport->timer.function = imx_timeout; 1912ab4382d2SGreg Kroah-Hartman sport->timer.data = (unsigned long)sport; 1913ab4382d2SGreg Kroah-Hartman 19143a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 19153a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 19163a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 1917833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 191842d34191SSachin Kamat return ret; 1919ab4382d2SGreg Kroah-Hartman } 1920ab4382d2SGreg Kroah-Hartman 19213a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 19223a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 19233a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 1924833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 192542d34191SSachin Kamat return ret; 19263a9465faSSascha Hauer } 19273a9465faSSascha Hauer 19283a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 1929ab4382d2SGreg Kroah-Hartman 1930c0d1c6b0SFabio Estevam /* 1931c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 1932c0d1c6b0SFabio Estevam * chips only have one interrupt. 1933c0d1c6b0SFabio Estevam */ 1934c0d1c6b0SFabio Estevam if (sport->txirq > 0) { 1935c0d1c6b0SFabio Estevam ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0, 1936c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 1937c0d1c6b0SFabio Estevam if (ret) 1938c0d1c6b0SFabio Estevam return ret; 1939c0d1c6b0SFabio Estevam 1940c0d1c6b0SFabio Estevam ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0, 1941c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 1942c0d1c6b0SFabio Estevam if (ret) 1943c0d1c6b0SFabio Estevam return ret; 1944c0d1c6b0SFabio Estevam 1945c0d1c6b0SFabio Estevam /* do not use RTS IRQ on IrDA */ 1946c0d1c6b0SFabio Estevam if (!USE_IRDA(sport)) { 1947c0d1c6b0SFabio Estevam ret = devm_request_irq(&pdev->dev, sport->rtsirq, 1948c0d1c6b0SFabio Estevam imx_rtsint, 0, 1949c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 1950c0d1c6b0SFabio Estevam if (ret) 1951c0d1c6b0SFabio Estevam return ret; 1952c0d1c6b0SFabio Estevam } 1953c0d1c6b0SFabio Estevam } else { 1954c0d1c6b0SFabio Estevam ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0, 1955c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 1956c0d1c6b0SFabio Estevam if (ret) 1957c0d1c6b0SFabio Estevam return ret; 1958c0d1c6b0SFabio Estevam } 1959c0d1c6b0SFabio Estevam 196022698aa2SShawn Guo imx_ports[sport->port.line] = sport; 1961ab4382d2SGreg Kroah-Hartman 19620a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 1963ab4382d2SGreg Kroah-Hartman 196445af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 1965ab4382d2SGreg Kroah-Hartman } 1966ab4382d2SGreg Kroah-Hartman 1967ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 1968ab4382d2SGreg Kroah-Hartman { 1969ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 1970ab4382d2SGreg Kroah-Hartman 197145af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 1972ab4382d2SGreg Kroah-Hartman } 1973ab4382d2SGreg Kroah-Hartman 1974ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 1975ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 1976ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 1977ab4382d2SGreg Kroah-Hartman 1978ab4382d2SGreg Kroah-Hartman .suspend = serial_imx_suspend, 1979ab4382d2SGreg Kroah-Hartman .resume = serial_imx_resume, 1980fe6b540aSShawn Guo .id_table = imx_uart_devtype, 1981ab4382d2SGreg Kroah-Hartman .driver = { 1982ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 198322698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 1984ab4382d2SGreg Kroah-Hartman }, 1985ab4382d2SGreg Kroah-Hartman }; 1986ab4382d2SGreg Kroah-Hartman 1987ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 1988ab4382d2SGreg Kroah-Hartman { 1989f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 1990ab4382d2SGreg Kroah-Hartman 1991ab4382d2SGreg Kroah-Hartman if (ret) 1992ab4382d2SGreg Kroah-Hartman return ret; 1993ab4382d2SGreg Kroah-Hartman 1994ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 1995ab4382d2SGreg Kroah-Hartman if (ret != 0) 1996ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 1997ab4382d2SGreg Kroah-Hartman 1998f227824eSUwe Kleine-König return ret; 1999ab4382d2SGreg Kroah-Hartman } 2000ab4382d2SGreg Kroah-Hartman 2001ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2002ab4382d2SGreg Kroah-Hartman { 2003ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2004ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2005ab4382d2SGreg Kroah-Hartman } 2006ab4382d2SGreg Kroah-Hartman 2007ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2008ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2009ab4382d2SGreg Kroah-Hartman 2010ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2011ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2012ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2013ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2014