1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 12ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 13ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 14ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 15ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 23bd78ecd6SAhmad Fatoum #include <linux/ktime.h> 24fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2722698aa2SShawn Guo #include <linux/of.h> 2822698aa2SShawn Guo #include <linux/of_device.h> 29e32a9f8fSSachin Kamat #include <linux/io.h> 30b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 31ab4382d2SGreg Kroah-Hartman 32ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 33c6547c2eSSascha Hauer #include <linux/dma/imx-dma.h> 34ab4382d2SGreg Kroah-Hartman 3558362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3658362d5bSUwe Kleine-König 37ab4382d2SGreg Kroah-Hartman /* Register definitions */ 38ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 39ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 40ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 41ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 42ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 43ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 44ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 45ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 46ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 47ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 48ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 49ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 50ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 51ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 52fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 53fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 54fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 55ab4382d2SGreg Kroah-Hartman 56ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 5755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 58ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 59ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 60ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 61ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 62ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 63ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 66ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 67ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 68ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 69b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 71302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 72ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 76302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 77fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 78b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 81ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 83ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 95ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 96ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 97ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 101b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10527e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 106fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 110ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 111ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 115b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1227be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 123ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 125ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 126ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 127ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 128ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 129ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 130ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 131ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13386a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13427e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 136ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 137ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 138ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 139ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 140ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14290ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14390ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14690ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 149ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 150ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 151ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 152ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 153ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 154ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 155ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 156ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 157ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 158ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 159ab4382d2SGreg Kroah-Hartman 160ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 161ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 162ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 163ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 164ab4382d2SGreg Kroah-Hartman 165ab4382d2SGreg Kroah-Hartman /* 166ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 167ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 168ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 169ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 170ab4382d2SGreg Kroah-Hartman */ 171ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 172ab4382d2SGreg Kroah-Hartman 173ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 174ab4382d2SGreg Kroah-Hartman 175ab4382d2SGreg Kroah-Hartman #define UART_NR 8 176ab4382d2SGreg Kroah-Hartman 177f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 178fe6b540aSShawn Guo enum imx_uart_type { 179fe6b540aSShawn Guo IMX1_UART, 180fe6b540aSShawn Guo IMX21_UART, 1811c06bde6SMartyn Welch IMX53_UART, 182a496e628SHuang Shijie IMX6Q_UART, 183fe6b540aSShawn Guo }; 184fe6b540aSShawn Guo 185fe6b540aSShawn Guo /* device type dependent stuff */ 186fe6b540aSShawn Guo struct imx_uart_data { 187fe6b540aSShawn Guo unsigned uts_reg; 188fe6b540aSShawn Guo enum imx_uart_type devtype; 189fe6b540aSShawn Guo }; 190fe6b540aSShawn Guo 191cb1a6092SUwe Kleine-König enum imx_tx_state { 192cb1a6092SUwe Kleine-König OFF, 193cb1a6092SUwe Kleine-König WAIT_AFTER_RTS, 194cb1a6092SUwe Kleine-König SEND, 195cb1a6092SUwe Kleine-König WAIT_AFTER_SEND, 196cb1a6092SUwe Kleine-König }; 197cb1a6092SUwe Kleine-König 198ab4382d2SGreg Kroah-Hartman struct imx_port { 199ab4382d2SGreg Kroah-Hartman struct uart_port port; 200ab4382d2SGreg Kroah-Hartman struct timer_list timer; 201ab4382d2SGreg Kroah-Hartman unsigned int old_status; 202ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2037b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20420ff2fe6SHuang Shijie unsigned int dte_mode:1; 2055a08a487SGeorge Hilliard unsigned int inverted_tx:1; 2065a08a487SGeorge Hilliard unsigned int inverted_rx:1; 2073a9465faSSascha Hauer struct clk *clk_ipg; 2083a9465faSSascha Hauer struct clk *clk_per; 2097d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 210b4cdc8f6SHuang Shijie 21158362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21258362d5bSUwe Kleine-König 2133a0ab62fSUwe Kleine-König /* shadow registers */ 2143a0ab62fSUwe Kleine-König unsigned int ucr1; 2153a0ab62fSUwe Kleine-König unsigned int ucr2; 2163a0ab62fSUwe Kleine-König unsigned int ucr3; 2173a0ab62fSUwe Kleine-König unsigned int ucr4; 2183a0ab62fSUwe Kleine-König unsigned int ufcr; 2193a0ab62fSUwe Kleine-König 220b4cdc8f6SHuang Shijie /* DMA fields */ 221b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 224b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 225b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 226b4cdc8f6SHuang Shijie void *rx_buf; 2279d297239SNandor Han struct circ_buf rx_ring; 228db0a196bSFabien Lahoudere unsigned int rx_buf_size; 229db0a196bSFabien Lahoudere unsigned int rx_period_length; 2309d297239SNandor Han unsigned int rx_periods; 2319d297239SNandor Han dma_cookie_t rx_cookie; 2327cb92fd2SHuang Shijie unsigned int tx_bytes; 233b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 23490bb6bd3SShenwei Wang unsigned int saved_reg[10]; 235c868cbb7SEduardo Valentin bool context_saved; 236cb1a6092SUwe Kleine-König 237cb1a6092SUwe Kleine-König enum imx_tx_state tx_state; 238bd78ecd6SAhmad Fatoum struct hrtimer trigger_start_tx; 239bd78ecd6SAhmad Fatoum struct hrtimer trigger_stop_tx; 240ab4382d2SGreg Kroah-Hartman }; 241ab4382d2SGreg Kroah-Hartman 2420ad5a814SDirk Behme struct imx_port_ucrs { 2430ad5a814SDirk Behme unsigned int ucr1; 2440ad5a814SDirk Behme unsigned int ucr2; 2450ad5a814SDirk Behme unsigned int ucr3; 2460ad5a814SDirk Behme }; 2470ad5a814SDirk Behme 248fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 249fe6b540aSShawn Guo [IMX1_UART] = { 250fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 251fe6b540aSShawn Guo .devtype = IMX1_UART, 252fe6b540aSShawn Guo }, 253fe6b540aSShawn Guo [IMX21_UART] = { 254fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 255fe6b540aSShawn Guo .devtype = IMX21_UART, 256fe6b540aSShawn Guo }, 2571c06bde6SMartyn Welch [IMX53_UART] = { 2581c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2591c06bde6SMartyn Welch .devtype = IMX53_UART, 2601c06bde6SMartyn Welch }, 261a496e628SHuang Shijie [IMX6Q_UART] = { 262a496e628SHuang Shijie .uts_reg = IMX21_UTS, 263a496e628SHuang Shijie .devtype = IMX6Q_UART, 264a496e628SHuang Shijie }, 265fe6b540aSShawn Guo }; 266fe6b540aSShawn Guo 267ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 268a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2691c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27022698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27122698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27222698aa2SShawn Guo { /* sentinel */ } 27322698aa2SShawn Guo }; 27422698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27522698aa2SShawn Guo 27627c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 27727c84426SUwe Kleine-König { 2783a0ab62fSUwe Kleine-König switch (offset) { 2793a0ab62fSUwe Kleine-König case UCR1: 2803a0ab62fSUwe Kleine-König sport->ucr1 = val; 2813a0ab62fSUwe Kleine-König break; 2823a0ab62fSUwe Kleine-König case UCR2: 2833a0ab62fSUwe Kleine-König sport->ucr2 = val; 2843a0ab62fSUwe Kleine-König break; 2853a0ab62fSUwe Kleine-König case UCR3: 2863a0ab62fSUwe Kleine-König sport->ucr3 = val; 2873a0ab62fSUwe Kleine-König break; 2883a0ab62fSUwe Kleine-König case UCR4: 2893a0ab62fSUwe Kleine-König sport->ucr4 = val; 2903a0ab62fSUwe Kleine-König break; 2913a0ab62fSUwe Kleine-König case UFCR: 2923a0ab62fSUwe Kleine-König sport->ufcr = val; 2933a0ab62fSUwe Kleine-König break; 2943a0ab62fSUwe Kleine-König default: 2953a0ab62fSUwe Kleine-König break; 2963a0ab62fSUwe Kleine-König } 29727c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 29827c84426SUwe Kleine-König } 29927c84426SUwe Kleine-König 30027c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30127c84426SUwe Kleine-König { 3023a0ab62fSUwe Kleine-König switch (offset) { 3033a0ab62fSUwe Kleine-König case UCR1: 3043a0ab62fSUwe Kleine-König return sport->ucr1; 3053a0ab62fSUwe Kleine-König break; 3063a0ab62fSUwe Kleine-König case UCR2: 3073a0ab62fSUwe Kleine-König /* 3083a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3093a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 310728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 311728e74a4SUwe Kleine-König * conditionally. 3123a0ab62fSUwe Kleine-König */ 3130aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3143a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3153a0ab62fSUwe Kleine-König return sport->ucr2; 3163a0ab62fSUwe Kleine-König break; 3173a0ab62fSUwe Kleine-König case UCR3: 3183a0ab62fSUwe Kleine-König return sport->ucr3; 3193a0ab62fSUwe Kleine-König break; 3203a0ab62fSUwe Kleine-König case UCR4: 3213a0ab62fSUwe Kleine-König return sport->ucr4; 3223a0ab62fSUwe Kleine-König break; 3233a0ab62fSUwe Kleine-König case UFCR: 3243a0ab62fSUwe Kleine-König return sport->ufcr; 3253a0ab62fSUwe Kleine-König break; 3263a0ab62fSUwe Kleine-König default: 32727c84426SUwe Kleine-König return readl(sport->port.membase + offset); 32827c84426SUwe Kleine-König } 3293a0ab62fSUwe Kleine-König } 33027c84426SUwe Kleine-König 3319d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 332fe6b540aSShawn Guo { 333fe6b540aSShawn Guo return sport->devdata->uts_reg; 334fe6b540aSShawn Guo } 335fe6b540aSShawn Guo 3369d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 337fe6b540aSShawn Guo { 338fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 339fe6b540aSShawn Guo } 340fe6b540aSShawn Guo 3419d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 342fe6b540aSShawn Guo { 343fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 344fe6b540aSShawn Guo } 345fe6b540aSShawn Guo 3469d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3471c06bde6SMartyn Welch { 3481c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3491c06bde6SMartyn Welch } 3501c06bde6SMartyn Welch 3519d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 352a496e628SHuang Shijie { 353a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 354a496e628SHuang Shijie } 355ab4382d2SGreg Kroah-Hartman /* 35644a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 35744a75411Sfabio.estevam@freescale.com */ 3580db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 3599d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 36044a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36144a75411Sfabio.estevam@freescale.com { 36244a75411Sfabio.estevam@freescale.com /* save control registers */ 36327c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 36427c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 36527c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 36644a75411Sfabio.estevam@freescale.com } 36744a75411Sfabio.estevam@freescale.com 3689d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 36944a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37044a75411Sfabio.estevam@freescale.com { 37144a75411Sfabio.estevam@freescale.com /* restore control registers */ 37227c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 37327c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 37427c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 37544a75411Sfabio.estevam@freescale.com } 376e8bfa760SFabio Estevam #endif 37744a75411Sfabio.estevam@freescale.com 3784e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3799d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 38058362d5bSUwe Kleine-König { 381bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38258362d5bSUwe Kleine-König 3837c7f9bc9SLukas Wunner mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); 38458362d5bSUwe Kleine-König } 38558362d5bSUwe Kleine-König 3864e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3879d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 38858362d5bSUwe Kleine-König { 389bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 390bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39158362d5bSUwe Kleine-König 3927c7f9bc9SLukas Wunner mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); 39358362d5bSUwe Kleine-König } 39458362d5bSUwe Kleine-König 395bd78ecd6SAhmad Fatoum static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 396bd78ecd6SAhmad Fatoum { 397f751ae1cSJiri Slaby hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 398bd78ecd6SAhmad Fatoum } 399bd78ecd6SAhmad Fatoum 4006aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 401*d45fb2e4SSergey Organov static void imx_uart_soft_reset(struct imx_port *sport) 402*d45fb2e4SSergey Organov { 403*d45fb2e4SSergey Organov int i = 10; 404*d45fb2e4SSergey Organov u32 ucr2, ubir, ubmr, uts; 405*d45fb2e4SSergey Organov 406*d45fb2e4SSergey Organov /* 407*d45fb2e4SSergey Organov * According to the Reference Manual description of the UART SRST bit: 408*d45fb2e4SSergey Organov * 409*d45fb2e4SSergey Organov * "Reset the transmit and receive state machines, 410*d45fb2e4SSergey Organov * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 411*d45fb2e4SSergey Organov * and UTS[6-3]". 412*d45fb2e4SSergey Organov * 413*d45fb2e4SSergey Organov * We don't need to restore the old values from USR1, USR2, URXD and 414*d45fb2e4SSergey Organov * UTXD. UBRC is read only, so only save/restore the other three 415*d45fb2e4SSergey Organov * registers. 416*d45fb2e4SSergey Organov */ 417*d45fb2e4SSergey Organov ubir = imx_uart_readl(sport, UBIR); 418*d45fb2e4SSergey Organov ubmr = imx_uart_readl(sport, UBMR); 419*d45fb2e4SSergey Organov uts = imx_uart_readl(sport, IMX21_UTS); 420*d45fb2e4SSergey Organov 421*d45fb2e4SSergey Organov ucr2 = imx_uart_readl(sport, UCR2); 422*d45fb2e4SSergey Organov imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2); 423*d45fb2e4SSergey Organov 424*d45fb2e4SSergey Organov while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 425*d45fb2e4SSergey Organov udelay(1); 426*d45fb2e4SSergey Organov 427*d45fb2e4SSergey Organov /* Restore the registers */ 428*d45fb2e4SSergey Organov imx_uart_writel(sport, ubir, UBIR); 429*d45fb2e4SSergey Organov imx_uart_writel(sport, ubmr, UBMR); 430*d45fb2e4SSergey Organov imx_uart_writel(sport, uts, IMX21_UTS); 431*d45fb2e4SSergey Organov } 432*d45fb2e4SSergey Organov 433*d45fb2e4SSergey Organov /* called with port.lock taken and irqs off */ 4349d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 43576821e22SUwe Kleine-König { 43676821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 43776821e22SUwe Kleine-König unsigned int ucr1, ucr2; 43876821e22SUwe Kleine-König 43976821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 44076821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 44176821e22SUwe Kleine-König 44276821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 44376821e22SUwe Kleine-König 44476821e22SUwe Kleine-König if (sport->dma_is_enabled) { 44576821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 44676821e22SUwe Kleine-König } else { 44776821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 44881ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 44976821e22SUwe Kleine-König } 45076821e22SUwe Kleine-König 45176821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 45276821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 45376821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 45476821e22SUwe Kleine-König } 45576821e22SUwe Kleine-König 45676821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4579d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 458ab4382d2SGreg Kroah-Hartman { 459ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 460cb1a6092SUwe Kleine-König u32 ucr1, ucr4, usr2; 461cb1a6092SUwe Kleine-König 462cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) 463cb1a6092SUwe Kleine-König return; 464ab4382d2SGreg Kroah-Hartman 4659ce4f8f3SGreg Kroah-Hartman /* 4669ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4679ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4689ce4f8f3SGreg Kroah-Hartman */ 469686351f3SUwe Kleine-König if (sport->dma_is_txing) 4709ce4f8f3SGreg Kroah-Hartman return; 471b4cdc8f6SHuang Shijie 4724444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 473c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 47417b8f2a3SUwe Kleine-König 475cb1a6092SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 476cb1a6092SUwe Kleine-König if (!(usr2 & USR2_TXDC)) { 477cb1a6092SUwe Kleine-König /* The shifter is still busy, so retry once TC triggers */ 478cb1a6092SUwe Kleine-König return; 479cb1a6092SUwe Kleine-König } 480cb1a6092SUwe Kleine-König 481cb1a6092SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 482cb1a6092SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 483cb1a6092SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 484cb1a6092SUwe Kleine-König 485cb1a6092SUwe Kleine-König /* in rs485 mode disable transmitter */ 486cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 487cb1a6092SUwe Kleine-König if (sport->tx_state == SEND) { 488cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_SEND; 489582e9a24SHarald Seiler 490582e9a24SHarald Seiler if (port->rs485.delay_rts_after_send > 0) { 491bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_stop_tx, 492bd78ecd6SAhmad Fatoum port->rs485.delay_rts_after_send); 493bd78ecd6SAhmad Fatoum return; 494cb1a6092SUwe Kleine-König } 495cb1a6092SUwe Kleine-König 496582e9a24SHarald Seiler /* continue without any delay */ 497582e9a24SHarald Seiler } 498582e9a24SHarald Seiler 499cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS || 500bd78ecd6SAhmad Fatoum sport->tx_state == WAIT_AFTER_SEND) { 501cb1a6092SUwe Kleine-König u32 ucr2; 502cb1a6092SUwe Kleine-König 503bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_start_tx); 504cb1a6092SUwe Kleine-König 505cb1a6092SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 50617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 5079d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 5081a613626SFabio Estevam else 5099d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 5104444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 51117b8f2a3SUwe Kleine-König 512ca530cfaSChristoph Niedermaier if (!port->rs485_rx_during_tx_gpio) 5139d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 51476821e22SUwe Kleine-König 515cb1a6092SUwe Kleine-König sport->tx_state = OFF; 516cb1a6092SUwe Kleine-König } 517cb1a6092SUwe Kleine-König } else { 518cb1a6092SUwe Kleine-König sport->tx_state = OFF; 51917b8f2a3SUwe Kleine-König } 520ab4382d2SGreg Kroah-Hartman } 521ab4382d2SGreg Kroah-Hartman 5226aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5239d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 524ab4382d2SGreg Kroah-Hartman { 525ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 52679d0224fSMarek Vasut u32 ucr1, ucr2, ucr4, uts; 527ab4382d2SGreg Kroah-Hartman 5284444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 52976821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 530028e0838SFugang Duan ucr4 = imx_uart_readl(sport, UCR4); 53176821e22SUwe Kleine-König 53276821e22SUwe Kleine-König if (sport->dma_is_enabled) { 53376821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 53476821e22SUwe Kleine-König } else { 53576821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 53681ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 537028e0838SFugang Duan ucr4 &= ~UCR4_OREN; 53876821e22SUwe Kleine-König } 53976821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 540028e0838SFugang Duan imx_uart_writel(sport, ucr4, UCR4); 54176821e22SUwe Kleine-König 54279d0224fSMarek Vasut /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 54379d0224fSMarek Vasut if (port->rs485.flags & SER_RS485_ENABLED && 54479d0224fSMarek Vasut port->rs485.flags & SER_RS485_RTS_ON_SEND && 54579d0224fSMarek Vasut sport->have_rtscts && !sport->have_rtsgpio) { 54679d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 54779d0224fSMarek Vasut uts |= UTS_LOOP; 54879d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 54979d0224fSMarek Vasut ucr2 |= UCR2_RXEN; 55079d0224fSMarek Vasut } else { 55176821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 55279d0224fSMarek Vasut } 55379d0224fSMarek Vasut 55476821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 555ab4382d2SGreg Kroah-Hartman } 556ab4382d2SGreg Kroah-Hartman 5576aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5589d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 559ab4382d2SGreg Kroah-Hartman { 560ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 561ab4382d2SGreg Kroah-Hartman 562ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 56358362d5bSUwe Kleine-König 56458362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 565ab4382d2SGreg Kroah-Hartman } 566ab4382d2SGreg Kroah-Hartman 5679d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 5686aed2a88SUwe Kleine-König 5696aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5709d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 571ab4382d2SGreg Kroah-Hartman { 572ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 573ab4382d2SGreg Kroah-Hartman 5745e42e9a3SPeter Hurley if (sport->port.x_char) { 5755e42e9a3SPeter Hurley /* Send next char */ 57627c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5777e2fb5aaSJiada Wang sport->port.icount.tx++; 5787e2fb5aaSJiada Wang sport->port.x_char = 0; 5795e42e9a3SPeter Hurley return; 5805e42e9a3SPeter Hurley } 5815e42e9a3SPeter Hurley 5825e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5839d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5845e42e9a3SPeter Hurley return; 5855e42e9a3SPeter Hurley } 5865e42e9a3SPeter Hurley 58791a1a909SJiada Wang if (sport->dma_is_enabled) { 5884444dcf1SUwe Kleine-König u32 ucr1; 58991a1a909SJiada Wang /* 59091a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 59191a1a909SJiada Wang * and the TX IRQ is disabled. 59291a1a909SJiada Wang **/ 5934444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 594c514a6f8SSergey Organov ucr1 &= ~UCR1_TRDYEN; 59591a1a909SJiada Wang if (sport->dma_is_txing) { 5964444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5974444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 59891a1a909SJiada Wang } else { 5994444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 6009d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 60191a1a909SJiada Wang } 60291a1a909SJiada Wang 6035aabd3b0SIan Jamison return; 6040c549223SUwe Kleine-König } 6055aabd3b0SIan Jamison 6065aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 6079d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 608ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 609ab4382d2SGreg Kroah-Hartman * out the port here */ 61027c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 61126e8f1d9SIlpo Järvinen uart_xmit_advance(&sport->port, 1); 612ab4382d2SGreg Kroah-Hartman } 613ab4382d2SGreg Kroah-Hartman 614ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 615ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 616ab4382d2SGreg Kroah-Hartman 617ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 6189d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 619ab4382d2SGreg Kroah-Hartman } 620ab4382d2SGreg Kroah-Hartman 6219d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 622b4cdc8f6SHuang Shijie { 623b4cdc8f6SHuang Shijie struct imx_port *sport = data; 624b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 625b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 626b4cdc8f6SHuang Shijie unsigned long flags; 6274444dcf1SUwe Kleine-König u32 ucr1; 628b4cdc8f6SHuang Shijie 62942f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 63042f752b3SDirk Behme 631b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 632b4cdc8f6SHuang Shijie 6334444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6344444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 6354444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 636a2c718ceSDirk Behme 63726e8f1d9SIlpo Järvinen uart_xmit_advance(&sport->port, sport->tx_bytes); 63842f752b3SDirk Behme 63942f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 64042f752b3SDirk Behme 641b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 642b4cdc8f6SHuang Shijie 643d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 644b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 6459ce4f8f3SGreg Kroah-Hartman 6460bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 6479d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 64818665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 64918665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 65018665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 65118665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 65218665414SUwe Kleine-König } 65364432a85SUwe Kleine-König 6540bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 655b4cdc8f6SHuang Shijie } 656b4cdc8f6SHuang Shijie 6576aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6589d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 659b4cdc8f6SHuang Shijie { 660b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 661b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 662b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 663b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 664b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 66518665414SUwe Kleine-König u32 ucr1, ucr4; 666b4cdc8f6SHuang Shijie int ret; 667b4cdc8f6SHuang Shijie 66842f752b3SDirk Behme if (sport->dma_is_txing) 669b4cdc8f6SHuang Shijie return; 670b4cdc8f6SHuang Shijie 67118665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 67218665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 67318665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 67418665414SUwe Kleine-König 675b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 676b4cdc8f6SHuang Shijie 677f7670783SFugang Duan if (xmit->tail < xmit->head || xmit->head == 0) { 6787942f857SDirk Behme sport->dma_tx_nents = 1; 6797942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6807942f857SDirk Behme } else { 681b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 682b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 683b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 684b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 685b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 686b4cdc8f6SHuang Shijie } 687b4cdc8f6SHuang Shijie 688b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 689b4cdc8f6SHuang Shijie if (ret == 0) { 690b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 691b4cdc8f6SHuang Shijie return; 692b4cdc8f6SHuang Shijie } 693596fd8dfSPeng Fan desc = dmaengine_prep_slave_sg(chan, sgl, ret, 694b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 695b4cdc8f6SHuang Shijie if (!desc) { 69624649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 69724649821SDirk Behme DMA_TO_DEVICE); 698b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 699b4cdc8f6SHuang Shijie return; 700b4cdc8f6SHuang Shijie } 7019d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 702b4cdc8f6SHuang Shijie desc->callback_param = sport; 703b4cdc8f6SHuang Shijie 704b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 705b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 706a2c718ceSDirk Behme 7074444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 7084444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 7094444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 710a2c718ceSDirk Behme 711b4cdc8f6SHuang Shijie /* fire it */ 712b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 713b4cdc8f6SHuang Shijie dmaengine_submit(desc); 714b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 715b4cdc8f6SHuang Shijie return; 716b4cdc8f6SHuang Shijie } 717b4cdc8f6SHuang Shijie 7186aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 7199d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 720ab4382d2SGreg Kroah-Hartman { 721ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 7224444dcf1SUwe Kleine-König u32 ucr1; 723ab4382d2SGreg Kroah-Hartman 72448669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 72548669b69SUwe Kleine-König return; 72648669b69SUwe Kleine-König 727cb1a6092SUwe Kleine-König /* 728cb1a6092SUwe Kleine-König * We cannot simply do nothing here if sport->tx_state == SEND already 729cb1a6092SUwe Kleine-König * because UCR1_TXMPTYEN might already have been cleared in 730cb1a6092SUwe Kleine-König * imx_uart_stop_tx(), but tx_state is still SEND. 731cb1a6092SUwe Kleine-König */ 7324444dcf1SUwe Kleine-König 733cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 734cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) { 735cb1a6092SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2); 73617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 7379d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 7381a613626SFabio Estevam else 7399d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 7404444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 74117b8f2a3SUwe Kleine-König 742ca530cfaSChristoph Niedermaier if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && 743ca530cfaSChristoph Niedermaier !port->rs485_rx_during_tx_gpio) 7449d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 74576821e22SUwe Kleine-König 746cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_RTS; 747582e9a24SHarald Seiler 748582e9a24SHarald Seiler if (port->rs485.delay_rts_before_send > 0) { 749bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_start_tx, 750bd78ecd6SAhmad Fatoum port->rs485.delay_rts_before_send); 751bd78ecd6SAhmad Fatoum return; 752cb1a6092SUwe Kleine-König } 753cb1a6092SUwe Kleine-König 754582e9a24SHarald Seiler /* continue without any delay */ 755582e9a24SHarald Seiler } 756582e9a24SHarald Seiler 757bd78ecd6SAhmad Fatoum if (sport->tx_state == WAIT_AFTER_SEND 758bd78ecd6SAhmad Fatoum || sport->tx_state == WAIT_AFTER_RTS) { 759cb1a6092SUwe Kleine-König 760bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_stop_tx); 761bd78ecd6SAhmad Fatoum 76218665414SUwe Kleine-König /* 763cb1a6092SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA 764cb1a6092SUwe Kleine-König * is off. In the DMA case this is done in the 765cb1a6092SUwe Kleine-König * tx-callback. 76618665414SUwe Kleine-König */ 76718665414SUwe Kleine-König if (!sport->dma_is_enabled) { 76818665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 7694444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 7704444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 77117b8f2a3SUwe Kleine-König } 772cb1a6092SUwe Kleine-König 773cb1a6092SUwe Kleine-König sport->tx_state = SEND; 774cb1a6092SUwe Kleine-König } 775cb1a6092SUwe Kleine-König } else { 776cb1a6092SUwe Kleine-König sport->tx_state = SEND; 77718665414SUwe Kleine-König } 77817b8f2a3SUwe Kleine-König 779b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 7804444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 781c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 782b4cdc8f6SHuang Shijie } 783ab4382d2SGreg Kroah-Hartman 784b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 78591a1a909SJiada Wang if (sport->port.x_char) { 78691a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 78791a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 7884444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 7894444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 790c514a6f8SSergey Organov ucr1 |= UCR1_TRDYEN; 7914444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 79291a1a909SJiada Wang return; 79391a1a909SJiada Wang } 79491a1a909SJiada Wang 7955e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 7965e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7979d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 798b4cdc8f6SHuang Shijie return; 799b4cdc8f6SHuang Shijie } 800ab4382d2SGreg Kroah-Hartman } 801ab4382d2SGreg Kroah-Hartman 802101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 803ab4382d2SGreg Kroah-Hartman { 804ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 8054444dcf1SUwe Kleine-König u32 usr1; 806ab4382d2SGreg Kroah-Hartman 80727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 8084444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 809968d6457SIlpo Järvinen uart_handle_cts_change(&sport->port, usr1); 810ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 811ab4382d2SGreg Kroah-Hartman 812ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 813ab4382d2SGreg Kroah-Hartman } 814ab4382d2SGreg Kroah-Hartman 815101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 816101aa46bSUwe Kleine-König { 817101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 818101aa46bSUwe Kleine-König irqreturn_t ret; 819101aa46bSUwe Kleine-König 820101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 821101aa46bSUwe Kleine-König 822101aa46bSUwe Kleine-König ret = __imx_uart_rtsint(irq, dev_id); 823101aa46bSUwe Kleine-König 824101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 825101aa46bSUwe Kleine-König 826101aa46bSUwe Kleine-König return ret; 827101aa46bSUwe Kleine-König } 828101aa46bSUwe Kleine-König 8299d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 830ab4382d2SGreg Kroah-Hartman { 831ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 832ab4382d2SGreg Kroah-Hartman 833c974991dSjun qian spin_lock(&sport->port.lock); 8349d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 835c974991dSjun qian spin_unlock(&sport->port.lock); 836ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 837ab4382d2SGreg Kroah-Hartman } 838ab4382d2SGreg Kroah-Hartman 839101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 840ab4382d2SGreg Kroah-Hartman { 841ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 842ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 84392a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 844ab4382d2SGreg Kroah-Hartman 84527c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 8464444dcf1SUwe Kleine-König u32 usr2; 8474444dcf1SUwe Kleine-König 848ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 849ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 850ab4382d2SGreg Kroah-Hartman 85127c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 852ab4382d2SGreg Kroah-Hartman 8534444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 8544444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 85527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 856ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 857ab4382d2SGreg Kroah-Hartman continue; 858ab4382d2SGreg Kroah-Hartman } 859ab4382d2SGreg Kroah-Hartman 860ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 861ab4382d2SGreg Kroah-Hartman continue; 862ab4382d2SGreg Kroah-Hartman 863019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 864019dc9eaSHui Wang if (rx & URXD_BRK) 865019dc9eaSHui Wang sport->port.icount.brk++; 866019dc9eaSHui Wang else if (rx & URXD_PRERR) 867ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 868ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 869ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 870ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 871ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 872ab4382d2SGreg Kroah-Hartman 873ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 874ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 875ab4382d2SGreg Kroah-Hartman goto out; 876ab4382d2SGreg Kroah-Hartman continue; 877ab4382d2SGreg Kroah-Hartman } 878ab4382d2SGreg Kroah-Hartman 8798d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 880ab4382d2SGreg Kroah-Hartman 881019dc9eaSHui Wang if (rx & URXD_BRK) 882019dc9eaSHui Wang flg = TTY_BREAK; 883019dc9eaSHui Wang else if (rx & URXD_PRERR) 884ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 885ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 886ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 887ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 888ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 889ab4382d2SGreg Kroah-Hartman 890ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 891ab4382d2SGreg Kroah-Hartman } 892ab4382d2SGreg Kroah-Hartman 89355d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 89455d8693aSJiada Wang goto out; 89555d8693aSJiada Wang 8969b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 8979b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 898ab4382d2SGreg Kroah-Hartman } 899ab4382d2SGreg Kroah-Hartman 900ab4382d2SGreg Kroah-Hartman out: 9012e124b4aSJiri Slaby tty_flip_buffer_push(port); 902101aa46bSUwe Kleine-König 903ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 904ab4382d2SGreg Kroah-Hartman } 905ab4382d2SGreg Kroah-Hartman 906101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 907101aa46bSUwe Kleine-König { 908101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 909101aa46bSUwe Kleine-König irqreturn_t ret; 910101aa46bSUwe Kleine-König 911101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 912101aa46bSUwe Kleine-König 913101aa46bSUwe Kleine-König ret = __imx_uart_rxint(irq, dev_id); 914101aa46bSUwe Kleine-König 915101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 916101aa46bSUwe Kleine-König 917101aa46bSUwe Kleine-König return ret; 918101aa46bSUwe Kleine-König } 919101aa46bSUwe Kleine-König 9209d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 921b4cdc8f6SHuang Shijie 92266f95884SUwe Kleine-König /* 92366f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 92466f95884SUwe Kleine-König */ 9259d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 92666f95884SUwe Kleine-König { 92766f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 92827c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 92927c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 93066f95884SUwe Kleine-König 93166f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 93266f95884SUwe Kleine-König tmp |= TIOCM_CTS; 93366f95884SUwe Kleine-König 93466f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 9354b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 93666f95884SUwe Kleine-König tmp |= TIOCM_CAR; 93766f95884SUwe Kleine-König 93866f95884SUwe Kleine-König if (sport->dte_mode) 93927c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 94066f95884SUwe Kleine-König tmp |= TIOCM_RI; 94166f95884SUwe Kleine-König 94266f95884SUwe Kleine-König return tmp; 94366f95884SUwe Kleine-König } 94466f95884SUwe Kleine-König 94566f95884SUwe Kleine-König /* 94666f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 94766f95884SUwe Kleine-König */ 9489d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 94966f95884SUwe Kleine-König { 95066f95884SUwe Kleine-König unsigned int status, changed; 95166f95884SUwe Kleine-König 9529d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 95366f95884SUwe Kleine-König changed = status ^ sport->old_status; 95466f95884SUwe Kleine-König 95566f95884SUwe Kleine-König if (changed == 0) 95666f95884SUwe Kleine-König return; 95766f95884SUwe Kleine-König 95866f95884SUwe Kleine-König sport->old_status = status; 95966f95884SUwe Kleine-König 96066f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 96166f95884SUwe Kleine-König sport->port.icount.rng++; 96266f95884SUwe Kleine-König if (changed & TIOCM_DSR) 96366f95884SUwe Kleine-König sport->port.icount.dsr++; 96466f95884SUwe Kleine-König if (changed & TIOCM_CAR) 96566f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 96666f95884SUwe Kleine-König if (changed & TIOCM_CTS) 96766f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 96866f95884SUwe Kleine-König 96966f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 97066f95884SUwe Kleine-König } 97166f95884SUwe Kleine-König 9729d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 973ab4382d2SGreg Kroah-Hartman { 974ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 97543776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 9764d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 977ab4382d2SGreg Kroah-Hartman 9789baedb7bSJohan Hovold spin_lock(&sport->port.lock); 979101aa46bSUwe Kleine-König 98027c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 98127c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 98227c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 98327c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 98427c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 98527c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 986ab4382d2SGreg Kroah-Hartman 98743776896SUwe Kleine-König /* 98843776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 98943776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 99043776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 99143776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 99243776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 99343776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 99443776896SUwe Kleine-König */ 99543776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 99643776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 99743776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 99843776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 999c514a6f8SSergey Organov if ((ucr1 & UCR1_TRDYEN) == 0) 100043776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 100143776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 100243776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 100343776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 100443776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 100543776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 100643776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 100743776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 100843776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 100943776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 101043776896SUwe Kleine-König usr2 &= ~USR2_ORE; 101143776896SUwe Kleine-König 101243776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 1013d1d996afSMatthias Schiffer imx_uart_writel(sport, USR1_AGTIM, USR1); 1014d1d996afSMatthias Schiffer 1015101aa46bSUwe Kleine-König __imx_uart_rxint(irq, dev_id); 10164d845a62SUwe Kleine-König ret = IRQ_HANDLED; 1017b4cdc8f6SHuang Shijie } 1018ab4382d2SGreg Kroah-Hartman 101943776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 1020101aa46bSUwe Kleine-König imx_uart_transmit_buffer(sport); 10214d845a62SUwe Kleine-König ret = IRQ_HANDLED; 10224d845a62SUwe Kleine-König } 1023ab4382d2SGreg Kroah-Hartman 10240399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 102527c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 102627e16501SUwe Kleine-König 10279d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 102827e16501SUwe Kleine-König 102927e16501SUwe Kleine-König ret = IRQ_HANDLED; 103027e16501SUwe Kleine-König } 103127e16501SUwe Kleine-König 10320399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 1033101aa46bSUwe Kleine-König __imx_uart_rtsint(irq, dev_id); 10344d845a62SUwe Kleine-König ret = IRQ_HANDLED; 10354d845a62SUwe Kleine-König } 1036ab4382d2SGreg Kroah-Hartman 10370399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 103827c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 10394d845a62SUwe Kleine-König ret = IRQ_HANDLED; 10404d845a62SUwe Kleine-König } 1041db1a9b55SFabio Estevam 10420399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 1043f1f836e4SAlexander Stein sport->port.icount.overrun++; 104427c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 10454d845a62SUwe Kleine-König ret = IRQ_HANDLED; 1046f1f836e4SAlexander Stein } 1047f1f836e4SAlexander Stein 10489baedb7bSJohan Hovold spin_unlock(&sport->port.lock); 1049101aa46bSUwe Kleine-König 10504d845a62SUwe Kleine-König return ret; 1051ab4382d2SGreg Kroah-Hartman } 1052ab4382d2SGreg Kroah-Hartman 1053ab4382d2SGreg Kroah-Hartman /* 1054ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 1055ab4382d2SGreg Kroah-Hartman */ 10569d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 1057ab4382d2SGreg Kroah-Hartman { 1058ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10591ce43e58SHuang Shijie unsigned int ret; 1060ab4382d2SGreg Kroah-Hartman 106127c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 10621ce43e58SHuang Shijie 10631ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 1064686351f3SUwe Kleine-König if (sport->dma_is_txing) 10651ce43e58SHuang Shijie ret = 0; 10661ce43e58SHuang Shijie 10671ce43e58SHuang Shijie return ret; 1068ab4382d2SGreg Kroah-Hartman } 1069ab4382d2SGreg Kroah-Hartman 10706aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10719d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 107258362d5bSUwe Kleine-König { 107358362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 10749d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 107558362d5bSUwe Kleine-König 107658362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 107758362d5bSUwe Kleine-König 107858362d5bSUwe Kleine-König return ret; 107958362d5bSUwe Kleine-König } 108058362d5bSUwe Kleine-König 10816aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10829d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1083ab4382d2SGreg Kroah-Hartman { 1084ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10854444dcf1SUwe Kleine-König u32 ucr3, uts; 1086ab4382d2SGreg Kroah-Hartman 108717b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 10884444dcf1SUwe Kleine-König u32 ucr2; 10894444dcf1SUwe Kleine-König 1090197540dcSSergey Organov /* 1091197540dcSSergey Organov * Turn off autoRTS if RTS is lowered and restore autoRTS 1092197540dcSSergey Organov * setting if RTS is raised. 1093197540dcSSergey Organov */ 10944444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 10954444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1096197540dcSSergey Organov if (mctrl & TIOCM_RTS) { 1097197540dcSSergey Organov ucr2 |= UCR2_CTS; 1098197540dcSSergey Organov /* 1099197540dcSSergey Organov * UCR2_IRTS is unset if and only if the port is 1100197540dcSSergey Organov * configured for CRTSCTS, so we use inverted UCR2_IRTS 1101197540dcSSergey Organov * to get the state to restore to. 1102197540dcSSergey Organov */ 1103197540dcSSergey Organov if (!(ucr2 & UCR2_IRTS)) 1104197540dcSSergey Organov ucr2 |= UCR2_CTSC; 1105197540dcSSergey Organov } 11064444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 110717b8f2a3SUwe Kleine-König } 11086b471a98SHuang Shijie 11094444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 111090ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 11114444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 11124444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 111390ebc483SUwe Kleine-König 11149d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 11156b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 11164444dcf1SUwe Kleine-König uts |= UTS_LOOP; 11179d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 111858362d5bSUwe Kleine-König 111958362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 1120ab4382d2SGreg Kroah-Hartman } 1121ab4382d2SGreg Kroah-Hartman 1122ab4382d2SGreg Kroah-Hartman /* 1123ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 1124ab4382d2SGreg Kroah-Hartman */ 11259d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1126ab4382d2SGreg Kroah-Hartman { 1127ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 11284444dcf1SUwe Kleine-König unsigned long flags; 11294444dcf1SUwe Kleine-König u32 ucr1; 1130ab4382d2SGreg Kroah-Hartman 1131ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1132ab4382d2SGreg Kroah-Hartman 11334444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1134ab4382d2SGreg Kroah-Hartman 1135ab4382d2SGreg Kroah-Hartman if (break_state != 0) 11364444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1137ab4382d2SGreg Kroah-Hartman 11384444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1139ab4382d2SGreg Kroah-Hartman 1140ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1141ab4382d2SGreg Kroah-Hartman } 1142ab4382d2SGreg Kroah-Hartman 1143cc568849SUwe Kleine-König /* 1144cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1145cc568849SUwe Kleine-König * modem status signals. 1146cc568849SUwe Kleine-König */ 11479d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1148cc568849SUwe Kleine-König { 1149e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1150cc568849SUwe Kleine-König unsigned long flags; 1151cc568849SUwe Kleine-König 1152cc568849SUwe Kleine-König if (sport->port.state) { 1153cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 11549d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1155cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1156cc568849SUwe Kleine-König 1157cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1158cc568849SUwe Kleine-König } 1159cc568849SUwe Kleine-König } 1160cc568849SUwe Kleine-König 1161b4cdc8f6SHuang Shijie /* 1162905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1163b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1164905c0decSLucas Stach * [2] the aging timer expires 1165b4cdc8f6SHuang Shijie * 1166905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1167905c0decSLucas Stach * for at least 8 byte durations. 1168b4cdc8f6SHuang Shijie */ 11699d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1170b4cdc8f6SHuang Shijie { 1171b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1172b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1173b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 11747cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1175b4cdc8f6SHuang Shijie struct dma_tx_state state; 11769d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1177b4cdc8f6SHuang Shijie enum dma_status status; 11789d297239SNandor Han unsigned int w_bytes = 0; 11799d297239SNandor Han unsigned int r_bytes; 11809d297239SNandor Han unsigned int bd_size; 1181b4cdc8f6SHuang Shijie 1182fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1183392bceedSPhilipp Zabel 11849d297239SNandor Han if (status == DMA_ERROR) { 11859d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 11869d297239SNandor Han return; 11879d297239SNandor Han } 1188b4cdc8f6SHuang Shijie 11899b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1190976b39cdSLucas Stach 1191976b39cdSLucas Stach /* 11929d297239SNandor Han * The state-residue variable represents the empty space 11939d297239SNandor Han * relative to the entire buffer. Taking this in consideration 11949d297239SNandor Han * the head is always calculated base on the buffer total 11959d297239SNandor Han * length - DMA transaction residue. The UART script from the 11969d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 11979d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 11989d297239SNandor Han * Taking this in consideration the tail is always at the 11999d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1200976b39cdSLucas Stach */ 12019d297239SNandor Han 12029d297239SNandor Han /* Calculate the head */ 12039d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 12049d297239SNandor Han 12059d297239SNandor Han /* Calculate the tail. */ 12069d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 12079d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 12089d297239SNandor Han 12099d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 12109d297239SNandor Han rx_ring->head > rx_ring->tail) { 12119d297239SNandor Han 12129d297239SNandor Han /* Move data from tail to head */ 12139d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 12149d297239SNandor Han 12159d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 12169d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 12179d297239SNandor Han DMA_FROM_DEVICE); 12189d297239SNandor Han 12199d297239SNandor Han w_bytes = tty_insert_flip_string(port, 12209d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 12219d297239SNandor Han 12229d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 12239d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 12249d297239SNandor Han DMA_FROM_DEVICE); 12259d297239SNandor Han 12269d297239SNandor Han if (w_bytes != r_bytes) 12279d297239SNandor Han sport->port.icount.buf_overrun++; 12289d297239SNandor Han 12299d297239SNandor Han sport->port.icount.rx += w_bytes; 12309d297239SNandor Han } else { 12319d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 12329d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1233ee5e7c10SRobin Gong } 12349d297239SNandor Han } 12359d297239SNandor Han 12369d297239SNandor Han if (w_bytes) { 12379d297239SNandor Han tty_flip_buffer_push(port); 12389d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 12399d297239SNandor Han } 12409d297239SNandor Han } 12419d297239SNandor Han 12429d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1243b4cdc8f6SHuang Shijie { 1244b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1245b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1246b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1247b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1248b4cdc8f6SHuang Shijie int ret; 1249b4cdc8f6SHuang Shijie 12509d297239SNandor Han sport->rx_ring.head = 0; 12519d297239SNandor Han sport->rx_ring.tail = 0; 12529d297239SNandor Han 1253db0a196bSFabien Lahoudere sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); 1254b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1255b4cdc8f6SHuang Shijie if (ret == 0) { 1256b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1257b4cdc8f6SHuang Shijie return -EINVAL; 1258b4cdc8f6SHuang Shijie } 12599d297239SNandor Han 12609d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 12619d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 12629d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 12639d297239SNandor Han 1264b4cdc8f6SHuang Shijie if (!desc) { 126524649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1266b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1267b4cdc8f6SHuang Shijie return -EINVAL; 1268b4cdc8f6SHuang Shijie } 12699d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1270b4cdc8f6SHuang Shijie desc->callback_param = sport; 1271b4cdc8f6SHuang Shijie 1272b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 12734139fd76SRomain Perier sport->dma_is_rxing = 1; 12749d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1275b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1276b4cdc8f6SHuang Shijie return 0; 1277b4cdc8f6SHuang Shijie } 1278b4cdc8f6SHuang Shijie 12799d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 128041d98b5dSNandor Han { 128145ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 12824444dcf1SUwe Kleine-König u32 usr1, usr2; 128341d98b5dSNandor Han 12844444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 12854444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 128641d98b5dSNandor Han 12874444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 128841d98b5dSNandor Han sport->port.icount.brk++; 128927c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 129045ca673eSTroy Kisky uart_handle_break(&sport->port); 129145ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 129245ca673eSTroy Kisky sport->port.icount.buf_overrun++; 129345ca673eSTroy Kisky tty_flip_buffer_push(port); 129445ca673eSTroy Kisky } else { 12954444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 129641d98b5dSNandor Han sport->port.icount.frame++; 129727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 12984444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 129941d98b5dSNandor Han sport->port.icount.parity++; 130027c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 130141d98b5dSNandor Han } 130245ca673eSTroy Kisky } 130341d98b5dSNandor Han 13044444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 130541d98b5dSNandor Han sport->port.icount.overrun++; 130627c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 130741d98b5dSNandor Han } 130841d98b5dSNandor Han 130941d98b5dSNandor Han } 131041d98b5dSNandor Han 1311cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 13127a637784STomasz Moń #define RXTL_DEFAULT 8 /* 8 characters or aging timer */ 1313184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1314184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1315cc32382dSLucas Stach 13169d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1317cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1318cc32382dSLucas Stach { 1319cc32382dSLucas Stach unsigned int val; 1320cc32382dSLucas Stach 1321cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 132227c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1323cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 132427c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1325cc32382dSLucas Stach } 1326cc32382dSLucas Stach 1327b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1328b4cdc8f6SHuang Shijie { 1329b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1330e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1331b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1332b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 13339d297239SNandor Han sport->rx_cookie = -EINVAL; 1334b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1335b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1336b4cdc8f6SHuang Shijie } 1337b4cdc8f6SHuang Shijie 1338b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1339e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1340b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1341b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1342b4cdc8f6SHuang Shijie } 1343b4cdc8f6SHuang Shijie } 1344b4cdc8f6SHuang Shijie 1345b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1346b4cdc8f6SHuang Shijie { 1347b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1348b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1349b4cdc8f6SHuang Shijie int ret; 1350b4cdc8f6SHuang Shijie 1351b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1352b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1353b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1354b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1355b4cdc8f6SHuang Shijie ret = -EINVAL; 1356b4cdc8f6SHuang Shijie goto err; 1357b4cdc8f6SHuang Shijie } 1358b4cdc8f6SHuang Shijie 1359b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1360b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1361b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1362184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1363184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1364b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1365b4cdc8f6SHuang Shijie if (ret) { 1366b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1367b4cdc8f6SHuang Shijie goto err; 1368b4cdc8f6SHuang Shijie } 1369b4cdc8f6SHuang Shijie 1370db0a196bSFabien Lahoudere sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; 1371db0a196bSFabien Lahoudere sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); 1372b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1373b4cdc8f6SHuang Shijie ret = -ENOMEM; 1374b4cdc8f6SHuang Shijie goto err; 1375b4cdc8f6SHuang Shijie } 13769d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1377b4cdc8f6SHuang Shijie 1378b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1379b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1380b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1381b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1382b4cdc8f6SHuang Shijie ret = -EINVAL; 1383b4cdc8f6SHuang Shijie goto err; 1384b4cdc8f6SHuang Shijie } 1385b4cdc8f6SHuang Shijie 1386b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1387b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1388b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1389184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1390b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1391b4cdc8f6SHuang Shijie if (ret) { 1392b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1393b4cdc8f6SHuang Shijie goto err; 1394b4cdc8f6SHuang Shijie } 1395b4cdc8f6SHuang Shijie 1396b4cdc8f6SHuang Shijie return 0; 1397b4cdc8f6SHuang Shijie err: 1398b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1399b4cdc8f6SHuang Shijie return ret; 1400b4cdc8f6SHuang Shijie } 1401b4cdc8f6SHuang Shijie 14029d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1403b4cdc8f6SHuang Shijie { 14044444dcf1SUwe Kleine-König u32 ucr1; 1405b4cdc8f6SHuang Shijie 14069d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 140702b0abd3SUwe Kleine-König 1408b4cdc8f6SHuang Shijie /* set UCR1 */ 14094444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 14104444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 14114444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1412b4cdc8f6SHuang Shijie 1413b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1414b4cdc8f6SHuang Shijie } 1415b4cdc8f6SHuang Shijie 14169d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1417b4cdc8f6SHuang Shijie { 1418676a31d8SSebastian Reichel u32 ucr1; 1419b4cdc8f6SHuang Shijie 1420b4cdc8f6SHuang Shijie /* clear UCR1 */ 14214444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 14224444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 14234444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1424b4cdc8f6SHuang Shijie 14259d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1426184bd70bSLucas Stach 1427b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1428b4cdc8f6SHuang Shijie } 1429b4cdc8f6SHuang Shijie 1430ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1431ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1432ab4382d2SGreg Kroah-Hartman 14339d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1434ab4382d2SGreg Kroah-Hartman { 1435ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1436*d45fb2e4SSergey Organov int retval; 14374444dcf1SUwe Kleine-König unsigned long flags; 14384238c00bSUwe Kleine-König int dma_is_inited = 0; 143979d0224fSMarek Vasut u32 ucr1, ucr2, ucr3, ucr4, uts; 1440ab4382d2SGreg Kroah-Hartman 144128eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 144228eb4274SHuang Shijie if (retval) 1443cb0f0a5fSFabio Estevam return retval; 144428eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 14450c375501SHuang Shijie if (retval) { 14460c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1447cb0f0a5fSFabio Estevam return retval; 14480c375501SHuang Shijie } 144928eb4274SHuang Shijie 14509d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1451ab4382d2SGreg Kroah-Hartman 1452ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1453ab4382d2SGreg Kroah-Hartman * requesting IRQs 1454ab4382d2SGreg Kroah-Hartman */ 14554444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1456ab4382d2SGreg Kroah-Hartman 1457ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 14584444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 14594444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1460ab4382d2SGreg Kroah-Hartman 14614444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1462ab4382d2SGreg Kroah-Hartman 14637e11577eSLucas Stach /* Can we enable the DMA support? */ 14644238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 14654238c00bSUwe Kleine-König dma_is_inited = 1; 14667e11577eSLucas Stach 146753794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1468*d45fb2e4SSergey Organov 1469772f8991SHuang Shijie /* Reset fifo's and state machines */ 1470*d45fb2e4SSergey Organov imx_uart_soft_reset(sport); 1471ab4382d2SGreg Kroah-Hartman 1472ab4382d2SGreg Kroah-Hartman /* 1473ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1474ab4382d2SGreg Kroah-Hartman */ 147527c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 147627c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1477ab4382d2SGreg Kroah-Hartman 14784444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 14794444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 14806376cd39SNandor Han if (sport->have_rtscts) 14814444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1482ab4382d2SGreg Kroah-Hartman 14834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1484ab4382d2SGreg Kroah-Hartman 14855a08a487SGeorge Hilliard ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 14863ee82c6eSJohan Hovold if (!dma_is_inited) 14874444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 14885a08a487SGeorge Hilliard if (sport->inverted_rx) 14895a08a487SGeorge Hilliard ucr4 |= UCR4_INVR; 14904444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 14916f026d6bSJiada Wang 14925a08a487SGeorge Hilliard ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 14935a08a487SGeorge Hilliard /* 14945a08a487SGeorge Hilliard * configure tx polarity before enabling tx 14955a08a487SGeorge Hilliard */ 14965a08a487SGeorge Hilliard if (sport->inverted_tx) 14975a08a487SGeorge Hilliard ucr3 |= UCR3_INVT; 14985a08a487SGeorge Hilliard 14995a08a487SGeorge Hilliard if (!imx_uart_is_imx1(sport)) { 15005a08a487SGeorge Hilliard ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 15015a08a487SGeorge Hilliard 15025a08a487SGeorge Hilliard if (sport->dte_mode) 15035a08a487SGeorge Hilliard /* disable broken interrupts */ 15045a08a487SGeorge Hilliard ucr3 &= ~(UCR3_RI | UCR3_DCD); 15055a08a487SGeorge Hilliard } 15065a08a487SGeorge Hilliard imx_uart_writel(sport, ucr3, UCR3); 15075a08a487SGeorge Hilliard 15084444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 15094444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1510bff09b09SLucas Stach if (!sport->have_rtscts) 15114444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 151216804d68SUwe Kleine-König /* 151316804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 151416804d68SUwe Kleine-König * we're using RTSD instead. 151516804d68SUwe Kleine-König */ 15169d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 15174444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 15184444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1519ab4382d2SGreg Kroah-Hartman 1520ab4382d2SGreg Kroah-Hartman /* 1521ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1522ab4382d2SGreg Kroah-Hartman */ 15239d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 152418a42088SPeter Senna Tschudin 152576821e22SUwe Kleine-König if (dma_is_inited) { 15269d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 15279d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 152876821e22SUwe Kleine-König } else { 152976821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 153076821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 153176821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 153281ca8e82SUwe Kleine-König 153381ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 153481ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 153581ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 153676821e22SUwe Kleine-König } 153718a42088SPeter Senna Tschudin 153879d0224fSMarek Vasut /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 153979d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 154079d0224fSMarek Vasut uts &= ~UTS_LOOP; 154179d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 154279d0224fSMarek Vasut 1543ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1544ab4382d2SGreg Kroah-Hartman 1545ab4382d2SGreg Kroah-Hartman return 0; 1546ab4382d2SGreg Kroah-Hartman } 1547ab4382d2SGreg Kroah-Hartman 15489d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1549ab4382d2SGreg Kroah-Hartman { 1550ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 15519ec1882dSXinyu Chen unsigned long flags; 155279d0224fSMarek Vasut u32 ucr1, ucr2, ucr4, uts; 1553ab4382d2SGreg Kroah-Hartman 1554b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1555e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 15567722c240SSebastian Reichel if (sport->dma_is_txing) { 15577722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 15587722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 15597722c240SSebastian Reichel sport->dma_is_txing = 0; 15607722c240SSebastian Reichel } 1561e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 15627722c240SSebastian Reichel if (sport->dma_is_rxing) { 15637722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 15647722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 15657722c240SSebastian Reichel sport->dma_is_rxing = 0; 15667722c240SSebastian Reichel } 15679d297239SNandor Han 156873631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 15699d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 15709d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 15719d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 157273631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1573b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1574b4cdc8f6SHuang Shijie } 1575b4cdc8f6SHuang Shijie 157658362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 157758362d5bSUwe Kleine-König 15789ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 15794444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15800fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 15814444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 15829ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1583ab4382d2SGreg Kroah-Hartman 1584ab4382d2SGreg Kroah-Hartman /* 1585ab4382d2SGreg Kroah-Hartman * Stop our timer. 1586ab4382d2SGreg Kroah-Hartman */ 1587ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1588ab4382d2SGreg Kroah-Hartman 1589ab4382d2SGreg Kroah-Hartman /* 1590ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1591ab4382d2SGreg Kroah-Hartman */ 1592ab4382d2SGreg Kroah-Hartman 15939ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1594edd64f30SMatthias Schiffer 15954444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 1596509597ebSSherry Sun ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | 1597509597ebSSherry Sun UCR1_ATDMAEN | UCR1_SNDBRK); 159879d0224fSMarek Vasut /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 159979d0224fSMarek Vasut if (port->rs485.flags & SER_RS485_ENABLED && 160079d0224fSMarek Vasut port->rs485.flags & SER_RS485_RTS_ON_SEND && 160179d0224fSMarek Vasut sport->have_rtscts && !sport->have_rtsgpio) { 160279d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 160379d0224fSMarek Vasut uts |= UTS_LOOP; 160479d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 160579d0224fSMarek Vasut ucr1 |= UCR1_UARTEN; 160679d0224fSMarek Vasut } else { 160779d0224fSMarek Vasut ucr1 &= ~UCR1_UARTEN; 160879d0224fSMarek Vasut } 16094444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1610edd64f30SMatthias Schiffer 1611edd64f30SMatthias Schiffer ucr4 = imx_uart_readl(sport, UCR4); 1612028e0838SFugang Duan ucr4 &= ~UCR4_TCEN; 1613edd64f30SMatthias Schiffer imx_uart_writel(sport, ucr4, UCR4); 1614edd64f30SMatthias Schiffer 16159ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 161628eb4274SHuang Shijie 161728eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 161828eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1619ab4382d2SGreg Kroah-Hartman } 1620ab4382d2SGreg Kroah-Hartman 16216aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 16229d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1623eb56b7edSHuang Shijie { 1624eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 162582e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1626eb56b7edSHuang Shijie 162782e86ae9SDirk Behme if (!sport->dma_chan_tx) 162882e86ae9SDirk Behme return; 162982e86ae9SDirk Behme 1630eb56b7edSHuang Shijie sport->tx_bytes = 0; 1631eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 163282e86ae9SDirk Behme if (sport->dma_is_txing) { 16334444dcf1SUwe Kleine-König u32 ucr1; 16344444dcf1SUwe Kleine-König 163582e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 163682e86ae9SDirk Behme DMA_TO_DEVICE); 16374444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 16384444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 16394444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 16400f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1641eb56b7edSHuang Shijie } 1642934084a9SFabio Estevam 1643*d45fb2e4SSergey Organov imx_uart_soft_reset(sport); 1644934084a9SFabio Estevam 1645eb56b7edSHuang Shijie } 1646eb56b7edSHuang Shijie 1647ab4382d2SGreg Kroah-Hartman static void 16489d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1649bec5b814SIlpo Järvinen const struct ktermios *old) 1650ab4382d2SGreg Kroah-Hartman { 1651ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1652ab4382d2SGreg Kroah-Hartman unsigned long flags; 165385f30fbfSSergey Organov u32 ucr2, old_ucr2, ufcr; 165458362d5bSUwe Kleine-König unsigned int baud, quot; 1655ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 16564444dcf1SUwe Kleine-König unsigned long div; 1657d47bcb4aSSergey Organov unsigned long num, denom, old_ubir, old_ubmr; 1658ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1659ab4382d2SGreg Kroah-Hartman 1660ab4382d2SGreg Kroah-Hartman /* 1661ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1662ab4382d2SGreg Kroah-Hartman */ 1663ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1664ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1665ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1666ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1667ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1668ab4382d2SGreg Kroah-Hartman } 1669ab4382d2SGreg Kroah-Hartman 16704e828c3eSSergey Organov del_timer_sync(&sport->timer); 16714e828c3eSSergey Organov 16724e828c3eSSergey Organov /* 16734e828c3eSSergey Organov * Ask the core to calculate the divisor for us. 16744e828c3eSSergey Organov */ 16754e828c3eSSergey Organov baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 16764e828c3eSSergey Organov quot = uart_get_divisor(port, baud); 16774e828c3eSSergey Organov 16784e828c3eSSergey Organov spin_lock_irqsave(&sport->port.lock, flags); 16794e828c3eSSergey Organov 1680011bd05dSSergey Organov /* 1681011bd05dSSergey Organov * Read current UCR2 and save it for future use, then clear all the bits 1682011bd05dSSergey Organov * except those we will or may need to preserve. 1683011bd05dSSergey Organov */ 1684011bd05dSSergey Organov old_ucr2 = imx_uart_readl(sport, UCR2); 1685011bd05dSSergey Organov ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1686011bd05dSSergey Organov 1687011bd05dSSergey Organov ucr2 |= UCR2_SRST | UCR2_IRTS; 168841ffa48eSSergey Organov if ((termios->c_cflag & CSIZE) == CS8) 168941ffa48eSSergey Organov ucr2 |= UCR2_WS; 1690ab4382d2SGreg Kroah-Hartman 1691ddf89e75SSergey Organov if (!sport->have_rtscts) 1692ddf89e75SSergey Organov termios->c_cflag &= ~CRTSCTS; 169317b8f2a3SUwe Kleine-König 169412fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 169517b8f2a3SUwe Kleine-König /* 169617b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 169717b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 169817b8f2a3SUwe Kleine-König * disabled. 169917b8f2a3SUwe Kleine-König */ 170058362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 17019d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 17021a613626SFabio Estevam else 17039d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 170458362d5bSUwe Kleine-König 1705b777b5deSSergey Organov } else if (termios->c_cflag & CRTSCTS) { 1706b777b5deSSergey Organov /* 1707b777b5deSSergey Organov * Only let receiver control RTS output if we were not requested 1708b777b5deSSergey Organov * to have RTS inactive (which then should take precedence). 1709b777b5deSSergey Organov */ 1710b777b5deSSergey Organov if (ucr2 & UCR2_CTS) 1711b777b5deSSergey Organov ucr2 |= UCR2_CTSC; 1712b777b5deSSergey Organov } 1713ddf89e75SSergey Organov 1714ddf89e75SSergey Organov if (termios->c_cflag & CRTSCTS) 1715ddf89e75SSergey Organov ucr2 &= ~UCR2_IRTS; 1716ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1717ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1718ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1719ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1720ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1721ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1722ab4382d2SGreg Kroah-Hartman } 1723ab4382d2SGreg Kroah-Hartman 1724ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1725ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1726ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1727ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1728ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1729ab4382d2SGreg Kroah-Hartman 1730ab4382d2SGreg Kroah-Hartman /* 1731ab4382d2SGreg Kroah-Hartman * Characters to ignore 1732ab4382d2SGreg Kroah-Hartman */ 1733ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1734ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1735865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1736ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1737ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1738ab4382d2SGreg Kroah-Hartman /* 1739ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1740ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1741ab4382d2SGreg Kroah-Hartman */ 1742ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1743ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1744ab4382d2SGreg Kroah-Hartman } 1745ab4382d2SGreg Kroah-Hartman 174655d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 174755d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 174855d8693aSJiada Wang 1749ab4382d2SGreg Kroah-Hartman /* 1750ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1751ab4382d2SGreg Kroah-Hartman */ 1752ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1753ab4382d2SGreg Kroah-Hartman 175409bd00f6SHubert Feurstein /* custom-baudrate handling */ 175509bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 175609bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 175709bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 175809bd00f6SHubert Feurstein 1759ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1760ab4382d2SGreg Kroah-Hartman if (div > 7) 1761ab4382d2SGreg Kroah-Hartman div = 7; 1762ab4382d2SGreg Kroah-Hartman if (!div) 1763ab4382d2SGreg Kroah-Hartman div = 1; 1764ab4382d2SGreg Kroah-Hartman 1765ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1766ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1767ab4382d2SGreg Kroah-Hartman 1768ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1769ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1770ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1771ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1772ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1773ab4382d2SGreg Kroah-Hartman 1774ab4382d2SGreg Kroah-Hartman num -= 1; 1775ab4382d2SGreg Kroah-Hartman denom -= 1; 1776ab4382d2SGreg Kroah-Hartman 177727c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1778ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 177927c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1780ab4382d2SGreg Kroah-Hartman 1781d47bcb4aSSergey Organov /* 1782d47bcb4aSSergey Organov * Two registers below should always be written both and in this 1783d47bcb4aSSergey Organov * particular order. One consequence is that we need to check if any of 1784d47bcb4aSSergey Organov * them changes and then update both. We do need the check for change 1785d47bcb4aSSergey Organov * as even writing the same values seem to "restart" 1786d47bcb4aSSergey Organov * transmission/receiving logic in the hardware, that leads to data 1787d47bcb4aSSergey Organov * breakage even when rate doesn't in fact change. E.g., user switches 1788d47bcb4aSSergey Organov * RTS/CTS handshake and suddenly gets broken bytes. 1789d47bcb4aSSergey Organov */ 1790d47bcb4aSSergey Organov old_ubir = imx_uart_readl(sport, UBIR); 1791d47bcb4aSSergey Organov old_ubmr = imx_uart_readl(sport, UBMR); 1792d47bcb4aSSergey Organov if (old_ubir != num || old_ubmr != denom) { 179327c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 179427c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1795d47bcb4aSSergey Organov } 1796ab4382d2SGreg Kroah-Hartman 17979d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 179827c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 179927c84426SUwe Kleine-König IMX21_ONEMS); 1800ab4382d2SGreg Kroah-Hartman 1801011bd05dSSergey Organov imx_uart_writel(sport, ucr2, UCR2); 1802ab4382d2SGreg Kroah-Hartman 1803ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 18049d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1805ab4382d2SGreg Kroah-Hartman 1806ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1807ab4382d2SGreg Kroah-Hartman } 1808ab4382d2SGreg Kroah-Hartman 18099d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1810ab4382d2SGreg Kroah-Hartman { 1811ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1812ab4382d2SGreg Kroah-Hartman 1813ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1814ab4382d2SGreg Kroah-Hartman } 1815ab4382d2SGreg Kroah-Hartman 1816ab4382d2SGreg Kroah-Hartman /* 1817ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1818ab4382d2SGreg Kroah-Hartman */ 18199d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1820ab4382d2SGreg Kroah-Hartman { 1821ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1822ab4382d2SGreg Kroah-Hartman 1823da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1824ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1825ab4382d2SGreg Kroah-Hartman } 1826ab4382d2SGreg Kroah-Hartman 1827ab4382d2SGreg Kroah-Hartman /* 1828ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1829ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1830ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1831ab4382d2SGreg Kroah-Hartman */ 1832ab4382d2SGreg Kroah-Hartman static int 18339d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1834ab4382d2SGreg Kroah-Hartman { 1835ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1836ab4382d2SGreg Kroah-Hartman int ret = 0; 1837ab4382d2SGreg Kroah-Hartman 1838ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1839ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1840ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1841ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1842ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1843ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1844ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1845ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1846a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1847ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1848ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1849ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1850ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1851ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1852ab4382d2SGreg Kroah-Hartman return ret; 1853ab4382d2SGreg Kroah-Hartman } 1854ab4382d2SGreg Kroah-Hartman 185501f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18566b8bdad9SDaniel Thompson 18579d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 18586b8bdad9SDaniel Thompson { 18596b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 18606b8bdad9SDaniel Thompson unsigned long flags; 18614444dcf1SUwe Kleine-König u32 ucr1, ucr2; 18626b8bdad9SDaniel Thompson int retval; 18636b8bdad9SDaniel Thompson 18646b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 18656b8bdad9SDaniel Thompson if (retval) 18666b8bdad9SDaniel Thompson return retval; 18676b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 18686b8bdad9SDaniel Thompson if (retval) 18696b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 18706b8bdad9SDaniel Thompson 18719d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 18726b8bdad9SDaniel Thompson 18736b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 18746b8bdad9SDaniel Thompson 187576821e22SUwe Kleine-König /* 187676821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 187776821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 187876821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 187976821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 188076821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 188176821e22SUwe Kleine-König */ 18824444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 188376821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 188476821e22SUwe Kleine-König 18859d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 18864444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 18876b8bdad9SDaniel Thompson 188876821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 1889c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 189076821e22SUwe Kleine-König 1891aef1b6a2SMingrui Ren ucr2 |= UCR2_RXEN | UCR2_TXEN; 189281ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 189376821e22SUwe Kleine-König 189476821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 18954444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 18966b8bdad9SDaniel Thompson 189776821e22SUwe Kleine-König /* now enable irqs */ 189876821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 189981ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 190076821e22SUwe Kleine-König 19016b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 19026b8bdad9SDaniel Thompson 19036b8bdad9SDaniel Thompson return 0; 19046b8bdad9SDaniel Thompson } 19056b8bdad9SDaniel Thompson 19069d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 190701f56abdSSaleem Abdulrasool { 190827c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 190927c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 191026c47412SDirk Behme return NO_POLL_CHAR; 191101f56abdSSaleem Abdulrasool 191227c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 191301f56abdSSaleem Abdulrasool } 191401f56abdSSaleem Abdulrasool 19159d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 191601f56abdSSaleem Abdulrasool { 191727c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 191801f56abdSSaleem Abdulrasool unsigned int status; 191901f56abdSSaleem Abdulrasool 192001f56abdSSaleem Abdulrasool /* drain */ 192101f56abdSSaleem Abdulrasool do { 192227c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 192301f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 192401f56abdSSaleem Abdulrasool 192501f56abdSSaleem Abdulrasool /* write */ 192627c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 192701f56abdSSaleem Abdulrasool 192801f56abdSSaleem Abdulrasool /* flush */ 192901f56abdSSaleem Abdulrasool do { 193027c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 193101f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 193201f56abdSSaleem Abdulrasool } 193301f56abdSSaleem Abdulrasool #endif 193401f56abdSSaleem Abdulrasool 19356aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 1936ae50bb27SIlpo Järvinen static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios, 193717b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 193817b8f2a3SUwe Kleine-König { 193917b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 19404444dcf1SUwe Kleine-König u32 ucr2; 194117b8f2a3SUwe Kleine-König 194217b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 19436d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 19446d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 19456d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 19466d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 19476d215f83SStefan Agner 194817b8f2a3SUwe Kleine-König /* disable transmitter */ 19494444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 195017b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 19519d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 19521a613626SFabio Estevam else 19539d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 19544444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 195517b8f2a3SUwe Kleine-König } 195617b8f2a3SUwe Kleine-König 19577d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 19587d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 195976821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 19609d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 19617d1cadcaSBaruch Siach 1962ca530cfaSChristoph Niedermaier if (port->rs485_rx_during_tx_gpio) 1963ca530cfaSChristoph Niedermaier gpiod_set_value_cansleep(port->rs485_rx_during_tx_gpio, 1964ca530cfaSChristoph Niedermaier !!(rs485conf->flags & SER_RS485_RX_DURING_TX)); 1965ca530cfaSChristoph Niedermaier 196617b8f2a3SUwe Kleine-König return 0; 196717b8f2a3SUwe Kleine-König } 196817b8f2a3SUwe Kleine-König 19699d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 19709d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 19719d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 19729d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 19739d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 19749d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 19759d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 19769d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 19779d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 19789d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 19799d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 19809d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 19819d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 19829d1a50a2SUwe Kleine-König .type = imx_uart_type, 19839d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 19849d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 198501f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 19869d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 19879d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 19889d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 198901f56abdSSaleem Abdulrasool #endif 1990ab4382d2SGreg Kroah-Hartman }; 1991ab4382d2SGreg Kroah-Hartman 19929d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1993ab4382d2SGreg Kroah-Hartman 19940db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 19953f8bab17SJiri Slaby static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch) 1996ab4382d2SGreg Kroah-Hartman { 1997ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1998ab4382d2SGreg Kroah-Hartman 19999d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 2000ab4382d2SGreg Kroah-Hartman barrier(); 2001ab4382d2SGreg Kroah-Hartman 200227c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 2003ab4382d2SGreg Kroah-Hartman } 2004ab4382d2SGreg Kroah-Hartman 2005ab4382d2SGreg Kroah-Hartman /* 2006ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 2007ab4382d2SGreg Kroah-Hartman */ 2008ab4382d2SGreg Kroah-Hartman static void 20099d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 2010ab4382d2SGreg Kroah-Hartman { 20119d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 20120ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 201318ee37e1SJohan Hovold unsigned long flags; 20140ad5a814SDirk Behme unsigned int ucr1; 2015677fe555SThomas Gleixner int locked = 1; 20169ec1882dSXinyu Chen 2017677fe555SThomas Gleixner if (sport->port.sysrq) 2018677fe555SThomas Gleixner locked = 0; 2019677fe555SThomas Gleixner else if (oops_in_progress) 2020677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 2021677fe555SThomas Gleixner else 20229ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 2023ab4382d2SGreg Kroah-Hartman 2024ab4382d2SGreg Kroah-Hartman /* 20250ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 2026ab4382d2SGreg Kroah-Hartman */ 20279d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 20280ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 2029ab4382d2SGreg Kroah-Hartman 20309d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 2031fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 2032ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 2033c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 2034ab4382d2SGreg Kroah-Hartman 203527c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2036ab4382d2SGreg Kroah-Hartman 203727c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2038ab4382d2SGreg Kroah-Hartman 20399d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2040ab4382d2SGreg Kroah-Hartman 2041ab4382d2SGreg Kroah-Hartman /* 2042ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 20430ad5a814SDirk Behme * and restore UCR1/2/3 2044ab4382d2SGreg Kroah-Hartman */ 204527c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2046ab4382d2SGreg Kroah-Hartman 20479d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 20489ec1882dSXinyu Chen 2049677fe555SThomas Gleixner if (locked) 20509ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 2051ab4382d2SGreg Kroah-Hartman } 2052ab4382d2SGreg Kroah-Hartman 2053ab4382d2SGreg Kroah-Hartman /* 2054ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 2055ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 2056ab4382d2SGreg Kroah-Hartman */ 20576d0d1b5aSStefan Agner static void 20589d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 2059ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 2060ab4382d2SGreg Kroah-Hartman { 2061ab4382d2SGreg Kroah-Hartman 206227c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2063ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 2064ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 2065ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 2066ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 2067ab4382d2SGreg Kroah-Hartman 206827c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 2069ab4382d2SGreg Kroah-Hartman 2070ab4382d2SGreg Kroah-Hartman *parity = 'n'; 2071ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 2072ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 2073ab4382d2SGreg Kroah-Hartman *parity = 'o'; 2074ab4382d2SGreg Kroah-Hartman else 2075ab4382d2SGreg Kroah-Hartman *parity = 'e'; 2076ab4382d2SGreg Kroah-Hartman } 2077ab4382d2SGreg Kroah-Hartman 2078ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 2079ab4382d2SGreg Kroah-Hartman *bits = 8; 2080ab4382d2SGreg Kroah-Hartman else 2081ab4382d2SGreg Kroah-Hartman *bits = 7; 2082ab4382d2SGreg Kroah-Hartman 208327c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 208427c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2085ab4382d2SGreg Kroah-Hartman 208627c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2087ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 2088ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 2089ab4382d2SGreg Kroah-Hartman else 2090ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 2091ab4382d2SGreg Kroah-Hartman 20923a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2093ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2094ab4382d2SGreg Kroah-Hartman 2095ab4382d2SGreg Kroah-Hartman { /* 2096ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2097ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2098ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2099ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2100ab4382d2SGreg Kroah-Hartman */ 2101ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2102ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2103ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2104ab4382d2SGreg Kroah-Hartman 2105ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2106ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2107ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2108ab4382d2SGreg Kroah-Hartman } 2109ab4382d2SGreg Kroah-Hartman 2110ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 2111f5a9e5f7SFabio Estevam dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2112ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2113ab4382d2SGreg Kroah-Hartman } 2114ab4382d2SGreg Kroah-Hartman } 2115ab4382d2SGreg Kroah-Hartman 21166d0d1b5aSStefan Agner static int 21179d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2118ab4382d2SGreg Kroah-Hartman { 2119ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2120ab4382d2SGreg Kroah-Hartman int baud = 9600; 2121ab4382d2SGreg Kroah-Hartman int bits = 8; 2122ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2123ab4382d2SGreg Kroah-Hartman int flow = 'n'; 21241cf93e0dSHuang Shijie int retval; 2125ab4382d2SGreg Kroah-Hartman 2126ab4382d2SGreg Kroah-Hartman /* 2127ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2128ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2129ab4382d2SGreg Kroah-Hartman * console support. 2130ab4382d2SGreg Kroah-Hartman */ 21319d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2132ab4382d2SGreg Kroah-Hartman co->index = 0; 21339d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2134ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2135ab4382d2SGreg Kroah-Hartman return -ENODEV; 2136ab4382d2SGreg Kroah-Hartman 21371cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 21381cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 21391cf93e0dSHuang Shijie if (retval) 21401cf93e0dSHuang Shijie goto error_console; 21411cf93e0dSHuang Shijie 2142ab4382d2SGreg Kroah-Hartman if (options) 2143ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2144ab4382d2SGreg Kroah-Hartman else 21459d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2146ab4382d2SGreg Kroah-Hartman 21479d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2148ab4382d2SGreg Kroah-Hartman 21491cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 21501cf93e0dSHuang Shijie 21510c727a42SFabio Estevam if (retval) { 2152e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21530c727a42SFabio Estevam goto error_console; 21540c727a42SFabio Estevam } 21550c727a42SFabio Estevam 2156e67c139cSFugang Duan retval = clk_prepare_enable(sport->clk_per); 21570c727a42SFabio Estevam if (retval) 2158e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21591cf93e0dSHuang Shijie 21601cf93e0dSHuang Shijie error_console: 21611cf93e0dSHuang Shijie return retval; 2162ab4382d2SGreg Kroah-Hartman } 2163ab4382d2SGreg Kroah-Hartman 21649768a37cSFrancesco Dolcini static int 21659768a37cSFrancesco Dolcini imx_uart_console_exit(struct console *co) 21669768a37cSFrancesco Dolcini { 21679768a37cSFrancesco Dolcini struct imx_port *sport = imx_uart_ports[co->index]; 21689768a37cSFrancesco Dolcini 21699768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_per); 21709768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_ipg); 21719768a37cSFrancesco Dolcini 21729768a37cSFrancesco Dolcini return 0; 21739768a37cSFrancesco Dolcini } 21749768a37cSFrancesco Dolcini 21759d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 21769d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2177ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 21789d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2179ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 21809d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 21819768a37cSFrancesco Dolcini .exit = imx_uart_console_exit, 2182ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2183ab4382d2SGreg Kroah-Hartman .index = -1, 21849d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2185ab4382d2SGreg Kroah-Hartman }; 2186ab4382d2SGreg Kroah-Hartman 21879d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2188913c6c0eSLucas Stach 2189ab4382d2SGreg Kroah-Hartman #else 2190ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2191ab4382d2SGreg Kroah-Hartman #endif 2192ab4382d2SGreg Kroah-Hartman 21939d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2194ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2195ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2196ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2197ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2198ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21999d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2200ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2201ab4382d2SGreg Kroah-Hartman }; 2202ab4382d2SGreg Kroah-Hartman 2203bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2204cb1a6092SUwe Kleine-König { 2205bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2206cb1a6092SUwe Kleine-König unsigned long flags; 2207cb1a6092SUwe Kleine-König 2208cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2209cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS) 2210cb1a6092SUwe Kleine-König imx_uart_start_tx(&sport->port); 2211cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2212bd78ecd6SAhmad Fatoum 2213bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2214cb1a6092SUwe Kleine-König } 2215cb1a6092SUwe Kleine-König 2216bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2217cb1a6092SUwe Kleine-König { 2218bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2219cb1a6092SUwe Kleine-König unsigned long flags; 2220cb1a6092SUwe Kleine-König 2221cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2222cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_SEND) 2223cb1a6092SUwe Kleine-König imx_uart_stop_tx(&sport->port); 2224cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2225bd78ecd6SAhmad Fatoum 2226bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2227cb1a6092SUwe Kleine-König } 2228cb1a6092SUwe Kleine-König 222900d7a00eSIlpo Järvinen static const struct serial_rs485 imx_no_rs485 = {}; /* No RS485 if no RTS */ 223000d7a00eSIlpo Järvinen static const struct serial_rs485 imx_rs485_supported = { 223100d7a00eSIlpo Järvinen .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 223200d7a00eSIlpo Järvinen SER_RS485_RX_DURING_TX, 223300d7a00eSIlpo Järvinen .delay_rts_before_send = 1, 223400d7a00eSIlpo Järvinen .delay_rts_after_send = 1, 223500d7a00eSIlpo Järvinen }; 223600d7a00eSIlpo Järvinen 2237db0a196bSFabien Lahoudere /* Default RX DMA buffer configuration */ 2238db0a196bSFabien Lahoudere #define RX_DMA_PERIODS 16 2239db0a196bSFabien Lahoudere #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4) 2240db0a196bSFabien Lahoudere 22419d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2242ab4382d2SGreg Kroah-Hartman { 22434661f46eSFabio Estevam struct device_node *np = pdev->dev.of_node; 2244ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2245ab4382d2SGreg Kroah-Hartman void __iomem *base; 2246db0a196bSFabien Lahoudere u32 dma_buf_conf[2]; 22474444dcf1SUwe Kleine-König int ret = 0; 224879d0224fSMarek Vasut u32 ucr1, ucr2, uts; 2249ab4382d2SGreg Kroah-Hartman struct resource *res; 2250842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2251ab4382d2SGreg Kroah-Hartman 225242d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2253ab4382d2SGreg Kroah-Hartman if (!sport) 2254ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2255ab4382d2SGreg Kroah-Hartman 22564661f46eSFabio Estevam sport->devdata = of_device_get_match_data(&pdev->dev); 22574661f46eSFabio Estevam 22584661f46eSFabio Estevam ret = of_alias_get_id(np, "serial"); 22594661f46eSFabio Estevam if (ret < 0) { 22604661f46eSFabio Estevam dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 226142d34191SSachin Kamat return ret; 22624661f46eSFabio Estevam } 22634661f46eSFabio Estevam sport->port.line = ret; 22644661f46eSFabio Estevam 22654661f46eSFabio Estevam if (of_get_property(np, "uart-has-rtscts", NULL) || 22664661f46eSFabio Estevam of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 22674661f46eSFabio Estevam sport->have_rtscts = 1; 22684661f46eSFabio Estevam 22694661f46eSFabio Estevam if (of_get_property(np, "fsl,dte-mode", NULL)) 22704661f46eSFabio Estevam sport->dte_mode = 1; 22714661f46eSFabio Estevam 22724661f46eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 22734661f46eSFabio Estevam sport->have_rtsgpio = 1; 22744661f46eSFabio Estevam 22754661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-tx", NULL)) 22764661f46eSFabio Estevam sport->inverted_tx = 1; 22774661f46eSFabio Estevam 22784661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-rx", NULL)) 22794661f46eSFabio Estevam sport->inverted_rx = 1; 228022698aa2SShawn Guo 2281db0a196bSFabien Lahoudere if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { 2282db0a196bSFabien Lahoudere sport->rx_period_length = dma_buf_conf[0]; 2283db0a196bSFabien Lahoudere sport->rx_periods = dma_buf_conf[1]; 2284db0a196bSFabien Lahoudere } else { 2285db0a196bSFabien Lahoudere sport->rx_period_length = RX_DMA_PERIOD_LEN; 2286db0a196bSFabien Lahoudere sport->rx_periods = RX_DMA_PERIODS; 2287db0a196bSFabien Lahoudere } 2288db0a196bSFabien Lahoudere 22899d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 229056734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 229156734448SGeert Uytterhoeven sport->port.line); 229256734448SGeert Uytterhoeven return -EINVAL; 229356734448SGeert Uytterhoeven } 229456734448SGeert Uytterhoeven 2295ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2296da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2297da82f997SAlexander Shiyan if (IS_ERR(base)) 2298da82f997SAlexander Shiyan return PTR_ERR(base); 2299ab4382d2SGreg Kroah-Hartman 2300842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2301aa49d8e8SAnson Huang if (rxirq < 0) 2302aa49d8e8SAnson Huang return rxirq; 230331a8d8faSAnson Huang txirq = platform_get_irq_optional(pdev, 1); 230431a8d8faSAnson Huang rtsirq = platform_get_irq_optional(pdev, 2); 2305842633bdSUwe Kleine-König 2306ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2307ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2308ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 23095b109564SZheng Yongjun sport->port.type = PORT_IMX; 2310ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2311842633bdSUwe Kleine-König sport->port.irq = rxirq; 2312ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2313aa3479d2SDmitry Safonov sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 23149d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 23159d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 231600d7a00eSIlpo Järvinen /* RTS is required to control the RS485 transmitter */ 231700d7a00eSIlpo Järvinen if (sport->have_rtscts || sport->have_rtsgpio) 23180139da50SIlpo Järvinen sport->port.rs485_supported = imx_rs485_supported; 231900d7a00eSIlpo Järvinen else 23200139da50SIlpo Järvinen sport->port.rs485_supported = imx_no_rs485; 2321ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 23229d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2323ab4382d2SGreg Kroah-Hartman 232458362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 232558362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 232658362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 232758362d5bSUwe Kleine-König 23283a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 23293a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 23303a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2331833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 233242d34191SSachin Kamat return ret; 2333ab4382d2SGreg Kroah-Hartman } 2334ab4382d2SGreg Kroah-Hartman 23353a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 23363a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 23373a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2338833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 233942d34191SSachin Kamat return ret; 23403a9465faSSascha Hauer } 23413a9465faSSascha Hauer 23423a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2343ab4382d2SGreg Kroah-Hartman 23448a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 23458a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 23461e512d45SUwe Kleine-König if (ret) { 23471e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 23488a61f0c7SFabio Estevam return ret; 23491e512d45SUwe Kleine-König } 23508a61f0c7SFabio Estevam 23513a0ab62fSUwe Kleine-König /* initialize shadow register values */ 23523a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 23533a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 23543a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 23553a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 23563a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 23573a0ab62fSUwe Kleine-König 2358c150c0f3SLukas Wunner ret = uart_get_rs485_mode(&sport->port); 2359c150c0f3SLukas Wunner if (ret) { 2360c150c0f3SLukas Wunner clk_disable_unprepare(sport->clk_ipg); 2361c150c0f3SLukas Wunner return ret; 2362c150c0f3SLukas Wunner } 2363743f93f8SLukas Wunner 2364b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23655d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2366b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2367b8f3bff0SLukas Wunner 23686d215f83SStefan Agner /* 23696d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 23706d215f83SStefan Agner * signal cannot be set low during transmission in case the 23716d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 23726d215f83SStefan Agner */ 23736d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23746d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 23756d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 23766d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 23776d215f83SStefan Agner dev_err(&pdev->dev, 23786d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 23796d215f83SStefan Agner 23808a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 23814444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 23825f0e708cSYe Bin ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 23834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 23848a61f0c7SFabio Estevam 2385ef25e16eSPeng Fan /* Disable Ageing Timer interrupt */ 2386ef25e16eSPeng Fan ucr2 = imx_uart_readl(sport, UCR2); 2387ef25e16eSPeng Fan ucr2 &= ~UCR2_ATEN; 2388ef25e16eSPeng Fan imx_uart_writel(sport, ucr2, UCR2); 2389ef25e16eSPeng Fan 239079d0224fSMarek Vasut /* 239179d0224fSMarek Vasut * In case RS485 is enabled without GPIO RTS control, the UART IP 239279d0224fSMarek Vasut * is used to control CTS signal. Keep both the UART and Receiver 239379d0224fSMarek Vasut * enabled, otherwise the UART IP pulls CTS signal always HIGH no 239479d0224fSMarek Vasut * matter how the UCR2 CTSC and CTS bits are set. To prevent any 239579d0224fSMarek Vasut * data from being fed into the RX FIFO, enable loopback mode in 239679d0224fSMarek Vasut * UTS register, which disconnects the RX path from external RXD 239779d0224fSMarek Vasut * pin and connects it to the Transceiver, which is disabled, so 239879d0224fSMarek Vasut * no data can be fed to the RX FIFO that way. 239979d0224fSMarek Vasut */ 240079d0224fSMarek Vasut if (sport->port.rs485.flags & SER_RS485_ENABLED && 240179d0224fSMarek Vasut sport->have_rtscts && !sport->have_rtsgpio) { 240279d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 240379d0224fSMarek Vasut uts |= UTS_LOOP; 240479d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 240579d0224fSMarek Vasut 240679d0224fSMarek Vasut ucr1 = imx_uart_readl(sport, UCR1); 240779d0224fSMarek Vasut ucr1 |= UCR1_UARTEN; 240879d0224fSMarek Vasut imx_uart_writel(sport, ucr1, UCR1); 240979d0224fSMarek Vasut 241079d0224fSMarek Vasut ucr2 = imx_uart_readl(sport, UCR2); 241179d0224fSMarek Vasut ucr2 |= UCR2_RXEN; 241279d0224fSMarek Vasut imx_uart_writel(sport, ucr2, UCR2); 241379d0224fSMarek Vasut } 241479d0224fSMarek Vasut 24159d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2416e61c38d8SUwe Kleine-König /* 2417e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2418e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2419e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2420e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2421e61c38d8SUwe Kleine-König */ 24224444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 24234444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 24244444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2425e61c38d8SUwe Kleine-König 2426e61c38d8SUwe Kleine-König /* 2427e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2428e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2429e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2430e61c38d8SUwe Kleine-König */ 243127c84426SUwe Kleine-König imx_uart_writel(sport, 243227c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 243327c84426SUwe Kleine-König UCR3); 2434e61c38d8SUwe Kleine-König 2435e61c38d8SUwe Kleine-König } else { 24364444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 24374444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 24384444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 24394444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 24406df765dcSUwe Kleine-König 24419d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 24426df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 244327c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2444e61c38d8SUwe Kleine-König } 2445e61c38d8SUwe Kleine-König 24468a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 24478a61f0c7SFabio Estevam 2448bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2449bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2450bd78ecd6SAhmad Fatoum sport->trigger_start_tx.function = imx_trigger_start_tx; 2451bd78ecd6SAhmad Fatoum sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2452cb1a6092SUwe Kleine-König 2453c0d1c6b0SFabio Estevam /* 2454c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2455c0d1c6b0SFabio Estevam * chips only have one interrupt. 2456c0d1c6b0SFabio Estevam */ 2457842633bdSUwe Kleine-König if (txirq > 0) { 24589d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2459c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24601e512d45SUwe Kleine-König if (ret) { 24611e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 24621e512d45SUwe Kleine-König ret); 2463c0d1c6b0SFabio Estevam return ret; 24641e512d45SUwe Kleine-König } 2465c0d1c6b0SFabio Estevam 24669d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2467c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24681e512d45SUwe Kleine-König if (ret) { 24691e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 24701e512d45SUwe Kleine-König ret); 2471c0d1c6b0SFabio Estevam return ret; 24721e512d45SUwe Kleine-König } 24737e620984SUwe Kleine-König 24747e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 24757e620984SUwe Kleine-König dev_name(&pdev->dev), sport); 24767e620984SUwe Kleine-König if (ret) { 24777e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n", 24787e620984SUwe Kleine-König ret); 24797e620984SUwe Kleine-König return ret; 24807e620984SUwe Kleine-König } 2481c0d1c6b0SFabio Estevam } else { 24829d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2483c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24841e512d45SUwe Kleine-König if (ret) { 24851e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2486c0d1c6b0SFabio Estevam return ret; 2487c0d1c6b0SFabio Estevam } 24881e512d45SUwe Kleine-König } 2489c0d1c6b0SFabio Estevam 24909d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2491ab4382d2SGreg Kroah-Hartman 24920a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2493ab4382d2SGreg Kroah-Hartman 24949d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2495ab4382d2SGreg Kroah-Hartman } 2496ab4382d2SGreg Kroah-Hartman 24979d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2498ab4382d2SGreg Kroah-Hartman { 2499ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2500ab4382d2SGreg Kroah-Hartman 25019d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2502ab4382d2SGreg Kroah-Hartman } 2503ab4382d2SGreg Kroah-Hartman 25049d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2505c868cbb7SEduardo Valentin { 250607b5e16eSAnson Huang unsigned long flags; 250707b5e16eSAnson Huang 250807b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 250907b5e16eSAnson Huang if (!sport->context_saved) { 251007b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2511c868cbb7SEduardo Valentin return; 251207b5e16eSAnson Huang } 2513c868cbb7SEduardo Valentin 251427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 251527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 251627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 251727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 251827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 251927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 252027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 252127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 252227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 252327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2524c868cbb7SEduardo Valentin sport->context_saved = false; 252507b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2526c868cbb7SEduardo Valentin } 2527c868cbb7SEduardo Valentin 25289d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2529c868cbb7SEduardo Valentin { 253007b5e16eSAnson Huang unsigned long flags; 253107b5e16eSAnson Huang 2532c868cbb7SEduardo Valentin /* Save necessary regs */ 253307b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 253427c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 253527c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 253627c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 253727c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 253827c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 253927c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 254027c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 254127c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 254227c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 254327c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2544c868cbb7SEduardo Valentin sport->context_saved = true; 254507b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2546c868cbb7SEduardo Valentin } 2547c868cbb7SEduardo Valentin 25489d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2549189550b8SEduardo Valentin { 25504444dcf1SUwe Kleine-König u32 ucr3; 2551189550b8SEduardo Valentin 25524444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 255309df0b34SMartin Kaiser if (on) { 255427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 25554444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 25564444dcf1SUwe Kleine-König } else { 25574444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 255809df0b34SMartin Kaiser } 25594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2560bc85734bSEduardo Valentin 256138b1f0fbSFabio Estevam if (sport->have_rtscts) { 25624444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2563c67643b4SFugang Duan if (on) { 2564c67643b4SFugang Duan imx_uart_writel(sport, USR1_RTSD, USR1); 25654444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2566c67643b4SFugang Duan } else { 25674444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 2568c67643b4SFugang Duan } 25694444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2570189550b8SEduardo Valentin } 257138b1f0fbSFabio Estevam } 2572189550b8SEduardo Valentin 25739d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 257490bb6bd3SShenwei Wang { 2575a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 257690bb6bd3SShenwei Wang 25779d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 257890bb6bd3SShenwei Wang 257990bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 258090bb6bd3SShenwei Wang 2581fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev); 2582fcfed1beSAnson Huang 258390bb6bd3SShenwei Wang return 0; 258490bb6bd3SShenwei Wang } 258590bb6bd3SShenwei Wang 25869d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 258790bb6bd3SShenwei Wang { 2588a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 258990bb6bd3SShenwei Wang int ret; 259090bb6bd3SShenwei Wang 2591fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev); 2592fcfed1beSAnson Huang 259390bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 259490bb6bd3SShenwei Wang if (ret) 259590bb6bd3SShenwei Wang return ret; 259690bb6bd3SShenwei Wang 25979d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 259890bb6bd3SShenwei Wang 259990bb6bd3SShenwei Wang return 0; 260090bb6bd3SShenwei Wang } 260190bb6bd3SShenwei Wang 26029d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 260390bb6bd3SShenwei Wang { 2604a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 260509df0b34SMartin Kaiser int ret; 260690bb6bd3SShenwei Wang 26079d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 260881b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 260990bb6bd3SShenwei Wang 261009df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 261109df0b34SMartin Kaiser if (ret) 261209df0b34SMartin Kaiser return ret; 261309df0b34SMartin Kaiser 261409df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 26159d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 261609df0b34SMartin Kaiser 261709df0b34SMartin Kaiser return 0; 261890bb6bd3SShenwei Wang } 261990bb6bd3SShenwei Wang 26209d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 262190bb6bd3SShenwei Wang { 2622a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 262390bb6bd3SShenwei Wang 262490bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 26259d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 262690bb6bd3SShenwei Wang 26279d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 262881b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 262990bb6bd3SShenwei Wang 263009df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 263129add68dSMartin Fuzzey 263290bb6bd3SShenwei Wang return 0; 263390bb6bd3SShenwei Wang } 263490bb6bd3SShenwei Wang 26359d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 263694be6d74SPhilipp Zabel { 2637a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 263894be6d74SPhilipp Zabel 26399d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 264094be6d74SPhilipp Zabel 264109df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 264294be6d74SPhilipp Zabel } 264394be6d74SPhilipp Zabel 26449d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 264594be6d74SPhilipp Zabel { 2646a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 264794be6d74SPhilipp Zabel 26489d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 264994be6d74SPhilipp Zabel 265009df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 265194be6d74SPhilipp Zabel 265294be6d74SPhilipp Zabel return 0; 265394be6d74SPhilipp Zabel } 265494be6d74SPhilipp Zabel 26559d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 26569d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 26579d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 26589d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 26594561d800SShawn Guo .thaw_noirq = imx_uart_resume_noirq, 26609d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 26619d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 26629d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 26639d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 26649d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 26659d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 266690bb6bd3SShenwei Wang }; 266790bb6bd3SShenwei Wang 26689d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 26699d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 26709d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2671ab4382d2SGreg Kroah-Hartman 2672ab4382d2SGreg Kroah-Hartman .driver = { 2673ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 267422698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 26759d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2676ab4382d2SGreg Kroah-Hartman }, 2677ab4382d2SGreg Kroah-Hartman }; 2678ab4382d2SGreg Kroah-Hartman 26799d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2680ab4382d2SGreg Kroah-Hartman { 26819d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2682ab4382d2SGreg Kroah-Hartman 2683ab4382d2SGreg Kroah-Hartman if (ret) 2684ab4382d2SGreg Kroah-Hartman return ret; 2685ab4382d2SGreg Kroah-Hartman 26869d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2687ab4382d2SGreg Kroah-Hartman if (ret != 0) 26889d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2689ab4382d2SGreg Kroah-Hartman 2690f227824eSUwe Kleine-König return ret; 2691ab4382d2SGreg Kroah-Hartman } 2692ab4382d2SGreg Kroah-Hartman 26939d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2694ab4382d2SGreg Kroah-Hartman { 26959d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 26969d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2697ab4382d2SGreg Kroah-Hartman } 2698ab4382d2SGreg Kroah-Hartman 26999d1a50a2SUwe Kleine-König module_init(imx_uart_init); 27009d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2701ab4382d2SGreg Kroah-Hartman 2702ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2703ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2704ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2705ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2706