1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 12ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 13ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 14ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 15ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 23bd78ecd6SAhmad Fatoum #include <linux/ktime.h> 24fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2722698aa2SShawn Guo #include <linux/of.h> 2822698aa2SShawn Guo #include <linux/of_device.h> 29e32a9f8fSSachin Kamat #include <linux/io.h> 30b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 31ab4382d2SGreg Kroah-Hartman 32ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 33c6547c2eSSascha Hauer #include <linux/dma/imx-dma.h> 34ab4382d2SGreg Kroah-Hartman 3558362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3658362d5bSUwe Kleine-König 37ab4382d2SGreg Kroah-Hartman /* Register definitions */ 38ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 39ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 40ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 41ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 42ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 43ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 44ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 45ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 46ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 47ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 48ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 49ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 50ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 51ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 52fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 53fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 54fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 55ab4382d2SGreg Kroah-Hartman 56ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 5755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 58ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 59ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 60ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 61ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 62ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 63ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 66ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 67ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 68ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 69b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 71302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 72ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 76302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 77fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 78b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 81ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 83ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 95ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 96ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 97ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 101b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10527e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 106fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 110ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 111ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 115b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1227be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 123ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 125ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 126ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 127ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 128ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 129ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 130ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 131ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13386a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13427e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 136ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 137ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 138ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 139ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 140ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14290ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14390ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14690ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 149ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 150ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 151ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 152ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 153ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 154ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 155ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 156ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 157ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 158ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 159ab4382d2SGreg Kroah-Hartman 160ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 161ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 162ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 163ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 164ab4382d2SGreg Kroah-Hartman 165ab4382d2SGreg Kroah-Hartman /* 166ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 167ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 168ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 169ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 170ab4382d2SGreg Kroah-Hartman */ 171ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 172ab4382d2SGreg Kroah-Hartman 173ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 174ab4382d2SGreg Kroah-Hartman 175ab4382d2SGreg Kroah-Hartman #define UART_NR 8 176ab4382d2SGreg Kroah-Hartman 177f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 178fe6b540aSShawn Guo enum imx_uart_type { 179fe6b540aSShawn Guo IMX1_UART, 180fe6b540aSShawn Guo IMX21_UART, 1811c06bde6SMartyn Welch IMX53_UART, 182a496e628SHuang Shijie IMX6Q_UART, 183fe6b540aSShawn Guo }; 184fe6b540aSShawn Guo 185fe6b540aSShawn Guo /* device type dependent stuff */ 186fe6b540aSShawn Guo struct imx_uart_data { 187fe6b540aSShawn Guo unsigned uts_reg; 188fe6b540aSShawn Guo enum imx_uart_type devtype; 189fe6b540aSShawn Guo }; 190fe6b540aSShawn Guo 191cb1a6092SUwe Kleine-König enum imx_tx_state { 192cb1a6092SUwe Kleine-König OFF, 193cb1a6092SUwe Kleine-König WAIT_AFTER_RTS, 194cb1a6092SUwe Kleine-König SEND, 195cb1a6092SUwe Kleine-König WAIT_AFTER_SEND, 196cb1a6092SUwe Kleine-König }; 197cb1a6092SUwe Kleine-König 198ab4382d2SGreg Kroah-Hartman struct imx_port { 199ab4382d2SGreg Kroah-Hartman struct uart_port port; 200ab4382d2SGreg Kroah-Hartman struct timer_list timer; 201ab4382d2SGreg Kroah-Hartman unsigned int old_status; 202ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2037b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20420ff2fe6SHuang Shijie unsigned int dte_mode:1; 2055a08a487SGeorge Hilliard unsigned int inverted_tx:1; 2065a08a487SGeorge Hilliard unsigned int inverted_rx:1; 2073a9465faSSascha Hauer struct clk *clk_ipg; 2083a9465faSSascha Hauer struct clk *clk_per; 2097d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 210b4cdc8f6SHuang Shijie 21158362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21258362d5bSUwe Kleine-König 2133a0ab62fSUwe Kleine-König /* shadow registers */ 2143a0ab62fSUwe Kleine-König unsigned int ucr1; 2153a0ab62fSUwe Kleine-König unsigned int ucr2; 2163a0ab62fSUwe Kleine-König unsigned int ucr3; 2173a0ab62fSUwe Kleine-König unsigned int ucr4; 2183a0ab62fSUwe Kleine-König unsigned int ufcr; 2193a0ab62fSUwe Kleine-König 220b4cdc8f6SHuang Shijie /* DMA fields */ 221b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 224b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 225b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 226b4cdc8f6SHuang Shijie void *rx_buf; 2279d297239SNandor Han struct circ_buf rx_ring; 228db0a196bSFabien Lahoudere unsigned int rx_buf_size; 229db0a196bSFabien Lahoudere unsigned int rx_period_length; 2309d297239SNandor Han unsigned int rx_periods; 2319d297239SNandor Han dma_cookie_t rx_cookie; 2327cb92fd2SHuang Shijie unsigned int tx_bytes; 233b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 23490bb6bd3SShenwei Wang unsigned int saved_reg[10]; 235c868cbb7SEduardo Valentin bool context_saved; 236cb1a6092SUwe Kleine-König 237cb1a6092SUwe Kleine-König enum imx_tx_state tx_state; 238bd78ecd6SAhmad Fatoum struct hrtimer trigger_start_tx; 239bd78ecd6SAhmad Fatoum struct hrtimer trigger_stop_tx; 240ab4382d2SGreg Kroah-Hartman }; 241ab4382d2SGreg Kroah-Hartman 2420ad5a814SDirk Behme struct imx_port_ucrs { 2430ad5a814SDirk Behme unsigned int ucr1; 2440ad5a814SDirk Behme unsigned int ucr2; 2450ad5a814SDirk Behme unsigned int ucr3; 2460ad5a814SDirk Behme }; 2470ad5a814SDirk Behme 248fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 249fe6b540aSShawn Guo [IMX1_UART] = { 250fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 251fe6b540aSShawn Guo .devtype = IMX1_UART, 252fe6b540aSShawn Guo }, 253fe6b540aSShawn Guo [IMX21_UART] = { 254fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 255fe6b540aSShawn Guo .devtype = IMX21_UART, 256fe6b540aSShawn Guo }, 2571c06bde6SMartyn Welch [IMX53_UART] = { 2581c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2591c06bde6SMartyn Welch .devtype = IMX53_UART, 2601c06bde6SMartyn Welch }, 261a496e628SHuang Shijie [IMX6Q_UART] = { 262a496e628SHuang Shijie .uts_reg = IMX21_UTS, 263a496e628SHuang Shijie .devtype = IMX6Q_UART, 264a496e628SHuang Shijie }, 265fe6b540aSShawn Guo }; 266fe6b540aSShawn Guo 267ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 268a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2691c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27022698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27122698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27222698aa2SShawn Guo { /* sentinel */ } 27322698aa2SShawn Guo }; 27422698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27522698aa2SShawn Guo 27627c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 27727c84426SUwe Kleine-König { 2783a0ab62fSUwe Kleine-König switch (offset) { 2793a0ab62fSUwe Kleine-König case UCR1: 2803a0ab62fSUwe Kleine-König sport->ucr1 = val; 2813a0ab62fSUwe Kleine-König break; 2823a0ab62fSUwe Kleine-König case UCR2: 2833a0ab62fSUwe Kleine-König sport->ucr2 = val; 2843a0ab62fSUwe Kleine-König break; 2853a0ab62fSUwe Kleine-König case UCR3: 2863a0ab62fSUwe Kleine-König sport->ucr3 = val; 2873a0ab62fSUwe Kleine-König break; 2883a0ab62fSUwe Kleine-König case UCR4: 2893a0ab62fSUwe Kleine-König sport->ucr4 = val; 2903a0ab62fSUwe Kleine-König break; 2913a0ab62fSUwe Kleine-König case UFCR: 2923a0ab62fSUwe Kleine-König sport->ufcr = val; 2933a0ab62fSUwe Kleine-König break; 2943a0ab62fSUwe Kleine-König default: 2953a0ab62fSUwe Kleine-König break; 2963a0ab62fSUwe Kleine-König } 29727c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 29827c84426SUwe Kleine-König } 29927c84426SUwe Kleine-König 30027c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30127c84426SUwe Kleine-König { 3023a0ab62fSUwe Kleine-König switch (offset) { 3033a0ab62fSUwe Kleine-König case UCR1: 3043a0ab62fSUwe Kleine-König return sport->ucr1; 3053a0ab62fSUwe Kleine-König break; 3063a0ab62fSUwe Kleine-König case UCR2: 3073a0ab62fSUwe Kleine-König /* 3083a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3093a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 310728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 311728e74a4SUwe Kleine-König * conditionally. 3123a0ab62fSUwe Kleine-König */ 3130aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3143a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3153a0ab62fSUwe Kleine-König return sport->ucr2; 3163a0ab62fSUwe Kleine-König break; 3173a0ab62fSUwe Kleine-König case UCR3: 3183a0ab62fSUwe Kleine-König return sport->ucr3; 3193a0ab62fSUwe Kleine-König break; 3203a0ab62fSUwe Kleine-König case UCR4: 3213a0ab62fSUwe Kleine-König return sport->ucr4; 3223a0ab62fSUwe Kleine-König break; 3233a0ab62fSUwe Kleine-König case UFCR: 3243a0ab62fSUwe Kleine-König return sport->ufcr; 3253a0ab62fSUwe Kleine-König break; 3263a0ab62fSUwe Kleine-König default: 32727c84426SUwe Kleine-König return readl(sport->port.membase + offset); 32827c84426SUwe Kleine-König } 3293a0ab62fSUwe Kleine-König } 33027c84426SUwe Kleine-König 3319d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 332fe6b540aSShawn Guo { 333fe6b540aSShawn Guo return sport->devdata->uts_reg; 334fe6b540aSShawn Guo } 335fe6b540aSShawn Guo 3369d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 337fe6b540aSShawn Guo { 338fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 339fe6b540aSShawn Guo } 340fe6b540aSShawn Guo 3419d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 342fe6b540aSShawn Guo { 343fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 344fe6b540aSShawn Guo } 345fe6b540aSShawn Guo 3469d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3471c06bde6SMartyn Welch { 3481c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3491c06bde6SMartyn Welch } 3501c06bde6SMartyn Welch 3519d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 352a496e628SHuang Shijie { 353a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 354a496e628SHuang Shijie } 355ab4382d2SGreg Kroah-Hartman /* 35644a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 35744a75411Sfabio.estevam@freescale.com */ 3580db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 3599d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 36044a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36144a75411Sfabio.estevam@freescale.com { 36244a75411Sfabio.estevam@freescale.com /* save control registers */ 36327c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 36427c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 36527c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 36644a75411Sfabio.estevam@freescale.com } 36744a75411Sfabio.estevam@freescale.com 3689d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 36944a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37044a75411Sfabio.estevam@freescale.com { 37144a75411Sfabio.estevam@freescale.com /* restore control registers */ 37227c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 37327c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 37427c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 37544a75411Sfabio.estevam@freescale.com } 376e8bfa760SFabio Estevam #endif 37744a75411Sfabio.estevam@freescale.com 3784e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3799d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 38058362d5bSUwe Kleine-König { 381bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38258362d5bSUwe Kleine-König 3837c7f9bc9SLukas Wunner mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); 38458362d5bSUwe Kleine-König } 38558362d5bSUwe Kleine-König 3864e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3879d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 38858362d5bSUwe Kleine-König { 389bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 390bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39158362d5bSUwe Kleine-König 3927c7f9bc9SLukas Wunner mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); 39358362d5bSUwe Kleine-König } 39458362d5bSUwe Kleine-König 395bd78ecd6SAhmad Fatoum static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 396bd78ecd6SAhmad Fatoum { 397f751ae1cSJiri Slaby hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 398bd78ecd6SAhmad Fatoum } 399bd78ecd6SAhmad Fatoum 4006aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4019d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 40276821e22SUwe Kleine-König { 40376821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 40476821e22SUwe Kleine-König unsigned int ucr1, ucr2; 40576821e22SUwe Kleine-König 40676821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 40776821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 40876821e22SUwe Kleine-König 40976821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41076821e22SUwe Kleine-König 41176821e22SUwe Kleine-König if (sport->dma_is_enabled) { 41276821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 41376821e22SUwe Kleine-König } else { 41476821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 41581ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 41676821e22SUwe Kleine-König } 41776821e22SUwe Kleine-König 41876821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 41976821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42076821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42176821e22SUwe Kleine-König } 42276821e22SUwe Kleine-König 42376821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4249d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 425ab4382d2SGreg Kroah-Hartman { 426ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 427cb1a6092SUwe Kleine-König u32 ucr1, ucr4, usr2; 428cb1a6092SUwe Kleine-König 429cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) 430cb1a6092SUwe Kleine-König return; 431ab4382d2SGreg Kroah-Hartman 4329ce4f8f3SGreg Kroah-Hartman /* 4339ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4349ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4359ce4f8f3SGreg Kroah-Hartman */ 436686351f3SUwe Kleine-König if (sport->dma_is_txing) 4379ce4f8f3SGreg Kroah-Hartman return; 438b4cdc8f6SHuang Shijie 4394444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 440c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 44117b8f2a3SUwe Kleine-König 442cb1a6092SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 443cb1a6092SUwe Kleine-König if (!(usr2 & USR2_TXDC)) { 444cb1a6092SUwe Kleine-König /* The shifter is still busy, so retry once TC triggers */ 445cb1a6092SUwe Kleine-König return; 446cb1a6092SUwe Kleine-König } 447cb1a6092SUwe Kleine-König 448cb1a6092SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 449cb1a6092SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 450cb1a6092SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 451cb1a6092SUwe Kleine-König 452cb1a6092SUwe Kleine-König /* in rs485 mode disable transmitter */ 453cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 454cb1a6092SUwe Kleine-König if (sport->tx_state == SEND) { 455cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_SEND; 456582e9a24SHarald Seiler 457582e9a24SHarald Seiler if (port->rs485.delay_rts_after_send > 0) { 458bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_stop_tx, 459bd78ecd6SAhmad Fatoum port->rs485.delay_rts_after_send); 460bd78ecd6SAhmad Fatoum return; 461cb1a6092SUwe Kleine-König } 462cb1a6092SUwe Kleine-König 463582e9a24SHarald Seiler /* continue without any delay */ 464582e9a24SHarald Seiler } 465582e9a24SHarald Seiler 466cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS || 467bd78ecd6SAhmad Fatoum sport->tx_state == WAIT_AFTER_SEND) { 468cb1a6092SUwe Kleine-König u32 ucr2; 469cb1a6092SUwe Kleine-König 470bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_start_tx); 471cb1a6092SUwe Kleine-König 472cb1a6092SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 47317b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4749d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4751a613626SFabio Estevam else 4769d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4774444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 47817b8f2a3SUwe Kleine-König 479*ca530cfaSChristoph Niedermaier if (!port->rs485_rx_during_tx_gpio) 4809d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 48176821e22SUwe Kleine-König 482cb1a6092SUwe Kleine-König sport->tx_state = OFF; 483cb1a6092SUwe Kleine-König } 484cb1a6092SUwe Kleine-König } else { 485cb1a6092SUwe Kleine-König sport->tx_state = OFF; 48617b8f2a3SUwe Kleine-König } 487ab4382d2SGreg Kroah-Hartman } 488ab4382d2SGreg Kroah-Hartman 4896aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4909d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 491ab4382d2SGreg Kroah-Hartman { 492ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 49379d0224fSMarek Vasut u32 ucr1, ucr2, ucr4, uts; 494ab4382d2SGreg Kroah-Hartman 4954444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 49676821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 497028e0838SFugang Duan ucr4 = imx_uart_readl(sport, UCR4); 49876821e22SUwe Kleine-König 49976821e22SUwe Kleine-König if (sport->dma_is_enabled) { 50076821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 50176821e22SUwe Kleine-König } else { 50276821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 50381ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 504028e0838SFugang Duan ucr4 &= ~UCR4_OREN; 50576821e22SUwe Kleine-König } 50676821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 507028e0838SFugang Duan imx_uart_writel(sport, ucr4, UCR4); 50876821e22SUwe Kleine-König 50979d0224fSMarek Vasut /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 51079d0224fSMarek Vasut if (port->rs485.flags & SER_RS485_ENABLED && 51179d0224fSMarek Vasut port->rs485.flags & SER_RS485_RTS_ON_SEND && 51279d0224fSMarek Vasut sport->have_rtscts && !sport->have_rtsgpio) { 51379d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 51479d0224fSMarek Vasut uts |= UTS_LOOP; 51579d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 51679d0224fSMarek Vasut ucr2 |= UCR2_RXEN; 51779d0224fSMarek Vasut } else { 51876821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 51979d0224fSMarek Vasut } 52079d0224fSMarek Vasut 52176821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 522ab4382d2SGreg Kroah-Hartman } 523ab4382d2SGreg Kroah-Hartman 5246aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5259d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 526ab4382d2SGreg Kroah-Hartman { 527ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 528ab4382d2SGreg Kroah-Hartman 529ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 53058362d5bSUwe Kleine-König 53158362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 532ab4382d2SGreg Kroah-Hartman } 533ab4382d2SGreg Kroah-Hartman 5349d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 5356aed2a88SUwe Kleine-König 5366aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5379d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 538ab4382d2SGreg Kroah-Hartman { 539ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 540ab4382d2SGreg Kroah-Hartman 5415e42e9a3SPeter Hurley if (sport->port.x_char) { 5425e42e9a3SPeter Hurley /* Send next char */ 54327c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5447e2fb5aaSJiada Wang sport->port.icount.tx++; 5457e2fb5aaSJiada Wang sport->port.x_char = 0; 5465e42e9a3SPeter Hurley return; 5475e42e9a3SPeter Hurley } 5485e42e9a3SPeter Hurley 5495e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5509d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5515e42e9a3SPeter Hurley return; 5525e42e9a3SPeter Hurley } 5535e42e9a3SPeter Hurley 55491a1a909SJiada Wang if (sport->dma_is_enabled) { 5554444dcf1SUwe Kleine-König u32 ucr1; 55691a1a909SJiada Wang /* 55791a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 55891a1a909SJiada Wang * and the TX IRQ is disabled. 55991a1a909SJiada Wang **/ 5604444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 561c514a6f8SSergey Organov ucr1 &= ~UCR1_TRDYEN; 56291a1a909SJiada Wang if (sport->dma_is_txing) { 5634444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5644444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 56591a1a909SJiada Wang } else { 5664444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5679d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 56891a1a909SJiada Wang } 56991a1a909SJiada Wang 5705aabd3b0SIan Jamison return; 5710c549223SUwe Kleine-König } 5725aabd3b0SIan Jamison 5735aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5749d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 575ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 576ab4382d2SGreg Kroah-Hartman * out the port here */ 57727c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 57826e8f1d9SIlpo Järvinen uart_xmit_advance(&sport->port, 1); 579ab4382d2SGreg Kroah-Hartman } 580ab4382d2SGreg Kroah-Hartman 581ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 582ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 583ab4382d2SGreg Kroah-Hartman 584ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5859d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 586ab4382d2SGreg Kroah-Hartman } 587ab4382d2SGreg Kroah-Hartman 5889d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 589b4cdc8f6SHuang Shijie { 590b4cdc8f6SHuang Shijie struct imx_port *sport = data; 591b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 592b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 593b4cdc8f6SHuang Shijie unsigned long flags; 5944444dcf1SUwe Kleine-König u32 ucr1; 595b4cdc8f6SHuang Shijie 59642f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 59742f752b3SDirk Behme 598b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 599b4cdc8f6SHuang Shijie 6004444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6014444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 6024444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 603a2c718ceSDirk Behme 60426e8f1d9SIlpo Järvinen uart_xmit_advance(&sport->port, sport->tx_bytes); 60542f752b3SDirk Behme 60642f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 60742f752b3SDirk Behme 608b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 609b4cdc8f6SHuang Shijie 610d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 611b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 6129ce4f8f3SGreg Kroah-Hartman 6130bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 6149d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 61518665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 61618665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 61718665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 61818665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 61918665414SUwe Kleine-König } 62064432a85SUwe Kleine-König 6210bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 622b4cdc8f6SHuang Shijie } 623b4cdc8f6SHuang Shijie 6246aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6259d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 626b4cdc8f6SHuang Shijie { 627b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 628b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 629b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 630b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 631b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 63218665414SUwe Kleine-König u32 ucr1, ucr4; 633b4cdc8f6SHuang Shijie int ret; 634b4cdc8f6SHuang Shijie 63542f752b3SDirk Behme if (sport->dma_is_txing) 636b4cdc8f6SHuang Shijie return; 637b4cdc8f6SHuang Shijie 63818665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 63918665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 64018665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 64118665414SUwe Kleine-König 642b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 643b4cdc8f6SHuang Shijie 644f7670783SFugang Duan if (xmit->tail < xmit->head || xmit->head == 0) { 6457942f857SDirk Behme sport->dma_tx_nents = 1; 6467942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6477942f857SDirk Behme } else { 648b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 649b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 650b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 651b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 652b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 653b4cdc8f6SHuang Shijie } 654b4cdc8f6SHuang Shijie 655b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 656b4cdc8f6SHuang Shijie if (ret == 0) { 657b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 658b4cdc8f6SHuang Shijie return; 659b4cdc8f6SHuang Shijie } 660596fd8dfSPeng Fan desc = dmaengine_prep_slave_sg(chan, sgl, ret, 661b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 662b4cdc8f6SHuang Shijie if (!desc) { 66324649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 66424649821SDirk Behme DMA_TO_DEVICE); 665b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 666b4cdc8f6SHuang Shijie return; 667b4cdc8f6SHuang Shijie } 6689d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 669b4cdc8f6SHuang Shijie desc->callback_param = sport; 670b4cdc8f6SHuang Shijie 671b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 672b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 673a2c718ceSDirk Behme 6744444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6754444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6764444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 677a2c718ceSDirk Behme 678b4cdc8f6SHuang Shijie /* fire it */ 679b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 680b4cdc8f6SHuang Shijie dmaengine_submit(desc); 681b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 682b4cdc8f6SHuang Shijie return; 683b4cdc8f6SHuang Shijie } 684b4cdc8f6SHuang Shijie 6856aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6869d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 687ab4382d2SGreg Kroah-Hartman { 688ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6894444dcf1SUwe Kleine-König u32 ucr1; 690ab4382d2SGreg Kroah-Hartman 69148669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 69248669b69SUwe Kleine-König return; 69348669b69SUwe Kleine-König 694cb1a6092SUwe Kleine-König /* 695cb1a6092SUwe Kleine-König * We cannot simply do nothing here if sport->tx_state == SEND already 696cb1a6092SUwe Kleine-König * because UCR1_TXMPTYEN might already have been cleared in 697cb1a6092SUwe Kleine-König * imx_uart_stop_tx(), but tx_state is still SEND. 698cb1a6092SUwe Kleine-König */ 6994444dcf1SUwe Kleine-König 700cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 701cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) { 702cb1a6092SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2); 70317b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 7049d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 7051a613626SFabio Estevam else 7069d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 7074444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 70817b8f2a3SUwe Kleine-König 709*ca530cfaSChristoph Niedermaier if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && 710*ca530cfaSChristoph Niedermaier !port->rs485_rx_during_tx_gpio) 7119d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 71276821e22SUwe Kleine-König 713cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_RTS; 714582e9a24SHarald Seiler 715582e9a24SHarald Seiler if (port->rs485.delay_rts_before_send > 0) { 716bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_start_tx, 717bd78ecd6SAhmad Fatoum port->rs485.delay_rts_before_send); 718bd78ecd6SAhmad Fatoum return; 719cb1a6092SUwe Kleine-König } 720cb1a6092SUwe Kleine-König 721582e9a24SHarald Seiler /* continue without any delay */ 722582e9a24SHarald Seiler } 723582e9a24SHarald Seiler 724bd78ecd6SAhmad Fatoum if (sport->tx_state == WAIT_AFTER_SEND 725bd78ecd6SAhmad Fatoum || sport->tx_state == WAIT_AFTER_RTS) { 726cb1a6092SUwe Kleine-König 727bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_stop_tx); 728bd78ecd6SAhmad Fatoum 72918665414SUwe Kleine-König /* 730cb1a6092SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA 731cb1a6092SUwe Kleine-König * is off. In the DMA case this is done in the 732cb1a6092SUwe Kleine-König * tx-callback. 73318665414SUwe Kleine-König */ 73418665414SUwe Kleine-König if (!sport->dma_is_enabled) { 73518665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 7364444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 7374444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 73817b8f2a3SUwe Kleine-König } 739cb1a6092SUwe Kleine-König 740cb1a6092SUwe Kleine-König sport->tx_state = SEND; 741cb1a6092SUwe Kleine-König } 742cb1a6092SUwe Kleine-König } else { 743cb1a6092SUwe Kleine-König sport->tx_state = SEND; 74418665414SUwe Kleine-König } 74517b8f2a3SUwe Kleine-König 746b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 7474444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 748c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 749b4cdc8f6SHuang Shijie } 750ab4382d2SGreg Kroah-Hartman 751b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 75291a1a909SJiada Wang if (sport->port.x_char) { 75391a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 75491a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 7554444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 7564444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 757c514a6f8SSergey Organov ucr1 |= UCR1_TRDYEN; 7584444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 75991a1a909SJiada Wang return; 76091a1a909SJiada Wang } 76191a1a909SJiada Wang 7625e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 7635e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7649d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 765b4cdc8f6SHuang Shijie return; 766b4cdc8f6SHuang Shijie } 767ab4382d2SGreg Kroah-Hartman } 768ab4382d2SGreg Kroah-Hartman 769101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 770ab4382d2SGreg Kroah-Hartman { 771ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7724444dcf1SUwe Kleine-König u32 usr1; 773ab4382d2SGreg Kroah-Hartman 77427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7754444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7764444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 777ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 778ab4382d2SGreg Kroah-Hartman 779ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 780ab4382d2SGreg Kroah-Hartman } 781ab4382d2SGreg Kroah-Hartman 782101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 783101aa46bSUwe Kleine-König { 784101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 785101aa46bSUwe Kleine-König irqreturn_t ret; 786101aa46bSUwe Kleine-König 787101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 788101aa46bSUwe Kleine-König 789101aa46bSUwe Kleine-König ret = __imx_uart_rtsint(irq, dev_id); 790101aa46bSUwe Kleine-König 791101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 792101aa46bSUwe Kleine-König 793101aa46bSUwe Kleine-König return ret; 794101aa46bSUwe Kleine-König } 795101aa46bSUwe Kleine-König 7969d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 797ab4382d2SGreg Kroah-Hartman { 798ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 799ab4382d2SGreg Kroah-Hartman 800c974991dSjun qian spin_lock(&sport->port.lock); 8019d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 802c974991dSjun qian spin_unlock(&sport->port.lock); 803ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 804ab4382d2SGreg Kroah-Hartman } 805ab4382d2SGreg Kroah-Hartman 806101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 807ab4382d2SGreg Kroah-Hartman { 808ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 809ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 81092a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 811ab4382d2SGreg Kroah-Hartman 81227c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 8134444dcf1SUwe Kleine-König u32 usr2; 8144444dcf1SUwe Kleine-König 815ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 816ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 817ab4382d2SGreg Kroah-Hartman 81827c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 819ab4382d2SGreg Kroah-Hartman 8204444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 8214444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 82227c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 823ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 824ab4382d2SGreg Kroah-Hartman continue; 825ab4382d2SGreg Kroah-Hartman } 826ab4382d2SGreg Kroah-Hartman 827ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 828ab4382d2SGreg Kroah-Hartman continue; 829ab4382d2SGreg Kroah-Hartman 830019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 831019dc9eaSHui Wang if (rx & URXD_BRK) 832019dc9eaSHui Wang sport->port.icount.brk++; 833019dc9eaSHui Wang else if (rx & URXD_PRERR) 834ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 835ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 836ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 837ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 838ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 839ab4382d2SGreg Kroah-Hartman 840ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 841ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 842ab4382d2SGreg Kroah-Hartman goto out; 843ab4382d2SGreg Kroah-Hartman continue; 844ab4382d2SGreg Kroah-Hartman } 845ab4382d2SGreg Kroah-Hartman 8468d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 847ab4382d2SGreg Kroah-Hartman 848019dc9eaSHui Wang if (rx & URXD_BRK) 849019dc9eaSHui Wang flg = TTY_BREAK; 850019dc9eaSHui Wang else if (rx & URXD_PRERR) 851ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 852ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 853ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 854ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 855ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 856ab4382d2SGreg Kroah-Hartman 857ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 858ab4382d2SGreg Kroah-Hartman } 859ab4382d2SGreg Kroah-Hartman 86055d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 86155d8693aSJiada Wang goto out; 86255d8693aSJiada Wang 8639b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 8649b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 865ab4382d2SGreg Kroah-Hartman } 866ab4382d2SGreg Kroah-Hartman 867ab4382d2SGreg Kroah-Hartman out: 8682e124b4aSJiri Slaby tty_flip_buffer_push(port); 869101aa46bSUwe Kleine-König 870ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 871ab4382d2SGreg Kroah-Hartman } 872ab4382d2SGreg Kroah-Hartman 873101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 874101aa46bSUwe Kleine-König { 875101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 876101aa46bSUwe Kleine-König irqreturn_t ret; 877101aa46bSUwe Kleine-König 878101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 879101aa46bSUwe Kleine-König 880101aa46bSUwe Kleine-König ret = __imx_uart_rxint(irq, dev_id); 881101aa46bSUwe Kleine-König 882101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 883101aa46bSUwe Kleine-König 884101aa46bSUwe Kleine-König return ret; 885101aa46bSUwe Kleine-König } 886101aa46bSUwe Kleine-König 8879d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 888b4cdc8f6SHuang Shijie 88966f95884SUwe Kleine-König /* 89066f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 89166f95884SUwe Kleine-König */ 8929d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 89366f95884SUwe Kleine-König { 89466f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 89527c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 89627c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 89766f95884SUwe Kleine-König 89866f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 89966f95884SUwe Kleine-König tmp |= TIOCM_CTS; 90066f95884SUwe Kleine-König 90166f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 9024b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 90366f95884SUwe Kleine-König tmp |= TIOCM_CAR; 90466f95884SUwe Kleine-König 90566f95884SUwe Kleine-König if (sport->dte_mode) 90627c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 90766f95884SUwe Kleine-König tmp |= TIOCM_RI; 90866f95884SUwe Kleine-König 90966f95884SUwe Kleine-König return tmp; 91066f95884SUwe Kleine-König } 91166f95884SUwe Kleine-König 91266f95884SUwe Kleine-König /* 91366f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 91466f95884SUwe Kleine-König */ 9159d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 91666f95884SUwe Kleine-König { 91766f95884SUwe Kleine-König unsigned int status, changed; 91866f95884SUwe Kleine-König 9199d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 92066f95884SUwe Kleine-König changed = status ^ sport->old_status; 92166f95884SUwe Kleine-König 92266f95884SUwe Kleine-König if (changed == 0) 92366f95884SUwe Kleine-König return; 92466f95884SUwe Kleine-König 92566f95884SUwe Kleine-König sport->old_status = status; 92666f95884SUwe Kleine-König 92766f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 92866f95884SUwe Kleine-König sport->port.icount.rng++; 92966f95884SUwe Kleine-König if (changed & TIOCM_DSR) 93066f95884SUwe Kleine-König sport->port.icount.dsr++; 93166f95884SUwe Kleine-König if (changed & TIOCM_CAR) 93266f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 93366f95884SUwe Kleine-König if (changed & TIOCM_CTS) 93466f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 93566f95884SUwe Kleine-König 93666f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 93766f95884SUwe Kleine-König } 93866f95884SUwe Kleine-König 9399d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 940ab4382d2SGreg Kroah-Hartman { 941ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 94243776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 9434d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 944ab4382d2SGreg Kroah-Hartman 9459baedb7bSJohan Hovold spin_lock(&sport->port.lock); 946101aa46bSUwe Kleine-König 94727c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 94827c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 94927c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 95027c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 95127c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 95227c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 953ab4382d2SGreg Kroah-Hartman 95443776896SUwe Kleine-König /* 95543776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 95643776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 95743776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 95843776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 95943776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 96043776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 96143776896SUwe Kleine-König */ 96243776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 96343776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 96443776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 96543776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 966c514a6f8SSergey Organov if ((ucr1 & UCR1_TRDYEN) == 0) 96743776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 96843776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 96943776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 97043776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 97143776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 97243776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 97343776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 97443776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 97543776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 97643776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 97743776896SUwe Kleine-König usr2 &= ~USR2_ORE; 97843776896SUwe Kleine-König 97943776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 980d1d996afSMatthias Schiffer imx_uart_writel(sport, USR1_AGTIM, USR1); 981d1d996afSMatthias Schiffer 982101aa46bSUwe Kleine-König __imx_uart_rxint(irq, dev_id); 9834d845a62SUwe Kleine-König ret = IRQ_HANDLED; 984b4cdc8f6SHuang Shijie } 985ab4382d2SGreg Kroah-Hartman 98643776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 987101aa46bSUwe Kleine-König imx_uart_transmit_buffer(sport); 9884d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9894d845a62SUwe Kleine-König } 990ab4382d2SGreg Kroah-Hartman 9910399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 99227c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 99327e16501SUwe Kleine-König 9949d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 99527e16501SUwe Kleine-König 99627e16501SUwe Kleine-König ret = IRQ_HANDLED; 99727e16501SUwe Kleine-König } 99827e16501SUwe Kleine-König 9990399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 1000101aa46bSUwe Kleine-König __imx_uart_rtsint(irq, dev_id); 10014d845a62SUwe Kleine-König ret = IRQ_HANDLED; 10024d845a62SUwe Kleine-König } 1003ab4382d2SGreg Kroah-Hartman 10040399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 100527c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 10064d845a62SUwe Kleine-König ret = IRQ_HANDLED; 10074d845a62SUwe Kleine-König } 1008db1a9b55SFabio Estevam 10090399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 1010f1f836e4SAlexander Stein sport->port.icount.overrun++; 101127c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 10124d845a62SUwe Kleine-König ret = IRQ_HANDLED; 1013f1f836e4SAlexander Stein } 1014f1f836e4SAlexander Stein 10159baedb7bSJohan Hovold spin_unlock(&sport->port.lock); 1016101aa46bSUwe Kleine-König 10174d845a62SUwe Kleine-König return ret; 1018ab4382d2SGreg Kroah-Hartman } 1019ab4382d2SGreg Kroah-Hartman 1020ab4382d2SGreg Kroah-Hartman /* 1021ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 1022ab4382d2SGreg Kroah-Hartman */ 10239d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 1024ab4382d2SGreg Kroah-Hartman { 1025ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10261ce43e58SHuang Shijie unsigned int ret; 1027ab4382d2SGreg Kroah-Hartman 102827c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 10291ce43e58SHuang Shijie 10301ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 1031686351f3SUwe Kleine-König if (sport->dma_is_txing) 10321ce43e58SHuang Shijie ret = 0; 10331ce43e58SHuang Shijie 10341ce43e58SHuang Shijie return ret; 1035ab4382d2SGreg Kroah-Hartman } 1036ab4382d2SGreg Kroah-Hartman 10376aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10389d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 103958362d5bSUwe Kleine-König { 104058362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 10419d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 104258362d5bSUwe Kleine-König 104358362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 104458362d5bSUwe Kleine-König 104558362d5bSUwe Kleine-König return ret; 104658362d5bSUwe Kleine-König } 104758362d5bSUwe Kleine-König 10486aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10499d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1050ab4382d2SGreg Kroah-Hartman { 1051ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10524444dcf1SUwe Kleine-König u32 ucr3, uts; 1053ab4382d2SGreg Kroah-Hartman 105417b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 10554444dcf1SUwe Kleine-König u32 ucr2; 10564444dcf1SUwe Kleine-König 1057197540dcSSergey Organov /* 1058197540dcSSergey Organov * Turn off autoRTS if RTS is lowered and restore autoRTS 1059197540dcSSergey Organov * setting if RTS is raised. 1060197540dcSSergey Organov */ 10614444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 10624444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1063197540dcSSergey Organov if (mctrl & TIOCM_RTS) { 1064197540dcSSergey Organov ucr2 |= UCR2_CTS; 1065197540dcSSergey Organov /* 1066197540dcSSergey Organov * UCR2_IRTS is unset if and only if the port is 1067197540dcSSergey Organov * configured for CRTSCTS, so we use inverted UCR2_IRTS 1068197540dcSSergey Organov * to get the state to restore to. 1069197540dcSSergey Organov */ 1070197540dcSSergey Organov if (!(ucr2 & UCR2_IRTS)) 1071197540dcSSergey Organov ucr2 |= UCR2_CTSC; 1072197540dcSSergey Organov } 10734444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 107417b8f2a3SUwe Kleine-König } 10756b471a98SHuang Shijie 10764444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 107790ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 10784444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 10794444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 108090ebc483SUwe Kleine-König 10819d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 10826b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 10834444dcf1SUwe Kleine-König uts |= UTS_LOOP; 10849d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 108558362d5bSUwe Kleine-König 108658362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 1087ab4382d2SGreg Kroah-Hartman } 1088ab4382d2SGreg Kroah-Hartman 1089ab4382d2SGreg Kroah-Hartman /* 1090ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 1091ab4382d2SGreg Kroah-Hartman */ 10929d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1093ab4382d2SGreg Kroah-Hartman { 1094ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10954444dcf1SUwe Kleine-König unsigned long flags; 10964444dcf1SUwe Kleine-König u32 ucr1; 1097ab4382d2SGreg Kroah-Hartman 1098ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1099ab4382d2SGreg Kroah-Hartman 11004444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1101ab4382d2SGreg Kroah-Hartman 1102ab4382d2SGreg Kroah-Hartman if (break_state != 0) 11034444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1104ab4382d2SGreg Kroah-Hartman 11054444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1106ab4382d2SGreg Kroah-Hartman 1107ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1108ab4382d2SGreg Kroah-Hartman } 1109ab4382d2SGreg Kroah-Hartman 1110cc568849SUwe Kleine-König /* 1111cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1112cc568849SUwe Kleine-König * modem status signals. 1113cc568849SUwe Kleine-König */ 11149d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1115cc568849SUwe Kleine-König { 1116e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1117cc568849SUwe Kleine-König unsigned long flags; 1118cc568849SUwe Kleine-König 1119cc568849SUwe Kleine-König if (sport->port.state) { 1120cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 11219d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1122cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1123cc568849SUwe Kleine-König 1124cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1125cc568849SUwe Kleine-König } 1126cc568849SUwe Kleine-König } 1127cc568849SUwe Kleine-König 1128b4cdc8f6SHuang Shijie /* 1129905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1130b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1131905c0decSLucas Stach * [2] the aging timer expires 1132b4cdc8f6SHuang Shijie * 1133905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1134905c0decSLucas Stach * for at least 8 byte durations. 1135b4cdc8f6SHuang Shijie */ 11369d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1137b4cdc8f6SHuang Shijie { 1138b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1139b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1140b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 11417cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1142b4cdc8f6SHuang Shijie struct dma_tx_state state; 11439d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1144b4cdc8f6SHuang Shijie enum dma_status status; 11459d297239SNandor Han unsigned int w_bytes = 0; 11469d297239SNandor Han unsigned int r_bytes; 11479d297239SNandor Han unsigned int bd_size; 1148b4cdc8f6SHuang Shijie 1149fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1150392bceedSPhilipp Zabel 11519d297239SNandor Han if (status == DMA_ERROR) { 11529d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 11539d297239SNandor Han return; 11549d297239SNandor Han } 1155b4cdc8f6SHuang Shijie 11569b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1157976b39cdSLucas Stach 1158976b39cdSLucas Stach /* 11599d297239SNandor Han * The state-residue variable represents the empty space 11609d297239SNandor Han * relative to the entire buffer. Taking this in consideration 11619d297239SNandor Han * the head is always calculated base on the buffer total 11629d297239SNandor Han * length - DMA transaction residue. The UART script from the 11639d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 11649d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 11659d297239SNandor Han * Taking this in consideration the tail is always at the 11669d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1167976b39cdSLucas Stach */ 11689d297239SNandor Han 11699d297239SNandor Han /* Calculate the head */ 11709d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 11719d297239SNandor Han 11729d297239SNandor Han /* Calculate the tail. */ 11739d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 11749d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 11759d297239SNandor Han 11769d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 11779d297239SNandor Han rx_ring->head > rx_ring->tail) { 11789d297239SNandor Han 11799d297239SNandor Han /* Move data from tail to head */ 11809d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 11819d297239SNandor Han 11829d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 11839d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 11849d297239SNandor Han DMA_FROM_DEVICE); 11859d297239SNandor Han 11869d297239SNandor Han w_bytes = tty_insert_flip_string(port, 11879d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 11889d297239SNandor Han 11899d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 11909d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 11919d297239SNandor Han DMA_FROM_DEVICE); 11929d297239SNandor Han 11939d297239SNandor Han if (w_bytes != r_bytes) 11949d297239SNandor Han sport->port.icount.buf_overrun++; 11959d297239SNandor Han 11969d297239SNandor Han sport->port.icount.rx += w_bytes; 11979d297239SNandor Han } else { 11989d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11999d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1200ee5e7c10SRobin Gong } 12019d297239SNandor Han } 12029d297239SNandor Han 12039d297239SNandor Han if (w_bytes) { 12049d297239SNandor Han tty_flip_buffer_push(port); 12059d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 12069d297239SNandor Han } 12079d297239SNandor Han } 12089d297239SNandor Han 12099d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1210b4cdc8f6SHuang Shijie { 1211b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1212b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1213b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1214b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1215b4cdc8f6SHuang Shijie int ret; 1216b4cdc8f6SHuang Shijie 12179d297239SNandor Han sport->rx_ring.head = 0; 12189d297239SNandor Han sport->rx_ring.tail = 0; 12199d297239SNandor Han 1220db0a196bSFabien Lahoudere sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); 1221b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1222b4cdc8f6SHuang Shijie if (ret == 0) { 1223b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1224b4cdc8f6SHuang Shijie return -EINVAL; 1225b4cdc8f6SHuang Shijie } 12269d297239SNandor Han 12279d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 12289d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 12299d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 12309d297239SNandor Han 1231b4cdc8f6SHuang Shijie if (!desc) { 123224649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1233b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1234b4cdc8f6SHuang Shijie return -EINVAL; 1235b4cdc8f6SHuang Shijie } 12369d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1237b4cdc8f6SHuang Shijie desc->callback_param = sport; 1238b4cdc8f6SHuang Shijie 1239b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 12404139fd76SRomain Perier sport->dma_is_rxing = 1; 12419d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1242b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1243b4cdc8f6SHuang Shijie return 0; 1244b4cdc8f6SHuang Shijie } 1245b4cdc8f6SHuang Shijie 12469d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 124741d98b5dSNandor Han { 124845ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 12494444dcf1SUwe Kleine-König u32 usr1, usr2; 125041d98b5dSNandor Han 12514444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 12524444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 125341d98b5dSNandor Han 12544444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 125541d98b5dSNandor Han sport->port.icount.brk++; 125627c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 125745ca673eSTroy Kisky uart_handle_break(&sport->port); 125845ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 125945ca673eSTroy Kisky sport->port.icount.buf_overrun++; 126045ca673eSTroy Kisky tty_flip_buffer_push(port); 126145ca673eSTroy Kisky } else { 12624444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 126341d98b5dSNandor Han sport->port.icount.frame++; 126427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 12654444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 126641d98b5dSNandor Han sport->port.icount.parity++; 126727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 126841d98b5dSNandor Han } 126945ca673eSTroy Kisky } 127041d98b5dSNandor Han 12714444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 127241d98b5dSNandor Han sport->port.icount.overrun++; 127327c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 127441d98b5dSNandor Han } 127541d98b5dSNandor Han 127641d98b5dSNandor Han } 127741d98b5dSNandor Han 1278cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 12797a637784STomasz Moń #define RXTL_DEFAULT 8 /* 8 characters or aging timer */ 1280184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1281184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1282cc32382dSLucas Stach 12839d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1284cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1285cc32382dSLucas Stach { 1286cc32382dSLucas Stach unsigned int val; 1287cc32382dSLucas Stach 1288cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 128927c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1290cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 129127c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1292cc32382dSLucas Stach } 1293cc32382dSLucas Stach 1294b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1295b4cdc8f6SHuang Shijie { 1296b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1297e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1298b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1299b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 13009d297239SNandor Han sport->rx_cookie = -EINVAL; 1301b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1302b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1303b4cdc8f6SHuang Shijie } 1304b4cdc8f6SHuang Shijie 1305b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1306e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1307b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1308b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1309b4cdc8f6SHuang Shijie } 1310b4cdc8f6SHuang Shijie } 1311b4cdc8f6SHuang Shijie 1312b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1313b4cdc8f6SHuang Shijie { 1314b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1315b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1316b4cdc8f6SHuang Shijie int ret; 1317b4cdc8f6SHuang Shijie 1318b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1319b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1320b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1321b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1322b4cdc8f6SHuang Shijie ret = -EINVAL; 1323b4cdc8f6SHuang Shijie goto err; 1324b4cdc8f6SHuang Shijie } 1325b4cdc8f6SHuang Shijie 1326b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1327b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1328b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1329184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1330184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1331b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1332b4cdc8f6SHuang Shijie if (ret) { 1333b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1334b4cdc8f6SHuang Shijie goto err; 1335b4cdc8f6SHuang Shijie } 1336b4cdc8f6SHuang Shijie 1337db0a196bSFabien Lahoudere sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; 1338db0a196bSFabien Lahoudere sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); 1339b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1340b4cdc8f6SHuang Shijie ret = -ENOMEM; 1341b4cdc8f6SHuang Shijie goto err; 1342b4cdc8f6SHuang Shijie } 13439d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1344b4cdc8f6SHuang Shijie 1345b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1346b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1347b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1348b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1349b4cdc8f6SHuang Shijie ret = -EINVAL; 1350b4cdc8f6SHuang Shijie goto err; 1351b4cdc8f6SHuang Shijie } 1352b4cdc8f6SHuang Shijie 1353b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1354b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1355b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1356184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1357b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1358b4cdc8f6SHuang Shijie if (ret) { 1359b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1360b4cdc8f6SHuang Shijie goto err; 1361b4cdc8f6SHuang Shijie } 1362b4cdc8f6SHuang Shijie 1363b4cdc8f6SHuang Shijie return 0; 1364b4cdc8f6SHuang Shijie err: 1365b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1366b4cdc8f6SHuang Shijie return ret; 1367b4cdc8f6SHuang Shijie } 1368b4cdc8f6SHuang Shijie 13699d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1370b4cdc8f6SHuang Shijie { 13714444dcf1SUwe Kleine-König u32 ucr1; 1372b4cdc8f6SHuang Shijie 13739d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 137402b0abd3SUwe Kleine-König 1375b4cdc8f6SHuang Shijie /* set UCR1 */ 13764444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13774444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 13784444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1379b4cdc8f6SHuang Shijie 1380b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1381b4cdc8f6SHuang Shijie } 1382b4cdc8f6SHuang Shijie 13839d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1384b4cdc8f6SHuang Shijie { 1385676a31d8SSebastian Reichel u32 ucr1; 1386b4cdc8f6SHuang Shijie 1387b4cdc8f6SHuang Shijie /* clear UCR1 */ 13884444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13894444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 13904444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1391b4cdc8f6SHuang Shijie 13929d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1393184bd70bSLucas Stach 1394b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1395b4cdc8f6SHuang Shijie } 1396b4cdc8f6SHuang Shijie 1397ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1398ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1399ab4382d2SGreg Kroah-Hartman 14009d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1401ab4382d2SGreg Kroah-Hartman { 1402ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1403458e2c82SFabio Estevam int retval, i; 14044444dcf1SUwe Kleine-König unsigned long flags; 14054238c00bSUwe Kleine-König int dma_is_inited = 0; 140679d0224fSMarek Vasut u32 ucr1, ucr2, ucr3, ucr4, uts; 1407ab4382d2SGreg Kroah-Hartman 140828eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 140928eb4274SHuang Shijie if (retval) 1410cb0f0a5fSFabio Estevam return retval; 141128eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 14120c375501SHuang Shijie if (retval) { 14130c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1414cb0f0a5fSFabio Estevam return retval; 14150c375501SHuang Shijie } 141628eb4274SHuang Shijie 14179d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1418ab4382d2SGreg Kroah-Hartman 1419ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1420ab4382d2SGreg Kroah-Hartman * requesting IRQs 1421ab4382d2SGreg Kroah-Hartman */ 14224444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1423ab4382d2SGreg Kroah-Hartman 1424ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 14254444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 14264444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1427ab4382d2SGreg Kroah-Hartman 14284444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1429ab4382d2SGreg Kroah-Hartman 14307e11577eSLucas Stach /* Can we enable the DMA support? */ 14314238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 14324238c00bSUwe Kleine-König dma_is_inited = 1; 14337e11577eSLucas Stach 143453794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1435772f8991SHuang Shijie /* Reset fifo's and state machines */ 1436458e2c82SFabio Estevam i = 100; 1437458e2c82SFabio Estevam 14384444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14394444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 14404444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1441458e2c82SFabio Estevam 144227c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1443458e2c82SFabio Estevam udelay(1); 1444ab4382d2SGreg Kroah-Hartman 1445ab4382d2SGreg Kroah-Hartman /* 1446ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1447ab4382d2SGreg Kroah-Hartman */ 144827c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 144927c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1450ab4382d2SGreg Kroah-Hartman 14514444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 14524444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 14536376cd39SNandor Han if (sport->have_rtscts) 14544444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1455ab4382d2SGreg Kroah-Hartman 14564444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1457ab4382d2SGreg Kroah-Hartman 14585a08a487SGeorge Hilliard ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 14593ee82c6eSJohan Hovold if (!dma_is_inited) 14604444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 14615a08a487SGeorge Hilliard if (sport->inverted_rx) 14625a08a487SGeorge Hilliard ucr4 |= UCR4_INVR; 14634444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 14646f026d6bSJiada Wang 14655a08a487SGeorge Hilliard ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 14665a08a487SGeorge Hilliard /* 14675a08a487SGeorge Hilliard * configure tx polarity before enabling tx 14685a08a487SGeorge Hilliard */ 14695a08a487SGeorge Hilliard if (sport->inverted_tx) 14705a08a487SGeorge Hilliard ucr3 |= UCR3_INVT; 14715a08a487SGeorge Hilliard 14725a08a487SGeorge Hilliard if (!imx_uart_is_imx1(sport)) { 14735a08a487SGeorge Hilliard ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 14745a08a487SGeorge Hilliard 14755a08a487SGeorge Hilliard if (sport->dte_mode) 14765a08a487SGeorge Hilliard /* disable broken interrupts */ 14775a08a487SGeorge Hilliard ucr3 &= ~(UCR3_RI | UCR3_DCD); 14785a08a487SGeorge Hilliard } 14795a08a487SGeorge Hilliard imx_uart_writel(sport, ucr3, UCR3); 14805a08a487SGeorge Hilliard 14814444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 14824444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1483bff09b09SLucas Stach if (!sport->have_rtscts) 14844444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 148516804d68SUwe Kleine-König /* 148616804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 148716804d68SUwe Kleine-König * we're using RTSD instead. 148816804d68SUwe Kleine-König */ 14899d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 14904444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 14914444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1492ab4382d2SGreg Kroah-Hartman 1493ab4382d2SGreg Kroah-Hartman /* 1494ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1495ab4382d2SGreg Kroah-Hartman */ 14969d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 149718a42088SPeter Senna Tschudin 149876821e22SUwe Kleine-König if (dma_is_inited) { 14999d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 15009d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 150176821e22SUwe Kleine-König } else { 150276821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 150376821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 150476821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 150581ca8e82SUwe Kleine-König 150681ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 150781ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 150881ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 150976821e22SUwe Kleine-König } 151018a42088SPeter Senna Tschudin 151179d0224fSMarek Vasut /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 151279d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 151379d0224fSMarek Vasut uts &= ~UTS_LOOP; 151479d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 151579d0224fSMarek Vasut 1516ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1517ab4382d2SGreg Kroah-Hartman 1518ab4382d2SGreg Kroah-Hartman return 0; 1519ab4382d2SGreg Kroah-Hartman } 1520ab4382d2SGreg Kroah-Hartman 15219d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1522ab4382d2SGreg Kroah-Hartman { 1523ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 15249ec1882dSXinyu Chen unsigned long flags; 152579d0224fSMarek Vasut u32 ucr1, ucr2, ucr4, uts; 1526ab4382d2SGreg Kroah-Hartman 1527b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1528e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 15297722c240SSebastian Reichel if (sport->dma_is_txing) { 15307722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 15317722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 15327722c240SSebastian Reichel sport->dma_is_txing = 0; 15337722c240SSebastian Reichel } 1534e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 15357722c240SSebastian Reichel if (sport->dma_is_rxing) { 15367722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 15377722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 15387722c240SSebastian Reichel sport->dma_is_rxing = 0; 15397722c240SSebastian Reichel } 15409d297239SNandor Han 154173631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 15429d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 15439d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 15449d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 154573631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1546b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1547b4cdc8f6SHuang Shijie } 1548b4cdc8f6SHuang Shijie 154958362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 155058362d5bSUwe Kleine-König 15519ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 15524444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15530fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 15544444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 15559ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1556ab4382d2SGreg Kroah-Hartman 1557ab4382d2SGreg Kroah-Hartman /* 1558ab4382d2SGreg Kroah-Hartman * Stop our timer. 1559ab4382d2SGreg Kroah-Hartman */ 1560ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1561ab4382d2SGreg Kroah-Hartman 1562ab4382d2SGreg Kroah-Hartman /* 1563ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1564ab4382d2SGreg Kroah-Hartman */ 1565ab4382d2SGreg Kroah-Hartman 15669ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1567edd64f30SMatthias Schiffer 15684444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 1569509597ebSSherry Sun ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | 1570509597ebSSherry Sun UCR1_ATDMAEN | UCR1_SNDBRK); 157179d0224fSMarek Vasut /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 157279d0224fSMarek Vasut if (port->rs485.flags & SER_RS485_ENABLED && 157379d0224fSMarek Vasut port->rs485.flags & SER_RS485_RTS_ON_SEND && 157479d0224fSMarek Vasut sport->have_rtscts && !sport->have_rtsgpio) { 157579d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 157679d0224fSMarek Vasut uts |= UTS_LOOP; 157779d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 157879d0224fSMarek Vasut ucr1 |= UCR1_UARTEN; 157979d0224fSMarek Vasut } else { 158079d0224fSMarek Vasut ucr1 &= ~UCR1_UARTEN; 158179d0224fSMarek Vasut } 15824444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1583edd64f30SMatthias Schiffer 1584edd64f30SMatthias Schiffer ucr4 = imx_uart_readl(sport, UCR4); 1585028e0838SFugang Duan ucr4 &= ~UCR4_TCEN; 1586edd64f30SMatthias Schiffer imx_uart_writel(sport, ucr4, UCR4); 1587edd64f30SMatthias Schiffer 15889ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 158928eb4274SHuang Shijie 159028eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 159128eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1592ab4382d2SGreg Kroah-Hartman } 1593ab4382d2SGreg Kroah-Hartman 15946aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 15959d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1596eb56b7edSHuang Shijie { 1597eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 159882e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 15994444dcf1SUwe Kleine-König u32 ucr2; 16004f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1601eb56b7edSHuang Shijie 160282e86ae9SDirk Behme if (!sport->dma_chan_tx) 160382e86ae9SDirk Behme return; 160482e86ae9SDirk Behme 1605eb56b7edSHuang Shijie sport->tx_bytes = 0; 1606eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 160782e86ae9SDirk Behme if (sport->dma_is_txing) { 16084444dcf1SUwe Kleine-König u32 ucr1; 16094444dcf1SUwe Kleine-König 161082e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 161182e86ae9SDirk Behme DMA_TO_DEVICE); 16124444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 16134444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 16144444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 16150f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1616eb56b7edSHuang Shijie } 1617934084a9SFabio Estevam 1618934084a9SFabio Estevam /* 1619934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1620263763c1SMartyn Welch * 1621934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1622934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1623263763c1SMartyn Welch * and UTS[6-3]". 1624263763c1SMartyn Welch * 1625263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1626263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1627263763c1SMartyn Welch * registers. 1628934084a9SFabio Estevam */ 162927c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 163027c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 163127c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1632934084a9SFabio Estevam 16334444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 16344444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 16354444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1636934084a9SFabio Estevam 163727c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1638934084a9SFabio Estevam udelay(1); 1639934084a9SFabio Estevam 1640934084a9SFabio Estevam /* Restore the registers */ 164127c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 164227c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 164327c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1644eb56b7edSHuang Shijie } 1645eb56b7edSHuang Shijie 1646ab4382d2SGreg Kroah-Hartman static void 16479d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1648bec5b814SIlpo Järvinen const struct ktermios *old) 1649ab4382d2SGreg Kroah-Hartman { 1650ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1651ab4382d2SGreg Kroah-Hartman unsigned long flags; 165285f30fbfSSergey Organov u32 ucr2, old_ucr2, ufcr; 165358362d5bSUwe Kleine-König unsigned int baud, quot; 1654ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 16554444dcf1SUwe Kleine-König unsigned long div; 1656d47bcb4aSSergey Organov unsigned long num, denom, old_ubir, old_ubmr; 1657ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1658ab4382d2SGreg Kroah-Hartman 1659ab4382d2SGreg Kroah-Hartman /* 1660ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1661ab4382d2SGreg Kroah-Hartman */ 1662ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1663ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1664ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1665ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1666ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1667ab4382d2SGreg Kroah-Hartman } 1668ab4382d2SGreg Kroah-Hartman 16694e828c3eSSergey Organov del_timer_sync(&sport->timer); 16704e828c3eSSergey Organov 16714e828c3eSSergey Organov /* 16724e828c3eSSergey Organov * Ask the core to calculate the divisor for us. 16734e828c3eSSergey Organov */ 16744e828c3eSSergey Organov baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 16754e828c3eSSergey Organov quot = uart_get_divisor(port, baud); 16764e828c3eSSergey Organov 16774e828c3eSSergey Organov spin_lock_irqsave(&sport->port.lock, flags); 16784e828c3eSSergey Organov 1679011bd05dSSergey Organov /* 1680011bd05dSSergey Organov * Read current UCR2 and save it for future use, then clear all the bits 1681011bd05dSSergey Organov * except those we will or may need to preserve. 1682011bd05dSSergey Organov */ 1683011bd05dSSergey Organov old_ucr2 = imx_uart_readl(sport, UCR2); 1684011bd05dSSergey Organov ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1685011bd05dSSergey Organov 1686011bd05dSSergey Organov ucr2 |= UCR2_SRST | UCR2_IRTS; 168741ffa48eSSergey Organov if ((termios->c_cflag & CSIZE) == CS8) 168841ffa48eSSergey Organov ucr2 |= UCR2_WS; 1689ab4382d2SGreg Kroah-Hartman 1690ddf89e75SSergey Organov if (!sport->have_rtscts) 1691ddf89e75SSergey Organov termios->c_cflag &= ~CRTSCTS; 169217b8f2a3SUwe Kleine-König 169312fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 169417b8f2a3SUwe Kleine-König /* 169517b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 169617b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 169717b8f2a3SUwe Kleine-König * disabled. 169817b8f2a3SUwe Kleine-König */ 169958362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 17009d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 17011a613626SFabio Estevam else 17029d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 170358362d5bSUwe Kleine-König 1704b777b5deSSergey Organov } else if (termios->c_cflag & CRTSCTS) { 1705b777b5deSSergey Organov /* 1706b777b5deSSergey Organov * Only let receiver control RTS output if we were not requested 1707b777b5deSSergey Organov * to have RTS inactive (which then should take precedence). 1708b777b5deSSergey Organov */ 1709b777b5deSSergey Organov if (ucr2 & UCR2_CTS) 1710b777b5deSSergey Organov ucr2 |= UCR2_CTSC; 1711b777b5deSSergey Organov } 1712ddf89e75SSergey Organov 1713ddf89e75SSergey Organov if (termios->c_cflag & CRTSCTS) 1714ddf89e75SSergey Organov ucr2 &= ~UCR2_IRTS; 1715ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1716ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1717ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1718ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1719ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1720ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1721ab4382d2SGreg Kroah-Hartman } 1722ab4382d2SGreg Kroah-Hartman 1723ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1724ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1725ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1726ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1727ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1728ab4382d2SGreg Kroah-Hartman 1729ab4382d2SGreg Kroah-Hartman /* 1730ab4382d2SGreg Kroah-Hartman * Characters to ignore 1731ab4382d2SGreg Kroah-Hartman */ 1732ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1733ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1734865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1735ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1736ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1737ab4382d2SGreg Kroah-Hartman /* 1738ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1739ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1740ab4382d2SGreg Kroah-Hartman */ 1741ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1742ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1743ab4382d2SGreg Kroah-Hartman } 1744ab4382d2SGreg Kroah-Hartman 174555d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 174655d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 174755d8693aSJiada Wang 1748ab4382d2SGreg Kroah-Hartman /* 1749ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1750ab4382d2SGreg Kroah-Hartman */ 1751ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1752ab4382d2SGreg Kroah-Hartman 175309bd00f6SHubert Feurstein /* custom-baudrate handling */ 175409bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 175509bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 175609bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 175709bd00f6SHubert Feurstein 1758ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1759ab4382d2SGreg Kroah-Hartman if (div > 7) 1760ab4382d2SGreg Kroah-Hartman div = 7; 1761ab4382d2SGreg Kroah-Hartman if (!div) 1762ab4382d2SGreg Kroah-Hartman div = 1; 1763ab4382d2SGreg Kroah-Hartman 1764ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1765ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1766ab4382d2SGreg Kroah-Hartman 1767ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1768ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1769ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1770ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1771ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1772ab4382d2SGreg Kroah-Hartman 1773ab4382d2SGreg Kroah-Hartman num -= 1; 1774ab4382d2SGreg Kroah-Hartman denom -= 1; 1775ab4382d2SGreg Kroah-Hartman 177627c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1777ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 177827c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1779ab4382d2SGreg Kroah-Hartman 1780d47bcb4aSSergey Organov /* 1781d47bcb4aSSergey Organov * Two registers below should always be written both and in this 1782d47bcb4aSSergey Organov * particular order. One consequence is that we need to check if any of 1783d47bcb4aSSergey Organov * them changes and then update both. We do need the check for change 1784d47bcb4aSSergey Organov * as even writing the same values seem to "restart" 1785d47bcb4aSSergey Organov * transmission/receiving logic in the hardware, that leads to data 1786d47bcb4aSSergey Organov * breakage even when rate doesn't in fact change. E.g., user switches 1787d47bcb4aSSergey Organov * RTS/CTS handshake and suddenly gets broken bytes. 1788d47bcb4aSSergey Organov */ 1789d47bcb4aSSergey Organov old_ubir = imx_uart_readl(sport, UBIR); 1790d47bcb4aSSergey Organov old_ubmr = imx_uart_readl(sport, UBMR); 1791d47bcb4aSSergey Organov if (old_ubir != num || old_ubmr != denom) { 179227c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 179327c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1794d47bcb4aSSergey Organov } 1795ab4382d2SGreg Kroah-Hartman 17969d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 179727c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 179827c84426SUwe Kleine-König IMX21_ONEMS); 1799ab4382d2SGreg Kroah-Hartman 1800011bd05dSSergey Organov imx_uart_writel(sport, ucr2, UCR2); 1801ab4382d2SGreg Kroah-Hartman 1802ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 18039d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1804ab4382d2SGreg Kroah-Hartman 1805ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1806ab4382d2SGreg Kroah-Hartman } 1807ab4382d2SGreg Kroah-Hartman 18089d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1809ab4382d2SGreg Kroah-Hartman { 1810ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1811ab4382d2SGreg Kroah-Hartman 1812ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1813ab4382d2SGreg Kroah-Hartman } 1814ab4382d2SGreg Kroah-Hartman 1815ab4382d2SGreg Kroah-Hartman /* 1816ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1817ab4382d2SGreg Kroah-Hartman */ 18189d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1819ab4382d2SGreg Kroah-Hartman { 1820ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1821ab4382d2SGreg Kroah-Hartman 1822da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1823ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1824ab4382d2SGreg Kroah-Hartman } 1825ab4382d2SGreg Kroah-Hartman 1826ab4382d2SGreg Kroah-Hartman /* 1827ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1828ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1829ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1830ab4382d2SGreg Kroah-Hartman */ 1831ab4382d2SGreg Kroah-Hartman static int 18329d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1833ab4382d2SGreg Kroah-Hartman { 1834ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1835ab4382d2SGreg Kroah-Hartman int ret = 0; 1836ab4382d2SGreg Kroah-Hartman 1837ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1838ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1839ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1840ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1841ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1842ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1843ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1844ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1845a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1846ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1847ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1848ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1849ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1850ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1851ab4382d2SGreg Kroah-Hartman return ret; 1852ab4382d2SGreg Kroah-Hartman } 1853ab4382d2SGreg Kroah-Hartman 185401f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18556b8bdad9SDaniel Thompson 18569d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 18576b8bdad9SDaniel Thompson { 18586b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 18596b8bdad9SDaniel Thompson unsigned long flags; 18604444dcf1SUwe Kleine-König u32 ucr1, ucr2; 18616b8bdad9SDaniel Thompson int retval; 18626b8bdad9SDaniel Thompson 18636b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 18646b8bdad9SDaniel Thompson if (retval) 18656b8bdad9SDaniel Thompson return retval; 18666b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 18676b8bdad9SDaniel Thompson if (retval) 18686b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 18696b8bdad9SDaniel Thompson 18709d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 18716b8bdad9SDaniel Thompson 18726b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 18736b8bdad9SDaniel Thompson 187476821e22SUwe Kleine-König /* 187576821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 187676821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 187776821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 187876821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 187976821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 188076821e22SUwe Kleine-König */ 18814444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 188276821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 188376821e22SUwe Kleine-König 18849d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 18854444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 18866b8bdad9SDaniel Thompson 188776821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 1888c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 188976821e22SUwe Kleine-König 1890aef1b6a2SMingrui Ren ucr2 |= UCR2_RXEN | UCR2_TXEN; 189181ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 189276821e22SUwe Kleine-König 189376821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 18944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 18956b8bdad9SDaniel Thompson 189676821e22SUwe Kleine-König /* now enable irqs */ 189776821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 189881ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 189976821e22SUwe Kleine-König 19006b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 19016b8bdad9SDaniel Thompson 19026b8bdad9SDaniel Thompson return 0; 19036b8bdad9SDaniel Thompson } 19046b8bdad9SDaniel Thompson 19059d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 190601f56abdSSaleem Abdulrasool { 190727c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 190827c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 190926c47412SDirk Behme return NO_POLL_CHAR; 191001f56abdSSaleem Abdulrasool 191127c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 191201f56abdSSaleem Abdulrasool } 191301f56abdSSaleem Abdulrasool 19149d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 191501f56abdSSaleem Abdulrasool { 191627c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 191701f56abdSSaleem Abdulrasool unsigned int status; 191801f56abdSSaleem Abdulrasool 191901f56abdSSaleem Abdulrasool /* drain */ 192001f56abdSSaleem Abdulrasool do { 192127c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 192201f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 192301f56abdSSaleem Abdulrasool 192401f56abdSSaleem Abdulrasool /* write */ 192527c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 192601f56abdSSaleem Abdulrasool 192701f56abdSSaleem Abdulrasool /* flush */ 192801f56abdSSaleem Abdulrasool do { 192927c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 193001f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 193101f56abdSSaleem Abdulrasool } 193201f56abdSSaleem Abdulrasool #endif 193301f56abdSSaleem Abdulrasool 19346aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 1935ae50bb27SIlpo Järvinen static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios, 193617b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 193717b8f2a3SUwe Kleine-König { 193817b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 19394444dcf1SUwe Kleine-König u32 ucr2; 194017b8f2a3SUwe Kleine-König 194117b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 19426d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 19436d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 19446d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 19456d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 19466d215f83SStefan Agner 194717b8f2a3SUwe Kleine-König /* disable transmitter */ 19484444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 194917b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 19509d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 19511a613626SFabio Estevam else 19529d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 19534444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 195417b8f2a3SUwe Kleine-König } 195517b8f2a3SUwe Kleine-König 19567d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 19577d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 195876821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 19599d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 19607d1cadcaSBaruch Siach 1961*ca530cfaSChristoph Niedermaier if (port->rs485_rx_during_tx_gpio) 1962*ca530cfaSChristoph Niedermaier gpiod_set_value_cansleep(port->rs485_rx_during_tx_gpio, 1963*ca530cfaSChristoph Niedermaier !!(rs485conf->flags & SER_RS485_RX_DURING_TX)); 1964*ca530cfaSChristoph Niedermaier 196517b8f2a3SUwe Kleine-König return 0; 196617b8f2a3SUwe Kleine-König } 196717b8f2a3SUwe Kleine-König 19689d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 19699d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 19709d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 19719d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 19729d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 19739d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 19749d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 19759d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 19769d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 19779d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 19789d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 19799d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 19809d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 19819d1a50a2SUwe Kleine-König .type = imx_uart_type, 19829d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 19839d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 198401f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 19859d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 19869d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 19879d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 198801f56abdSSaleem Abdulrasool #endif 1989ab4382d2SGreg Kroah-Hartman }; 1990ab4382d2SGreg Kroah-Hartman 19919d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1992ab4382d2SGreg Kroah-Hartman 19930db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 19943f8bab17SJiri Slaby static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch) 1995ab4382d2SGreg Kroah-Hartman { 1996ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1997ab4382d2SGreg Kroah-Hartman 19989d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1999ab4382d2SGreg Kroah-Hartman barrier(); 2000ab4382d2SGreg Kroah-Hartman 200127c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 2002ab4382d2SGreg Kroah-Hartman } 2003ab4382d2SGreg Kroah-Hartman 2004ab4382d2SGreg Kroah-Hartman /* 2005ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 2006ab4382d2SGreg Kroah-Hartman */ 2007ab4382d2SGreg Kroah-Hartman static void 20089d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 2009ab4382d2SGreg Kroah-Hartman { 20109d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 20110ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 201218ee37e1SJohan Hovold unsigned long flags; 20130ad5a814SDirk Behme unsigned int ucr1; 2014677fe555SThomas Gleixner int locked = 1; 20159ec1882dSXinyu Chen 2016677fe555SThomas Gleixner if (sport->port.sysrq) 2017677fe555SThomas Gleixner locked = 0; 2018677fe555SThomas Gleixner else if (oops_in_progress) 2019677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 2020677fe555SThomas Gleixner else 20219ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 2022ab4382d2SGreg Kroah-Hartman 2023ab4382d2SGreg Kroah-Hartman /* 20240ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 2025ab4382d2SGreg Kroah-Hartman */ 20269d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 20270ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 2028ab4382d2SGreg Kroah-Hartman 20299d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 2030fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 2031ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 2032c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 2033ab4382d2SGreg Kroah-Hartman 203427c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2035ab4382d2SGreg Kroah-Hartman 203627c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2037ab4382d2SGreg Kroah-Hartman 20389d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2039ab4382d2SGreg Kroah-Hartman 2040ab4382d2SGreg Kroah-Hartman /* 2041ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 20420ad5a814SDirk Behme * and restore UCR1/2/3 2043ab4382d2SGreg Kroah-Hartman */ 204427c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2045ab4382d2SGreg Kroah-Hartman 20469d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 20479ec1882dSXinyu Chen 2048677fe555SThomas Gleixner if (locked) 20499ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 2050ab4382d2SGreg Kroah-Hartman } 2051ab4382d2SGreg Kroah-Hartman 2052ab4382d2SGreg Kroah-Hartman /* 2053ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 2054ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 2055ab4382d2SGreg Kroah-Hartman */ 20566d0d1b5aSStefan Agner static void 20579d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 2058ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 2059ab4382d2SGreg Kroah-Hartman { 2060ab4382d2SGreg Kroah-Hartman 206127c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2062ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 2063ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 2064ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 2065ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 2066ab4382d2SGreg Kroah-Hartman 206727c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 2068ab4382d2SGreg Kroah-Hartman 2069ab4382d2SGreg Kroah-Hartman *parity = 'n'; 2070ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 2071ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 2072ab4382d2SGreg Kroah-Hartman *parity = 'o'; 2073ab4382d2SGreg Kroah-Hartman else 2074ab4382d2SGreg Kroah-Hartman *parity = 'e'; 2075ab4382d2SGreg Kroah-Hartman } 2076ab4382d2SGreg Kroah-Hartman 2077ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 2078ab4382d2SGreg Kroah-Hartman *bits = 8; 2079ab4382d2SGreg Kroah-Hartman else 2080ab4382d2SGreg Kroah-Hartman *bits = 7; 2081ab4382d2SGreg Kroah-Hartman 208227c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 208327c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2084ab4382d2SGreg Kroah-Hartman 208527c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2086ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 2087ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 2088ab4382d2SGreg Kroah-Hartman else 2089ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 2090ab4382d2SGreg Kroah-Hartman 20913a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2092ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2093ab4382d2SGreg Kroah-Hartman 2094ab4382d2SGreg Kroah-Hartman { /* 2095ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2096ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2097ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2098ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2099ab4382d2SGreg Kroah-Hartman */ 2100ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2101ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2102ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2103ab4382d2SGreg Kroah-Hartman 2104ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2105ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2106ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2107ab4382d2SGreg Kroah-Hartman } 2108ab4382d2SGreg Kroah-Hartman 2109ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 2110f5a9e5f7SFabio Estevam dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2111ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2112ab4382d2SGreg Kroah-Hartman } 2113ab4382d2SGreg Kroah-Hartman } 2114ab4382d2SGreg Kroah-Hartman 21156d0d1b5aSStefan Agner static int 21169d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2117ab4382d2SGreg Kroah-Hartman { 2118ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2119ab4382d2SGreg Kroah-Hartman int baud = 9600; 2120ab4382d2SGreg Kroah-Hartman int bits = 8; 2121ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2122ab4382d2SGreg Kroah-Hartman int flow = 'n'; 21231cf93e0dSHuang Shijie int retval; 2124ab4382d2SGreg Kroah-Hartman 2125ab4382d2SGreg Kroah-Hartman /* 2126ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2127ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2128ab4382d2SGreg Kroah-Hartman * console support. 2129ab4382d2SGreg Kroah-Hartman */ 21309d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2131ab4382d2SGreg Kroah-Hartman co->index = 0; 21329d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2133ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2134ab4382d2SGreg Kroah-Hartman return -ENODEV; 2135ab4382d2SGreg Kroah-Hartman 21361cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 21371cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 21381cf93e0dSHuang Shijie if (retval) 21391cf93e0dSHuang Shijie goto error_console; 21401cf93e0dSHuang Shijie 2141ab4382d2SGreg Kroah-Hartman if (options) 2142ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2143ab4382d2SGreg Kroah-Hartman else 21449d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2145ab4382d2SGreg Kroah-Hartman 21469d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2147ab4382d2SGreg Kroah-Hartman 21481cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 21491cf93e0dSHuang Shijie 21500c727a42SFabio Estevam if (retval) { 2151e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21520c727a42SFabio Estevam goto error_console; 21530c727a42SFabio Estevam } 21540c727a42SFabio Estevam 2155e67c139cSFugang Duan retval = clk_prepare_enable(sport->clk_per); 21560c727a42SFabio Estevam if (retval) 2157e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21581cf93e0dSHuang Shijie 21591cf93e0dSHuang Shijie error_console: 21601cf93e0dSHuang Shijie return retval; 2161ab4382d2SGreg Kroah-Hartman } 2162ab4382d2SGreg Kroah-Hartman 21639768a37cSFrancesco Dolcini static int 21649768a37cSFrancesco Dolcini imx_uart_console_exit(struct console *co) 21659768a37cSFrancesco Dolcini { 21669768a37cSFrancesco Dolcini struct imx_port *sport = imx_uart_ports[co->index]; 21679768a37cSFrancesco Dolcini 21689768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_per); 21699768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_ipg); 21709768a37cSFrancesco Dolcini 21719768a37cSFrancesco Dolcini return 0; 21729768a37cSFrancesco Dolcini } 21739768a37cSFrancesco Dolcini 21749d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 21759d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2176ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 21779d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2178ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 21799d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 21809768a37cSFrancesco Dolcini .exit = imx_uart_console_exit, 2181ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2182ab4382d2SGreg Kroah-Hartman .index = -1, 21839d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2184ab4382d2SGreg Kroah-Hartman }; 2185ab4382d2SGreg Kroah-Hartman 21869d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2187913c6c0eSLucas Stach 2188ab4382d2SGreg Kroah-Hartman #else 2189ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2190ab4382d2SGreg Kroah-Hartman #endif 2191ab4382d2SGreg Kroah-Hartman 21929d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2193ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2194ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2195ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2196ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2197ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21989d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2199ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2200ab4382d2SGreg Kroah-Hartman }; 2201ab4382d2SGreg Kroah-Hartman 2202bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2203cb1a6092SUwe Kleine-König { 2204bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2205cb1a6092SUwe Kleine-König unsigned long flags; 2206cb1a6092SUwe Kleine-König 2207cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2208cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS) 2209cb1a6092SUwe Kleine-König imx_uart_start_tx(&sport->port); 2210cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2211bd78ecd6SAhmad Fatoum 2212bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2213cb1a6092SUwe Kleine-König } 2214cb1a6092SUwe Kleine-König 2215bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2216cb1a6092SUwe Kleine-König { 2217bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2218cb1a6092SUwe Kleine-König unsigned long flags; 2219cb1a6092SUwe Kleine-König 2220cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2221cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_SEND) 2222cb1a6092SUwe Kleine-König imx_uart_stop_tx(&sport->port); 2223cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2224bd78ecd6SAhmad Fatoum 2225bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2226cb1a6092SUwe Kleine-König } 2227cb1a6092SUwe Kleine-König 222800d7a00eSIlpo Järvinen static const struct serial_rs485 imx_no_rs485 = {}; /* No RS485 if no RTS */ 222900d7a00eSIlpo Järvinen static const struct serial_rs485 imx_rs485_supported = { 223000d7a00eSIlpo Järvinen .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 223100d7a00eSIlpo Järvinen SER_RS485_RX_DURING_TX, 223200d7a00eSIlpo Järvinen .delay_rts_before_send = 1, 223300d7a00eSIlpo Järvinen .delay_rts_after_send = 1, 223400d7a00eSIlpo Järvinen }; 223500d7a00eSIlpo Järvinen 2236db0a196bSFabien Lahoudere /* Default RX DMA buffer configuration */ 2237db0a196bSFabien Lahoudere #define RX_DMA_PERIODS 16 2238db0a196bSFabien Lahoudere #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4) 2239db0a196bSFabien Lahoudere 22409d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2241ab4382d2SGreg Kroah-Hartman { 22424661f46eSFabio Estevam struct device_node *np = pdev->dev.of_node; 2243ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2244ab4382d2SGreg Kroah-Hartman void __iomem *base; 2245db0a196bSFabien Lahoudere u32 dma_buf_conf[2]; 22464444dcf1SUwe Kleine-König int ret = 0; 224779d0224fSMarek Vasut u32 ucr1, ucr2, uts; 2248ab4382d2SGreg Kroah-Hartman struct resource *res; 2249842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2250ab4382d2SGreg Kroah-Hartman 225142d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2252ab4382d2SGreg Kroah-Hartman if (!sport) 2253ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2254ab4382d2SGreg Kroah-Hartman 22554661f46eSFabio Estevam sport->devdata = of_device_get_match_data(&pdev->dev); 22564661f46eSFabio Estevam 22574661f46eSFabio Estevam ret = of_alias_get_id(np, "serial"); 22584661f46eSFabio Estevam if (ret < 0) { 22594661f46eSFabio Estevam dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 226042d34191SSachin Kamat return ret; 22614661f46eSFabio Estevam } 22624661f46eSFabio Estevam sport->port.line = ret; 22634661f46eSFabio Estevam 22644661f46eSFabio Estevam if (of_get_property(np, "uart-has-rtscts", NULL) || 22654661f46eSFabio Estevam of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 22664661f46eSFabio Estevam sport->have_rtscts = 1; 22674661f46eSFabio Estevam 22684661f46eSFabio Estevam if (of_get_property(np, "fsl,dte-mode", NULL)) 22694661f46eSFabio Estevam sport->dte_mode = 1; 22704661f46eSFabio Estevam 22714661f46eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 22724661f46eSFabio Estevam sport->have_rtsgpio = 1; 22734661f46eSFabio Estevam 22744661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-tx", NULL)) 22754661f46eSFabio Estevam sport->inverted_tx = 1; 22764661f46eSFabio Estevam 22774661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-rx", NULL)) 22784661f46eSFabio Estevam sport->inverted_rx = 1; 227922698aa2SShawn Guo 2280db0a196bSFabien Lahoudere if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { 2281db0a196bSFabien Lahoudere sport->rx_period_length = dma_buf_conf[0]; 2282db0a196bSFabien Lahoudere sport->rx_periods = dma_buf_conf[1]; 2283db0a196bSFabien Lahoudere } else { 2284db0a196bSFabien Lahoudere sport->rx_period_length = RX_DMA_PERIOD_LEN; 2285db0a196bSFabien Lahoudere sport->rx_periods = RX_DMA_PERIODS; 2286db0a196bSFabien Lahoudere } 2287db0a196bSFabien Lahoudere 22889d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 228956734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 229056734448SGeert Uytterhoeven sport->port.line); 229156734448SGeert Uytterhoeven return -EINVAL; 229256734448SGeert Uytterhoeven } 229356734448SGeert Uytterhoeven 2294ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2295da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2296da82f997SAlexander Shiyan if (IS_ERR(base)) 2297da82f997SAlexander Shiyan return PTR_ERR(base); 2298ab4382d2SGreg Kroah-Hartman 2299842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2300aa49d8e8SAnson Huang if (rxirq < 0) 2301aa49d8e8SAnson Huang return rxirq; 230231a8d8faSAnson Huang txirq = platform_get_irq_optional(pdev, 1); 230331a8d8faSAnson Huang rtsirq = platform_get_irq_optional(pdev, 2); 2304842633bdSUwe Kleine-König 2305ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2306ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2307ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 23085b109564SZheng Yongjun sport->port.type = PORT_IMX; 2309ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2310842633bdSUwe Kleine-König sport->port.irq = rxirq; 2311ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2312aa3479d2SDmitry Safonov sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 23139d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 23149d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 231500d7a00eSIlpo Järvinen /* RTS is required to control the RS485 transmitter */ 231600d7a00eSIlpo Järvinen if (sport->have_rtscts || sport->have_rtsgpio) 23170139da50SIlpo Järvinen sport->port.rs485_supported = imx_rs485_supported; 231800d7a00eSIlpo Järvinen else 23190139da50SIlpo Järvinen sport->port.rs485_supported = imx_no_rs485; 2320ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 23219d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2322ab4382d2SGreg Kroah-Hartman 232358362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 232458362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 232558362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 232658362d5bSUwe Kleine-König 23273a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 23283a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 23293a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2330833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 233142d34191SSachin Kamat return ret; 2332ab4382d2SGreg Kroah-Hartman } 2333ab4382d2SGreg Kroah-Hartman 23343a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 23353a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 23363a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2337833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 233842d34191SSachin Kamat return ret; 23393a9465faSSascha Hauer } 23403a9465faSSascha Hauer 23413a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2342ab4382d2SGreg Kroah-Hartman 23438a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 23448a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 23451e512d45SUwe Kleine-König if (ret) { 23461e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 23478a61f0c7SFabio Estevam return ret; 23481e512d45SUwe Kleine-König } 23498a61f0c7SFabio Estevam 23503a0ab62fSUwe Kleine-König /* initialize shadow register values */ 23513a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 23523a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 23533a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 23543a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 23553a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 23563a0ab62fSUwe Kleine-König 2357c150c0f3SLukas Wunner ret = uart_get_rs485_mode(&sport->port); 2358c150c0f3SLukas Wunner if (ret) { 2359c150c0f3SLukas Wunner clk_disable_unprepare(sport->clk_ipg); 2360c150c0f3SLukas Wunner return ret; 2361c150c0f3SLukas Wunner } 2362743f93f8SLukas Wunner 2363b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23645d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2365b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2366b8f3bff0SLukas Wunner 23676d215f83SStefan Agner /* 23686d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 23696d215f83SStefan Agner * signal cannot be set low during transmission in case the 23706d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 23716d215f83SStefan Agner */ 23726d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23736d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 23746d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 23756d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 23766d215f83SStefan Agner dev_err(&pdev->dev, 23776d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 23786d215f83SStefan Agner 23798a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 23804444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 23815f0e708cSYe Bin ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 23824444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 23838a61f0c7SFabio Estevam 238479d0224fSMarek Vasut /* 238579d0224fSMarek Vasut * In case RS485 is enabled without GPIO RTS control, the UART IP 238679d0224fSMarek Vasut * is used to control CTS signal. Keep both the UART and Receiver 238779d0224fSMarek Vasut * enabled, otherwise the UART IP pulls CTS signal always HIGH no 238879d0224fSMarek Vasut * matter how the UCR2 CTSC and CTS bits are set. To prevent any 238979d0224fSMarek Vasut * data from being fed into the RX FIFO, enable loopback mode in 239079d0224fSMarek Vasut * UTS register, which disconnects the RX path from external RXD 239179d0224fSMarek Vasut * pin and connects it to the Transceiver, which is disabled, so 239279d0224fSMarek Vasut * no data can be fed to the RX FIFO that way. 239379d0224fSMarek Vasut */ 239479d0224fSMarek Vasut if (sport->port.rs485.flags & SER_RS485_ENABLED && 239579d0224fSMarek Vasut sport->have_rtscts && !sport->have_rtsgpio) { 239679d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 239779d0224fSMarek Vasut uts |= UTS_LOOP; 239879d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 239979d0224fSMarek Vasut 240079d0224fSMarek Vasut ucr1 = imx_uart_readl(sport, UCR1); 240179d0224fSMarek Vasut ucr1 |= UCR1_UARTEN; 240279d0224fSMarek Vasut imx_uart_writel(sport, ucr1, UCR1); 240379d0224fSMarek Vasut 240479d0224fSMarek Vasut ucr2 = imx_uart_readl(sport, UCR2); 240579d0224fSMarek Vasut ucr2 |= UCR2_RXEN; 240679d0224fSMarek Vasut imx_uart_writel(sport, ucr2, UCR2); 240779d0224fSMarek Vasut } 240879d0224fSMarek Vasut 24099d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2410e61c38d8SUwe Kleine-König /* 2411e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2412e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2413e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2414e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2415e61c38d8SUwe Kleine-König */ 24164444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 24174444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 24184444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2419e61c38d8SUwe Kleine-König 2420e61c38d8SUwe Kleine-König /* 2421e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2422e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2423e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2424e61c38d8SUwe Kleine-König */ 242527c84426SUwe Kleine-König imx_uart_writel(sport, 242627c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 242727c84426SUwe Kleine-König UCR3); 2428e61c38d8SUwe Kleine-König 2429e61c38d8SUwe Kleine-König } else { 24304444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 24314444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 24324444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 24334444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 24346df765dcSUwe Kleine-König 24359d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 24366df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 243727c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2438e61c38d8SUwe Kleine-König } 2439e61c38d8SUwe Kleine-König 24408a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 24418a61f0c7SFabio Estevam 2442bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2443bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2444bd78ecd6SAhmad Fatoum sport->trigger_start_tx.function = imx_trigger_start_tx; 2445bd78ecd6SAhmad Fatoum sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2446cb1a6092SUwe Kleine-König 2447c0d1c6b0SFabio Estevam /* 2448c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2449c0d1c6b0SFabio Estevam * chips only have one interrupt. 2450c0d1c6b0SFabio Estevam */ 2451842633bdSUwe Kleine-König if (txirq > 0) { 24529d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2453c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24541e512d45SUwe Kleine-König if (ret) { 24551e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 24561e512d45SUwe Kleine-König ret); 2457c0d1c6b0SFabio Estevam return ret; 24581e512d45SUwe Kleine-König } 2459c0d1c6b0SFabio Estevam 24609d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2461c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24621e512d45SUwe Kleine-König if (ret) { 24631e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 24641e512d45SUwe Kleine-König ret); 2465c0d1c6b0SFabio Estevam return ret; 24661e512d45SUwe Kleine-König } 24677e620984SUwe Kleine-König 24687e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 24697e620984SUwe Kleine-König dev_name(&pdev->dev), sport); 24707e620984SUwe Kleine-König if (ret) { 24717e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n", 24727e620984SUwe Kleine-König ret); 24737e620984SUwe Kleine-König return ret; 24747e620984SUwe Kleine-König } 2475c0d1c6b0SFabio Estevam } else { 24769d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2477c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24781e512d45SUwe Kleine-König if (ret) { 24791e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2480c0d1c6b0SFabio Estevam return ret; 2481c0d1c6b0SFabio Estevam } 24821e512d45SUwe Kleine-König } 2483c0d1c6b0SFabio Estevam 24849d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2485ab4382d2SGreg Kroah-Hartman 24860a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2487ab4382d2SGreg Kroah-Hartman 24889d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2489ab4382d2SGreg Kroah-Hartman } 2490ab4382d2SGreg Kroah-Hartman 24919d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2492ab4382d2SGreg Kroah-Hartman { 2493ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2494ab4382d2SGreg Kroah-Hartman 24959d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2496ab4382d2SGreg Kroah-Hartman } 2497ab4382d2SGreg Kroah-Hartman 24989d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2499c868cbb7SEduardo Valentin { 250007b5e16eSAnson Huang unsigned long flags; 250107b5e16eSAnson Huang 250207b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 250307b5e16eSAnson Huang if (!sport->context_saved) { 250407b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2505c868cbb7SEduardo Valentin return; 250607b5e16eSAnson Huang } 2507c868cbb7SEduardo Valentin 250827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 250927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 251027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 251127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 251227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 251327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 251427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 251527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 251627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 251727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2518c868cbb7SEduardo Valentin sport->context_saved = false; 251907b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2520c868cbb7SEduardo Valentin } 2521c868cbb7SEduardo Valentin 25229d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2523c868cbb7SEduardo Valentin { 252407b5e16eSAnson Huang unsigned long flags; 252507b5e16eSAnson Huang 2526c868cbb7SEduardo Valentin /* Save necessary regs */ 252707b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 252827c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 252927c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 253027c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 253127c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 253227c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 253327c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 253427c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 253527c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 253627c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 253727c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2538c868cbb7SEduardo Valentin sport->context_saved = true; 253907b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2540c868cbb7SEduardo Valentin } 2541c868cbb7SEduardo Valentin 25429d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2543189550b8SEduardo Valentin { 25444444dcf1SUwe Kleine-König u32 ucr3; 2545189550b8SEduardo Valentin 25464444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 254709df0b34SMartin Kaiser if (on) { 254827c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 25494444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 25504444dcf1SUwe Kleine-König } else { 25514444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 255209df0b34SMartin Kaiser } 25534444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2554bc85734bSEduardo Valentin 255538b1f0fbSFabio Estevam if (sport->have_rtscts) { 25564444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2557c67643b4SFugang Duan if (on) { 2558c67643b4SFugang Duan imx_uart_writel(sport, USR1_RTSD, USR1); 25594444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2560c67643b4SFugang Duan } else { 25614444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 2562c67643b4SFugang Duan } 25634444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2564189550b8SEduardo Valentin } 256538b1f0fbSFabio Estevam } 2566189550b8SEduardo Valentin 25679d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 256890bb6bd3SShenwei Wang { 2569a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 257090bb6bd3SShenwei Wang 25719d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 257290bb6bd3SShenwei Wang 257390bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 257490bb6bd3SShenwei Wang 2575fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev); 2576fcfed1beSAnson Huang 257790bb6bd3SShenwei Wang return 0; 257890bb6bd3SShenwei Wang } 257990bb6bd3SShenwei Wang 25809d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 258190bb6bd3SShenwei Wang { 2582a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 258390bb6bd3SShenwei Wang int ret; 258490bb6bd3SShenwei Wang 2585fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev); 2586fcfed1beSAnson Huang 258790bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 258890bb6bd3SShenwei Wang if (ret) 258990bb6bd3SShenwei Wang return ret; 259090bb6bd3SShenwei Wang 25919d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 259290bb6bd3SShenwei Wang 259390bb6bd3SShenwei Wang return 0; 259490bb6bd3SShenwei Wang } 259590bb6bd3SShenwei Wang 25969d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 259790bb6bd3SShenwei Wang { 2598a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 259909df0b34SMartin Kaiser int ret; 260090bb6bd3SShenwei Wang 26019d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 260281b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 260390bb6bd3SShenwei Wang 260409df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 260509df0b34SMartin Kaiser if (ret) 260609df0b34SMartin Kaiser return ret; 260709df0b34SMartin Kaiser 260809df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 26099d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 261009df0b34SMartin Kaiser 261109df0b34SMartin Kaiser return 0; 261290bb6bd3SShenwei Wang } 261390bb6bd3SShenwei Wang 26149d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 261590bb6bd3SShenwei Wang { 2616a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 261790bb6bd3SShenwei Wang 261890bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 26199d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 262090bb6bd3SShenwei Wang 26219d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 262281b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 262390bb6bd3SShenwei Wang 262409df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 262529add68dSMartin Fuzzey 262690bb6bd3SShenwei Wang return 0; 262790bb6bd3SShenwei Wang } 262890bb6bd3SShenwei Wang 26299d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 263094be6d74SPhilipp Zabel { 2631a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 263294be6d74SPhilipp Zabel 26339d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 263494be6d74SPhilipp Zabel 263509df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 263694be6d74SPhilipp Zabel } 263794be6d74SPhilipp Zabel 26389d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 263994be6d74SPhilipp Zabel { 2640a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 264194be6d74SPhilipp Zabel 26429d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 264394be6d74SPhilipp Zabel 264409df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 264594be6d74SPhilipp Zabel 264694be6d74SPhilipp Zabel return 0; 264794be6d74SPhilipp Zabel } 264894be6d74SPhilipp Zabel 26499d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 26509d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 26519d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 26529d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 26534561d800SShawn Guo .thaw_noirq = imx_uart_resume_noirq, 26549d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 26559d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 26569d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 26579d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 26589d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 26599d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 266090bb6bd3SShenwei Wang }; 266190bb6bd3SShenwei Wang 26629d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 26639d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 26649d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2665ab4382d2SGreg Kroah-Hartman 2666ab4382d2SGreg Kroah-Hartman .driver = { 2667ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 266822698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 26699d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2670ab4382d2SGreg Kroah-Hartman }, 2671ab4382d2SGreg Kroah-Hartman }; 2672ab4382d2SGreg Kroah-Hartman 26739d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2674ab4382d2SGreg Kroah-Hartman { 26759d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2676ab4382d2SGreg Kroah-Hartman 2677ab4382d2SGreg Kroah-Hartman if (ret) 2678ab4382d2SGreg Kroah-Hartman return ret; 2679ab4382d2SGreg Kroah-Hartman 26809d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2681ab4382d2SGreg Kroah-Hartman if (ret != 0) 26829d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2683ab4382d2SGreg Kroah-Hartman 2684f227824eSUwe Kleine-König return ret; 2685ab4382d2SGreg Kroah-Hartman } 2686ab4382d2SGreg Kroah-Hartman 26879d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2688ab4382d2SGreg Kroah-Hartman { 26899d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 26909d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2691ab4382d2SGreg Kroah-Hartman } 2692ab4382d2SGreg Kroah-Hartman 26939d1a50a2SUwe Kleine-König module_init(imx_uart_init); 26949d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2695ab4382d2SGreg Kroah-Hartman 2696ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2697ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2698ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2699ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2700