1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 13ab4382d2SGreg Kroah-Hartman #endif 14ab4382d2SGreg Kroah-Hartman 15ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 23ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 24ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2922698aa2SShawn Guo #include <linux/of.h> 3022698aa2SShawn Guo #include <linux/of_device.h> 31e32a9f8fSSachin Kamat #include <linux/io.h> 32b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 3582906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 36b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 37ab4382d2SGreg Kroah-Hartman 3858362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3958362d5bSUwe Kleine-König 40ab4382d2SGreg Kroah-Hartman /* Register definitions */ 41ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 42ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 43ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 44ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 45ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 46ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 47ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 48ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 49ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 50ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 51ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 52ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 53ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 54ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 55fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 56fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 57fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 58ab4382d2SGreg Kroah-Hartman 59ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6055d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 61ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 62ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 63ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 64ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 65ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 66ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6726c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6825985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 69ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 71ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 72b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 74302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 77ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 79302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 80fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 81b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9401f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 101ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 104b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 105ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10827e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 109fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 115ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 118b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1257be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 126ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 127ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 128ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 129ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 130ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 131ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 133ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 134ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13686a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13727e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 138ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 142ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 143ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14590ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14690ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14990ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 150ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 151ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 152ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 153ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 154ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 155ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 156ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 157ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 158ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 159ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 160ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 161ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 162ab4382d2SGreg Kroah-Hartman 163ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 164ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 165ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 166ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 167ab4382d2SGreg Kroah-Hartman 168ab4382d2SGreg Kroah-Hartman /* 169ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 170ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 171ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 172ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 173ab4382d2SGreg Kroah-Hartman */ 174ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 175ab4382d2SGreg Kroah-Hartman 176ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 177ab4382d2SGreg Kroah-Hartman 178ab4382d2SGreg Kroah-Hartman #define UART_NR 8 179ab4382d2SGreg Kroah-Hartman 180f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 181fe6b540aSShawn Guo enum imx_uart_type { 182fe6b540aSShawn Guo IMX1_UART, 183fe6b540aSShawn Guo IMX21_UART, 1841c06bde6SMartyn Welch IMX53_UART, 185a496e628SHuang Shijie IMX6Q_UART, 186fe6b540aSShawn Guo }; 187fe6b540aSShawn Guo 188fe6b540aSShawn Guo /* device type dependent stuff */ 189fe6b540aSShawn Guo struct imx_uart_data { 190fe6b540aSShawn Guo unsigned uts_reg; 191fe6b540aSShawn Guo enum imx_uart_type devtype; 192fe6b540aSShawn Guo }; 193fe6b540aSShawn Guo 194ab4382d2SGreg Kroah-Hartman struct imx_port { 195ab4382d2SGreg Kroah-Hartman struct uart_port port; 196ab4382d2SGreg Kroah-Hartman struct timer_list timer; 197ab4382d2SGreg Kroah-Hartman unsigned int old_status; 198ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 1997b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20020ff2fe6SHuang Shijie unsigned int dte_mode:1; 2013a9465faSSascha Hauer struct clk *clk_ipg; 2023a9465faSSascha Hauer struct clk *clk_per; 2037d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 204b4cdc8f6SHuang Shijie 20558362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 20658362d5bSUwe Kleine-König 2073a0ab62fSUwe Kleine-König /* shadow registers */ 2083a0ab62fSUwe Kleine-König unsigned int ucr1; 2093a0ab62fSUwe Kleine-König unsigned int ucr2; 2103a0ab62fSUwe Kleine-König unsigned int ucr3; 2113a0ab62fSUwe Kleine-König unsigned int ucr4; 2123a0ab62fSUwe Kleine-König unsigned int ufcr; 2133a0ab62fSUwe Kleine-König 214b4cdc8f6SHuang Shijie /* DMA fields */ 215b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 216b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 217b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 218b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 219b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 220b4cdc8f6SHuang Shijie void *rx_buf; 2219d297239SNandor Han struct circ_buf rx_ring; 2229d297239SNandor Han unsigned int rx_periods; 2239d297239SNandor Han dma_cookie_t rx_cookie; 2247cb92fd2SHuang Shijie unsigned int tx_bytes; 225b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 22690bb6bd3SShenwei Wang unsigned int saved_reg[10]; 227c868cbb7SEduardo Valentin bool context_saved; 228ab4382d2SGreg Kroah-Hartman }; 229ab4382d2SGreg Kroah-Hartman 2300ad5a814SDirk Behme struct imx_port_ucrs { 2310ad5a814SDirk Behme unsigned int ucr1; 2320ad5a814SDirk Behme unsigned int ucr2; 2330ad5a814SDirk Behme unsigned int ucr3; 2340ad5a814SDirk Behme }; 2350ad5a814SDirk Behme 236fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 237fe6b540aSShawn Guo [IMX1_UART] = { 238fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 239fe6b540aSShawn Guo .devtype = IMX1_UART, 240fe6b540aSShawn Guo }, 241fe6b540aSShawn Guo [IMX21_UART] = { 242fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 243fe6b540aSShawn Guo .devtype = IMX21_UART, 244fe6b540aSShawn Guo }, 2451c06bde6SMartyn Welch [IMX53_UART] = { 2461c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2471c06bde6SMartyn Welch .devtype = IMX53_UART, 2481c06bde6SMartyn Welch }, 249a496e628SHuang Shijie [IMX6Q_UART] = { 250a496e628SHuang Shijie .uts_reg = IMX21_UTS, 251a496e628SHuang Shijie .devtype = IMX6Q_UART, 252a496e628SHuang Shijie }, 253fe6b540aSShawn Guo }; 254fe6b540aSShawn Guo 25531ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 256fe6b540aSShawn Guo { 257fe6b540aSShawn Guo .name = "imx1-uart", 258fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 259fe6b540aSShawn Guo }, { 260fe6b540aSShawn Guo .name = "imx21-uart", 261fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 262fe6b540aSShawn Guo }, { 2631c06bde6SMartyn Welch .name = "imx53-uart", 2641c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2651c06bde6SMartyn Welch }, { 266a496e628SHuang Shijie .name = "imx6q-uart", 267a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 268a496e628SHuang Shijie }, { 269fe6b540aSShawn Guo /* sentinel */ 270fe6b540aSShawn Guo } 271fe6b540aSShawn Guo }; 272fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 273fe6b540aSShawn Guo 274ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 275a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2761c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27722698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27822698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27922698aa2SShawn Guo { /* sentinel */ } 28022698aa2SShawn Guo }; 28122698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28222698aa2SShawn Guo 28327c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 28427c84426SUwe Kleine-König { 2853a0ab62fSUwe Kleine-König switch (offset) { 2863a0ab62fSUwe Kleine-König case UCR1: 2873a0ab62fSUwe Kleine-König sport->ucr1 = val; 2883a0ab62fSUwe Kleine-König break; 2893a0ab62fSUwe Kleine-König case UCR2: 2903a0ab62fSUwe Kleine-König sport->ucr2 = val; 2913a0ab62fSUwe Kleine-König break; 2923a0ab62fSUwe Kleine-König case UCR3: 2933a0ab62fSUwe Kleine-König sport->ucr3 = val; 2943a0ab62fSUwe Kleine-König break; 2953a0ab62fSUwe Kleine-König case UCR4: 2963a0ab62fSUwe Kleine-König sport->ucr4 = val; 2973a0ab62fSUwe Kleine-König break; 2983a0ab62fSUwe Kleine-König case UFCR: 2993a0ab62fSUwe Kleine-König sport->ufcr = val; 3003a0ab62fSUwe Kleine-König break; 3013a0ab62fSUwe Kleine-König default: 3023a0ab62fSUwe Kleine-König break; 3033a0ab62fSUwe Kleine-König } 30427c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 30527c84426SUwe Kleine-König } 30627c84426SUwe Kleine-König 30727c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30827c84426SUwe Kleine-König { 3093a0ab62fSUwe Kleine-König switch (offset) { 3103a0ab62fSUwe Kleine-König case UCR1: 3113a0ab62fSUwe Kleine-König return sport->ucr1; 3123a0ab62fSUwe Kleine-König break; 3133a0ab62fSUwe Kleine-König case UCR2: 3143a0ab62fSUwe Kleine-König /* 3153a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3163a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 317728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 318728e74a4SUwe Kleine-König * conditionally. 3193a0ab62fSUwe Kleine-König */ 3200aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3213a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3223a0ab62fSUwe Kleine-König return sport->ucr2; 3233a0ab62fSUwe Kleine-König break; 3243a0ab62fSUwe Kleine-König case UCR3: 3253a0ab62fSUwe Kleine-König return sport->ucr3; 3263a0ab62fSUwe Kleine-König break; 3273a0ab62fSUwe Kleine-König case UCR4: 3283a0ab62fSUwe Kleine-König return sport->ucr4; 3293a0ab62fSUwe Kleine-König break; 3303a0ab62fSUwe Kleine-König case UFCR: 3313a0ab62fSUwe Kleine-König return sport->ufcr; 3323a0ab62fSUwe Kleine-König break; 3333a0ab62fSUwe Kleine-König default: 33427c84426SUwe Kleine-König return readl(sport->port.membase + offset); 33527c84426SUwe Kleine-König } 3363a0ab62fSUwe Kleine-König } 33727c84426SUwe Kleine-König 3389d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 339fe6b540aSShawn Guo { 340fe6b540aSShawn Guo return sport->devdata->uts_reg; 341fe6b540aSShawn Guo } 342fe6b540aSShawn Guo 3439d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 344fe6b540aSShawn Guo { 345fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 346fe6b540aSShawn Guo } 347fe6b540aSShawn Guo 3489d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 349fe6b540aSShawn Guo { 350fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 351fe6b540aSShawn Guo } 352fe6b540aSShawn Guo 3539d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3541c06bde6SMartyn Welch { 3551c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3561c06bde6SMartyn Welch } 3571c06bde6SMartyn Welch 3589d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 359a496e628SHuang Shijie { 360a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 361a496e628SHuang Shijie } 362ab4382d2SGreg Kroah-Hartman /* 36344a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 36444a75411Sfabio.estevam@freescale.com */ 36593d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 3669d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 36744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36844a75411Sfabio.estevam@freescale.com { 36944a75411Sfabio.estevam@freescale.com /* save control registers */ 37027c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 37127c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 37227c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 37344a75411Sfabio.estevam@freescale.com } 37444a75411Sfabio.estevam@freescale.com 3759d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 37644a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37744a75411Sfabio.estevam@freescale.com { 37844a75411Sfabio.estevam@freescale.com /* restore control registers */ 37927c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 38027c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 38127c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 38244a75411Sfabio.estevam@freescale.com } 383e8bfa760SFabio Estevam #endif 38444a75411Sfabio.estevam@freescale.com 3859d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 38658362d5bSUwe Kleine-König { 387bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38858362d5bSUwe Kleine-König 389a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 390a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39158362d5bSUwe Kleine-König } 39258362d5bSUwe Kleine-König 3939d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 39458362d5bSUwe Kleine-König { 395bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 396bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39758362d5bSUwe Kleine-König 398a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 399a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 40058362d5bSUwe Kleine-König } 40158362d5bSUwe Kleine-König 4029d1a50a2SUwe Kleine-König static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2) 40358362d5bSUwe Kleine-König { 40458362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 40558362d5bSUwe Kleine-König } 40658362d5bSUwe Kleine-König 4076aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4089d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 40976821e22SUwe Kleine-König { 41076821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 41176821e22SUwe Kleine-König unsigned int ucr1, ucr2; 41276821e22SUwe Kleine-König 41376821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 41476821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 41576821e22SUwe Kleine-König 41676821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41776821e22SUwe Kleine-König 41876821e22SUwe Kleine-König if (sport->dma_is_enabled) { 41976821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 42076821e22SUwe Kleine-König } else { 42176821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 42281ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 42376821e22SUwe Kleine-König } 42476821e22SUwe Kleine-König 42576821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 42676821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42776821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42876821e22SUwe Kleine-König } 42976821e22SUwe Kleine-König 43076821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4319d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 432ab4382d2SGreg Kroah-Hartman { 433ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4344444dcf1SUwe Kleine-König u32 ucr1; 435ab4382d2SGreg Kroah-Hartman 4369ce4f8f3SGreg Kroah-Hartman /* 4379ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4389ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4399ce4f8f3SGreg Kroah-Hartman */ 440686351f3SUwe Kleine-König if (sport->dma_is_txing) 4419ce4f8f3SGreg Kroah-Hartman return; 442b4cdc8f6SHuang Shijie 4434444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 4444444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1); 44517b8f2a3SUwe Kleine-König 44617b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 44717b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 44827c84426SUwe Kleine-König imx_uart_readl(sport, USR2) & USR2_TXDC) { 4494444dcf1SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 45017b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4519d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4521a613626SFabio Estevam else 4539d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4544444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 45517b8f2a3SUwe Kleine-König 4569d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 45776821e22SUwe Kleine-König 4584444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 4594444dcf1SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 4604444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 46117b8f2a3SUwe Kleine-König } 462ab4382d2SGreg Kroah-Hartman } 463ab4382d2SGreg Kroah-Hartman 4646aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4659d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 466ab4382d2SGreg Kroah-Hartman { 467ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4684444dcf1SUwe Kleine-König u32 ucr1, ucr2; 469ab4382d2SGreg Kroah-Hartman 4704444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 47176821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 47276821e22SUwe Kleine-König 47376821e22SUwe Kleine-König if (sport->dma_is_enabled) { 47476821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 47576821e22SUwe Kleine-König } else { 47676821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 47781ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 47876821e22SUwe Kleine-König } 47976821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 48076821e22SUwe Kleine-König 48176821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 48276821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 483ab4382d2SGreg Kroah-Hartman } 484ab4382d2SGreg Kroah-Hartman 4856aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4869d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 487ab4382d2SGreg Kroah-Hartman { 488ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 489ab4382d2SGreg Kroah-Hartman 490ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 49158362d5bSUwe Kleine-König 49258362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 493ab4382d2SGreg Kroah-Hartman } 494ab4382d2SGreg Kroah-Hartman 4959d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 4966aed2a88SUwe Kleine-König 4976aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4989d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 499ab4382d2SGreg Kroah-Hartman { 500ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 501ab4382d2SGreg Kroah-Hartman 5025e42e9a3SPeter Hurley if (sport->port.x_char) { 5035e42e9a3SPeter Hurley /* Send next char */ 50427c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5057e2fb5aaSJiada Wang sport->port.icount.tx++; 5067e2fb5aaSJiada Wang sport->port.x_char = 0; 5075e42e9a3SPeter Hurley return; 5085e42e9a3SPeter Hurley } 5095e42e9a3SPeter Hurley 5105e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5119d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5125e42e9a3SPeter Hurley return; 5135e42e9a3SPeter Hurley } 5145e42e9a3SPeter Hurley 51591a1a909SJiada Wang if (sport->dma_is_enabled) { 5164444dcf1SUwe Kleine-König u32 ucr1; 51791a1a909SJiada Wang /* 51891a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 51991a1a909SJiada Wang * and the TX IRQ is disabled. 52091a1a909SJiada Wang **/ 5214444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5224444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXMPTYEN; 52391a1a909SJiada Wang if (sport->dma_is_txing) { 5244444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5254444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 52691a1a909SJiada Wang } else { 5274444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5289d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 52991a1a909SJiada Wang } 53091a1a909SJiada Wang 5315aabd3b0SIan Jamison return; 5320c549223SUwe Kleine-König } 5335aabd3b0SIan Jamison 5345aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5359d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 536ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 537ab4382d2SGreg Kroah-Hartman * out the port here */ 53827c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 539ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 540ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 541ab4382d2SGreg Kroah-Hartman } 542ab4382d2SGreg Kroah-Hartman 543ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 544ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 545ab4382d2SGreg Kroah-Hartman 546ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5479d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 548ab4382d2SGreg Kroah-Hartman } 549ab4382d2SGreg Kroah-Hartman 5509d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 551b4cdc8f6SHuang Shijie { 552b4cdc8f6SHuang Shijie struct imx_port *sport = data; 553b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 554b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 555b4cdc8f6SHuang Shijie unsigned long flags; 5564444dcf1SUwe Kleine-König u32 ucr1; 557b4cdc8f6SHuang Shijie 55842f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 55942f752b3SDirk Behme 560b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 561b4cdc8f6SHuang Shijie 5624444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5634444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5644444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 565a2c718ceSDirk Behme 56642f752b3SDirk Behme /* update the stat */ 56742f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 56842f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 56942f752b3SDirk Behme 57042f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 57142f752b3SDirk Behme 572b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 573b4cdc8f6SHuang Shijie 574d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 575b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5769ce4f8f3SGreg Kroah-Hartman 5770bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5789d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 57918665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 58018665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 58118665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 58218665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 58318665414SUwe Kleine-König } 58464432a85SUwe Kleine-König 5850bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 586b4cdc8f6SHuang Shijie } 587b4cdc8f6SHuang Shijie 5886aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5899d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 590b4cdc8f6SHuang Shijie { 591b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 592b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 593b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 594b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 595b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 59618665414SUwe Kleine-König u32 ucr1, ucr4; 597b4cdc8f6SHuang Shijie int ret; 598b4cdc8f6SHuang Shijie 59942f752b3SDirk Behme if (sport->dma_is_txing) 600b4cdc8f6SHuang Shijie return; 601b4cdc8f6SHuang Shijie 60218665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 60318665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 60418665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 60518665414SUwe Kleine-König 606b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 607b4cdc8f6SHuang Shijie 6087942f857SDirk Behme if (xmit->tail < xmit->head) { 6097942f857SDirk Behme sport->dma_tx_nents = 1; 6107942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6117942f857SDirk Behme } else { 612b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 613b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 614b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 615b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 616b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 617b4cdc8f6SHuang Shijie } 618b4cdc8f6SHuang Shijie 619b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 620b4cdc8f6SHuang Shijie if (ret == 0) { 621b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 622b4cdc8f6SHuang Shijie return; 623b4cdc8f6SHuang Shijie } 624b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 625b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 626b4cdc8f6SHuang Shijie if (!desc) { 62724649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 62824649821SDirk Behme DMA_TO_DEVICE); 629b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 630b4cdc8f6SHuang Shijie return; 631b4cdc8f6SHuang Shijie } 6329d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 633b4cdc8f6SHuang Shijie desc->callback_param = sport; 634b4cdc8f6SHuang Shijie 635b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 636b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 637a2c718ceSDirk Behme 6384444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6394444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6404444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 641a2c718ceSDirk Behme 642b4cdc8f6SHuang Shijie /* fire it */ 643b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 644b4cdc8f6SHuang Shijie dmaengine_submit(desc); 645b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 646b4cdc8f6SHuang Shijie return; 647b4cdc8f6SHuang Shijie } 648b4cdc8f6SHuang Shijie 6496aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6509d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 651ab4382d2SGreg Kroah-Hartman { 652ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6534444dcf1SUwe Kleine-König u32 ucr1; 654ab4382d2SGreg Kroah-Hartman 65548669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 65648669b69SUwe Kleine-König return; 65748669b69SUwe Kleine-König 65817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 65918665414SUwe Kleine-König u32 ucr2; 6604444dcf1SUwe Kleine-König 6614444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 66217b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6639d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 6641a613626SFabio Estevam else 6659d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 6664444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 66717b8f2a3SUwe Kleine-König 66876821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 6699d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 67076821e22SUwe Kleine-König 67118665414SUwe Kleine-König /* 67218665414SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA is off. 67318665414SUwe Kleine-König * In the DMA case this is done in the tx-callback. 67418665414SUwe Kleine-König */ 67518665414SUwe Kleine-König if (!sport->dma_is_enabled) { 67618665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 6774444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 6784444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 67917b8f2a3SUwe Kleine-König } 68018665414SUwe Kleine-König } 68117b8f2a3SUwe Kleine-König 682b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 6834444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6844444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1); 685b4cdc8f6SHuang Shijie } 686ab4382d2SGreg Kroah-Hartman 687b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 68891a1a909SJiada Wang if (sport->port.x_char) { 68991a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 69091a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 6914444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6924444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 6934444dcf1SUwe Kleine-König ucr1 |= UCR1_TXMPTYEN; 6944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 69591a1a909SJiada Wang return; 69691a1a909SJiada Wang } 69791a1a909SJiada Wang 6985e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6995e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7009d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 701b4cdc8f6SHuang Shijie return; 702b4cdc8f6SHuang Shijie } 703ab4382d2SGreg Kroah-Hartman } 704ab4382d2SGreg Kroah-Hartman 7059d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 706ab4382d2SGreg Kroah-Hartman { 707ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7084444dcf1SUwe Kleine-König u32 usr1; 709ab4382d2SGreg Kroah-Hartman 710c974991dSjun qian spin_lock(&sport->port.lock); 711ab4382d2SGreg Kroah-Hartman 71227c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7134444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7144444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 715ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 716ab4382d2SGreg Kroah-Hartman 717c974991dSjun qian spin_unlock(&sport->port.lock); 718ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 719ab4382d2SGreg Kroah-Hartman } 720ab4382d2SGreg Kroah-Hartman 7219d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 722ab4382d2SGreg Kroah-Hartman { 723ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 724ab4382d2SGreg Kroah-Hartman 725c974991dSjun qian spin_lock(&sport->port.lock); 7269d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 727c974991dSjun qian spin_unlock(&sport->port.lock); 728ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 729ab4382d2SGreg Kroah-Hartman } 730ab4382d2SGreg Kroah-Hartman 7319d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 732ab4382d2SGreg Kroah-Hartman { 733ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 734ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 73592a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 736ab4382d2SGreg Kroah-Hartman 737c974991dSjun qian spin_lock(&sport->port.lock); 738ab4382d2SGreg Kroah-Hartman 73927c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 7404444dcf1SUwe Kleine-König u32 usr2; 7414444dcf1SUwe Kleine-König 742ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 743ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 744ab4382d2SGreg Kroah-Hartman 74527c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 746ab4382d2SGreg Kroah-Hartman 7474444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 7484444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 74927c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 750ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 751ab4382d2SGreg Kroah-Hartman continue; 752ab4382d2SGreg Kroah-Hartman } 753ab4382d2SGreg Kroah-Hartman 754ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 755ab4382d2SGreg Kroah-Hartman continue; 756ab4382d2SGreg Kroah-Hartman 757019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 758019dc9eaSHui Wang if (rx & URXD_BRK) 759019dc9eaSHui Wang sport->port.icount.brk++; 760019dc9eaSHui Wang else if (rx & URXD_PRERR) 761ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 762ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 763ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 764ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 765ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 766ab4382d2SGreg Kroah-Hartman 767ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 768ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 769ab4382d2SGreg Kroah-Hartman goto out; 770ab4382d2SGreg Kroah-Hartman continue; 771ab4382d2SGreg Kroah-Hartman } 772ab4382d2SGreg Kroah-Hartman 7738d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 774ab4382d2SGreg Kroah-Hartman 775019dc9eaSHui Wang if (rx & URXD_BRK) 776019dc9eaSHui Wang flg = TTY_BREAK; 777019dc9eaSHui Wang else if (rx & URXD_PRERR) 778ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 779ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 780ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 781ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 782ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 783ab4382d2SGreg Kroah-Hartman 784ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 785ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 786ab4382d2SGreg Kroah-Hartman #endif 787ab4382d2SGreg Kroah-Hartman } 788ab4382d2SGreg Kroah-Hartman 78955d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 79055d8693aSJiada Wang goto out; 79155d8693aSJiada Wang 7929b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 7939b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 794ab4382d2SGreg Kroah-Hartman } 795ab4382d2SGreg Kroah-Hartman 796ab4382d2SGreg Kroah-Hartman out: 797c974991dSjun qian spin_unlock(&sport->port.lock); 7982e124b4aSJiri Slaby tty_flip_buffer_push(port); 799ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 800ab4382d2SGreg Kroah-Hartman } 801ab4382d2SGreg Kroah-Hartman 8029d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 803b4cdc8f6SHuang Shijie 80466f95884SUwe Kleine-König /* 80566f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 80666f95884SUwe Kleine-König */ 8079d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 80866f95884SUwe Kleine-König { 80966f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 81027c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 81127c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 81266f95884SUwe Kleine-König 81366f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 81466f95884SUwe Kleine-König tmp |= TIOCM_CTS; 81566f95884SUwe Kleine-König 81666f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 8174b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 81866f95884SUwe Kleine-König tmp |= TIOCM_CAR; 81966f95884SUwe Kleine-König 82066f95884SUwe Kleine-König if (sport->dte_mode) 82127c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 82266f95884SUwe Kleine-König tmp |= TIOCM_RI; 82366f95884SUwe Kleine-König 82466f95884SUwe Kleine-König return tmp; 82566f95884SUwe Kleine-König } 82666f95884SUwe Kleine-König 82766f95884SUwe Kleine-König /* 82866f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 82966f95884SUwe Kleine-König */ 8309d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 83166f95884SUwe Kleine-König { 83266f95884SUwe Kleine-König unsigned int status, changed; 83366f95884SUwe Kleine-König 8349d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 83566f95884SUwe Kleine-König changed = status ^ sport->old_status; 83666f95884SUwe Kleine-König 83766f95884SUwe Kleine-König if (changed == 0) 83866f95884SUwe Kleine-König return; 83966f95884SUwe Kleine-König 84066f95884SUwe Kleine-König sport->old_status = status; 84166f95884SUwe Kleine-König 84266f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 84366f95884SUwe Kleine-König sport->port.icount.rng++; 84466f95884SUwe Kleine-König if (changed & TIOCM_DSR) 84566f95884SUwe Kleine-König sport->port.icount.dsr++; 84666f95884SUwe Kleine-König if (changed & TIOCM_CAR) 84766f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 84866f95884SUwe Kleine-König if (changed & TIOCM_CTS) 84966f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 85066f95884SUwe Kleine-König 85166f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 85266f95884SUwe Kleine-König } 85366f95884SUwe Kleine-König 8549d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 855ab4382d2SGreg Kroah-Hartman { 856ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 85743776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 8584d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 859ab4382d2SGreg Kroah-Hartman 86027c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 86127c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 86227c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 86327c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 86427c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 86527c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 866ab4382d2SGreg Kroah-Hartman 86743776896SUwe Kleine-König /* 86843776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 86943776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 87043776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 87143776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 87243776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 87343776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 87443776896SUwe Kleine-König */ 87543776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 87643776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 87743776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 87843776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 87943776896SUwe Kleine-König if ((ucr1 & UCR1_TXMPTYEN) == 0) 88043776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 88143776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 88243776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 88343776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 88443776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 88543776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 88643776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 88743776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 88843776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 88943776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 89043776896SUwe Kleine-König usr2 &= ~USR2_ORE; 89143776896SUwe Kleine-König 89243776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 8939d1a50a2SUwe Kleine-König imx_uart_rxint(irq, dev_id); 8944d845a62SUwe Kleine-König ret = IRQ_HANDLED; 895b4cdc8f6SHuang Shijie } 896ab4382d2SGreg Kroah-Hartman 89743776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 8989d1a50a2SUwe Kleine-König imx_uart_txint(irq, dev_id); 8994d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9004d845a62SUwe Kleine-König } 901ab4382d2SGreg Kroah-Hartman 9020399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 90327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 90427e16501SUwe Kleine-König 905c974991dSjun qian spin_lock(&sport->port.lock); 9069d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 907c974991dSjun qian spin_unlock(&sport->port.lock); 90827e16501SUwe Kleine-König 90927e16501SUwe Kleine-König ret = IRQ_HANDLED; 91027e16501SUwe Kleine-König } 91127e16501SUwe Kleine-König 9120399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 9139d1a50a2SUwe Kleine-König imx_uart_rtsint(irq, dev_id); 9144d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9154d845a62SUwe Kleine-König } 916ab4382d2SGreg Kroah-Hartman 9170399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 91827c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 9194d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9204d845a62SUwe Kleine-König } 921db1a9b55SFabio Estevam 9220399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 923f1f836e4SAlexander Stein sport->port.icount.overrun++; 92427c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 9254d845a62SUwe Kleine-König ret = IRQ_HANDLED; 926f1f836e4SAlexander Stein } 927f1f836e4SAlexander Stein 9284d845a62SUwe Kleine-König return ret; 929ab4382d2SGreg Kroah-Hartman } 930ab4382d2SGreg Kroah-Hartman 931ab4382d2SGreg Kroah-Hartman /* 932ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 933ab4382d2SGreg Kroah-Hartman */ 9349d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 935ab4382d2SGreg Kroah-Hartman { 936ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9371ce43e58SHuang Shijie unsigned int ret; 938ab4382d2SGreg Kroah-Hartman 93927c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 9401ce43e58SHuang Shijie 9411ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 942686351f3SUwe Kleine-König if (sport->dma_is_txing) 9431ce43e58SHuang Shijie ret = 0; 9441ce43e58SHuang Shijie 9451ce43e58SHuang Shijie return ret; 946ab4382d2SGreg Kroah-Hartman } 947ab4382d2SGreg Kroah-Hartman 9486aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 9499d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 95058362d5bSUwe Kleine-König { 95158362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 9529d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 95358362d5bSUwe Kleine-König 95458362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 95558362d5bSUwe Kleine-König 95658362d5bSUwe Kleine-König return ret; 95758362d5bSUwe Kleine-König } 95858362d5bSUwe Kleine-König 9596aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 9609d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 961ab4382d2SGreg Kroah-Hartman { 962ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9634444dcf1SUwe Kleine-König u32 ucr3, uts; 964ab4382d2SGreg Kroah-Hartman 96517b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 9664444dcf1SUwe Kleine-König u32 ucr2; 9674444dcf1SUwe Kleine-König 9684444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 9694444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 970ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 9714444dcf1SUwe Kleine-König ucr2 |= UCR2_CTS | UCR2_CTSC; 9724444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 97317b8f2a3SUwe Kleine-König } 9746b471a98SHuang Shijie 9754444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 97690ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 9774444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 9784444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 97990ebc483SUwe Kleine-König 9809d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 9816b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 9824444dcf1SUwe Kleine-König uts |= UTS_LOOP; 9839d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 98458362d5bSUwe Kleine-König 98558362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 986ab4382d2SGreg Kroah-Hartman } 987ab4382d2SGreg Kroah-Hartman 988ab4382d2SGreg Kroah-Hartman /* 989ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 990ab4382d2SGreg Kroah-Hartman */ 9919d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 992ab4382d2SGreg Kroah-Hartman { 993ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9944444dcf1SUwe Kleine-König unsigned long flags; 9954444dcf1SUwe Kleine-König u32 ucr1; 996ab4382d2SGreg Kroah-Hartman 997ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 998ab4382d2SGreg Kroah-Hartman 9994444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1000ab4382d2SGreg Kroah-Hartman 1001ab4382d2SGreg Kroah-Hartman if (break_state != 0) 10024444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1003ab4382d2SGreg Kroah-Hartman 10044444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1005ab4382d2SGreg Kroah-Hartman 1006ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1007ab4382d2SGreg Kroah-Hartman } 1008ab4382d2SGreg Kroah-Hartman 1009cc568849SUwe Kleine-König /* 1010cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1011cc568849SUwe Kleine-König * modem status signals. 1012cc568849SUwe Kleine-König */ 10139d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1014cc568849SUwe Kleine-König { 1015e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1016cc568849SUwe Kleine-König unsigned long flags; 1017cc568849SUwe Kleine-König 1018cc568849SUwe Kleine-König if (sport->port.state) { 1019cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 10209d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1021cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1022cc568849SUwe Kleine-König 1023cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1024cc568849SUwe Kleine-König } 1025cc568849SUwe Kleine-König } 1026cc568849SUwe Kleine-König 1027351ea50dSGreg Kroah-Hartman #define RX_BUF_SIZE (PAGE_SIZE) 1028351ea50dSGreg Kroah-Hartman 1029b4cdc8f6SHuang Shijie /* 1030905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1031b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1032905c0decSLucas Stach * [2] the aging timer expires 1033b4cdc8f6SHuang Shijie * 1034905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1035905c0decSLucas Stach * for at least 8 byte durations. 1036b4cdc8f6SHuang Shijie */ 10379d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1038b4cdc8f6SHuang Shijie { 1039b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1040b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1041b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 10427cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1043b4cdc8f6SHuang Shijie struct dma_tx_state state; 10449d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1045b4cdc8f6SHuang Shijie enum dma_status status; 10469d297239SNandor Han unsigned int w_bytes = 0; 10479d297239SNandor Han unsigned int r_bytes; 10489d297239SNandor Han unsigned int bd_size; 1049b4cdc8f6SHuang Shijie 1050fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1051392bceedSPhilipp Zabel 10529d297239SNandor Han if (status == DMA_ERROR) { 10539d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 10549d297239SNandor Han return; 10559d297239SNandor Han } 1056b4cdc8f6SHuang Shijie 10579b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1058976b39cdSLucas Stach 1059976b39cdSLucas Stach /* 10609d297239SNandor Han * The state-residue variable represents the empty space 10619d297239SNandor Han * relative to the entire buffer. Taking this in consideration 10629d297239SNandor Han * the head is always calculated base on the buffer total 10639d297239SNandor Han * length - DMA transaction residue. The UART script from the 10649d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 10659d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 10669d297239SNandor Han * Taking this in consideration the tail is always at the 10679d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1068976b39cdSLucas Stach */ 10699d297239SNandor Han 10709d297239SNandor Han /* Calculate the head */ 10719d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 10729d297239SNandor Han 10739d297239SNandor Han /* Calculate the tail. */ 10749d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 10759d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 10769d297239SNandor Han 10779d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 10789d297239SNandor Han rx_ring->head > rx_ring->tail) { 10799d297239SNandor Han 10809d297239SNandor Han /* Move data from tail to head */ 10819d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 10829d297239SNandor Han 10839d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 10849d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 10859d297239SNandor Han DMA_FROM_DEVICE); 10869d297239SNandor Han 10879d297239SNandor Han w_bytes = tty_insert_flip_string(port, 10889d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 10899d297239SNandor Han 10909d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 10919d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 10929d297239SNandor Han DMA_FROM_DEVICE); 10939d297239SNandor Han 10949d297239SNandor Han if (w_bytes != r_bytes) 10959d297239SNandor Han sport->port.icount.buf_overrun++; 10969d297239SNandor Han 10979d297239SNandor Han sport->port.icount.rx += w_bytes; 10989d297239SNandor Han } else { 10999d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11009d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1101ee5e7c10SRobin Gong } 11029d297239SNandor Han } 11039d297239SNandor Han 11049d297239SNandor Han if (w_bytes) { 11059d297239SNandor Han tty_flip_buffer_push(port); 11069d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 11079d297239SNandor Han } 11089d297239SNandor Han } 11099d297239SNandor Han 1110351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 1111351ea50dSGreg Kroah-Hartman #define RX_DMA_PERIODS 4 1112351ea50dSGreg Kroah-Hartman 11139d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1114b4cdc8f6SHuang Shijie { 1115b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1116b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1117b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1118b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1119b4cdc8f6SHuang Shijie int ret; 1120b4cdc8f6SHuang Shijie 11219d297239SNandor Han sport->rx_ring.head = 0; 11229d297239SNandor Han sport->rx_ring.tail = 0; 1123351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 11249d297239SNandor Han 1125351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1126b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1127b4cdc8f6SHuang Shijie if (ret == 0) { 1128b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1129b4cdc8f6SHuang Shijie return -EINVAL; 1130b4cdc8f6SHuang Shijie } 11319d297239SNandor Han 11329d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 11339d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 11349d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 11359d297239SNandor Han 1136b4cdc8f6SHuang Shijie if (!desc) { 113724649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1138b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1139b4cdc8f6SHuang Shijie return -EINVAL; 1140b4cdc8f6SHuang Shijie } 11419d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1142b4cdc8f6SHuang Shijie desc->callback_param = sport; 1143b4cdc8f6SHuang Shijie 1144b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 11454139fd76SRomain Perier sport->dma_is_rxing = 1; 11469d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1147b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1148b4cdc8f6SHuang Shijie return 0; 1149b4cdc8f6SHuang Shijie } 1150b4cdc8f6SHuang Shijie 11519d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 115241d98b5dSNandor Han { 115345ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 11544444dcf1SUwe Kleine-König u32 usr1, usr2; 115541d98b5dSNandor Han 11564444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 11574444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 115841d98b5dSNandor Han 11594444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 116041d98b5dSNandor Han sport->port.icount.brk++; 116127c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 116245ca673eSTroy Kisky uart_handle_break(&sport->port); 116345ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 116445ca673eSTroy Kisky sport->port.icount.buf_overrun++; 116545ca673eSTroy Kisky tty_flip_buffer_push(port); 116645ca673eSTroy Kisky } else { 116745ca673eSTroy Kisky dev_err(sport->port.dev, "DMA transaction error.\n"); 11684444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 116941d98b5dSNandor Han sport->port.icount.frame++; 117027c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 11714444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 117241d98b5dSNandor Han sport->port.icount.parity++; 117327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 117441d98b5dSNandor Han } 117545ca673eSTroy Kisky } 117641d98b5dSNandor Han 11774444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 117841d98b5dSNandor Han sport->port.icount.overrun++; 117927c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 118041d98b5dSNandor Han } 118141d98b5dSNandor Han 118241d98b5dSNandor Han } 118341d98b5dSNandor Han 1184cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1185cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1186184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1187184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1188cc32382dSLucas Stach 11899d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1190cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1191cc32382dSLucas Stach { 1192cc32382dSLucas Stach unsigned int val; 1193cc32382dSLucas Stach 1194cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 119527c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1196cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 119727c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1198cc32382dSLucas Stach } 1199cc32382dSLucas Stach 1200b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1201b4cdc8f6SHuang Shijie { 1202b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1203e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1204b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1205b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 12069d297239SNandor Han sport->rx_cookie = -EINVAL; 1207b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1208b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1209b4cdc8f6SHuang Shijie } 1210b4cdc8f6SHuang Shijie 1211b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1212e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1213b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1214b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1215b4cdc8f6SHuang Shijie } 1216b4cdc8f6SHuang Shijie } 1217b4cdc8f6SHuang Shijie 1218b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1219b4cdc8f6SHuang Shijie { 1220b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1221b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1222b4cdc8f6SHuang Shijie int ret; 1223b4cdc8f6SHuang Shijie 1224b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1225b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1226b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1227b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1228b4cdc8f6SHuang Shijie ret = -EINVAL; 1229b4cdc8f6SHuang Shijie goto err; 1230b4cdc8f6SHuang Shijie } 1231b4cdc8f6SHuang Shijie 1232b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1233b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1234b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1235184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1236184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1237b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1238b4cdc8f6SHuang Shijie if (ret) { 1239b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1240b4cdc8f6SHuang Shijie goto err; 1241b4cdc8f6SHuang Shijie } 1242b4cdc8f6SHuang Shijie 1243f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1244b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1245b4cdc8f6SHuang Shijie ret = -ENOMEM; 1246b4cdc8f6SHuang Shijie goto err; 1247b4cdc8f6SHuang Shijie } 12489d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1249b4cdc8f6SHuang Shijie 1250b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1251b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1252b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1253b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1254b4cdc8f6SHuang Shijie ret = -EINVAL; 1255b4cdc8f6SHuang Shijie goto err; 1256b4cdc8f6SHuang Shijie } 1257b4cdc8f6SHuang Shijie 1258b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1259b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1260b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1261184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1262b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1263b4cdc8f6SHuang Shijie if (ret) { 1264b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1265b4cdc8f6SHuang Shijie goto err; 1266b4cdc8f6SHuang Shijie } 1267b4cdc8f6SHuang Shijie 1268b4cdc8f6SHuang Shijie return 0; 1269b4cdc8f6SHuang Shijie err: 1270b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1271b4cdc8f6SHuang Shijie return ret; 1272b4cdc8f6SHuang Shijie } 1273b4cdc8f6SHuang Shijie 12749d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1275b4cdc8f6SHuang Shijie { 12764444dcf1SUwe Kleine-König u32 ucr1; 1277b4cdc8f6SHuang Shijie 12789d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 127902b0abd3SUwe Kleine-König 1280b4cdc8f6SHuang Shijie /* set UCR1 */ 12814444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12824444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 12834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1284b4cdc8f6SHuang Shijie 1285b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1286b4cdc8f6SHuang Shijie } 1287b4cdc8f6SHuang Shijie 12889d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1289b4cdc8f6SHuang Shijie { 1290676a31d8SSebastian Reichel u32 ucr1; 1291b4cdc8f6SHuang Shijie 1292b4cdc8f6SHuang Shijie /* clear UCR1 */ 12934444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12944444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 12954444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1296b4cdc8f6SHuang Shijie 12979d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1298184bd70bSLucas Stach 1299b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1300b4cdc8f6SHuang Shijie } 1301b4cdc8f6SHuang Shijie 1302ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1303ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1304ab4382d2SGreg Kroah-Hartman 13059d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1306ab4382d2SGreg Kroah-Hartman { 1307ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1308458e2c82SFabio Estevam int retval, i; 13094444dcf1SUwe Kleine-König unsigned long flags; 13104238c00bSUwe Kleine-König int dma_is_inited = 0; 13114444dcf1SUwe Kleine-König u32 ucr1, ucr2, ucr4; 1312ab4382d2SGreg Kroah-Hartman 131328eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 131428eb4274SHuang Shijie if (retval) 1315cb0f0a5fSFabio Estevam return retval; 131628eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 13170c375501SHuang Shijie if (retval) { 13180c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1319cb0f0a5fSFabio Estevam return retval; 13200c375501SHuang Shijie } 132128eb4274SHuang Shijie 13229d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1323ab4382d2SGreg Kroah-Hartman 1324ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1325ab4382d2SGreg Kroah-Hartman * requesting IRQs 1326ab4382d2SGreg Kroah-Hartman */ 13274444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1328ab4382d2SGreg Kroah-Hartman 1329ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 13304444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 13314444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1332ab4382d2SGreg Kroah-Hartman 13334444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1334ab4382d2SGreg Kroah-Hartman 13357e11577eSLucas Stach /* Can we enable the DMA support? */ 13364238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 13374238c00bSUwe Kleine-König dma_is_inited = 1; 13387e11577eSLucas Stach 133953794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1340772f8991SHuang Shijie /* Reset fifo's and state machines */ 1341458e2c82SFabio Estevam i = 100; 1342458e2c82SFabio Estevam 13434444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 13444444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 13454444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1346458e2c82SFabio Estevam 134727c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1348458e2c82SFabio Estevam udelay(1); 1349ab4382d2SGreg Kroah-Hartman 1350ab4382d2SGreg Kroah-Hartman /* 1351ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1352ab4382d2SGreg Kroah-Hartman */ 135327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 135427c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1355ab4382d2SGreg Kroah-Hartman 13564444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 13574444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 13586376cd39SNandor Han if (sport->have_rtscts) 13594444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1360ab4382d2SGreg Kroah-Hartman 13614444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1362ab4382d2SGreg Kroah-Hartman 13634444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 13641f043572STroy Kisky if (!sport->dma_is_enabled) 13654444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 13664444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 13676f026d6bSJiada Wang 13684444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 13694444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1370bff09b09SLucas Stach if (!sport->have_rtscts) 13714444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 137216804d68SUwe Kleine-König /* 137316804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 137416804d68SUwe Kleine-König * we're using RTSD instead. 137516804d68SUwe Kleine-König */ 13769d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 13774444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 13784444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1379ab4382d2SGreg Kroah-Hartman 13809d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) { 13814444dcf1SUwe Kleine-König u32 ucr3; 138216804d68SUwe Kleine-König 13834444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 13844444dcf1SUwe Kleine-König 13854444dcf1SUwe Kleine-König ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 138616804d68SUwe Kleine-König 138716804d68SUwe Kleine-König if (sport->dte_mode) 1388e61c38d8SUwe Kleine-König /* disable broken interrupts */ 13894444dcf1SUwe Kleine-König ucr3 &= ~(UCR3_RI | UCR3_DCD); 139016804d68SUwe Kleine-König 13914444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 1392ab4382d2SGreg Kroah-Hartman } 1393ab4382d2SGreg Kroah-Hartman 1394ab4382d2SGreg Kroah-Hartman /* 1395ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1396ab4382d2SGreg Kroah-Hartman */ 13979d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 139818a42088SPeter Senna Tschudin 139976821e22SUwe Kleine-König if (dma_is_inited) { 14009d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 14019d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 140276821e22SUwe Kleine-König } else { 140376821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 140476821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 140576821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 140681ca8e82SUwe Kleine-König 140781ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 140881ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 140981ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 141076821e22SUwe Kleine-König } 141118a42088SPeter Senna Tschudin 1412ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1413ab4382d2SGreg Kroah-Hartman 1414ab4382d2SGreg Kroah-Hartman return 0; 1415ab4382d2SGreg Kroah-Hartman } 1416ab4382d2SGreg Kroah-Hartman 14179d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1418ab4382d2SGreg Kroah-Hartman { 1419ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 14209ec1882dSXinyu Chen unsigned long flags; 1421339c7a87SSebastian Reichel u32 ucr1, ucr2, ucr4; 1422ab4382d2SGreg Kroah-Hartman 1423b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1424e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 14257722c240SSebastian Reichel if (sport->dma_is_txing) { 14267722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 14277722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 14287722c240SSebastian Reichel sport->dma_is_txing = 0; 14297722c240SSebastian Reichel } 1430e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 14317722c240SSebastian Reichel if (sport->dma_is_rxing) { 14327722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 14337722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 14347722c240SSebastian Reichel sport->dma_is_rxing = 0; 14357722c240SSebastian Reichel } 14369d297239SNandor Han 143773631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 14389d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 14399d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 14409d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 144173631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1442b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1443b4cdc8f6SHuang Shijie } 1444b4cdc8f6SHuang Shijie 144558362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 144658362d5bSUwe Kleine-König 14479ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14484444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14490fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 14504444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1451339c7a87SSebastian Reichel 1452339c7a87SSebastian Reichel ucr4 = imx_uart_readl(sport, UCR4); 1453339c7a87SSebastian Reichel ucr4 &= ~UCR4_OREN; 1454339c7a87SSebastian Reichel imx_uart_writel(sport, ucr4, UCR4); 14559ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1456ab4382d2SGreg Kroah-Hartman 1457ab4382d2SGreg Kroah-Hartman /* 1458ab4382d2SGreg Kroah-Hartman * Stop our timer. 1459ab4382d2SGreg Kroah-Hartman */ 1460ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1461ab4382d2SGreg Kroah-Hartman 1462ab4382d2SGreg Kroah-Hartman /* 1463ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1464ab4382d2SGreg Kroah-Hartman */ 1465ab4382d2SGreg Kroah-Hartman 14669ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14674444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 146876821e22SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1469ab4382d2SGreg Kroah-Hartman 14704444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14719ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 147228eb4274SHuang Shijie 147328eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 147428eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1475ab4382d2SGreg Kroah-Hartman } 1476ab4382d2SGreg Kroah-Hartman 14776aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 14789d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1479eb56b7edSHuang Shijie { 1480eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 148182e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 14824444dcf1SUwe Kleine-König u32 ucr2; 14834f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1484eb56b7edSHuang Shijie 148582e86ae9SDirk Behme if (!sport->dma_chan_tx) 148682e86ae9SDirk Behme return; 148782e86ae9SDirk Behme 1488eb56b7edSHuang Shijie sport->tx_bytes = 0; 1489eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 149082e86ae9SDirk Behme if (sport->dma_is_txing) { 14914444dcf1SUwe Kleine-König u32 ucr1; 14924444dcf1SUwe Kleine-König 149382e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 149482e86ae9SDirk Behme DMA_TO_DEVICE); 14954444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 14964444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 14974444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14980f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1499eb56b7edSHuang Shijie } 1500934084a9SFabio Estevam 1501934084a9SFabio Estevam /* 1502934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1503263763c1SMartyn Welch * 1504934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1505934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1506263763c1SMartyn Welch * and UTS[6-3]". 1507263763c1SMartyn Welch * 1508263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1509263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1510263763c1SMartyn Welch * registers. 1511934084a9SFabio Estevam */ 151227c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 151327c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 151427c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1515934084a9SFabio Estevam 15164444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15174444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 15184444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1519934084a9SFabio Estevam 152027c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1521934084a9SFabio Estevam udelay(1); 1522934084a9SFabio Estevam 1523934084a9SFabio Estevam /* Restore the registers */ 152427c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 152527c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 152627c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1527eb56b7edSHuang Shijie } 1528eb56b7edSHuang Shijie 1529ab4382d2SGreg Kroah-Hartman static void 15309d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1531ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1532ab4382d2SGreg Kroah-Hartman { 1533ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1534ab4382d2SGreg Kroah-Hartman unsigned long flags; 15354444dcf1SUwe Kleine-König u32 ucr2, old_ucr1, old_ucr2, ufcr; 153658362d5bSUwe Kleine-König unsigned int baud, quot; 1537ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 15384444dcf1SUwe Kleine-König unsigned long div; 1539ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1540ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1541ab4382d2SGreg Kroah-Hartman 1542ab4382d2SGreg Kroah-Hartman /* 1543ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1544ab4382d2SGreg Kroah-Hartman */ 1545ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1546ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1547ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1548ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1549ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1550ab4382d2SGreg Kroah-Hartman } 1551ab4382d2SGreg Kroah-Hartman 1552ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1553ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1554ab4382d2SGreg Kroah-Hartman else 1555ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1556ab4382d2SGreg Kroah-Hartman 1557ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1558ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1559ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 156017b8f2a3SUwe Kleine-König 156112fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 156217b8f2a3SUwe Kleine-König /* 156317b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 156417b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 156517b8f2a3SUwe Kleine-König * disabled. 156617b8f2a3SUwe Kleine-König */ 156758362d5bSUwe Kleine-König if (port->rs485.flags & 156858362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 15699d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 15701a613626SFabio Estevam else 15719d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 157212fe59f9SFabio Estevam } else { 15739d1a50a2SUwe Kleine-König imx_uart_rts_auto(sport, &ucr2); 157412fe59f9SFabio Estevam } 1575ab4382d2SGreg Kroah-Hartman } else { 1576ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1577ab4382d2SGreg Kroah-Hartman } 157858362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 157917b8f2a3SUwe Kleine-König /* disable transmitter */ 158058362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 15819d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 15821a613626SFabio Estevam else 15839d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 158458362d5bSUwe Kleine-König } 158558362d5bSUwe Kleine-König 1586ab4382d2SGreg Kroah-Hartman 1587ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1588ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1589ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1590ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1591ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1592ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1593ab4382d2SGreg Kroah-Hartman } 1594ab4382d2SGreg Kroah-Hartman 1595995234daSEric Miao del_timer_sync(&sport->timer); 1596995234daSEric Miao 1597ab4382d2SGreg Kroah-Hartman /* 1598ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1599ab4382d2SGreg Kroah-Hartman */ 1600ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1601ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1602ab4382d2SGreg Kroah-Hartman 1603ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1604ab4382d2SGreg Kroah-Hartman 1605ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1606ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1607ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1608ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1609ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1610ab4382d2SGreg Kroah-Hartman 1611ab4382d2SGreg Kroah-Hartman /* 1612ab4382d2SGreg Kroah-Hartman * Characters to ignore 1613ab4382d2SGreg Kroah-Hartman */ 1614ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1615ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1616865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1617ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1618ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1619ab4382d2SGreg Kroah-Hartman /* 1620ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1621ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1622ab4382d2SGreg Kroah-Hartman */ 1623ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1624ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1625ab4382d2SGreg Kroah-Hartman } 1626ab4382d2SGreg Kroah-Hartman 162755d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 162855d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 162955d8693aSJiada Wang 1630ab4382d2SGreg Kroah-Hartman /* 1631ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1632ab4382d2SGreg Kroah-Hartman */ 1633ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1634ab4382d2SGreg Kroah-Hartman 1635ab4382d2SGreg Kroah-Hartman /* 1636ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1637ab4382d2SGreg Kroah-Hartman */ 163827c84426SUwe Kleine-König old_ucr1 = imx_uart_readl(sport, UCR1); 163927c84426SUwe Kleine-König imx_uart_writel(sport, 164027c84426SUwe Kleine-König old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 164127c84426SUwe Kleine-König UCR1); 164281ca8e82SUwe Kleine-König old_ucr2 = imx_uart_readl(sport, UCR2); 164381ca8e82SUwe Kleine-König imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2); 1644ab4382d2SGreg Kroah-Hartman 164527c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)) 1646ab4382d2SGreg Kroah-Hartman barrier(); 1647ab4382d2SGreg Kroah-Hartman 1648ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 164981ca8e82SUwe Kleine-König imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2); 165086a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1651ab4382d2SGreg Kroah-Hartman 165209bd00f6SHubert Feurstein /* custom-baudrate handling */ 165309bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 165409bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 165509bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 165609bd00f6SHubert Feurstein 1657ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1658ab4382d2SGreg Kroah-Hartman if (div > 7) 1659ab4382d2SGreg Kroah-Hartman div = 7; 1660ab4382d2SGreg Kroah-Hartman if (!div) 1661ab4382d2SGreg Kroah-Hartman div = 1; 1662ab4382d2SGreg Kroah-Hartman 1663ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1664ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1665ab4382d2SGreg Kroah-Hartman 1666ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1667ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1668ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1669ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1670ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1671ab4382d2SGreg Kroah-Hartman 1672ab4382d2SGreg Kroah-Hartman num -= 1; 1673ab4382d2SGreg Kroah-Hartman denom -= 1; 1674ab4382d2SGreg Kroah-Hartman 167527c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1676ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 167727c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1678ab4382d2SGreg Kroah-Hartman 167927c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 168027c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1681ab4382d2SGreg Kroah-Hartman 16829d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 168327c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 168427c84426SUwe Kleine-König IMX21_ONEMS); 1685ab4382d2SGreg Kroah-Hartman 168627c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr1, UCR1); 1687ab4382d2SGreg Kroah-Hartman 1688ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 168927c84426SUwe Kleine-König imx_uart_writel(sport, ucr2 | old_ucr2, UCR2); 1690ab4382d2SGreg Kroah-Hartman 1691ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 16929d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1693ab4382d2SGreg Kroah-Hartman 1694ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1695ab4382d2SGreg Kroah-Hartman } 1696ab4382d2SGreg Kroah-Hartman 16979d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1698ab4382d2SGreg Kroah-Hartman { 1699ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1700ab4382d2SGreg Kroah-Hartman 1701ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1702ab4382d2SGreg Kroah-Hartman } 1703ab4382d2SGreg Kroah-Hartman 1704ab4382d2SGreg Kroah-Hartman /* 1705ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1706ab4382d2SGreg Kroah-Hartman */ 17079d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1708ab4382d2SGreg Kroah-Hartman { 1709ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1710ab4382d2SGreg Kroah-Hartman 1711da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1712ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1713ab4382d2SGreg Kroah-Hartman } 1714ab4382d2SGreg Kroah-Hartman 1715ab4382d2SGreg Kroah-Hartman /* 1716ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1717ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1718ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1719ab4382d2SGreg Kroah-Hartman */ 1720ab4382d2SGreg Kroah-Hartman static int 17219d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1722ab4382d2SGreg Kroah-Hartman { 1723ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1724ab4382d2SGreg Kroah-Hartman int ret = 0; 1725ab4382d2SGreg Kroah-Hartman 1726ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1727ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1728ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1729ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1730ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1731ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1732ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1733ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1734a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1735ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1736ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1737ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1738ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1739ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1740ab4382d2SGreg Kroah-Hartman return ret; 1741ab4382d2SGreg Kroah-Hartman } 1742ab4382d2SGreg Kroah-Hartman 174301f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17446b8bdad9SDaniel Thompson 17459d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 17466b8bdad9SDaniel Thompson { 17476b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 17486b8bdad9SDaniel Thompson unsigned long flags; 17494444dcf1SUwe Kleine-König u32 ucr1, ucr2; 17506b8bdad9SDaniel Thompson int retval; 17516b8bdad9SDaniel Thompson 17526b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 17536b8bdad9SDaniel Thompson if (retval) 17546b8bdad9SDaniel Thompson return retval; 17556b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 17566b8bdad9SDaniel Thompson if (retval) 17576b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 17586b8bdad9SDaniel Thompson 17599d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 17606b8bdad9SDaniel Thompson 17616b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 17626b8bdad9SDaniel Thompson 176376821e22SUwe Kleine-König /* 176476821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 176576821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 176676821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 176776821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 176876821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 176976821e22SUwe Kleine-König */ 17704444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 177176821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 177276821e22SUwe Kleine-König 17739d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 17744444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 17756b8bdad9SDaniel Thompson 177676821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 177776821e22SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN); 177876821e22SUwe Kleine-König 17794444dcf1SUwe Kleine-König ucr2 |= UCR2_RXEN; 178081ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 178176821e22SUwe Kleine-König 178276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 17834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 17846b8bdad9SDaniel Thompson 178576821e22SUwe Kleine-König /* now enable irqs */ 178676821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 178781ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 178876821e22SUwe Kleine-König 17896b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 17906b8bdad9SDaniel Thompson 17916b8bdad9SDaniel Thompson return 0; 17926b8bdad9SDaniel Thompson } 17936b8bdad9SDaniel Thompson 17949d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 179501f56abdSSaleem Abdulrasool { 179627c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 179727c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 179826c47412SDirk Behme return NO_POLL_CHAR; 179901f56abdSSaleem Abdulrasool 180027c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 180101f56abdSSaleem Abdulrasool } 180201f56abdSSaleem Abdulrasool 18039d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 180401f56abdSSaleem Abdulrasool { 180527c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 180601f56abdSSaleem Abdulrasool unsigned int status; 180701f56abdSSaleem Abdulrasool 180801f56abdSSaleem Abdulrasool /* drain */ 180901f56abdSSaleem Abdulrasool do { 181027c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 181101f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 181201f56abdSSaleem Abdulrasool 181301f56abdSSaleem Abdulrasool /* write */ 181427c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 181501f56abdSSaleem Abdulrasool 181601f56abdSSaleem Abdulrasool /* flush */ 181701f56abdSSaleem Abdulrasool do { 181827c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 181901f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 182001f56abdSSaleem Abdulrasool } 182101f56abdSSaleem Abdulrasool #endif 182201f56abdSSaleem Abdulrasool 18236aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 18249d1a50a2SUwe Kleine-König static int imx_uart_rs485_config(struct uart_port *port, 182517b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 182617b8f2a3SUwe Kleine-König { 182717b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 18284444dcf1SUwe Kleine-König u32 ucr2; 182917b8f2a3SUwe Kleine-König 183017b8f2a3SUwe Kleine-König /* unimplemented */ 183117b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 183217b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 183317b8f2a3SUwe Kleine-König 183417b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 18357b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 183617b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 183717b8f2a3SUwe Kleine-König 183817b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 18396d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 18406d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 18416d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 18426d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 18436d215f83SStefan Agner 184417b8f2a3SUwe Kleine-König /* disable transmitter */ 18454444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 184617b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 18479d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 18481a613626SFabio Estevam else 18499d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 18504444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 185117b8f2a3SUwe Kleine-König } 185217b8f2a3SUwe Kleine-König 18537d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 18547d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 185576821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 18569d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 18577d1cadcaSBaruch Siach 185817b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 185917b8f2a3SUwe Kleine-König 186017b8f2a3SUwe Kleine-König return 0; 186117b8f2a3SUwe Kleine-König } 186217b8f2a3SUwe Kleine-König 18639d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 18649d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 18659d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 18669d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 18679d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 18689d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 18699d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 18709d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 18719d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 18729d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 18739d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 18749d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 18759d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 18769d1a50a2SUwe Kleine-König .type = imx_uart_type, 18779d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 18789d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 187901f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18809d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 18819d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 18829d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 188301f56abdSSaleem Abdulrasool #endif 1884ab4382d2SGreg Kroah-Hartman }; 1885ab4382d2SGreg Kroah-Hartman 18869d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1887ab4382d2SGreg Kroah-Hartman 1888ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 18899d1a50a2SUwe Kleine-König static void imx_uart_console_putchar(struct uart_port *port, int ch) 1890ab4382d2SGreg Kroah-Hartman { 1891ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1892ab4382d2SGreg Kroah-Hartman 18939d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1894ab4382d2SGreg Kroah-Hartman barrier(); 1895ab4382d2SGreg Kroah-Hartman 189627c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1897ab4382d2SGreg Kroah-Hartman } 1898ab4382d2SGreg Kroah-Hartman 1899ab4382d2SGreg Kroah-Hartman /* 1900ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1901ab4382d2SGreg Kroah-Hartman */ 1902ab4382d2SGreg Kroah-Hartman static void 19039d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1904ab4382d2SGreg Kroah-Hartman { 19059d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 19060ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 19070ad5a814SDirk Behme unsigned int ucr1; 1908f30e8260SShawn Guo unsigned long flags = 0; 1909677fe555SThomas Gleixner int locked = 1; 19101cf93e0dSHuang Shijie int retval; 19111cf93e0dSHuang Shijie 19120c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 19131cf93e0dSHuang Shijie if (retval) 19141cf93e0dSHuang Shijie return; 19150c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 19161cf93e0dSHuang Shijie if (retval) { 19170c727a42SFabio Estevam clk_disable(sport->clk_per); 19181cf93e0dSHuang Shijie return; 19191cf93e0dSHuang Shijie } 19209ec1882dSXinyu Chen 1921677fe555SThomas Gleixner if (sport->port.sysrq) 1922677fe555SThomas Gleixner locked = 0; 1923677fe555SThomas Gleixner else if (oops_in_progress) 1924677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1925677fe555SThomas Gleixner else 19269ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1927ab4382d2SGreg Kroah-Hartman 1928ab4382d2SGreg Kroah-Hartman /* 19290ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1930ab4382d2SGreg Kroah-Hartman */ 19319d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 19320ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1933ab4382d2SGreg Kroah-Hartman 19349d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 1935fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1936ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1937ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1938ab4382d2SGreg Kroah-Hartman 193927c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1940ab4382d2SGreg Kroah-Hartman 194127c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1942ab4382d2SGreg Kroah-Hartman 19439d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 1944ab4382d2SGreg Kroah-Hartman 1945ab4382d2SGreg Kroah-Hartman /* 1946ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 19470ad5a814SDirk Behme * and restore UCR1/2/3 1948ab4382d2SGreg Kroah-Hartman */ 194927c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1950ab4382d2SGreg Kroah-Hartman 19519d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 19529ec1882dSXinyu Chen 1953677fe555SThomas Gleixner if (locked) 19549ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 19551cf93e0dSHuang Shijie 19560c727a42SFabio Estevam clk_disable(sport->clk_ipg); 19570c727a42SFabio Estevam clk_disable(sport->clk_per); 1958ab4382d2SGreg Kroah-Hartman } 1959ab4382d2SGreg Kroah-Hartman 1960ab4382d2SGreg Kroah-Hartman /* 1961ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1962ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1963ab4382d2SGreg Kroah-Hartman */ 1964ab4382d2SGreg Kroah-Hartman static void __init 19659d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 1966ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1967ab4382d2SGreg Kroah-Hartman { 1968ab4382d2SGreg Kroah-Hartman 196927c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1970ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1971ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1972ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1973ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1974ab4382d2SGreg Kroah-Hartman 197527c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 1976ab4382d2SGreg Kroah-Hartman 1977ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1978ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1979ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1980ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1981ab4382d2SGreg Kroah-Hartman else 1982ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1983ab4382d2SGreg Kroah-Hartman } 1984ab4382d2SGreg Kroah-Hartman 1985ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1986ab4382d2SGreg Kroah-Hartman *bits = 8; 1987ab4382d2SGreg Kroah-Hartman else 1988ab4382d2SGreg Kroah-Hartman *bits = 7; 1989ab4382d2SGreg Kroah-Hartman 199027c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 199127c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 1992ab4382d2SGreg Kroah-Hartman 199327c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 1994ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1995ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1996ab4382d2SGreg Kroah-Hartman else 1997ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1998ab4382d2SGreg Kroah-Hartman 19993a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2000ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2001ab4382d2SGreg Kroah-Hartman 2002ab4382d2SGreg Kroah-Hartman { /* 2003ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2004ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2005ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2006ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2007ab4382d2SGreg Kroah-Hartman */ 2008ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2009ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2010ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2011ab4382d2SGreg Kroah-Hartman 2012ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2013ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2014ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2015ab4382d2SGreg Kroah-Hartman } 2016ab4382d2SGreg Kroah-Hartman 2017ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 201850bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 2019ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2020ab4382d2SGreg Kroah-Hartman } 2021ab4382d2SGreg Kroah-Hartman } 2022ab4382d2SGreg Kroah-Hartman 2023ab4382d2SGreg Kroah-Hartman static int __init 20249d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2025ab4382d2SGreg Kroah-Hartman { 2026ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2027ab4382d2SGreg Kroah-Hartman int baud = 9600; 2028ab4382d2SGreg Kroah-Hartman int bits = 8; 2029ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2030ab4382d2SGreg Kroah-Hartman int flow = 'n'; 20311cf93e0dSHuang Shijie int retval; 2032ab4382d2SGreg Kroah-Hartman 2033ab4382d2SGreg Kroah-Hartman /* 2034ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2035ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2036ab4382d2SGreg Kroah-Hartman * console support. 2037ab4382d2SGreg Kroah-Hartman */ 20389d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2039ab4382d2SGreg Kroah-Hartman co->index = 0; 20409d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2041ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2042ab4382d2SGreg Kroah-Hartman return -ENODEV; 2043ab4382d2SGreg Kroah-Hartman 20441cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 20451cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 20461cf93e0dSHuang Shijie if (retval) 20471cf93e0dSHuang Shijie goto error_console; 20481cf93e0dSHuang Shijie 2049ab4382d2SGreg Kroah-Hartman if (options) 2050ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2051ab4382d2SGreg Kroah-Hartman else 20529d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2053ab4382d2SGreg Kroah-Hartman 20549d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2055ab4382d2SGreg Kroah-Hartman 20561cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 20571cf93e0dSHuang Shijie 20580c727a42SFabio Estevam clk_disable(sport->clk_ipg); 20590c727a42SFabio Estevam if (retval) { 20600c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 20610c727a42SFabio Estevam goto error_console; 20620c727a42SFabio Estevam } 20630c727a42SFabio Estevam 20640c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 20650c727a42SFabio Estevam if (retval) 20661cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 20671cf93e0dSHuang Shijie 20681cf93e0dSHuang Shijie error_console: 20691cf93e0dSHuang Shijie return retval; 2070ab4382d2SGreg Kroah-Hartman } 2071ab4382d2SGreg Kroah-Hartman 20729d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 20739d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2074ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 20759d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2076ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 20779d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 2078ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2079ab4382d2SGreg Kroah-Hartman .index = -1, 20809d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2081ab4382d2SGreg Kroah-Hartman }; 2082ab4382d2SGreg Kroah-Hartman 20839d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2084913c6c0eSLucas Stach 2085913c6c0eSLucas Stach #ifdef CONFIG_OF 20869d1a50a2SUwe Kleine-König static void imx_uart_console_early_putchar(struct uart_port *port, int ch) 2087913c6c0eSLucas Stach { 208827c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 208927c84426SUwe Kleine-König 209027c84426SUwe Kleine-König while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2091913c6c0eSLucas Stach cpu_relax(); 2092913c6c0eSLucas Stach 209327c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 2094913c6c0eSLucas Stach } 2095913c6c0eSLucas Stach 20969d1a50a2SUwe Kleine-König static void imx_uart_console_early_write(struct console *con, const char *s, 2097913c6c0eSLucas Stach unsigned count) 2098913c6c0eSLucas Stach { 2099913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 2100913c6c0eSLucas Stach 21019d1a50a2SUwe Kleine-König uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar); 2102913c6c0eSLucas Stach } 2103913c6c0eSLucas Stach 2104913c6c0eSLucas Stach static int __init 2105913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2106913c6c0eSLucas Stach { 2107913c6c0eSLucas Stach if (!dev->port.membase) 2108913c6c0eSLucas Stach return -ENODEV; 2109913c6c0eSLucas Stach 21109d1a50a2SUwe Kleine-König dev->con->write = imx_uart_console_early_write; 2111913c6c0eSLucas Stach 2112913c6c0eSLucas Stach return 0; 2113913c6c0eSLucas Stach } 2114913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2115913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2116913c6c0eSLucas Stach #endif 2117913c6c0eSLucas Stach 2118ab4382d2SGreg Kroah-Hartman #else 2119ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2120ab4382d2SGreg Kroah-Hartman #endif 2121ab4382d2SGreg Kroah-Hartman 21229d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2123ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2124ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2125ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2126ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2127ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21289d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2129ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2130ab4382d2SGreg Kroah-Hartman }; 2131ab4382d2SGreg Kroah-Hartman 213222698aa2SShawn Guo #ifdef CONFIG_OF 213320bb8095SUwe Kleine-König /* 213420bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 213520bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 213620bb8095SUwe Kleine-König */ 21379d1a50a2SUwe Kleine-König static int imx_uart_probe_dt(struct imx_port *sport, 213822698aa2SShawn Guo struct platform_device *pdev) 213922698aa2SShawn Guo { 214022698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2141ff05967aSShawn Guo int ret; 214222698aa2SShawn Guo 21435f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 21445f8b9043SLABBE Corentin if (!sport->devdata) 214520bb8095SUwe Kleine-König /* no device tree device */ 214620bb8095SUwe Kleine-König return 1; 214722698aa2SShawn Guo 2148ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2149ff05967aSShawn Guo if (ret < 0) { 2150ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2151a197a191SUwe Kleine-König return ret; 2152ff05967aSShawn Guo } 2153ff05967aSShawn Guo sport->port.line = ret; 215422698aa2SShawn Guo 21551006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 21561006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 215722698aa2SShawn Guo sport->have_rtscts = 1; 215822698aa2SShawn Guo 215920ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 216020ff2fe6SHuang Shijie sport->dte_mode = 1; 216120ff2fe6SHuang Shijie 21627b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 21637b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 21647b7e8e8eSFabio Estevam 216522698aa2SShawn Guo return 0; 216622698aa2SShawn Guo } 216722698aa2SShawn Guo #else 21689d1a50a2SUwe Kleine-König static inline int imx_uart_probe_dt(struct imx_port *sport, 216922698aa2SShawn Guo struct platform_device *pdev) 217022698aa2SShawn Guo { 217120bb8095SUwe Kleine-König return 1; 217222698aa2SShawn Guo } 217322698aa2SShawn Guo #endif 217422698aa2SShawn Guo 21759d1a50a2SUwe Kleine-König static void imx_uart_probe_pdata(struct imx_port *sport, 217622698aa2SShawn Guo struct platform_device *pdev) 217722698aa2SShawn Guo { 2178574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 217922698aa2SShawn Guo 218022698aa2SShawn Guo sport->port.line = pdev->id; 218122698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 218222698aa2SShawn Guo 218322698aa2SShawn Guo if (!pdata) 218422698aa2SShawn Guo return; 218522698aa2SShawn Guo 218622698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 218722698aa2SShawn Guo sport->have_rtscts = 1; 218822698aa2SShawn Guo } 218922698aa2SShawn Guo 21909d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2191ab4382d2SGreg Kroah-Hartman { 2192ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2193ab4382d2SGreg Kroah-Hartman void __iomem *base; 21944444dcf1SUwe Kleine-König int ret = 0; 21954444dcf1SUwe Kleine-König u32 ucr1; 2196ab4382d2SGreg Kroah-Hartman struct resource *res; 2197842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2198ab4382d2SGreg Kroah-Hartman 219942d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2200ab4382d2SGreg Kroah-Hartman if (!sport) 2201ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2202ab4382d2SGreg Kroah-Hartman 22039d1a50a2SUwe Kleine-König ret = imx_uart_probe_dt(sport, pdev); 220420bb8095SUwe Kleine-König if (ret > 0) 22059d1a50a2SUwe Kleine-König imx_uart_probe_pdata(sport, pdev); 220620bb8095SUwe Kleine-König else if (ret < 0) 220742d34191SSachin Kamat return ret; 220822698aa2SShawn Guo 22099d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 221056734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 221156734448SGeert Uytterhoeven sport->port.line); 221256734448SGeert Uytterhoeven return -EINVAL; 221356734448SGeert Uytterhoeven } 221456734448SGeert Uytterhoeven 2215ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2216da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2217da82f997SAlexander Shiyan if (IS_ERR(base)) 2218da82f997SAlexander Shiyan return PTR_ERR(base); 2219ab4382d2SGreg Kroah-Hartman 2220842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2221842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2222842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2223842633bdSUwe Kleine-König 2224ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2225ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2226ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2227ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2228ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2229842633bdSUwe Kleine-König sport->port.irq = rxirq; 2230ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 22319d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 22329d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 2233ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 22349d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2235ab4382d2SGreg Kroah-Hartman 223658362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 223758362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 223858362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 223958362d5bSUwe Kleine-König 22403a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 22413a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 22423a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2243833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 224442d34191SSachin Kamat return ret; 2245ab4382d2SGreg Kroah-Hartman } 2246ab4382d2SGreg Kroah-Hartman 22473a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 22483a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 22493a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2250833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 225142d34191SSachin Kamat return ret; 22523a9465faSSascha Hauer } 22533a9465faSSascha Hauer 22543a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2255ab4382d2SGreg Kroah-Hartman 22568a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 22578a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 22581e512d45SUwe Kleine-König if (ret) { 22591e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 22608a61f0c7SFabio Estevam return ret; 22611e512d45SUwe Kleine-König } 22628a61f0c7SFabio Estevam 22633a0ab62fSUwe Kleine-König /* initialize shadow register values */ 22643a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 22653a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 22663a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 22673a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 22683a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 22693a0ab62fSUwe Kleine-König 2270743f93f8SLukas Wunner uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2271743f93f8SLukas Wunner 2272b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 22735d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2274b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2275b8f3bff0SLukas Wunner 22766d215f83SStefan Agner /* 22776d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 22786d215f83SStefan Agner * signal cannot be set low during transmission in case the 22796d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 22806d215f83SStefan Agner */ 22816d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 22826d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 22836d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 22846d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 22856d215f83SStefan Agner dev_err(&pdev->dev, 22866d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 22876d215f83SStefan Agner 22889d1a50a2SUwe Kleine-König imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2289b8f3bff0SLukas Wunner 22908a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 22914444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 22924444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 22938a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 22944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 22958a61f0c7SFabio Estevam 22969d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2297e61c38d8SUwe Kleine-König /* 2298e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2299e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2300e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2301e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2302e61c38d8SUwe Kleine-König */ 23034444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23044444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 23054444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2306e61c38d8SUwe Kleine-König 2307e61c38d8SUwe Kleine-König /* 2308e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2309e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2310e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2311e61c38d8SUwe Kleine-König */ 231227c84426SUwe Kleine-König imx_uart_writel(sport, 231327c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 231427c84426SUwe Kleine-König UCR3); 2315e61c38d8SUwe Kleine-König 2316e61c38d8SUwe Kleine-König } else { 23174444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 23184444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23194444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 23204444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 23216df765dcSUwe Kleine-König 23229d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 23236df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 232427c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2325e61c38d8SUwe Kleine-König } 2326e61c38d8SUwe Kleine-König 23278a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 23288a61f0c7SFabio Estevam 2329c0d1c6b0SFabio Estevam /* 2330c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2331c0d1c6b0SFabio Estevam * chips only have one interrupt. 2332c0d1c6b0SFabio Estevam */ 2333842633bdSUwe Kleine-König if (txirq > 0) { 23349d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2335c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23361e512d45SUwe Kleine-König if (ret) { 23371e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 23381e512d45SUwe Kleine-König ret); 2339c0d1c6b0SFabio Estevam return ret; 23401e512d45SUwe Kleine-König } 2341c0d1c6b0SFabio Estevam 23429d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2343c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23441e512d45SUwe Kleine-König if (ret) { 23451e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 23461e512d45SUwe Kleine-König ret); 2347c0d1c6b0SFabio Estevam return ret; 23481e512d45SUwe Kleine-König } 2349c0d1c6b0SFabio Estevam } else { 23509d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2351c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23521e512d45SUwe Kleine-König if (ret) { 23531e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2354c0d1c6b0SFabio Estevam return ret; 2355c0d1c6b0SFabio Estevam } 23561e512d45SUwe Kleine-König } 2357c0d1c6b0SFabio Estevam 23589d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2359ab4382d2SGreg Kroah-Hartman 23600a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2361ab4382d2SGreg Kroah-Hartman 23629d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2363ab4382d2SGreg Kroah-Hartman } 2364ab4382d2SGreg Kroah-Hartman 23659d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2366ab4382d2SGreg Kroah-Hartman { 2367ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2368ab4382d2SGreg Kroah-Hartman 23699d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2370ab4382d2SGreg Kroah-Hartman } 2371ab4382d2SGreg Kroah-Hartman 23729d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2373c868cbb7SEduardo Valentin { 2374c868cbb7SEduardo Valentin if (!sport->context_saved) 2375c868cbb7SEduardo Valentin return; 2376c868cbb7SEduardo Valentin 237727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 237827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 237927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 238027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 238127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 238227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 238327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 238427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 238527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 238627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2387c868cbb7SEduardo Valentin sport->context_saved = false; 2388c868cbb7SEduardo Valentin } 2389c868cbb7SEduardo Valentin 23909d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2391c868cbb7SEduardo Valentin { 2392c868cbb7SEduardo Valentin /* Save necessary regs */ 239327c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 239427c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 239527c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 239627c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 239727c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 239827c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 239927c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 240027c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 240127c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 240227c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2403c868cbb7SEduardo Valentin sport->context_saved = true; 2404c868cbb7SEduardo Valentin } 2405c868cbb7SEduardo Valentin 24069d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2407189550b8SEduardo Valentin { 24084444dcf1SUwe Kleine-König u32 ucr3; 2409189550b8SEduardo Valentin 24104444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 241109df0b34SMartin Kaiser if (on) { 241227c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 24134444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 24144444dcf1SUwe Kleine-König } else { 24154444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 241609df0b34SMartin Kaiser } 24174444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2418bc85734bSEduardo Valentin 241938b1f0fbSFabio Estevam if (sport->have_rtscts) { 24204444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2421bc85734bSEduardo Valentin if (on) 24224444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2423bc85734bSEduardo Valentin else 24244444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 24254444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2426189550b8SEduardo Valentin } 242738b1f0fbSFabio Estevam } 2428189550b8SEduardo Valentin 24299d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 243090bb6bd3SShenwei Wang { 2431a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 243290bb6bd3SShenwei Wang 24339d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 243490bb6bd3SShenwei Wang 243590bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 243690bb6bd3SShenwei Wang 243790bb6bd3SShenwei Wang return 0; 243890bb6bd3SShenwei Wang } 243990bb6bd3SShenwei Wang 24409d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 244190bb6bd3SShenwei Wang { 2442a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 244390bb6bd3SShenwei Wang int ret; 244490bb6bd3SShenwei Wang 244590bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 244690bb6bd3SShenwei Wang if (ret) 244790bb6bd3SShenwei Wang return ret; 244890bb6bd3SShenwei Wang 24499d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 245090bb6bd3SShenwei Wang 245190bb6bd3SShenwei Wang return 0; 245290bb6bd3SShenwei Wang } 245390bb6bd3SShenwei Wang 24549d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 245590bb6bd3SShenwei Wang { 2456a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 245709df0b34SMartin Kaiser int ret; 245890bb6bd3SShenwei Wang 24599d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 246081b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 246190bb6bd3SShenwei Wang 246209df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 246309df0b34SMartin Kaiser if (ret) 246409df0b34SMartin Kaiser return ret; 246509df0b34SMartin Kaiser 246609df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 24679d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 246809df0b34SMartin Kaiser 246909df0b34SMartin Kaiser return 0; 247090bb6bd3SShenwei Wang } 247190bb6bd3SShenwei Wang 24729d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 247390bb6bd3SShenwei Wang { 2474a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 247590bb6bd3SShenwei Wang 247690bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 24779d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 247890bb6bd3SShenwei Wang 24799d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 248081b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 248190bb6bd3SShenwei Wang 248209df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 248329add68dSMartin Fuzzey 248490bb6bd3SShenwei Wang return 0; 248590bb6bd3SShenwei Wang } 248690bb6bd3SShenwei Wang 24879d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 248894be6d74SPhilipp Zabel { 2489a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 249094be6d74SPhilipp Zabel 24919d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 249294be6d74SPhilipp Zabel 249309df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 249494be6d74SPhilipp Zabel } 249594be6d74SPhilipp Zabel 24969d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 249794be6d74SPhilipp Zabel { 2498a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 249994be6d74SPhilipp Zabel 25009d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 250194be6d74SPhilipp Zabel 250209df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 250394be6d74SPhilipp Zabel 250494be6d74SPhilipp Zabel return 0; 250594be6d74SPhilipp Zabel } 250694be6d74SPhilipp Zabel 25079d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 25089d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 25099d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 25109d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 25119d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 25129d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 25139d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 25149d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 25159d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 25169d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 251790bb6bd3SShenwei Wang }; 251890bb6bd3SShenwei Wang 25199d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 25209d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 25219d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2522ab4382d2SGreg Kroah-Hartman 2523fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2524ab4382d2SGreg Kroah-Hartman .driver = { 2525ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 252622698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 25279d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2528ab4382d2SGreg Kroah-Hartman }, 2529ab4382d2SGreg Kroah-Hartman }; 2530ab4382d2SGreg Kroah-Hartman 25319d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2532ab4382d2SGreg Kroah-Hartman { 25339d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2534ab4382d2SGreg Kroah-Hartman 2535ab4382d2SGreg Kroah-Hartman if (ret) 2536ab4382d2SGreg Kroah-Hartman return ret; 2537ab4382d2SGreg Kroah-Hartman 25389d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2539ab4382d2SGreg Kroah-Hartman if (ret != 0) 25409d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2541ab4382d2SGreg Kroah-Hartman 2542f227824eSUwe Kleine-König return ret; 2543ab4382d2SGreg Kroah-Hartman } 2544ab4382d2SGreg Kroah-Hartman 25459d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2546ab4382d2SGreg Kroah-Hartman { 25479d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 25489d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2549ab4382d2SGreg Kroah-Hartman } 2550ab4382d2SGreg Kroah-Hartman 25519d1a50a2SUwe Kleine-König module_init(imx_uart_init); 25529d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2553ab4382d2SGreg Kroah-Hartman 2554ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2555ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2556ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2557ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2558