1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 13ab4382d2SGreg Kroah-Hartman #endif 14ab4382d2SGreg Kroah-Hartman 15ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 23ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 24ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 27fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 29ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 3022698aa2SShawn Guo #include <linux/of.h> 3122698aa2SShawn Guo #include <linux/of_device.h> 32e32a9f8fSSachin Kamat #include <linux/io.h> 33b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 34ab4382d2SGreg Kroah-Hartman 35ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 3682906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 37b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 38ab4382d2SGreg Kroah-Hartman 3958362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 4058362d5bSUwe Kleine-König 41ab4382d2SGreg Kroah-Hartman /* Register definitions */ 42ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 43ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 44ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 45ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 46ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 47ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 48ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 49ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 50ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 51ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 52ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 53ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 54ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 55ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 56fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 57fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 58fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 59ab4382d2SGreg Kroah-Hartman 60ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6155d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 62ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 63ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 64ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 65ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 66ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 67ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6826c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6925985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 71ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 72ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 73b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 75302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 77ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 80302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 81fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 82b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 84ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9501f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 98ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 101ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 104ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 105b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 106ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10927e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 110fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 112ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 115ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 119b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 125ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1267be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 127ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 128ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 129ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 130ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 131ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 132ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 133ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 134ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 135ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 136ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13786a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13827e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 139ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 142ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 143ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 144ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14690ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14790ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 148ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 15090ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 151ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 152ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 153ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 154ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 155ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 156ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 157ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 158ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 159ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 160ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 161ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 162ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 163ab4382d2SGreg Kroah-Hartman 164ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 165ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 166ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 167ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 168ab4382d2SGreg Kroah-Hartman 169ab4382d2SGreg Kroah-Hartman /* 170ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 171ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 172ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 173ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 174ab4382d2SGreg Kroah-Hartman */ 175ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 176ab4382d2SGreg Kroah-Hartman 177ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 178ab4382d2SGreg Kroah-Hartman 179ab4382d2SGreg Kroah-Hartman #define UART_NR 8 180ab4382d2SGreg Kroah-Hartman 181f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 182fe6b540aSShawn Guo enum imx_uart_type { 183fe6b540aSShawn Guo IMX1_UART, 184fe6b540aSShawn Guo IMX21_UART, 1851c06bde6SMartyn Welch IMX53_UART, 186a496e628SHuang Shijie IMX6Q_UART, 187fe6b540aSShawn Guo }; 188fe6b540aSShawn Guo 189fe6b540aSShawn Guo /* device type dependent stuff */ 190fe6b540aSShawn Guo struct imx_uart_data { 191fe6b540aSShawn Guo unsigned uts_reg; 192fe6b540aSShawn Guo enum imx_uart_type devtype; 193fe6b540aSShawn Guo }; 194fe6b540aSShawn Guo 195ab4382d2SGreg Kroah-Hartman struct imx_port { 196ab4382d2SGreg Kroah-Hartman struct uart_port port; 197ab4382d2SGreg Kroah-Hartman struct timer_list timer; 198ab4382d2SGreg Kroah-Hartman unsigned int old_status; 199ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2007b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20120ff2fe6SHuang Shijie unsigned int dte_mode:1; 2023a9465faSSascha Hauer struct clk *clk_ipg; 2033a9465faSSascha Hauer struct clk *clk_per; 2047d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 205b4cdc8f6SHuang Shijie 20658362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 20758362d5bSUwe Kleine-König 2083a0ab62fSUwe Kleine-König /* shadow registers */ 2093a0ab62fSUwe Kleine-König unsigned int ucr1; 2103a0ab62fSUwe Kleine-König unsigned int ucr2; 2113a0ab62fSUwe Kleine-König unsigned int ucr3; 2123a0ab62fSUwe Kleine-König unsigned int ucr4; 2133a0ab62fSUwe Kleine-König unsigned int ufcr; 2143a0ab62fSUwe Kleine-König 215b4cdc8f6SHuang Shijie /* DMA fields */ 216b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 217b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 218b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 219b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 220b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 221b4cdc8f6SHuang Shijie void *rx_buf; 2229d297239SNandor Han struct circ_buf rx_ring; 2239d297239SNandor Han unsigned int rx_periods; 2249d297239SNandor Han dma_cookie_t rx_cookie; 2257cb92fd2SHuang Shijie unsigned int tx_bytes; 226b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 22790bb6bd3SShenwei Wang unsigned int saved_reg[10]; 228c868cbb7SEduardo Valentin bool context_saved; 229ab4382d2SGreg Kroah-Hartman }; 230ab4382d2SGreg Kroah-Hartman 2310ad5a814SDirk Behme struct imx_port_ucrs { 2320ad5a814SDirk Behme unsigned int ucr1; 2330ad5a814SDirk Behme unsigned int ucr2; 2340ad5a814SDirk Behme unsigned int ucr3; 2350ad5a814SDirk Behme }; 2360ad5a814SDirk Behme 237fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 238fe6b540aSShawn Guo [IMX1_UART] = { 239fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 240fe6b540aSShawn Guo .devtype = IMX1_UART, 241fe6b540aSShawn Guo }, 242fe6b540aSShawn Guo [IMX21_UART] = { 243fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 244fe6b540aSShawn Guo .devtype = IMX21_UART, 245fe6b540aSShawn Guo }, 2461c06bde6SMartyn Welch [IMX53_UART] = { 2471c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2481c06bde6SMartyn Welch .devtype = IMX53_UART, 2491c06bde6SMartyn Welch }, 250a496e628SHuang Shijie [IMX6Q_UART] = { 251a496e628SHuang Shijie .uts_reg = IMX21_UTS, 252a496e628SHuang Shijie .devtype = IMX6Q_UART, 253a496e628SHuang Shijie }, 254fe6b540aSShawn Guo }; 255fe6b540aSShawn Guo 25631ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 257fe6b540aSShawn Guo { 258fe6b540aSShawn Guo .name = "imx1-uart", 259fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 260fe6b540aSShawn Guo }, { 261fe6b540aSShawn Guo .name = "imx21-uart", 262fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 263fe6b540aSShawn Guo }, { 2641c06bde6SMartyn Welch .name = "imx53-uart", 2651c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2661c06bde6SMartyn Welch }, { 267a496e628SHuang Shijie .name = "imx6q-uart", 268a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 269a496e628SHuang Shijie }, { 270fe6b540aSShawn Guo /* sentinel */ 271fe6b540aSShawn Guo } 272fe6b540aSShawn Guo }; 273fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 274fe6b540aSShawn Guo 275ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 276a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2771c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27822698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27922698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 28022698aa2SShawn Guo { /* sentinel */ } 28122698aa2SShawn Guo }; 28222698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28322698aa2SShawn Guo 28427c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 28527c84426SUwe Kleine-König { 2863a0ab62fSUwe Kleine-König switch (offset) { 2873a0ab62fSUwe Kleine-König case UCR1: 2883a0ab62fSUwe Kleine-König sport->ucr1 = val; 2893a0ab62fSUwe Kleine-König break; 2903a0ab62fSUwe Kleine-König case UCR2: 2913a0ab62fSUwe Kleine-König sport->ucr2 = val; 2923a0ab62fSUwe Kleine-König break; 2933a0ab62fSUwe Kleine-König case UCR3: 2943a0ab62fSUwe Kleine-König sport->ucr3 = val; 2953a0ab62fSUwe Kleine-König break; 2963a0ab62fSUwe Kleine-König case UCR4: 2973a0ab62fSUwe Kleine-König sport->ucr4 = val; 2983a0ab62fSUwe Kleine-König break; 2993a0ab62fSUwe Kleine-König case UFCR: 3003a0ab62fSUwe Kleine-König sport->ufcr = val; 3013a0ab62fSUwe Kleine-König break; 3023a0ab62fSUwe Kleine-König default: 3033a0ab62fSUwe Kleine-König break; 3043a0ab62fSUwe Kleine-König } 30527c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 30627c84426SUwe Kleine-König } 30727c84426SUwe Kleine-König 30827c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30927c84426SUwe Kleine-König { 3103a0ab62fSUwe Kleine-König switch (offset) { 3113a0ab62fSUwe Kleine-König case UCR1: 3123a0ab62fSUwe Kleine-König return sport->ucr1; 3133a0ab62fSUwe Kleine-König break; 3143a0ab62fSUwe Kleine-König case UCR2: 3153a0ab62fSUwe Kleine-König /* 3163a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3173a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 318728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 319728e74a4SUwe Kleine-König * conditionally. 3203a0ab62fSUwe Kleine-König */ 3210aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3223a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3233a0ab62fSUwe Kleine-König return sport->ucr2; 3243a0ab62fSUwe Kleine-König break; 3253a0ab62fSUwe Kleine-König case UCR3: 3263a0ab62fSUwe Kleine-König return sport->ucr3; 3273a0ab62fSUwe Kleine-König break; 3283a0ab62fSUwe Kleine-König case UCR4: 3293a0ab62fSUwe Kleine-König return sport->ucr4; 3303a0ab62fSUwe Kleine-König break; 3313a0ab62fSUwe Kleine-König case UFCR: 3323a0ab62fSUwe Kleine-König return sport->ufcr; 3333a0ab62fSUwe Kleine-König break; 3343a0ab62fSUwe Kleine-König default: 33527c84426SUwe Kleine-König return readl(sport->port.membase + offset); 33627c84426SUwe Kleine-König } 3373a0ab62fSUwe Kleine-König } 33827c84426SUwe Kleine-König 3399d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 340fe6b540aSShawn Guo { 341fe6b540aSShawn Guo return sport->devdata->uts_reg; 342fe6b540aSShawn Guo } 343fe6b540aSShawn Guo 3449d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 345fe6b540aSShawn Guo { 346fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 347fe6b540aSShawn Guo } 348fe6b540aSShawn Guo 3499d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 350fe6b540aSShawn Guo { 351fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 352fe6b540aSShawn Guo } 353fe6b540aSShawn Guo 3549d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3551c06bde6SMartyn Welch { 3561c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3571c06bde6SMartyn Welch } 3581c06bde6SMartyn Welch 3599d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 360a496e628SHuang Shijie { 361a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 362a496e628SHuang Shijie } 363ab4382d2SGreg Kroah-Hartman /* 36444a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 36544a75411Sfabio.estevam@freescale.com */ 36693d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 3679d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 36844a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36944a75411Sfabio.estevam@freescale.com { 37044a75411Sfabio.estevam@freescale.com /* save control registers */ 37127c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 37227c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 37327c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 37444a75411Sfabio.estevam@freescale.com } 37544a75411Sfabio.estevam@freescale.com 3769d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 37744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37844a75411Sfabio.estevam@freescale.com { 37944a75411Sfabio.estevam@freescale.com /* restore control registers */ 38027c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 38127c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 38227c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 38344a75411Sfabio.estevam@freescale.com } 384e8bfa760SFabio Estevam #endif 38544a75411Sfabio.estevam@freescale.com 3864e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3879d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 38858362d5bSUwe Kleine-König { 389bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 39058362d5bSUwe Kleine-König 391a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 392a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39358362d5bSUwe Kleine-König } 39458362d5bSUwe Kleine-König 3954e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3969d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 39758362d5bSUwe Kleine-König { 398bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 399bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 40058362d5bSUwe Kleine-König 401a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 402a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 40358362d5bSUwe Kleine-König } 40458362d5bSUwe Kleine-König 4056aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4069d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 40776821e22SUwe Kleine-König { 40876821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 40976821e22SUwe Kleine-König unsigned int ucr1, ucr2; 41076821e22SUwe Kleine-König 41176821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 41276821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 41376821e22SUwe Kleine-König 41476821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41576821e22SUwe Kleine-König 41676821e22SUwe Kleine-König if (sport->dma_is_enabled) { 41776821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 41876821e22SUwe Kleine-König } else { 41976821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 42081ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 42176821e22SUwe Kleine-König } 42276821e22SUwe Kleine-König 42376821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 42476821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42576821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42676821e22SUwe Kleine-König } 42776821e22SUwe Kleine-König 42876821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4299d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 430ab4382d2SGreg Kroah-Hartman { 431ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4324444dcf1SUwe Kleine-König u32 ucr1; 433ab4382d2SGreg Kroah-Hartman 4349ce4f8f3SGreg Kroah-Hartman /* 4359ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4369ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4379ce4f8f3SGreg Kroah-Hartman */ 438686351f3SUwe Kleine-König if (sport->dma_is_txing) 4399ce4f8f3SGreg Kroah-Hartman return; 440b4cdc8f6SHuang Shijie 4414444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 442c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 44317b8f2a3SUwe Kleine-König 44417b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 44517b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 44627c84426SUwe Kleine-König imx_uart_readl(sport, USR2) & USR2_TXDC) { 4474444dcf1SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 44817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4499d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4501a613626SFabio Estevam else 4519d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4524444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 45317b8f2a3SUwe Kleine-König 4549d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 45576821e22SUwe Kleine-König 4564444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 4574444dcf1SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 4584444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 45917b8f2a3SUwe Kleine-König } 460ab4382d2SGreg Kroah-Hartman } 461ab4382d2SGreg Kroah-Hartman 4626aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4639d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 464ab4382d2SGreg Kroah-Hartman { 465ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4664444dcf1SUwe Kleine-König u32 ucr1, ucr2; 467ab4382d2SGreg Kroah-Hartman 4684444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 46976821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 47076821e22SUwe Kleine-König 47176821e22SUwe Kleine-König if (sport->dma_is_enabled) { 47276821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 47376821e22SUwe Kleine-König } else { 47476821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 47581ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 47676821e22SUwe Kleine-König } 47776821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 47876821e22SUwe Kleine-König 47976821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 48076821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 481ab4382d2SGreg Kroah-Hartman } 482ab4382d2SGreg Kroah-Hartman 4836aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4849d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 485ab4382d2SGreg Kroah-Hartman { 486ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 487ab4382d2SGreg Kroah-Hartman 488ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 48958362d5bSUwe Kleine-König 49058362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 491ab4382d2SGreg Kroah-Hartman } 492ab4382d2SGreg Kroah-Hartman 4939d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 4946aed2a88SUwe Kleine-König 4956aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4969d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 497ab4382d2SGreg Kroah-Hartman { 498ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 499ab4382d2SGreg Kroah-Hartman 5005e42e9a3SPeter Hurley if (sport->port.x_char) { 5015e42e9a3SPeter Hurley /* Send next char */ 50227c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5037e2fb5aaSJiada Wang sport->port.icount.tx++; 5047e2fb5aaSJiada Wang sport->port.x_char = 0; 5055e42e9a3SPeter Hurley return; 5065e42e9a3SPeter Hurley } 5075e42e9a3SPeter Hurley 5085e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5099d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5105e42e9a3SPeter Hurley return; 5115e42e9a3SPeter Hurley } 5125e42e9a3SPeter Hurley 51391a1a909SJiada Wang if (sport->dma_is_enabled) { 5144444dcf1SUwe Kleine-König u32 ucr1; 51591a1a909SJiada Wang /* 51691a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 51791a1a909SJiada Wang * and the TX IRQ is disabled. 51891a1a909SJiada Wang **/ 5194444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 520c514a6f8SSergey Organov ucr1 &= ~UCR1_TRDYEN; 52191a1a909SJiada Wang if (sport->dma_is_txing) { 5224444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5234444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 52491a1a909SJiada Wang } else { 5254444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5269d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 52791a1a909SJiada Wang } 52891a1a909SJiada Wang 5295aabd3b0SIan Jamison return; 5300c549223SUwe Kleine-König } 5315aabd3b0SIan Jamison 5325aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5339d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 534ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 535ab4382d2SGreg Kroah-Hartman * out the port here */ 53627c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 537ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 538ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 539ab4382d2SGreg Kroah-Hartman } 540ab4382d2SGreg Kroah-Hartman 541ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 542ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 543ab4382d2SGreg Kroah-Hartman 544ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5459d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 546ab4382d2SGreg Kroah-Hartman } 547ab4382d2SGreg Kroah-Hartman 5489d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 549b4cdc8f6SHuang Shijie { 550b4cdc8f6SHuang Shijie struct imx_port *sport = data; 551b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 552b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 553b4cdc8f6SHuang Shijie unsigned long flags; 5544444dcf1SUwe Kleine-König u32 ucr1; 555b4cdc8f6SHuang Shijie 55642f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 55742f752b3SDirk Behme 558b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 559b4cdc8f6SHuang Shijie 5604444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5614444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5624444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 563a2c718ceSDirk Behme 56442f752b3SDirk Behme /* update the stat */ 56542f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 56642f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 56742f752b3SDirk Behme 56842f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 56942f752b3SDirk Behme 570b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 571b4cdc8f6SHuang Shijie 572d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 573b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5749ce4f8f3SGreg Kroah-Hartman 5750bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5769d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 57718665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 57818665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 57918665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 58018665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 58118665414SUwe Kleine-König } 58264432a85SUwe Kleine-König 5830bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 584b4cdc8f6SHuang Shijie } 585b4cdc8f6SHuang Shijie 5866aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5879d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 588b4cdc8f6SHuang Shijie { 589b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 590b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 591b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 592b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 593b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 59418665414SUwe Kleine-König u32 ucr1, ucr4; 595b4cdc8f6SHuang Shijie int ret; 596b4cdc8f6SHuang Shijie 59742f752b3SDirk Behme if (sport->dma_is_txing) 598b4cdc8f6SHuang Shijie return; 599b4cdc8f6SHuang Shijie 60018665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 60118665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 60218665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 60318665414SUwe Kleine-König 604b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 605b4cdc8f6SHuang Shijie 6067942f857SDirk Behme if (xmit->tail < xmit->head) { 6077942f857SDirk Behme sport->dma_tx_nents = 1; 6087942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6097942f857SDirk Behme } else { 610b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 611b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 612b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 613b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 614b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 615b4cdc8f6SHuang Shijie } 616b4cdc8f6SHuang Shijie 617b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 618b4cdc8f6SHuang Shijie if (ret == 0) { 619b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 620b4cdc8f6SHuang Shijie return; 621b4cdc8f6SHuang Shijie } 622b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 623b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 624b4cdc8f6SHuang Shijie if (!desc) { 62524649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 62624649821SDirk Behme DMA_TO_DEVICE); 627b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 628b4cdc8f6SHuang Shijie return; 629b4cdc8f6SHuang Shijie } 6309d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 631b4cdc8f6SHuang Shijie desc->callback_param = sport; 632b4cdc8f6SHuang Shijie 633b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 634b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 635a2c718ceSDirk Behme 6364444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6374444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6384444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 639a2c718ceSDirk Behme 640b4cdc8f6SHuang Shijie /* fire it */ 641b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 642b4cdc8f6SHuang Shijie dmaengine_submit(desc); 643b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 644b4cdc8f6SHuang Shijie return; 645b4cdc8f6SHuang Shijie } 646b4cdc8f6SHuang Shijie 6476aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6489d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 649ab4382d2SGreg Kroah-Hartman { 650ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6514444dcf1SUwe Kleine-König u32 ucr1; 652ab4382d2SGreg Kroah-Hartman 65348669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 65448669b69SUwe Kleine-König return; 65548669b69SUwe Kleine-König 65617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 65718665414SUwe Kleine-König u32 ucr2; 6584444dcf1SUwe Kleine-König 6594444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 66017b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6619d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 6621a613626SFabio Estevam else 6639d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 6644444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 66517b8f2a3SUwe Kleine-König 66676821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 6679d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 66876821e22SUwe Kleine-König 66918665414SUwe Kleine-König /* 67018665414SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA is off. 67118665414SUwe Kleine-König * In the DMA case this is done in the tx-callback. 67218665414SUwe Kleine-König */ 67318665414SUwe Kleine-König if (!sport->dma_is_enabled) { 67418665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 6754444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 6764444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 67717b8f2a3SUwe Kleine-König } 67818665414SUwe Kleine-König } 67917b8f2a3SUwe Kleine-König 680b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 6814444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 682c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 683b4cdc8f6SHuang Shijie } 684ab4382d2SGreg Kroah-Hartman 685b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 68691a1a909SJiada Wang if (sport->port.x_char) { 68791a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 68891a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 6894444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6904444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 691c514a6f8SSergey Organov ucr1 |= UCR1_TRDYEN; 6924444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 69391a1a909SJiada Wang return; 69491a1a909SJiada Wang } 69591a1a909SJiada Wang 6965e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6975e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6989d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 699b4cdc8f6SHuang Shijie return; 700b4cdc8f6SHuang Shijie } 701ab4382d2SGreg Kroah-Hartman } 702ab4382d2SGreg Kroah-Hartman 7039d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 704ab4382d2SGreg Kroah-Hartman { 705ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7064444dcf1SUwe Kleine-König u32 usr1; 707ab4382d2SGreg Kroah-Hartman 708c974991dSjun qian spin_lock(&sport->port.lock); 709ab4382d2SGreg Kroah-Hartman 71027c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7114444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7124444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 713ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 714ab4382d2SGreg Kroah-Hartman 715c974991dSjun qian spin_unlock(&sport->port.lock); 716ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 717ab4382d2SGreg Kroah-Hartman } 718ab4382d2SGreg Kroah-Hartman 7199d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 720ab4382d2SGreg Kroah-Hartman { 721ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 722ab4382d2SGreg Kroah-Hartman 723c974991dSjun qian spin_lock(&sport->port.lock); 7249d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 725c974991dSjun qian spin_unlock(&sport->port.lock); 726ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 727ab4382d2SGreg Kroah-Hartman } 728ab4382d2SGreg Kroah-Hartman 7299d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 730ab4382d2SGreg Kroah-Hartman { 731ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 732ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 73392a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 734ab4382d2SGreg Kroah-Hartman 735c974991dSjun qian spin_lock(&sport->port.lock); 736ab4382d2SGreg Kroah-Hartman 73727c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 7384444dcf1SUwe Kleine-König u32 usr2; 7394444dcf1SUwe Kleine-König 740ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 741ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 742ab4382d2SGreg Kroah-Hartman 74327c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 744ab4382d2SGreg Kroah-Hartman 7454444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 7464444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 74727c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 748ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 749ab4382d2SGreg Kroah-Hartman continue; 750ab4382d2SGreg Kroah-Hartman } 751ab4382d2SGreg Kroah-Hartman 752ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 753ab4382d2SGreg Kroah-Hartman continue; 754ab4382d2SGreg Kroah-Hartman 755019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 756019dc9eaSHui Wang if (rx & URXD_BRK) 757019dc9eaSHui Wang sport->port.icount.brk++; 758019dc9eaSHui Wang else if (rx & URXD_PRERR) 759ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 760ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 761ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 762ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 763ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 764ab4382d2SGreg Kroah-Hartman 765ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 766ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 767ab4382d2SGreg Kroah-Hartman goto out; 768ab4382d2SGreg Kroah-Hartman continue; 769ab4382d2SGreg Kroah-Hartman } 770ab4382d2SGreg Kroah-Hartman 7718d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 772ab4382d2SGreg Kroah-Hartman 773019dc9eaSHui Wang if (rx & URXD_BRK) 774019dc9eaSHui Wang flg = TTY_BREAK; 775019dc9eaSHui Wang else if (rx & URXD_PRERR) 776ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 777ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 778ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 779ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 780ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 781ab4382d2SGreg Kroah-Hartman 782ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 783ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 784ab4382d2SGreg Kroah-Hartman #endif 785ab4382d2SGreg Kroah-Hartman } 786ab4382d2SGreg Kroah-Hartman 78755d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 78855d8693aSJiada Wang goto out; 78955d8693aSJiada Wang 7909b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 7919b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 792ab4382d2SGreg Kroah-Hartman } 793ab4382d2SGreg Kroah-Hartman 794ab4382d2SGreg Kroah-Hartman out: 795c974991dSjun qian spin_unlock(&sport->port.lock); 7962e124b4aSJiri Slaby tty_flip_buffer_push(port); 797ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 798ab4382d2SGreg Kroah-Hartman } 799ab4382d2SGreg Kroah-Hartman 8009d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 801b4cdc8f6SHuang Shijie 80266f95884SUwe Kleine-König /* 80366f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 80466f95884SUwe Kleine-König */ 8059d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 80666f95884SUwe Kleine-König { 80766f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 80827c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 80927c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 81066f95884SUwe Kleine-König 81166f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 81266f95884SUwe Kleine-König tmp |= TIOCM_CTS; 81366f95884SUwe Kleine-König 81466f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 8154b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 81666f95884SUwe Kleine-König tmp |= TIOCM_CAR; 81766f95884SUwe Kleine-König 81866f95884SUwe Kleine-König if (sport->dte_mode) 81927c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 82066f95884SUwe Kleine-König tmp |= TIOCM_RI; 82166f95884SUwe Kleine-König 82266f95884SUwe Kleine-König return tmp; 82366f95884SUwe Kleine-König } 82466f95884SUwe Kleine-König 82566f95884SUwe Kleine-König /* 82666f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 82766f95884SUwe Kleine-König */ 8289d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 82966f95884SUwe Kleine-König { 83066f95884SUwe Kleine-König unsigned int status, changed; 83166f95884SUwe Kleine-König 8329d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 83366f95884SUwe Kleine-König changed = status ^ sport->old_status; 83466f95884SUwe Kleine-König 83566f95884SUwe Kleine-König if (changed == 0) 83666f95884SUwe Kleine-König return; 83766f95884SUwe Kleine-König 83866f95884SUwe Kleine-König sport->old_status = status; 83966f95884SUwe Kleine-König 84066f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 84166f95884SUwe Kleine-König sport->port.icount.rng++; 84266f95884SUwe Kleine-König if (changed & TIOCM_DSR) 84366f95884SUwe Kleine-König sport->port.icount.dsr++; 84466f95884SUwe Kleine-König if (changed & TIOCM_CAR) 84566f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 84666f95884SUwe Kleine-König if (changed & TIOCM_CTS) 84766f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 84866f95884SUwe Kleine-König 84966f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 85066f95884SUwe Kleine-König } 85166f95884SUwe Kleine-König 8529d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 853ab4382d2SGreg Kroah-Hartman { 854ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 85543776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 8564d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 857ab4382d2SGreg Kroah-Hartman 85827c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 85927c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 86027c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 86127c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 86227c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 86327c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 864ab4382d2SGreg Kroah-Hartman 86543776896SUwe Kleine-König /* 86643776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 86743776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 86843776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 86943776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 87043776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 87143776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 87243776896SUwe Kleine-König */ 87343776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 87443776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 87543776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 87643776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 877c514a6f8SSergey Organov if ((ucr1 & UCR1_TRDYEN) == 0) 87843776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 87943776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 88043776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 88143776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 88243776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 88343776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 88443776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 88543776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 88643776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 88743776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 88843776896SUwe Kleine-König usr2 &= ~USR2_ORE; 88943776896SUwe Kleine-König 89043776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 8919d1a50a2SUwe Kleine-König imx_uart_rxint(irq, dev_id); 8924d845a62SUwe Kleine-König ret = IRQ_HANDLED; 893b4cdc8f6SHuang Shijie } 894ab4382d2SGreg Kroah-Hartman 89543776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 8969d1a50a2SUwe Kleine-König imx_uart_txint(irq, dev_id); 8974d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8984d845a62SUwe Kleine-König } 899ab4382d2SGreg Kroah-Hartman 9000399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 90127c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 90227e16501SUwe Kleine-König 903c974991dSjun qian spin_lock(&sport->port.lock); 9049d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 905c974991dSjun qian spin_unlock(&sport->port.lock); 90627e16501SUwe Kleine-König 90727e16501SUwe Kleine-König ret = IRQ_HANDLED; 90827e16501SUwe Kleine-König } 90927e16501SUwe Kleine-König 9100399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 9119d1a50a2SUwe Kleine-König imx_uart_rtsint(irq, dev_id); 9124d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9134d845a62SUwe Kleine-König } 914ab4382d2SGreg Kroah-Hartman 9150399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 91627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 9174d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9184d845a62SUwe Kleine-König } 919db1a9b55SFabio Estevam 9200399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 921f1f836e4SAlexander Stein sport->port.icount.overrun++; 92227c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 9234d845a62SUwe Kleine-König ret = IRQ_HANDLED; 924f1f836e4SAlexander Stein } 925f1f836e4SAlexander Stein 9264d845a62SUwe Kleine-König return ret; 927ab4382d2SGreg Kroah-Hartman } 928ab4382d2SGreg Kroah-Hartman 929ab4382d2SGreg Kroah-Hartman /* 930ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 931ab4382d2SGreg Kroah-Hartman */ 9329d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 933ab4382d2SGreg Kroah-Hartman { 934ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9351ce43e58SHuang Shijie unsigned int ret; 936ab4382d2SGreg Kroah-Hartman 93727c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 9381ce43e58SHuang Shijie 9391ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 940686351f3SUwe Kleine-König if (sport->dma_is_txing) 9411ce43e58SHuang Shijie ret = 0; 9421ce43e58SHuang Shijie 9431ce43e58SHuang Shijie return ret; 944ab4382d2SGreg Kroah-Hartman } 945ab4382d2SGreg Kroah-Hartman 9466aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 9479d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 94858362d5bSUwe Kleine-König { 94958362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 9509d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 95158362d5bSUwe Kleine-König 95258362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 95358362d5bSUwe Kleine-König 95458362d5bSUwe Kleine-König return ret; 95558362d5bSUwe Kleine-König } 95658362d5bSUwe Kleine-König 9576aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 9589d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 959ab4382d2SGreg Kroah-Hartman { 960ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9614444dcf1SUwe Kleine-König u32 ucr3, uts; 962ab4382d2SGreg Kroah-Hartman 96317b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 9644444dcf1SUwe Kleine-König u32 ucr2; 9654444dcf1SUwe Kleine-König 966197540dcSSergey Organov /* 967197540dcSSergey Organov * Turn off autoRTS if RTS is lowered and restore autoRTS 968197540dcSSergey Organov * setting if RTS is raised. 969197540dcSSergey Organov */ 9704444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 9714444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 972197540dcSSergey Organov if (mctrl & TIOCM_RTS) { 973197540dcSSergey Organov ucr2 |= UCR2_CTS; 974197540dcSSergey Organov /* 975197540dcSSergey Organov * UCR2_IRTS is unset if and only if the port is 976197540dcSSergey Organov * configured for CRTSCTS, so we use inverted UCR2_IRTS 977197540dcSSergey Organov * to get the state to restore to. 978197540dcSSergey Organov */ 979197540dcSSergey Organov if (!(ucr2 & UCR2_IRTS)) 980197540dcSSergey Organov ucr2 |= UCR2_CTSC; 981197540dcSSergey Organov } 9824444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 98317b8f2a3SUwe Kleine-König } 9846b471a98SHuang Shijie 9854444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 98690ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 9874444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 9884444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 98990ebc483SUwe Kleine-König 9909d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 9916b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 9924444dcf1SUwe Kleine-König uts |= UTS_LOOP; 9939d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 99458362d5bSUwe Kleine-König 99558362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 996ab4382d2SGreg Kroah-Hartman } 997ab4382d2SGreg Kroah-Hartman 998ab4382d2SGreg Kroah-Hartman /* 999ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 1000ab4382d2SGreg Kroah-Hartman */ 10019d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1002ab4382d2SGreg Kroah-Hartman { 1003ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10044444dcf1SUwe Kleine-König unsigned long flags; 10054444dcf1SUwe Kleine-König u32 ucr1; 1006ab4382d2SGreg Kroah-Hartman 1007ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1008ab4382d2SGreg Kroah-Hartman 10094444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1010ab4382d2SGreg Kroah-Hartman 1011ab4382d2SGreg Kroah-Hartman if (break_state != 0) 10124444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1013ab4382d2SGreg Kroah-Hartman 10144444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1015ab4382d2SGreg Kroah-Hartman 1016ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1017ab4382d2SGreg Kroah-Hartman } 1018ab4382d2SGreg Kroah-Hartman 1019cc568849SUwe Kleine-König /* 1020cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1021cc568849SUwe Kleine-König * modem status signals. 1022cc568849SUwe Kleine-König */ 10239d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1024cc568849SUwe Kleine-König { 1025e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1026cc568849SUwe Kleine-König unsigned long flags; 1027cc568849SUwe Kleine-König 1028cc568849SUwe Kleine-König if (sport->port.state) { 1029cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 10309d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1031cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1032cc568849SUwe Kleine-König 1033cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1034cc568849SUwe Kleine-König } 1035cc568849SUwe Kleine-König } 1036cc568849SUwe Kleine-König 1037351ea50dSGreg Kroah-Hartman #define RX_BUF_SIZE (PAGE_SIZE) 1038351ea50dSGreg Kroah-Hartman 1039b4cdc8f6SHuang Shijie /* 1040905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1041b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1042905c0decSLucas Stach * [2] the aging timer expires 1043b4cdc8f6SHuang Shijie * 1044905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1045905c0decSLucas Stach * for at least 8 byte durations. 1046b4cdc8f6SHuang Shijie */ 10479d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1048b4cdc8f6SHuang Shijie { 1049b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1050b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1051b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 10527cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1053b4cdc8f6SHuang Shijie struct dma_tx_state state; 10549d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1055b4cdc8f6SHuang Shijie enum dma_status status; 10569d297239SNandor Han unsigned int w_bytes = 0; 10579d297239SNandor Han unsigned int r_bytes; 10589d297239SNandor Han unsigned int bd_size; 1059b4cdc8f6SHuang Shijie 1060fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1061392bceedSPhilipp Zabel 10629d297239SNandor Han if (status == DMA_ERROR) { 10639d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 10649d297239SNandor Han return; 10659d297239SNandor Han } 1066b4cdc8f6SHuang Shijie 10679b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1068976b39cdSLucas Stach 1069976b39cdSLucas Stach /* 10709d297239SNandor Han * The state-residue variable represents the empty space 10719d297239SNandor Han * relative to the entire buffer. Taking this in consideration 10729d297239SNandor Han * the head is always calculated base on the buffer total 10739d297239SNandor Han * length - DMA transaction residue. The UART script from the 10749d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 10759d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 10769d297239SNandor Han * Taking this in consideration the tail is always at the 10779d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1078976b39cdSLucas Stach */ 10799d297239SNandor Han 10809d297239SNandor Han /* Calculate the head */ 10819d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 10829d297239SNandor Han 10839d297239SNandor Han /* Calculate the tail. */ 10849d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 10859d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 10869d297239SNandor Han 10879d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 10889d297239SNandor Han rx_ring->head > rx_ring->tail) { 10899d297239SNandor Han 10909d297239SNandor Han /* Move data from tail to head */ 10919d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 10929d297239SNandor Han 10939d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 10949d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 10959d297239SNandor Han DMA_FROM_DEVICE); 10969d297239SNandor Han 10979d297239SNandor Han w_bytes = tty_insert_flip_string(port, 10989d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 10999d297239SNandor Han 11009d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 11019d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 11029d297239SNandor Han DMA_FROM_DEVICE); 11039d297239SNandor Han 11049d297239SNandor Han if (w_bytes != r_bytes) 11059d297239SNandor Han sport->port.icount.buf_overrun++; 11069d297239SNandor Han 11079d297239SNandor Han sport->port.icount.rx += w_bytes; 11089d297239SNandor Han } else { 11099d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11109d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1111ee5e7c10SRobin Gong } 11129d297239SNandor Han } 11139d297239SNandor Han 11149d297239SNandor Han if (w_bytes) { 11159d297239SNandor Han tty_flip_buffer_push(port); 11169d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 11179d297239SNandor Han } 11189d297239SNandor Han } 11199d297239SNandor Han 1120351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 1121351ea50dSGreg Kroah-Hartman #define RX_DMA_PERIODS 4 1122351ea50dSGreg Kroah-Hartman 11239d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1124b4cdc8f6SHuang Shijie { 1125b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1126b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1127b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1128b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1129b4cdc8f6SHuang Shijie int ret; 1130b4cdc8f6SHuang Shijie 11319d297239SNandor Han sport->rx_ring.head = 0; 11329d297239SNandor Han sport->rx_ring.tail = 0; 1133351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 11349d297239SNandor Han 1135351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1136b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1137b4cdc8f6SHuang Shijie if (ret == 0) { 1138b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1139b4cdc8f6SHuang Shijie return -EINVAL; 1140b4cdc8f6SHuang Shijie } 11419d297239SNandor Han 11429d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 11439d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 11449d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 11459d297239SNandor Han 1146b4cdc8f6SHuang Shijie if (!desc) { 114724649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1148b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1149b4cdc8f6SHuang Shijie return -EINVAL; 1150b4cdc8f6SHuang Shijie } 11519d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1152b4cdc8f6SHuang Shijie desc->callback_param = sport; 1153b4cdc8f6SHuang Shijie 1154b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 11554139fd76SRomain Perier sport->dma_is_rxing = 1; 11569d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1157b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1158b4cdc8f6SHuang Shijie return 0; 1159b4cdc8f6SHuang Shijie } 1160b4cdc8f6SHuang Shijie 11619d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 116241d98b5dSNandor Han { 116345ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 11644444dcf1SUwe Kleine-König u32 usr1, usr2; 116541d98b5dSNandor Han 11664444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 11674444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 116841d98b5dSNandor Han 11694444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 117041d98b5dSNandor Han sport->port.icount.brk++; 117127c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 117245ca673eSTroy Kisky uart_handle_break(&sport->port); 117345ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 117445ca673eSTroy Kisky sport->port.icount.buf_overrun++; 117545ca673eSTroy Kisky tty_flip_buffer_push(port); 117645ca673eSTroy Kisky } else { 11774444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 117841d98b5dSNandor Han sport->port.icount.frame++; 117927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 11804444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 118141d98b5dSNandor Han sport->port.icount.parity++; 118227c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 118341d98b5dSNandor Han } 118445ca673eSTroy Kisky } 118541d98b5dSNandor Han 11864444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 118741d98b5dSNandor Han sport->port.icount.overrun++; 118827c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 118941d98b5dSNandor Han } 119041d98b5dSNandor Han 119141d98b5dSNandor Han } 119241d98b5dSNandor Han 1193cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1194cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1195184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1196184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1197cc32382dSLucas Stach 11989d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1199cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1200cc32382dSLucas Stach { 1201cc32382dSLucas Stach unsigned int val; 1202cc32382dSLucas Stach 1203cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 120427c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1205cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 120627c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1207cc32382dSLucas Stach } 1208cc32382dSLucas Stach 1209b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1210b4cdc8f6SHuang Shijie { 1211b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1212e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1213b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1214b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 12159d297239SNandor Han sport->rx_cookie = -EINVAL; 1216b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1217b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1218b4cdc8f6SHuang Shijie } 1219b4cdc8f6SHuang Shijie 1220b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1221e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1222b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1223b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1224b4cdc8f6SHuang Shijie } 1225b4cdc8f6SHuang Shijie } 1226b4cdc8f6SHuang Shijie 1227b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1228b4cdc8f6SHuang Shijie { 1229b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1230b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1231b4cdc8f6SHuang Shijie int ret; 1232b4cdc8f6SHuang Shijie 1233b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1234b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1235b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1236b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1237b4cdc8f6SHuang Shijie ret = -EINVAL; 1238b4cdc8f6SHuang Shijie goto err; 1239b4cdc8f6SHuang Shijie } 1240b4cdc8f6SHuang Shijie 1241b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1242b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1243b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1244184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1245184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1246b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1247b4cdc8f6SHuang Shijie if (ret) { 1248b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1249b4cdc8f6SHuang Shijie goto err; 1250b4cdc8f6SHuang Shijie } 1251b4cdc8f6SHuang Shijie 1252f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1253b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1254b4cdc8f6SHuang Shijie ret = -ENOMEM; 1255b4cdc8f6SHuang Shijie goto err; 1256b4cdc8f6SHuang Shijie } 12579d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1258b4cdc8f6SHuang Shijie 1259b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1260b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1261b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1262b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1263b4cdc8f6SHuang Shijie ret = -EINVAL; 1264b4cdc8f6SHuang Shijie goto err; 1265b4cdc8f6SHuang Shijie } 1266b4cdc8f6SHuang Shijie 1267b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1268b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1269b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1270184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1271b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1272b4cdc8f6SHuang Shijie if (ret) { 1273b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1274b4cdc8f6SHuang Shijie goto err; 1275b4cdc8f6SHuang Shijie } 1276b4cdc8f6SHuang Shijie 1277b4cdc8f6SHuang Shijie return 0; 1278b4cdc8f6SHuang Shijie err: 1279b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1280b4cdc8f6SHuang Shijie return ret; 1281b4cdc8f6SHuang Shijie } 1282b4cdc8f6SHuang Shijie 12839d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1284b4cdc8f6SHuang Shijie { 12854444dcf1SUwe Kleine-König u32 ucr1; 1286b4cdc8f6SHuang Shijie 12879d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 128802b0abd3SUwe Kleine-König 1289b4cdc8f6SHuang Shijie /* set UCR1 */ 12904444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12914444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 12924444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1293b4cdc8f6SHuang Shijie 1294b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1295b4cdc8f6SHuang Shijie } 1296b4cdc8f6SHuang Shijie 12979d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1298b4cdc8f6SHuang Shijie { 1299676a31d8SSebastian Reichel u32 ucr1; 1300b4cdc8f6SHuang Shijie 1301b4cdc8f6SHuang Shijie /* clear UCR1 */ 13024444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13034444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 13044444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1305b4cdc8f6SHuang Shijie 13069d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1307184bd70bSLucas Stach 1308b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1309b4cdc8f6SHuang Shijie } 1310b4cdc8f6SHuang Shijie 1311ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1312ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1313ab4382d2SGreg Kroah-Hartman 13149d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1315ab4382d2SGreg Kroah-Hartman { 1316ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1317458e2c82SFabio Estevam int retval, i; 13184444dcf1SUwe Kleine-König unsigned long flags; 13194238c00bSUwe Kleine-König int dma_is_inited = 0; 13204444dcf1SUwe Kleine-König u32 ucr1, ucr2, ucr4; 1321ab4382d2SGreg Kroah-Hartman 132228eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 132328eb4274SHuang Shijie if (retval) 1324cb0f0a5fSFabio Estevam return retval; 132528eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 13260c375501SHuang Shijie if (retval) { 13270c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1328cb0f0a5fSFabio Estevam return retval; 13290c375501SHuang Shijie } 133028eb4274SHuang Shijie 13319d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1332ab4382d2SGreg Kroah-Hartman 1333ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1334ab4382d2SGreg Kroah-Hartman * requesting IRQs 1335ab4382d2SGreg Kroah-Hartman */ 13364444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1337ab4382d2SGreg Kroah-Hartman 1338ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 13394444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 13404444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1341ab4382d2SGreg Kroah-Hartman 13424444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1343ab4382d2SGreg Kroah-Hartman 13447e11577eSLucas Stach /* Can we enable the DMA support? */ 13454238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 13464238c00bSUwe Kleine-König dma_is_inited = 1; 13477e11577eSLucas Stach 134853794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1349772f8991SHuang Shijie /* Reset fifo's and state machines */ 1350458e2c82SFabio Estevam i = 100; 1351458e2c82SFabio Estevam 13524444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 13534444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 13544444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1355458e2c82SFabio Estevam 135627c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1357458e2c82SFabio Estevam udelay(1); 1358ab4382d2SGreg Kroah-Hartman 1359ab4382d2SGreg Kroah-Hartman /* 1360ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1361ab4382d2SGreg Kroah-Hartman */ 136227c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 136327c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1364ab4382d2SGreg Kroah-Hartman 13654444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 13664444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 13676376cd39SNandor Han if (sport->have_rtscts) 13684444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1369ab4382d2SGreg Kroah-Hartman 13704444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1371ab4382d2SGreg Kroah-Hartman 13724444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 13731f043572STroy Kisky if (!sport->dma_is_enabled) 13744444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 13754444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 13766f026d6bSJiada Wang 13774444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 13784444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1379bff09b09SLucas Stach if (!sport->have_rtscts) 13804444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 138116804d68SUwe Kleine-König /* 138216804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 138316804d68SUwe Kleine-König * we're using RTSD instead. 138416804d68SUwe Kleine-König */ 13859d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 13864444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 13874444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1388ab4382d2SGreg Kroah-Hartman 13899d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) { 13904444dcf1SUwe Kleine-König u32 ucr3; 139116804d68SUwe Kleine-König 13924444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 13934444dcf1SUwe Kleine-König 13944444dcf1SUwe Kleine-König ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 139516804d68SUwe Kleine-König 139616804d68SUwe Kleine-König if (sport->dte_mode) 1397e61c38d8SUwe Kleine-König /* disable broken interrupts */ 13984444dcf1SUwe Kleine-König ucr3 &= ~(UCR3_RI | UCR3_DCD); 139916804d68SUwe Kleine-König 14004444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 1401ab4382d2SGreg Kroah-Hartman } 1402ab4382d2SGreg Kroah-Hartman 1403ab4382d2SGreg Kroah-Hartman /* 1404ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1405ab4382d2SGreg Kroah-Hartman */ 14069d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 140718a42088SPeter Senna Tschudin 140876821e22SUwe Kleine-König if (dma_is_inited) { 14099d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 14109d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 141176821e22SUwe Kleine-König } else { 141276821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 141376821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 141476821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 141581ca8e82SUwe Kleine-König 141681ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 141781ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 141881ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 141976821e22SUwe Kleine-König } 142018a42088SPeter Senna Tschudin 1421ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1422ab4382d2SGreg Kroah-Hartman 1423ab4382d2SGreg Kroah-Hartman return 0; 1424ab4382d2SGreg Kroah-Hartman } 1425ab4382d2SGreg Kroah-Hartman 14269d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1427ab4382d2SGreg Kroah-Hartman { 1428ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 14299ec1882dSXinyu Chen unsigned long flags; 1430339c7a87SSebastian Reichel u32 ucr1, ucr2, ucr4; 1431ab4382d2SGreg Kroah-Hartman 1432b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1433e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 14347722c240SSebastian Reichel if (sport->dma_is_txing) { 14357722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 14367722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 14377722c240SSebastian Reichel sport->dma_is_txing = 0; 14387722c240SSebastian Reichel } 1439e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 14407722c240SSebastian Reichel if (sport->dma_is_rxing) { 14417722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 14427722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 14437722c240SSebastian Reichel sport->dma_is_rxing = 0; 14447722c240SSebastian Reichel } 14459d297239SNandor Han 144673631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 14479d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 14489d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 14499d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 145073631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1451b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1452b4cdc8f6SHuang Shijie } 1453b4cdc8f6SHuang Shijie 145458362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 145558362d5bSUwe Kleine-König 14569ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14574444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14580fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 14594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1460339c7a87SSebastian Reichel 1461339c7a87SSebastian Reichel ucr4 = imx_uart_readl(sport, UCR4); 1462339c7a87SSebastian Reichel ucr4 &= ~UCR4_OREN; 1463339c7a87SSebastian Reichel imx_uart_writel(sport, ucr4, UCR4); 14649ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1465ab4382d2SGreg Kroah-Hartman 1466ab4382d2SGreg Kroah-Hartman /* 1467ab4382d2SGreg Kroah-Hartman * Stop our timer. 1468ab4382d2SGreg Kroah-Hartman */ 1469ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1470ab4382d2SGreg Kroah-Hartman 1471ab4382d2SGreg Kroah-Hartman /* 1472ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1473ab4382d2SGreg Kroah-Hartman */ 1474ab4382d2SGreg Kroah-Hartman 14759ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14764444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 1477c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1478ab4382d2SGreg Kroah-Hartman 14794444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14809ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 148128eb4274SHuang Shijie 148228eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 148328eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1484ab4382d2SGreg Kroah-Hartman } 1485ab4382d2SGreg Kroah-Hartman 14866aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 14879d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1488eb56b7edSHuang Shijie { 1489eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 149082e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 14914444dcf1SUwe Kleine-König u32 ucr2; 14924f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1493eb56b7edSHuang Shijie 149482e86ae9SDirk Behme if (!sport->dma_chan_tx) 149582e86ae9SDirk Behme return; 149682e86ae9SDirk Behme 1497eb56b7edSHuang Shijie sport->tx_bytes = 0; 1498eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 149982e86ae9SDirk Behme if (sport->dma_is_txing) { 15004444dcf1SUwe Kleine-König u32 ucr1; 15014444dcf1SUwe Kleine-König 150282e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 150382e86ae9SDirk Behme DMA_TO_DEVICE); 15044444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 15054444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 15064444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 15070f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1508eb56b7edSHuang Shijie } 1509934084a9SFabio Estevam 1510934084a9SFabio Estevam /* 1511934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1512263763c1SMartyn Welch * 1513934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1514934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1515263763c1SMartyn Welch * and UTS[6-3]". 1516263763c1SMartyn Welch * 1517263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1518263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1519263763c1SMartyn Welch * registers. 1520934084a9SFabio Estevam */ 152127c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 152227c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 152327c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1524934084a9SFabio Estevam 15254444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15264444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 15274444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1528934084a9SFabio Estevam 152927c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1530934084a9SFabio Estevam udelay(1); 1531934084a9SFabio Estevam 1532934084a9SFabio Estevam /* Restore the registers */ 153327c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 153427c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 153527c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1536eb56b7edSHuang Shijie } 1537eb56b7edSHuang Shijie 1538ab4382d2SGreg Kroah-Hartman static void 15399d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1540ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1541ab4382d2SGreg Kroah-Hartman { 1542ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1543ab4382d2SGreg Kroah-Hartman unsigned long flags; 154485f30fbfSSergey Organov u32 ucr2, old_ucr2, ufcr; 154558362d5bSUwe Kleine-König unsigned int baud, quot; 1546ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 15474444dcf1SUwe Kleine-König unsigned long div; 1548d47bcb4aSSergey Organov unsigned long num, denom, old_ubir, old_ubmr; 1549ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1550ab4382d2SGreg Kroah-Hartman 1551ab4382d2SGreg Kroah-Hartman /* 1552ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1553ab4382d2SGreg Kroah-Hartman */ 1554ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1555ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1556ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1557ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1558ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1559ab4382d2SGreg Kroah-Hartman } 1560ab4382d2SGreg Kroah-Hartman 15614e828c3eSSergey Organov del_timer_sync(&sport->timer); 15624e828c3eSSergey Organov 15634e828c3eSSergey Organov /* 15644e828c3eSSergey Organov * Ask the core to calculate the divisor for us. 15654e828c3eSSergey Organov */ 15664e828c3eSSergey Organov baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 15674e828c3eSSergey Organov quot = uart_get_divisor(port, baud); 15684e828c3eSSergey Organov 15694e828c3eSSergey Organov spin_lock_irqsave(&sport->port.lock, flags); 15704e828c3eSSergey Organov 1571011bd05dSSergey Organov /* 1572011bd05dSSergey Organov * Read current UCR2 and save it for future use, then clear all the bits 1573011bd05dSSergey Organov * except those we will or may need to preserve. 1574011bd05dSSergey Organov */ 1575011bd05dSSergey Organov old_ucr2 = imx_uart_readl(sport, UCR2); 1576011bd05dSSergey Organov ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1577011bd05dSSergey Organov 1578011bd05dSSergey Organov ucr2 |= UCR2_SRST | UCR2_IRTS; 157941ffa48eSSergey Organov if ((termios->c_cflag & CSIZE) == CS8) 158041ffa48eSSergey Organov ucr2 |= UCR2_WS; 1581ab4382d2SGreg Kroah-Hartman 1582ddf89e75SSergey Organov if (!sport->have_rtscts) 1583ddf89e75SSergey Organov termios->c_cflag &= ~CRTSCTS; 158417b8f2a3SUwe Kleine-König 158512fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 158617b8f2a3SUwe Kleine-König /* 158717b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 158817b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 158917b8f2a3SUwe Kleine-König * disabled. 159017b8f2a3SUwe Kleine-König */ 159158362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 15929d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 15931a613626SFabio Estevam else 15949d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 159558362d5bSUwe Kleine-König 1596b777b5deSSergey Organov } else if (termios->c_cflag & CRTSCTS) { 1597b777b5deSSergey Organov /* 1598b777b5deSSergey Organov * Only let receiver control RTS output if we were not requested 1599b777b5deSSergey Organov * to have RTS inactive (which then should take precedence). 1600b777b5deSSergey Organov */ 1601b777b5deSSergey Organov if (ucr2 & UCR2_CTS) 1602b777b5deSSergey Organov ucr2 |= UCR2_CTSC; 1603b777b5deSSergey Organov } 1604ddf89e75SSergey Organov 1605ddf89e75SSergey Organov if (termios->c_cflag & CRTSCTS) 1606ddf89e75SSergey Organov ucr2 &= ~UCR2_IRTS; 1607ab4382d2SGreg Kroah-Hartman 1608ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1609ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1610ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1611ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1612ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1613ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1614ab4382d2SGreg Kroah-Hartman } 1615ab4382d2SGreg Kroah-Hartman 1616ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1617ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1618ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1619ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1620ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1621ab4382d2SGreg Kroah-Hartman 1622ab4382d2SGreg Kroah-Hartman /* 1623ab4382d2SGreg Kroah-Hartman * Characters to ignore 1624ab4382d2SGreg Kroah-Hartman */ 1625ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1626ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1627865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1628ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1629ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1630ab4382d2SGreg Kroah-Hartman /* 1631ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1632ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1633ab4382d2SGreg Kroah-Hartman */ 1634ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1635ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1636ab4382d2SGreg Kroah-Hartman } 1637ab4382d2SGreg Kroah-Hartman 163855d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 163955d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 164055d8693aSJiada Wang 1641ab4382d2SGreg Kroah-Hartman /* 1642ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1643ab4382d2SGreg Kroah-Hartman */ 1644ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1645ab4382d2SGreg Kroah-Hartman 164609bd00f6SHubert Feurstein /* custom-baudrate handling */ 164709bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 164809bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 164909bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 165009bd00f6SHubert Feurstein 1651ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1652ab4382d2SGreg Kroah-Hartman if (div > 7) 1653ab4382d2SGreg Kroah-Hartman div = 7; 1654ab4382d2SGreg Kroah-Hartman if (!div) 1655ab4382d2SGreg Kroah-Hartman div = 1; 1656ab4382d2SGreg Kroah-Hartman 1657ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1658ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1659ab4382d2SGreg Kroah-Hartman 1660ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1661ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1662ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1663ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1664ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1665ab4382d2SGreg Kroah-Hartman 1666ab4382d2SGreg Kroah-Hartman num -= 1; 1667ab4382d2SGreg Kroah-Hartman denom -= 1; 1668ab4382d2SGreg Kroah-Hartman 166927c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1670ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 167127c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1672ab4382d2SGreg Kroah-Hartman 1673d47bcb4aSSergey Organov /* 1674d47bcb4aSSergey Organov * Two registers below should always be written both and in this 1675d47bcb4aSSergey Organov * particular order. One consequence is that we need to check if any of 1676d47bcb4aSSergey Organov * them changes and then update both. We do need the check for change 1677d47bcb4aSSergey Organov * as even writing the same values seem to "restart" 1678d47bcb4aSSergey Organov * transmission/receiving logic in the hardware, that leads to data 1679d47bcb4aSSergey Organov * breakage even when rate doesn't in fact change. E.g., user switches 1680d47bcb4aSSergey Organov * RTS/CTS handshake and suddenly gets broken bytes. 1681d47bcb4aSSergey Organov */ 1682d47bcb4aSSergey Organov old_ubir = imx_uart_readl(sport, UBIR); 1683d47bcb4aSSergey Organov old_ubmr = imx_uart_readl(sport, UBMR); 1684d47bcb4aSSergey Organov if (old_ubir != num || old_ubmr != denom) { 168527c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 168627c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1687d47bcb4aSSergey Organov } 1688ab4382d2SGreg Kroah-Hartman 16899d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 169027c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 169127c84426SUwe Kleine-König IMX21_ONEMS); 1692ab4382d2SGreg Kroah-Hartman 1693011bd05dSSergey Organov imx_uart_writel(sport, ucr2, UCR2); 1694ab4382d2SGreg Kroah-Hartman 1695ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 16969d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1697ab4382d2SGreg Kroah-Hartman 1698ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1699ab4382d2SGreg Kroah-Hartman } 1700ab4382d2SGreg Kroah-Hartman 17019d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1702ab4382d2SGreg Kroah-Hartman { 1703ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1704ab4382d2SGreg Kroah-Hartman 1705ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1706ab4382d2SGreg Kroah-Hartman } 1707ab4382d2SGreg Kroah-Hartman 1708ab4382d2SGreg Kroah-Hartman /* 1709ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1710ab4382d2SGreg Kroah-Hartman */ 17119d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1712ab4382d2SGreg Kroah-Hartman { 1713ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1714ab4382d2SGreg Kroah-Hartman 1715da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1716ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1717ab4382d2SGreg Kroah-Hartman } 1718ab4382d2SGreg Kroah-Hartman 1719ab4382d2SGreg Kroah-Hartman /* 1720ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1721ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1722ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1723ab4382d2SGreg Kroah-Hartman */ 1724ab4382d2SGreg Kroah-Hartman static int 17259d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1726ab4382d2SGreg Kroah-Hartman { 1727ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1728ab4382d2SGreg Kroah-Hartman int ret = 0; 1729ab4382d2SGreg Kroah-Hartman 1730ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1731ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1732ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1733ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1734ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1735ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1736ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1737ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1738a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1739ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1740ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1741ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1742ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1743ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1744ab4382d2SGreg Kroah-Hartman return ret; 1745ab4382d2SGreg Kroah-Hartman } 1746ab4382d2SGreg Kroah-Hartman 174701f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17486b8bdad9SDaniel Thompson 17499d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 17506b8bdad9SDaniel Thompson { 17516b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 17526b8bdad9SDaniel Thompson unsigned long flags; 17534444dcf1SUwe Kleine-König u32 ucr1, ucr2; 17546b8bdad9SDaniel Thompson int retval; 17556b8bdad9SDaniel Thompson 17566b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 17576b8bdad9SDaniel Thompson if (retval) 17586b8bdad9SDaniel Thompson return retval; 17596b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 17606b8bdad9SDaniel Thompson if (retval) 17616b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 17626b8bdad9SDaniel Thompson 17639d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 17646b8bdad9SDaniel Thompson 17656b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 17666b8bdad9SDaniel Thompson 176776821e22SUwe Kleine-König /* 176876821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 176976821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 177076821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 177176821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 177276821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 177376821e22SUwe Kleine-König */ 17744444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 177576821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 177676821e22SUwe Kleine-König 17779d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 17784444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 17796b8bdad9SDaniel Thompson 178076821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 1781c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 178276821e22SUwe Kleine-König 17834444dcf1SUwe Kleine-König ucr2 |= UCR2_RXEN; 178481ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 178576821e22SUwe Kleine-König 178676821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 17874444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 17886b8bdad9SDaniel Thompson 178976821e22SUwe Kleine-König /* now enable irqs */ 179076821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 179181ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 179276821e22SUwe Kleine-König 17936b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 17946b8bdad9SDaniel Thompson 17956b8bdad9SDaniel Thompson return 0; 17966b8bdad9SDaniel Thompson } 17976b8bdad9SDaniel Thompson 17989d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 179901f56abdSSaleem Abdulrasool { 180027c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 180127c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 180226c47412SDirk Behme return NO_POLL_CHAR; 180301f56abdSSaleem Abdulrasool 180427c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 180501f56abdSSaleem Abdulrasool } 180601f56abdSSaleem Abdulrasool 18079d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 180801f56abdSSaleem Abdulrasool { 180927c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 181001f56abdSSaleem Abdulrasool unsigned int status; 181101f56abdSSaleem Abdulrasool 181201f56abdSSaleem Abdulrasool /* drain */ 181301f56abdSSaleem Abdulrasool do { 181427c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 181501f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 181601f56abdSSaleem Abdulrasool 181701f56abdSSaleem Abdulrasool /* write */ 181827c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 181901f56abdSSaleem Abdulrasool 182001f56abdSSaleem Abdulrasool /* flush */ 182101f56abdSSaleem Abdulrasool do { 182227c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 182301f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 182401f56abdSSaleem Abdulrasool } 182501f56abdSSaleem Abdulrasool #endif 182601f56abdSSaleem Abdulrasool 18276aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 18289d1a50a2SUwe Kleine-König static int imx_uart_rs485_config(struct uart_port *port, 182917b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 183017b8f2a3SUwe Kleine-König { 183117b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 18324444dcf1SUwe Kleine-König u32 ucr2; 183317b8f2a3SUwe Kleine-König 183417b8f2a3SUwe Kleine-König /* unimplemented */ 183517b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 183617b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 183717b8f2a3SUwe Kleine-König 183817b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 18397b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 184017b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 184117b8f2a3SUwe Kleine-König 184217b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 18436d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 18446d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 18456d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 18466d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 18476d215f83SStefan Agner 184817b8f2a3SUwe Kleine-König /* disable transmitter */ 18494444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 185017b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 18519d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 18521a613626SFabio Estevam else 18539d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 18544444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 185517b8f2a3SUwe Kleine-König } 185617b8f2a3SUwe Kleine-König 18577d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 18587d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 185976821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 18609d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 18617d1cadcaSBaruch Siach 186217b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 186317b8f2a3SUwe Kleine-König 186417b8f2a3SUwe Kleine-König return 0; 186517b8f2a3SUwe Kleine-König } 186617b8f2a3SUwe Kleine-König 18679d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 18689d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 18699d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 18709d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 18719d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 18729d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 18739d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 18749d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 18759d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 18769d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 18779d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 18789d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 18799d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 18809d1a50a2SUwe Kleine-König .type = imx_uart_type, 18819d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 18829d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 188301f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18849d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 18859d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 18869d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 188701f56abdSSaleem Abdulrasool #endif 1888ab4382d2SGreg Kroah-Hartman }; 1889ab4382d2SGreg Kroah-Hartman 18909d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1891ab4382d2SGreg Kroah-Hartman 1892ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 18939d1a50a2SUwe Kleine-König static void imx_uart_console_putchar(struct uart_port *port, int ch) 1894ab4382d2SGreg Kroah-Hartman { 1895ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1896ab4382d2SGreg Kroah-Hartman 18979d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1898ab4382d2SGreg Kroah-Hartman barrier(); 1899ab4382d2SGreg Kroah-Hartman 190027c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1901ab4382d2SGreg Kroah-Hartman } 1902ab4382d2SGreg Kroah-Hartman 1903ab4382d2SGreg Kroah-Hartman /* 1904ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1905ab4382d2SGreg Kroah-Hartman */ 1906ab4382d2SGreg Kroah-Hartman static void 19079d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1908ab4382d2SGreg Kroah-Hartman { 19099d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 19100ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 19110ad5a814SDirk Behme unsigned int ucr1; 1912f30e8260SShawn Guo unsigned long flags = 0; 1913677fe555SThomas Gleixner int locked = 1; 19141cf93e0dSHuang Shijie int retval; 19151cf93e0dSHuang Shijie 19160c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 19171cf93e0dSHuang Shijie if (retval) 19181cf93e0dSHuang Shijie return; 19190c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 19201cf93e0dSHuang Shijie if (retval) { 19210c727a42SFabio Estevam clk_disable(sport->clk_per); 19221cf93e0dSHuang Shijie return; 19231cf93e0dSHuang Shijie } 19249ec1882dSXinyu Chen 1925677fe555SThomas Gleixner if (sport->port.sysrq) 1926677fe555SThomas Gleixner locked = 0; 1927677fe555SThomas Gleixner else if (oops_in_progress) 1928677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1929677fe555SThomas Gleixner else 19309ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1931ab4382d2SGreg Kroah-Hartman 1932ab4382d2SGreg Kroah-Hartman /* 19330ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1934ab4382d2SGreg Kroah-Hartman */ 19359d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 19360ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1937ab4382d2SGreg Kroah-Hartman 19389d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 1939fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1940ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1941c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1942ab4382d2SGreg Kroah-Hartman 194327c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1944ab4382d2SGreg Kroah-Hartman 194527c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1946ab4382d2SGreg Kroah-Hartman 19479d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 1948ab4382d2SGreg Kroah-Hartman 1949ab4382d2SGreg Kroah-Hartman /* 1950ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 19510ad5a814SDirk Behme * and restore UCR1/2/3 1952ab4382d2SGreg Kroah-Hartman */ 195327c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1954ab4382d2SGreg Kroah-Hartman 19559d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 19569ec1882dSXinyu Chen 1957677fe555SThomas Gleixner if (locked) 19589ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 19591cf93e0dSHuang Shijie 19600c727a42SFabio Estevam clk_disable(sport->clk_ipg); 19610c727a42SFabio Estevam clk_disable(sport->clk_per); 1962ab4382d2SGreg Kroah-Hartman } 1963ab4382d2SGreg Kroah-Hartman 1964ab4382d2SGreg Kroah-Hartman /* 1965ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1966ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1967ab4382d2SGreg Kroah-Hartman */ 1968ab4382d2SGreg Kroah-Hartman static void __init 19699d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 1970ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1971ab4382d2SGreg Kroah-Hartman { 1972ab4382d2SGreg Kroah-Hartman 197327c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1974ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1975ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1976ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1977ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1978ab4382d2SGreg Kroah-Hartman 197927c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 1980ab4382d2SGreg Kroah-Hartman 1981ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1982ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1983ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1984ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1985ab4382d2SGreg Kroah-Hartman else 1986ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1987ab4382d2SGreg Kroah-Hartman } 1988ab4382d2SGreg Kroah-Hartman 1989ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1990ab4382d2SGreg Kroah-Hartman *bits = 8; 1991ab4382d2SGreg Kroah-Hartman else 1992ab4382d2SGreg Kroah-Hartman *bits = 7; 1993ab4382d2SGreg Kroah-Hartman 199427c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 199527c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 1996ab4382d2SGreg Kroah-Hartman 199727c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 1998ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1999ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 2000ab4382d2SGreg Kroah-Hartman else 2001ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 2002ab4382d2SGreg Kroah-Hartman 20033a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2004ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2005ab4382d2SGreg Kroah-Hartman 2006ab4382d2SGreg Kroah-Hartman { /* 2007ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2008ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2009ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2010ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2011ab4382d2SGreg Kroah-Hartman */ 2012ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2013ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2014ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2015ab4382d2SGreg Kroah-Hartman 2016ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2017ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2018ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2019ab4382d2SGreg Kroah-Hartman } 2020ab4382d2SGreg Kroah-Hartman 2021ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 2022f5a9e5f7SFabio Estevam dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2023ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2024ab4382d2SGreg Kroah-Hartman } 2025ab4382d2SGreg Kroah-Hartman } 2026ab4382d2SGreg Kroah-Hartman 2027ab4382d2SGreg Kroah-Hartman static int __init 20289d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2029ab4382d2SGreg Kroah-Hartman { 2030ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2031ab4382d2SGreg Kroah-Hartman int baud = 9600; 2032ab4382d2SGreg Kroah-Hartman int bits = 8; 2033ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2034ab4382d2SGreg Kroah-Hartman int flow = 'n'; 20351cf93e0dSHuang Shijie int retval; 2036ab4382d2SGreg Kroah-Hartman 2037ab4382d2SGreg Kroah-Hartman /* 2038ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2039ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2040ab4382d2SGreg Kroah-Hartman * console support. 2041ab4382d2SGreg Kroah-Hartman */ 20429d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2043ab4382d2SGreg Kroah-Hartman co->index = 0; 20449d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2045ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2046ab4382d2SGreg Kroah-Hartman return -ENODEV; 2047ab4382d2SGreg Kroah-Hartman 20481cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 20491cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 20501cf93e0dSHuang Shijie if (retval) 20511cf93e0dSHuang Shijie goto error_console; 20521cf93e0dSHuang Shijie 2053ab4382d2SGreg Kroah-Hartman if (options) 2054ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2055ab4382d2SGreg Kroah-Hartman else 20569d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2057ab4382d2SGreg Kroah-Hartman 20589d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2059ab4382d2SGreg Kroah-Hartman 20601cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 20611cf93e0dSHuang Shijie 20620c727a42SFabio Estevam clk_disable(sport->clk_ipg); 20630c727a42SFabio Estevam if (retval) { 20640c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 20650c727a42SFabio Estevam goto error_console; 20660c727a42SFabio Estevam } 20670c727a42SFabio Estevam 20680c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 20690c727a42SFabio Estevam if (retval) 207063fd4b94SStefan Agner clk_unprepare(sport->clk_ipg); 20711cf93e0dSHuang Shijie 20721cf93e0dSHuang Shijie error_console: 20731cf93e0dSHuang Shijie return retval; 2074ab4382d2SGreg Kroah-Hartman } 2075ab4382d2SGreg Kroah-Hartman 20769d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 20779d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2078ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 20799d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2080ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 20819d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 2082ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2083ab4382d2SGreg Kroah-Hartman .index = -1, 20849d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2085ab4382d2SGreg Kroah-Hartman }; 2086ab4382d2SGreg Kroah-Hartman 20879d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2088913c6c0eSLucas Stach 2089913c6c0eSLucas Stach #ifdef CONFIG_OF 20909d1a50a2SUwe Kleine-König static void imx_uart_console_early_putchar(struct uart_port *port, int ch) 2091913c6c0eSLucas Stach { 209227c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 209327c84426SUwe Kleine-König 209427c84426SUwe Kleine-König while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2095913c6c0eSLucas Stach cpu_relax(); 2096913c6c0eSLucas Stach 209727c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 2098913c6c0eSLucas Stach } 2099913c6c0eSLucas Stach 21009d1a50a2SUwe Kleine-König static void imx_uart_console_early_write(struct console *con, const char *s, 2101913c6c0eSLucas Stach unsigned count) 2102913c6c0eSLucas Stach { 2103913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 2104913c6c0eSLucas Stach 21059d1a50a2SUwe Kleine-König uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar); 2106913c6c0eSLucas Stach } 2107913c6c0eSLucas Stach 2108913c6c0eSLucas Stach static int __init 2109913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2110913c6c0eSLucas Stach { 2111913c6c0eSLucas Stach if (!dev->port.membase) 2112913c6c0eSLucas Stach return -ENODEV; 2113913c6c0eSLucas Stach 21149d1a50a2SUwe Kleine-König dev->con->write = imx_uart_console_early_write; 2115913c6c0eSLucas Stach 2116913c6c0eSLucas Stach return 0; 2117913c6c0eSLucas Stach } 2118913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2119913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2120913c6c0eSLucas Stach #endif 2121913c6c0eSLucas Stach 2122ab4382d2SGreg Kroah-Hartman #else 2123ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2124ab4382d2SGreg Kroah-Hartman #endif 2125ab4382d2SGreg Kroah-Hartman 21269d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2127ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2128ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2129ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2130ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2131ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21329d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2133ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2134ab4382d2SGreg Kroah-Hartman }; 2135ab4382d2SGreg Kroah-Hartman 213622698aa2SShawn Guo #ifdef CONFIG_OF 213720bb8095SUwe Kleine-König /* 213820bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 213920bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 214020bb8095SUwe Kleine-König */ 21419d1a50a2SUwe Kleine-König static int imx_uart_probe_dt(struct imx_port *sport, 214222698aa2SShawn Guo struct platform_device *pdev) 214322698aa2SShawn Guo { 214422698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2145ff05967aSShawn Guo int ret; 214622698aa2SShawn Guo 21475f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 21485f8b9043SLABBE Corentin if (!sport->devdata) 214920bb8095SUwe Kleine-König /* no device tree device */ 215020bb8095SUwe Kleine-König return 1; 215122698aa2SShawn Guo 2152ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2153ff05967aSShawn Guo if (ret < 0) { 2154ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2155a197a191SUwe Kleine-König return ret; 2156ff05967aSShawn Guo } 2157ff05967aSShawn Guo sport->port.line = ret; 215822698aa2SShawn Guo 21591006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 21601006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 216122698aa2SShawn Guo sport->have_rtscts = 1; 216222698aa2SShawn Guo 216320ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 216420ff2fe6SHuang Shijie sport->dte_mode = 1; 216520ff2fe6SHuang Shijie 21667b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 21677b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 21687b7e8e8eSFabio Estevam 216922698aa2SShawn Guo return 0; 217022698aa2SShawn Guo } 217122698aa2SShawn Guo #else 21729d1a50a2SUwe Kleine-König static inline int imx_uart_probe_dt(struct imx_port *sport, 217322698aa2SShawn Guo struct platform_device *pdev) 217422698aa2SShawn Guo { 217520bb8095SUwe Kleine-König return 1; 217622698aa2SShawn Guo } 217722698aa2SShawn Guo #endif 217822698aa2SShawn Guo 21799d1a50a2SUwe Kleine-König static void imx_uart_probe_pdata(struct imx_port *sport, 218022698aa2SShawn Guo struct platform_device *pdev) 218122698aa2SShawn Guo { 2182574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 218322698aa2SShawn Guo 218422698aa2SShawn Guo sport->port.line = pdev->id; 218522698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 218622698aa2SShawn Guo 218722698aa2SShawn Guo if (!pdata) 218822698aa2SShawn Guo return; 218922698aa2SShawn Guo 219022698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 219122698aa2SShawn Guo sport->have_rtscts = 1; 219222698aa2SShawn Guo } 219322698aa2SShawn Guo 21949d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2195ab4382d2SGreg Kroah-Hartman { 2196ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2197ab4382d2SGreg Kroah-Hartman void __iomem *base; 21984444dcf1SUwe Kleine-König int ret = 0; 21994444dcf1SUwe Kleine-König u32 ucr1; 2200ab4382d2SGreg Kroah-Hartman struct resource *res; 2201842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2202ab4382d2SGreg Kroah-Hartman 220342d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2204ab4382d2SGreg Kroah-Hartman if (!sport) 2205ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2206ab4382d2SGreg Kroah-Hartman 22079d1a50a2SUwe Kleine-König ret = imx_uart_probe_dt(sport, pdev); 220820bb8095SUwe Kleine-König if (ret > 0) 22099d1a50a2SUwe Kleine-König imx_uart_probe_pdata(sport, pdev); 221020bb8095SUwe Kleine-König else if (ret < 0) 221142d34191SSachin Kamat return ret; 221222698aa2SShawn Guo 22139d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 221456734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 221556734448SGeert Uytterhoeven sport->port.line); 221656734448SGeert Uytterhoeven return -EINVAL; 221756734448SGeert Uytterhoeven } 221856734448SGeert Uytterhoeven 2219ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2220da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2221da82f997SAlexander Shiyan if (IS_ERR(base)) 2222da82f997SAlexander Shiyan return PTR_ERR(base); 2223ab4382d2SGreg Kroah-Hartman 2224842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2225842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2226842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2227842633bdSUwe Kleine-König 2228ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2229ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2230ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2231ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2232ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2233842633bdSUwe Kleine-König sport->port.irq = rxirq; 2234ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 22359d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 22369d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 2237ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 22389d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2239ab4382d2SGreg Kroah-Hartman 224058362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 224158362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 224258362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 224358362d5bSUwe Kleine-König 22443a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 22453a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 22463a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2247833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 224842d34191SSachin Kamat return ret; 2249ab4382d2SGreg Kroah-Hartman } 2250ab4382d2SGreg Kroah-Hartman 22513a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 22523a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 22533a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2254833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 225542d34191SSachin Kamat return ret; 22563a9465faSSascha Hauer } 22573a9465faSSascha Hauer 22583a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2259ab4382d2SGreg Kroah-Hartman 22608a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 22618a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 22621e512d45SUwe Kleine-König if (ret) { 22631e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 22648a61f0c7SFabio Estevam return ret; 22651e512d45SUwe Kleine-König } 22668a61f0c7SFabio Estevam 22673a0ab62fSUwe Kleine-König /* initialize shadow register values */ 22683a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 22693a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 22703a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 22713a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 22723a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 22733a0ab62fSUwe Kleine-König 2274743f93f8SLukas Wunner uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2275743f93f8SLukas Wunner 2276b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 22775d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2278b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2279b8f3bff0SLukas Wunner 22806d215f83SStefan Agner /* 22816d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 22826d215f83SStefan Agner * signal cannot be set low during transmission in case the 22836d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 22846d215f83SStefan Agner */ 22856d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 22866d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 22876d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 22886d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 22896d215f83SStefan Agner dev_err(&pdev->dev, 22906d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 22916d215f83SStefan Agner 22929d1a50a2SUwe Kleine-König imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2293b8f3bff0SLukas Wunner 22948a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 22954444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 22964444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 2297c514a6f8SSergey Organov UCR1_TRDYEN | UCR1_RTSDEN); 22984444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 22998a61f0c7SFabio Estevam 23009d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2301e61c38d8SUwe Kleine-König /* 2302e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2303e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2304e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2305e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2306e61c38d8SUwe Kleine-König */ 23074444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23084444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 23094444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2310e61c38d8SUwe Kleine-König 2311e61c38d8SUwe Kleine-König /* 2312e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2313e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2314e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2315e61c38d8SUwe Kleine-König */ 231627c84426SUwe Kleine-König imx_uart_writel(sport, 231727c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 231827c84426SUwe Kleine-König UCR3); 2319e61c38d8SUwe Kleine-König 2320e61c38d8SUwe Kleine-König } else { 23214444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 23224444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23234444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 23244444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 23256df765dcSUwe Kleine-König 23269d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 23276df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 232827c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2329e61c38d8SUwe Kleine-König } 2330e61c38d8SUwe Kleine-König 23318a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 23328a61f0c7SFabio Estevam 2333c0d1c6b0SFabio Estevam /* 2334c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2335c0d1c6b0SFabio Estevam * chips only have one interrupt. 2336c0d1c6b0SFabio Estevam */ 2337842633bdSUwe Kleine-König if (txirq > 0) { 23389d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2339c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23401e512d45SUwe Kleine-König if (ret) { 23411e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 23421e512d45SUwe Kleine-König ret); 2343c0d1c6b0SFabio Estevam return ret; 23441e512d45SUwe Kleine-König } 2345c0d1c6b0SFabio Estevam 23469d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2347c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23481e512d45SUwe Kleine-König if (ret) { 23491e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 23501e512d45SUwe Kleine-König ret); 2351c0d1c6b0SFabio Estevam return ret; 23521e512d45SUwe Kleine-König } 23537e620984SUwe Kleine-König 23547e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 23557e620984SUwe Kleine-König dev_name(&pdev->dev), sport); 23567e620984SUwe Kleine-König if (ret) { 23577e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n", 23587e620984SUwe Kleine-König ret); 23597e620984SUwe Kleine-König return ret; 23607e620984SUwe Kleine-König } 2361c0d1c6b0SFabio Estevam } else { 23629d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2363c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23641e512d45SUwe Kleine-König if (ret) { 23651e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2366c0d1c6b0SFabio Estevam return ret; 2367c0d1c6b0SFabio Estevam } 23681e512d45SUwe Kleine-König } 2369c0d1c6b0SFabio Estevam 23709d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2371ab4382d2SGreg Kroah-Hartman 23720a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2373ab4382d2SGreg Kroah-Hartman 23749d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2375ab4382d2SGreg Kroah-Hartman } 2376ab4382d2SGreg Kroah-Hartman 23779d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2378ab4382d2SGreg Kroah-Hartman { 2379ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2380ab4382d2SGreg Kroah-Hartman 23819d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2382ab4382d2SGreg Kroah-Hartman } 2383ab4382d2SGreg Kroah-Hartman 23849d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2385c868cbb7SEduardo Valentin { 238607b5e16eSAnson Huang unsigned long flags; 238707b5e16eSAnson Huang 238807b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 238907b5e16eSAnson Huang if (!sport->context_saved) { 239007b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2391c868cbb7SEduardo Valentin return; 239207b5e16eSAnson Huang } 2393c868cbb7SEduardo Valentin 239427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 239527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 239627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 239727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 239827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 239927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 240027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 240127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 240227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 240327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2404c868cbb7SEduardo Valentin sport->context_saved = false; 240507b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2406c868cbb7SEduardo Valentin } 2407c868cbb7SEduardo Valentin 24089d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2409c868cbb7SEduardo Valentin { 241007b5e16eSAnson Huang unsigned long flags; 241107b5e16eSAnson Huang 2412c868cbb7SEduardo Valentin /* Save necessary regs */ 241307b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 241427c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 241527c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 241627c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 241727c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 241827c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 241927c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 242027c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 242127c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 242227c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 242327c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2424c868cbb7SEduardo Valentin sport->context_saved = true; 242507b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2426c868cbb7SEduardo Valentin } 2427c868cbb7SEduardo Valentin 24289d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2429189550b8SEduardo Valentin { 24304444dcf1SUwe Kleine-König u32 ucr3; 2431189550b8SEduardo Valentin 24324444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 243309df0b34SMartin Kaiser if (on) { 243427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 24354444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 24364444dcf1SUwe Kleine-König } else { 24374444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 243809df0b34SMartin Kaiser } 24394444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2440bc85734bSEduardo Valentin 244138b1f0fbSFabio Estevam if (sport->have_rtscts) { 24424444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2443bc85734bSEduardo Valentin if (on) 24444444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2445bc85734bSEduardo Valentin else 24464444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 24474444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2448189550b8SEduardo Valentin } 244938b1f0fbSFabio Estevam } 2450189550b8SEduardo Valentin 24519d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 245290bb6bd3SShenwei Wang { 2453a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 245490bb6bd3SShenwei Wang 24559d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 245690bb6bd3SShenwei Wang 245790bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 245890bb6bd3SShenwei Wang 2459fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev); 2460fcfed1beSAnson Huang 246190bb6bd3SShenwei Wang return 0; 246290bb6bd3SShenwei Wang } 246390bb6bd3SShenwei Wang 24649d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 246590bb6bd3SShenwei Wang { 2466a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 246790bb6bd3SShenwei Wang int ret; 246890bb6bd3SShenwei Wang 2469fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev); 2470fcfed1beSAnson Huang 247190bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 247290bb6bd3SShenwei Wang if (ret) 247390bb6bd3SShenwei Wang return ret; 247490bb6bd3SShenwei Wang 24759d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 247690bb6bd3SShenwei Wang 247790bb6bd3SShenwei Wang return 0; 247890bb6bd3SShenwei Wang } 247990bb6bd3SShenwei Wang 24809d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 248190bb6bd3SShenwei Wang { 2482a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 248309df0b34SMartin Kaiser int ret; 248490bb6bd3SShenwei Wang 24859d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 248681b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 248790bb6bd3SShenwei Wang 248809df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 248909df0b34SMartin Kaiser if (ret) 249009df0b34SMartin Kaiser return ret; 249109df0b34SMartin Kaiser 249209df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 24939d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 249409df0b34SMartin Kaiser 249509df0b34SMartin Kaiser return 0; 249690bb6bd3SShenwei Wang } 249790bb6bd3SShenwei Wang 24989d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 249990bb6bd3SShenwei Wang { 2500a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 250190bb6bd3SShenwei Wang 250290bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 25039d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 250490bb6bd3SShenwei Wang 25059d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 250681b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 250790bb6bd3SShenwei Wang 250809df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 250929add68dSMartin Fuzzey 251090bb6bd3SShenwei Wang return 0; 251190bb6bd3SShenwei Wang } 251290bb6bd3SShenwei Wang 25139d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 251494be6d74SPhilipp Zabel { 2515a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 251694be6d74SPhilipp Zabel 25179d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 251894be6d74SPhilipp Zabel 251909df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 252094be6d74SPhilipp Zabel } 252194be6d74SPhilipp Zabel 25229d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 252394be6d74SPhilipp Zabel { 2524a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 252594be6d74SPhilipp Zabel 25269d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 252794be6d74SPhilipp Zabel 252809df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 252994be6d74SPhilipp Zabel 253094be6d74SPhilipp Zabel return 0; 253194be6d74SPhilipp Zabel } 253294be6d74SPhilipp Zabel 25339d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 25349d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 25359d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 25369d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 25379d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 25389d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 25399d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 25409d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 25419d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 25429d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 254390bb6bd3SShenwei Wang }; 254490bb6bd3SShenwei Wang 25459d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 25469d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 25479d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2548ab4382d2SGreg Kroah-Hartman 2549fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2550ab4382d2SGreg Kroah-Hartman .driver = { 2551ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 255222698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 25539d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2554ab4382d2SGreg Kroah-Hartman }, 2555ab4382d2SGreg Kroah-Hartman }; 2556ab4382d2SGreg Kroah-Hartman 25579d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2558ab4382d2SGreg Kroah-Hartman { 25599d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2560ab4382d2SGreg Kroah-Hartman 2561ab4382d2SGreg Kroah-Hartman if (ret) 2562ab4382d2SGreg Kroah-Hartman return ret; 2563ab4382d2SGreg Kroah-Hartman 25649d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2565ab4382d2SGreg Kroah-Hartman if (ret != 0) 25669d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2567ab4382d2SGreg Kroah-Hartman 2568f227824eSUwe Kleine-König return ret; 2569ab4382d2SGreg Kroah-Hartman } 2570ab4382d2SGreg Kroah-Hartman 25719d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2572ab4382d2SGreg Kroah-Hartman { 25739d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 25749d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2575ab4382d2SGreg Kroah-Hartman } 2576ab4382d2SGreg Kroah-Hartman 25779d1a50a2SUwe Kleine-König module_init(imx_uart_init); 25789d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2579ab4382d2SGreg Kroah-Hartman 2580ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2581ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2582ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2583ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2584