1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 13ab4382d2SGreg Kroah-Hartman #endif 14ab4382d2SGreg Kroah-Hartman 15ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 23ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 24ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2922698aa2SShawn Guo #include <linux/of.h> 3022698aa2SShawn Guo #include <linux/of_device.h> 31e32a9f8fSSachin Kamat #include <linux/io.h> 32b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 3582906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 36b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 37ab4382d2SGreg Kroah-Hartman 3858362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3958362d5bSUwe Kleine-König 40ab4382d2SGreg Kroah-Hartman /* Register definitions */ 41ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 42ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 43ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 44ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 45ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 46ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 47ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 48ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 49ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 50ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 51ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 52ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 53ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 54ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 55fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 56fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 57fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 58ab4382d2SGreg Kroah-Hartman 59ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6055d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 61ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 62ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 63ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 64ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 65ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 66ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6726c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6825985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 69ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 71ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 72b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 77ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 80fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 81b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9401f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 101ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 104b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 105ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10827e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 109fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 115ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 118b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1257be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 126ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 127ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 128ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 129ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 130ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 131ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 133ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 134ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13686a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13727e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 138ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 142ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 143ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14590ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14690ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14990ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 150ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 151ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 152ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 153ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 154ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 155ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 156ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 157ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 158ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 159ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 160ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 161ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 162ab4382d2SGreg Kroah-Hartman 163ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 164ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 165ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 166ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 167ab4382d2SGreg Kroah-Hartman 168ab4382d2SGreg Kroah-Hartman /* 169ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 170ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 171ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 172ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 173ab4382d2SGreg Kroah-Hartman */ 174ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 175ab4382d2SGreg Kroah-Hartman 176ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 177ab4382d2SGreg Kroah-Hartman 178ab4382d2SGreg Kroah-Hartman #define UART_NR 8 179ab4382d2SGreg Kroah-Hartman 180f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 181fe6b540aSShawn Guo enum imx_uart_type { 182fe6b540aSShawn Guo IMX1_UART, 183fe6b540aSShawn Guo IMX21_UART, 1841c06bde6SMartyn Welch IMX53_UART, 185a496e628SHuang Shijie IMX6Q_UART, 186fe6b540aSShawn Guo }; 187fe6b540aSShawn Guo 188fe6b540aSShawn Guo /* device type dependent stuff */ 189fe6b540aSShawn Guo struct imx_uart_data { 190fe6b540aSShawn Guo unsigned uts_reg; 191fe6b540aSShawn Guo enum imx_uart_type devtype; 192fe6b540aSShawn Guo }; 193fe6b540aSShawn Guo 194ab4382d2SGreg Kroah-Hartman struct imx_port { 195ab4382d2SGreg Kroah-Hartman struct uart_port port; 196ab4382d2SGreg Kroah-Hartman struct timer_list timer; 197ab4382d2SGreg Kroah-Hartman unsigned int old_status; 198ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 1997b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20020ff2fe6SHuang Shijie unsigned int dte_mode:1; 2013a9465faSSascha Hauer struct clk *clk_ipg; 2023a9465faSSascha Hauer struct clk *clk_per; 2037d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 204b4cdc8f6SHuang Shijie 20558362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 20658362d5bSUwe Kleine-König 207b4cdc8f6SHuang Shijie /* DMA fields */ 208b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 209b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 210b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 211b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 212b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 213b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 214b4cdc8f6SHuang Shijie void *rx_buf; 2159d297239SNandor Han struct circ_buf rx_ring; 2169d297239SNandor Han unsigned int rx_periods; 2179d297239SNandor Han dma_cookie_t rx_cookie; 2187cb92fd2SHuang Shijie unsigned int tx_bytes; 219b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 22090bb6bd3SShenwei Wang unsigned int saved_reg[10]; 221c868cbb7SEduardo Valentin bool context_saved; 222ab4382d2SGreg Kroah-Hartman }; 223ab4382d2SGreg Kroah-Hartman 2240ad5a814SDirk Behme struct imx_port_ucrs { 2250ad5a814SDirk Behme unsigned int ucr1; 2260ad5a814SDirk Behme unsigned int ucr2; 2270ad5a814SDirk Behme unsigned int ucr3; 2280ad5a814SDirk Behme }; 2290ad5a814SDirk Behme 230fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 231fe6b540aSShawn Guo [IMX1_UART] = { 232fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 233fe6b540aSShawn Guo .devtype = IMX1_UART, 234fe6b540aSShawn Guo }, 235fe6b540aSShawn Guo [IMX21_UART] = { 236fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 237fe6b540aSShawn Guo .devtype = IMX21_UART, 238fe6b540aSShawn Guo }, 2391c06bde6SMartyn Welch [IMX53_UART] = { 2401c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2411c06bde6SMartyn Welch .devtype = IMX53_UART, 2421c06bde6SMartyn Welch }, 243a496e628SHuang Shijie [IMX6Q_UART] = { 244a496e628SHuang Shijie .uts_reg = IMX21_UTS, 245a496e628SHuang Shijie .devtype = IMX6Q_UART, 246a496e628SHuang Shijie }, 247fe6b540aSShawn Guo }; 248fe6b540aSShawn Guo 24931ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 250fe6b540aSShawn Guo { 251fe6b540aSShawn Guo .name = "imx1-uart", 252fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 253fe6b540aSShawn Guo }, { 254fe6b540aSShawn Guo .name = "imx21-uart", 255fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 256fe6b540aSShawn Guo }, { 2571c06bde6SMartyn Welch .name = "imx53-uart", 2581c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2591c06bde6SMartyn Welch }, { 260a496e628SHuang Shijie .name = "imx6q-uart", 261a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 262a496e628SHuang Shijie }, { 263fe6b540aSShawn Guo /* sentinel */ 264fe6b540aSShawn Guo } 265fe6b540aSShawn Guo }; 266fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 267fe6b540aSShawn Guo 268ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 269a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2701c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27122698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27222698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27322698aa2SShawn Guo { /* sentinel */ } 27422698aa2SShawn Guo }; 27522698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27622698aa2SShawn Guo 277fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 278fe6b540aSShawn Guo { 279fe6b540aSShawn Guo return sport->devdata->uts_reg; 280fe6b540aSShawn Guo } 281fe6b540aSShawn Guo 282fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 283fe6b540aSShawn Guo { 284fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 285fe6b540aSShawn Guo } 286fe6b540aSShawn Guo 287fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 288fe6b540aSShawn Guo { 289fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 290fe6b540aSShawn Guo } 291fe6b540aSShawn Guo 2921c06bde6SMartyn Welch static inline int is_imx53_uart(struct imx_port *sport) 2931c06bde6SMartyn Welch { 2941c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 2951c06bde6SMartyn Welch } 2961c06bde6SMartyn Welch 297a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 298a496e628SHuang Shijie { 299a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 300a496e628SHuang Shijie } 301ab4382d2SGreg Kroah-Hartman /* 30244a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 30344a75411Sfabio.estevam@freescale.com */ 30493d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 30544a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 30644a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30744a75411Sfabio.estevam@freescale.com { 30844a75411Sfabio.estevam@freescale.com /* save control registers */ 30944a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 31044a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 31144a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 31244a75411Sfabio.estevam@freescale.com } 31344a75411Sfabio.estevam@freescale.com 31444a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 31544a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 31644a75411Sfabio.estevam@freescale.com { 31744a75411Sfabio.estevam@freescale.com /* restore control registers */ 31844a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 31944a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 32044a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 32144a75411Sfabio.estevam@freescale.com } 322e8bfa760SFabio Estevam #endif 32344a75411Sfabio.estevam@freescale.com 32458362d5bSUwe Kleine-König static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2) 32558362d5bSUwe Kleine-König { 326bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 32758362d5bSUwe Kleine-König 328a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 329a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 33058362d5bSUwe Kleine-König } 33158362d5bSUwe Kleine-König 33258362d5bSUwe Kleine-König static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2) 33358362d5bSUwe Kleine-König { 334bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 335bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 33658362d5bSUwe Kleine-König 337a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 338a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 33958362d5bSUwe Kleine-König } 34058362d5bSUwe Kleine-König 34158362d5bSUwe Kleine-König static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2) 34258362d5bSUwe Kleine-König { 34358362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 34458362d5bSUwe Kleine-König } 34558362d5bSUwe Kleine-König 34644a75411Sfabio.estevam@freescale.com /* 347ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 348ab4382d2SGreg Kroah-Hartman */ 349ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 350ab4382d2SGreg Kroah-Hartman { 351ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 352ab4382d2SGreg Kroah-Hartman unsigned long temp; 353ab4382d2SGreg Kroah-Hartman 3549ce4f8f3SGreg Kroah-Hartman /* 3559ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 3569ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 3579ce4f8f3SGreg Kroah-Hartman */ 3589ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 3599ce4f8f3SGreg Kroah-Hartman return; 360b4cdc8f6SHuang Shijie 36117b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR1); 36217b8f2a3SUwe Kleine-König writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); 36317b8f2a3SUwe Kleine-König 36417b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 36517b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 36617b8f2a3SUwe Kleine-König readl(port->membase + USR2) & USR2_TXDC) { 36717b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 36817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 36958362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 3701a613626SFabio Estevam else 3711a613626SFabio Estevam imx_port_rts_inactive(sport, &temp); 3727d1cadcaSBaruch Siach temp |= UCR2_RXEN; 37317b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 37417b8f2a3SUwe Kleine-König 37517b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 37617b8f2a3SUwe Kleine-König temp &= ~UCR4_TCEN; 37717b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 37817b8f2a3SUwe Kleine-König } 379ab4382d2SGreg Kroah-Hartman } 380ab4382d2SGreg Kroah-Hartman 381ab4382d2SGreg Kroah-Hartman /* 382ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 383ab4382d2SGreg Kroah-Hartman */ 384ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 385ab4382d2SGreg Kroah-Hartman { 386ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 387ab4382d2SGreg Kroah-Hartman unsigned long temp; 388ab4382d2SGreg Kroah-Hartman 38945564a66SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) { 39045564a66SHuang Shijie if (sport->port.suspended) { 39145564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 39245564a66SHuang Shijie sport->dma_is_rxing = 0; 39345564a66SHuang Shijie } else { 3949ce4f8f3SGreg Kroah-Hartman return; 39545564a66SHuang Shijie } 39645564a66SHuang Shijie } 397b4cdc8f6SHuang Shijie 398ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 399ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 40085878399SHuang Shijie 40185878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 40285878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 40385878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 404ab4382d2SGreg Kroah-Hartman } 405ab4382d2SGreg Kroah-Hartman 406ab4382d2SGreg Kroah-Hartman /* 407ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 408ab4382d2SGreg Kroah-Hartman */ 409ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 410ab4382d2SGreg Kroah-Hartman { 411ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 412ab4382d2SGreg Kroah-Hartman 413ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 41458362d5bSUwe Kleine-König 41558362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 416ab4382d2SGreg Kroah-Hartman } 417ab4382d2SGreg Kroah-Hartman 41891a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 419ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 420ab4382d2SGreg Kroah-Hartman { 421ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 42291a1a909SJiada Wang unsigned long temp; 423ab4382d2SGreg Kroah-Hartman 4245e42e9a3SPeter Hurley if (sport->port.x_char) { 4255e42e9a3SPeter Hurley /* Send next char */ 4265e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4277e2fb5aaSJiada Wang sport->port.icount.tx++; 4287e2fb5aaSJiada Wang sport->port.x_char = 0; 4295e42e9a3SPeter Hurley return; 4305e42e9a3SPeter Hurley } 4315e42e9a3SPeter Hurley 4325e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4335e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4345e42e9a3SPeter Hurley return; 4355e42e9a3SPeter Hurley } 4365e42e9a3SPeter Hurley 43791a1a909SJiada Wang if (sport->dma_is_enabled) { 43891a1a909SJiada Wang /* 43991a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 44091a1a909SJiada Wang * and the TX IRQ is disabled. 44191a1a909SJiada Wang **/ 44291a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 44391a1a909SJiada Wang temp &= ~UCR1_TXMPTYEN; 44491a1a909SJiada Wang if (sport->dma_is_txing) { 44591a1a909SJiada Wang temp |= UCR1_TDMAEN; 44691a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 44791a1a909SJiada Wang } else { 44891a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 44991a1a909SJiada Wang imx_dma_tx(sport); 45091a1a909SJiada Wang } 45191a1a909SJiada Wang } 45291a1a909SJiada Wang 4535aabd3b0SIan Jamison if (sport->dma_is_txing) 4545aabd3b0SIan Jamison return; 4555aabd3b0SIan Jamison 4565aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 4575e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 458ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 459ab4382d2SGreg Kroah-Hartman * out the port here */ 460ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 461ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 462ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 463ab4382d2SGreg Kroah-Hartman } 464ab4382d2SGreg Kroah-Hartman 465ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 466ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 467ab4382d2SGreg Kroah-Hartman 468ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 469ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 470ab4382d2SGreg Kroah-Hartman } 471ab4382d2SGreg Kroah-Hartman 472b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 473b4cdc8f6SHuang Shijie { 474b4cdc8f6SHuang Shijie struct imx_port *sport = data; 475b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 476b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 477b4cdc8f6SHuang Shijie unsigned long flags; 478a2c718ceSDirk Behme unsigned long temp; 479b4cdc8f6SHuang Shijie 48042f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 48142f752b3SDirk Behme 482b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 483b4cdc8f6SHuang Shijie 484a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 485a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 486a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 487a2c718ceSDirk Behme 48842f752b3SDirk Behme /* update the stat */ 48942f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 49042f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 49142f752b3SDirk Behme 49242f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 49342f752b3SDirk Behme 494b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 495b4cdc8f6SHuang Shijie 496d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 497b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 4989ce4f8f3SGreg Kroah-Hartman 4990bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5000bbc9b81SJiada Wang imx_dma_tx(sport); 50164432a85SUwe Kleine-König 5020bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 503b4cdc8f6SHuang Shijie } 504b4cdc8f6SHuang Shijie 5057cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 506b4cdc8f6SHuang Shijie { 507b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 508b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 509b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 510b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 511b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 512a2c718ceSDirk Behme unsigned long temp; 513b4cdc8f6SHuang Shijie int ret; 514b4cdc8f6SHuang Shijie 51542f752b3SDirk Behme if (sport->dma_is_txing) 516b4cdc8f6SHuang Shijie return; 517b4cdc8f6SHuang Shijie 518b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 519b4cdc8f6SHuang Shijie 5207942f857SDirk Behme if (xmit->tail < xmit->head) { 5217942f857SDirk Behme sport->dma_tx_nents = 1; 5227942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5237942f857SDirk Behme } else { 524b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 525b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 526b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 527b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 528b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 529b4cdc8f6SHuang Shijie } 530b4cdc8f6SHuang Shijie 531b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 532b4cdc8f6SHuang Shijie if (ret == 0) { 533b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 534b4cdc8f6SHuang Shijie return; 535b4cdc8f6SHuang Shijie } 536b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 537b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 538b4cdc8f6SHuang Shijie if (!desc) { 53924649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 54024649821SDirk Behme DMA_TO_DEVICE); 541b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 542b4cdc8f6SHuang Shijie return; 543b4cdc8f6SHuang Shijie } 544b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 545b4cdc8f6SHuang Shijie desc->callback_param = sport; 546b4cdc8f6SHuang Shijie 547b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 548b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 549a2c718ceSDirk Behme 550a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 551a2c718ceSDirk Behme temp |= UCR1_TDMAEN; 552a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 553a2c718ceSDirk Behme 554b4cdc8f6SHuang Shijie /* fire it */ 555b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 556b4cdc8f6SHuang Shijie dmaengine_submit(desc); 557b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 558b4cdc8f6SHuang Shijie return; 559b4cdc8f6SHuang Shijie } 560b4cdc8f6SHuang Shijie 561ab4382d2SGreg Kroah-Hartman /* 562ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 563ab4382d2SGreg Kroah-Hartman */ 564ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 565ab4382d2SGreg Kroah-Hartman { 566ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 567ab4382d2SGreg Kroah-Hartman unsigned long temp; 568ab4382d2SGreg Kroah-Hartman 56917b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 57017b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 57117b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 57258362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 5731a613626SFabio Estevam else 5741a613626SFabio Estevam imx_port_rts_inactive(sport, &temp); 5757d1cadcaSBaruch Siach if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 5767d1cadcaSBaruch Siach temp &= ~UCR2_RXEN; 57717b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 57817b8f2a3SUwe Kleine-König 57958362d5bSUwe Kleine-König /* enable transmitter and shifter empty irq */ 58017b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 58117b8f2a3SUwe Kleine-König temp |= UCR4_TCEN; 58217b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 58317b8f2a3SUwe Kleine-König } 58417b8f2a3SUwe Kleine-König 585b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 586ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 587ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 588b4cdc8f6SHuang Shijie } 589ab4382d2SGreg Kroah-Hartman 590b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 59191a1a909SJiada Wang if (sport->port.x_char) { 59291a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 59391a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 59491a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 59591a1a909SJiada Wang temp &= ~UCR1_TDMAEN; 59691a1a909SJiada Wang temp |= UCR1_TXMPTYEN; 59791a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 59891a1a909SJiada Wang return; 59991a1a909SJiada Wang } 60091a1a909SJiada Wang 6015e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6025e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6037cb92fd2SHuang Shijie imx_dma_tx(sport); 604b4cdc8f6SHuang Shijie return; 605b4cdc8f6SHuang Shijie } 606ab4382d2SGreg Kroah-Hartman } 607ab4382d2SGreg Kroah-Hartman 608ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 609ab4382d2SGreg Kroah-Hartman { 610ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6115680e941SUwe Kleine-König unsigned int val; 612ab4382d2SGreg Kroah-Hartman unsigned long flags; 613ab4382d2SGreg Kroah-Hartman 614ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 615ab4382d2SGreg Kroah-Hartman 616ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6175680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 618ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 619ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 620ab4382d2SGreg Kroah-Hartman 621ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 622ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 623ab4382d2SGreg Kroah-Hartman } 624ab4382d2SGreg Kroah-Hartman 625ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 626ab4382d2SGreg Kroah-Hartman { 627ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 628ab4382d2SGreg Kroah-Hartman unsigned long flags; 629ab4382d2SGreg Kroah-Hartman 630ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 631ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 632ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 633ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 634ab4382d2SGreg Kroah-Hartman } 635ab4382d2SGreg Kroah-Hartman 636ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 637ab4382d2SGreg Kroah-Hartman { 638ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 639ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 64092a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 641ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 642ab4382d2SGreg Kroah-Hartman 643ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 644ab4382d2SGreg Kroah-Hartman 645ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 646ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 647ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 648ab4382d2SGreg Kroah-Hartman 649ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 650ab4382d2SGreg Kroah-Hartman 651ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 652ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 653ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 654ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 655ab4382d2SGreg Kroah-Hartman continue; 656ab4382d2SGreg Kroah-Hartman } 657ab4382d2SGreg Kroah-Hartman 658ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 659ab4382d2SGreg Kroah-Hartman continue; 660ab4382d2SGreg Kroah-Hartman 661019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 662019dc9eaSHui Wang if (rx & URXD_BRK) 663019dc9eaSHui Wang sport->port.icount.brk++; 664019dc9eaSHui Wang else if (rx & URXD_PRERR) 665ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 666ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 667ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 668ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 669ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 670ab4382d2SGreg Kroah-Hartman 671ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 672ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 673ab4382d2SGreg Kroah-Hartman goto out; 674ab4382d2SGreg Kroah-Hartman continue; 675ab4382d2SGreg Kroah-Hartman } 676ab4382d2SGreg Kroah-Hartman 6778d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 678ab4382d2SGreg Kroah-Hartman 679019dc9eaSHui Wang if (rx & URXD_BRK) 680019dc9eaSHui Wang flg = TTY_BREAK; 681019dc9eaSHui Wang else if (rx & URXD_PRERR) 682ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 683ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 684ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 685ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 686ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 687ab4382d2SGreg Kroah-Hartman 688ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 689ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 690ab4382d2SGreg Kroah-Hartman #endif 691ab4382d2SGreg Kroah-Hartman } 692ab4382d2SGreg Kroah-Hartman 69355d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 69455d8693aSJiada Wang goto out; 69555d8693aSJiada Wang 6969b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 6979b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 698ab4382d2SGreg Kroah-Hartman } 699ab4382d2SGreg Kroah-Hartman 700ab4382d2SGreg Kroah-Hartman out: 701ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7022e124b4aSJiri Slaby tty_flip_buffer_push(port); 703ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 704ab4382d2SGreg Kroah-Hartman } 705ab4382d2SGreg Kroah-Hartman 70618a42088SPeter Senna Tschudin static void clear_rx_errors(struct imx_port *sport); 707b4cdc8f6SHuang Shijie 70866f95884SUwe Kleine-König /* 70966f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 71066f95884SUwe Kleine-König */ 71166f95884SUwe Kleine-König static unsigned int imx_get_hwmctrl(struct imx_port *sport) 71266f95884SUwe Kleine-König { 71366f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 71466f95884SUwe Kleine-König unsigned usr1 = readl(sport->port.membase + USR1); 7154b75f800SSascha Hauer unsigned usr2 = readl(sport->port.membase + USR2); 71666f95884SUwe Kleine-König 71766f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 71866f95884SUwe Kleine-König tmp |= TIOCM_CTS; 71966f95884SUwe Kleine-König 72066f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 7214b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 72266f95884SUwe Kleine-König tmp |= TIOCM_CAR; 72366f95884SUwe Kleine-König 72466f95884SUwe Kleine-König if (sport->dte_mode) 72566f95884SUwe Kleine-König if (!(readl(sport->port.membase + USR2) & USR2_RIIN)) 72666f95884SUwe Kleine-König tmp |= TIOCM_RI; 72766f95884SUwe Kleine-König 72866f95884SUwe Kleine-König return tmp; 72966f95884SUwe Kleine-König } 73066f95884SUwe Kleine-König 73166f95884SUwe Kleine-König /* 73266f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 73366f95884SUwe Kleine-König */ 73466f95884SUwe Kleine-König static void imx_mctrl_check(struct imx_port *sport) 73566f95884SUwe Kleine-König { 73666f95884SUwe Kleine-König unsigned int status, changed; 73766f95884SUwe Kleine-König 73866f95884SUwe Kleine-König status = imx_get_hwmctrl(sport); 73966f95884SUwe Kleine-König changed = status ^ sport->old_status; 74066f95884SUwe Kleine-König 74166f95884SUwe Kleine-König if (changed == 0) 74266f95884SUwe Kleine-König return; 74366f95884SUwe Kleine-König 74466f95884SUwe Kleine-König sport->old_status = status; 74566f95884SUwe Kleine-König 74666f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 74766f95884SUwe Kleine-König sport->port.icount.rng++; 74866f95884SUwe Kleine-König if (changed & TIOCM_DSR) 74966f95884SUwe Kleine-König sport->port.icount.dsr++; 75066f95884SUwe Kleine-König if (changed & TIOCM_CAR) 75166f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 75266f95884SUwe Kleine-König if (changed & TIOCM_CTS) 75366f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 75466f95884SUwe Kleine-König 75566f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 75666f95884SUwe Kleine-König } 75766f95884SUwe Kleine-König 758ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 759ab4382d2SGreg Kroah-Hartman { 760ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 761ab4382d2SGreg Kroah-Hartman unsigned int sts; 762f1f836e4SAlexander Stein unsigned int sts2; 7634d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 764ab4382d2SGreg Kroah-Hartman 765ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 76617b8f2a3SUwe Kleine-König sts2 = readl(sport->port.membase + USR2); 767ab4382d2SGreg Kroah-Hartman 7689ce99a3aSTroy Kisky if (!sport->dma_is_enabled && (sts & (USR1_RRDY | USR1_AGTIM))) { 769ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 7704d845a62SUwe Kleine-König ret = IRQ_HANDLED; 771b4cdc8f6SHuang Shijie } 772ab4382d2SGreg Kroah-Hartman 77317b8f2a3SUwe Kleine-König if ((sts & USR1_TRDY && 77417b8f2a3SUwe Kleine-König readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || 77517b8f2a3SUwe Kleine-König (sts2 & USR2_TXDC && 7764d845a62SUwe Kleine-König readl(sport->port.membase + UCR4) & UCR4_TCEN)) { 777ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 7784d845a62SUwe Kleine-König ret = IRQ_HANDLED; 7794d845a62SUwe Kleine-König } 780ab4382d2SGreg Kroah-Hartman 78127e16501SUwe Kleine-König if (sts & USR1_DTRD) { 78227e16501SUwe Kleine-König unsigned long flags; 78327e16501SUwe Kleine-König 78427e16501SUwe Kleine-König if (sts & USR1_DTRD) 78527e16501SUwe Kleine-König writel(USR1_DTRD, sport->port.membase + USR1); 78627e16501SUwe Kleine-König 78727e16501SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 78827e16501SUwe Kleine-König imx_mctrl_check(sport); 78927e16501SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 79027e16501SUwe Kleine-König 79127e16501SUwe Kleine-König ret = IRQ_HANDLED; 79227e16501SUwe Kleine-König } 79327e16501SUwe Kleine-König 7944d845a62SUwe Kleine-König if (sts & USR1_RTSD) { 795ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 7964d845a62SUwe Kleine-König ret = IRQ_HANDLED; 7974d845a62SUwe Kleine-König } 798ab4382d2SGreg Kroah-Hartman 7994d845a62SUwe Kleine-König if (sts & USR1_AWAKE) { 800db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 8014d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8024d845a62SUwe Kleine-König } 803db1a9b55SFabio Estevam 804f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 805f1f836e4SAlexander Stein sport->port.icount.overrun++; 80691555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 8074d845a62SUwe Kleine-König ret = IRQ_HANDLED; 808f1f836e4SAlexander Stein } 809f1f836e4SAlexander Stein 8104d845a62SUwe Kleine-König return ret; 811ab4382d2SGreg Kroah-Hartman } 812ab4382d2SGreg Kroah-Hartman 813ab4382d2SGreg Kroah-Hartman /* 814ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 815ab4382d2SGreg Kroah-Hartman */ 816ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 817ab4382d2SGreg Kroah-Hartman { 818ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 8191ce43e58SHuang Shijie unsigned int ret; 820ab4382d2SGreg Kroah-Hartman 8211ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 8221ce43e58SHuang Shijie 8231ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 8241ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 8251ce43e58SHuang Shijie ret = 0; 8261ce43e58SHuang Shijie 8271ce43e58SHuang Shijie return ret; 828ab4382d2SGreg Kroah-Hartman } 829ab4382d2SGreg Kroah-Hartman 83058362d5bSUwe Kleine-König static unsigned int imx_get_mctrl(struct uart_port *port) 83158362d5bSUwe Kleine-König { 83258362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 83358362d5bSUwe Kleine-König unsigned int ret = imx_get_hwmctrl(sport); 83458362d5bSUwe Kleine-König 83558362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 83658362d5bSUwe Kleine-König 83758362d5bSUwe Kleine-König return ret; 83858362d5bSUwe Kleine-König } 83958362d5bSUwe Kleine-König 840ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 841ab4382d2SGreg Kroah-Hartman { 842ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 843ab4382d2SGreg Kroah-Hartman unsigned long temp; 844ab4382d2SGreg Kroah-Hartman 84517b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 84617b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 84717b8f2a3SUwe Kleine-König temp &= ~(UCR2_CTS | UCR2_CTSC); 848ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 849bb2f861aSFugang Duan temp |= UCR2_CTS | UCR2_CTSC; 850ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 85117b8f2a3SUwe Kleine-König } 8526b471a98SHuang Shijie 85390ebc483SUwe Kleine-König temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR; 85490ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 85590ebc483SUwe Kleine-König temp |= UCR3_DSR; 85690ebc483SUwe Kleine-König writel(temp, sport->port.membase + UCR3); 85790ebc483SUwe Kleine-König 8586b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8596b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8606b471a98SHuang Shijie temp |= UTS_LOOP; 8616b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 86258362d5bSUwe Kleine-König 86358362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 864ab4382d2SGreg Kroah-Hartman } 865ab4382d2SGreg Kroah-Hartman 866ab4382d2SGreg Kroah-Hartman /* 867ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 868ab4382d2SGreg Kroah-Hartman */ 869ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 870ab4382d2SGreg Kroah-Hartman { 871ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 872ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 873ab4382d2SGreg Kroah-Hartman 874ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 875ab4382d2SGreg Kroah-Hartman 876ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 877ab4382d2SGreg Kroah-Hartman 878ab4382d2SGreg Kroah-Hartman if (break_state != 0) 879ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 880ab4382d2SGreg Kroah-Hartman 881ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 882ab4382d2SGreg Kroah-Hartman 883ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 884ab4382d2SGreg Kroah-Hartman } 885ab4382d2SGreg Kroah-Hartman 886cc568849SUwe Kleine-König /* 887cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 888cc568849SUwe Kleine-König * modem status signals. 889cc568849SUwe Kleine-König */ 890e99e88a9SKees Cook static void imx_timeout(struct timer_list *t) 891cc568849SUwe Kleine-König { 892e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 893cc568849SUwe Kleine-König unsigned long flags; 894cc568849SUwe Kleine-König 895cc568849SUwe Kleine-König if (sport->port.state) { 896cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 897cc568849SUwe Kleine-König imx_mctrl_check(sport); 898cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 899cc568849SUwe Kleine-König 900cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 901cc568849SUwe Kleine-König } 902cc568849SUwe Kleine-König } 903cc568849SUwe Kleine-König 904351ea50dSGreg Kroah-Hartman #define RX_BUF_SIZE (PAGE_SIZE) 905351ea50dSGreg Kroah-Hartman 906b4cdc8f6SHuang Shijie /* 907905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 908b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 909905c0decSLucas Stach * [2] the aging timer expires 910b4cdc8f6SHuang Shijie * 911905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 912905c0decSLucas Stach * for at least 8 byte durations. 913b4cdc8f6SHuang Shijie */ 914b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 915b4cdc8f6SHuang Shijie { 916b4cdc8f6SHuang Shijie struct imx_port *sport = data; 917b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 918b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9197cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 920b4cdc8f6SHuang Shijie struct dma_tx_state state; 9219d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 922b4cdc8f6SHuang Shijie enum dma_status status; 9239d297239SNandor Han unsigned int w_bytes = 0; 9249d297239SNandor Han unsigned int r_bytes; 9259d297239SNandor Han unsigned int bd_size; 926b4cdc8f6SHuang Shijie 927f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 928392bceedSPhilipp Zabel 9299d297239SNandor Han if (status == DMA_ERROR) { 9309d297239SNandor Han dev_err(sport->port.dev, "DMA transaction error.\n"); 93141d98b5dSNandor Han clear_rx_errors(sport); 9329d297239SNandor Han return; 9339d297239SNandor Han } 934b4cdc8f6SHuang Shijie 9359b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 936976b39cdSLucas Stach 937976b39cdSLucas Stach /* 9389d297239SNandor Han * The state-residue variable represents the empty space 9399d297239SNandor Han * relative to the entire buffer. Taking this in consideration 9409d297239SNandor Han * the head is always calculated base on the buffer total 9419d297239SNandor Han * length - DMA transaction residue. The UART script from the 9429d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 9439d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 9449d297239SNandor Han * Taking this in consideration the tail is always at the 9459d297239SNandor Han * beginning of the buffer descriptor that contains the head. 946976b39cdSLucas Stach */ 9479d297239SNandor Han 9489d297239SNandor Han /* Calculate the head */ 9499d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 9509d297239SNandor Han 9519d297239SNandor Han /* Calculate the tail. */ 9529d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 9539d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 9549d297239SNandor Han 9559d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 9569d297239SNandor Han rx_ring->head > rx_ring->tail) { 9579d297239SNandor Han 9589d297239SNandor Han /* Move data from tail to head */ 9599d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 9609d297239SNandor Han 9619d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 9629d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 9639d297239SNandor Han DMA_FROM_DEVICE); 9649d297239SNandor Han 9659d297239SNandor Han w_bytes = tty_insert_flip_string(port, 9669d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 9679d297239SNandor Han 9689d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 9699d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 9709d297239SNandor Han DMA_FROM_DEVICE); 9719d297239SNandor Han 9729d297239SNandor Han if (w_bytes != r_bytes) 9739d297239SNandor Han sport->port.icount.buf_overrun++; 9749d297239SNandor Han 9759d297239SNandor Han sport->port.icount.rx += w_bytes; 9769d297239SNandor Han } else { 9779d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 9789d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 979ee5e7c10SRobin Gong } 9809d297239SNandor Han } 9819d297239SNandor Han 9829d297239SNandor Han if (w_bytes) { 9839d297239SNandor Han tty_flip_buffer_push(port); 9849d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 9859d297239SNandor Han } 9869d297239SNandor Han } 9879d297239SNandor Han 988351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 989351ea50dSGreg Kroah-Hartman #define RX_DMA_PERIODS 4 990351ea50dSGreg Kroah-Hartman 991b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 992b4cdc8f6SHuang Shijie { 993b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 994b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 995b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 996b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 997b4cdc8f6SHuang Shijie int ret; 998b4cdc8f6SHuang Shijie 9999d297239SNandor Han sport->rx_ring.head = 0; 10009d297239SNandor Han sport->rx_ring.tail = 0; 1001351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 10029d297239SNandor Han 1003351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1004b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1005b4cdc8f6SHuang Shijie if (ret == 0) { 1006b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1007b4cdc8f6SHuang Shijie return -EINVAL; 1008b4cdc8f6SHuang Shijie } 10099d297239SNandor Han 10109d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 10119d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 10129d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 10139d297239SNandor Han 1014b4cdc8f6SHuang Shijie if (!desc) { 101524649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1016b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1017b4cdc8f6SHuang Shijie return -EINVAL; 1018b4cdc8f6SHuang Shijie } 1019b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 1020b4cdc8f6SHuang Shijie desc->callback_param = sport; 1021b4cdc8f6SHuang Shijie 1022b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 10234139fd76SRomain Perier sport->dma_is_rxing = 1; 10249d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1025b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1026b4cdc8f6SHuang Shijie return 0; 1027b4cdc8f6SHuang Shijie } 1028b4cdc8f6SHuang Shijie 102941d98b5dSNandor Han static void clear_rx_errors(struct imx_port *sport) 103041d98b5dSNandor Han { 103141d98b5dSNandor Han unsigned int status_usr1, status_usr2; 103241d98b5dSNandor Han 103341d98b5dSNandor Han status_usr1 = readl(sport->port.membase + USR1); 103441d98b5dSNandor Han status_usr2 = readl(sport->port.membase + USR2); 103541d98b5dSNandor Han 103641d98b5dSNandor Han if (status_usr2 & USR2_BRCD) { 103741d98b5dSNandor Han sport->port.icount.brk++; 103841d98b5dSNandor Han writel(USR2_BRCD, sport->port.membase + USR2); 103941d98b5dSNandor Han } else if (status_usr1 & USR1_FRAMERR) { 104041d98b5dSNandor Han sport->port.icount.frame++; 104141d98b5dSNandor Han writel(USR1_FRAMERR, sport->port.membase + USR1); 104241d98b5dSNandor Han } else if (status_usr1 & USR1_PARITYERR) { 104341d98b5dSNandor Han sport->port.icount.parity++; 104441d98b5dSNandor Han writel(USR1_PARITYERR, sport->port.membase + USR1); 104541d98b5dSNandor Han } 104641d98b5dSNandor Han 104741d98b5dSNandor Han if (status_usr2 & USR2_ORE) { 104841d98b5dSNandor Han sport->port.icount.overrun++; 104941d98b5dSNandor Han writel(USR2_ORE, sport->port.membase + USR2); 105041d98b5dSNandor Han } 105141d98b5dSNandor Han 105241d98b5dSNandor Han } 105341d98b5dSNandor Han 1054cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1055cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1056184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1057184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1058cc32382dSLucas Stach 1059cc32382dSLucas Stach static void imx_setup_ufcr(struct imx_port *sport, 1060cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1061cc32382dSLucas Stach { 1062cc32382dSLucas Stach unsigned int val; 1063cc32382dSLucas Stach 1064cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 1065cc32382dSLucas Stach val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1066cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 1067cc32382dSLucas Stach writel(val, sport->port.membase + UFCR); 1068cc32382dSLucas Stach } 1069cc32382dSLucas Stach 1070b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1071b4cdc8f6SHuang Shijie { 1072b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1073e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1074b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1075b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 10769d297239SNandor Han sport->rx_cookie = -EINVAL; 1077b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1078b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1079b4cdc8f6SHuang Shijie } 1080b4cdc8f6SHuang Shijie 1081b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1082e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1083b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1084b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1085b4cdc8f6SHuang Shijie } 1086b4cdc8f6SHuang Shijie 1087b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 1088b4cdc8f6SHuang Shijie } 1089b4cdc8f6SHuang Shijie 1090b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1091b4cdc8f6SHuang Shijie { 1092b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1093b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1094b4cdc8f6SHuang Shijie int ret; 1095b4cdc8f6SHuang Shijie 1096b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1097b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1098b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1099b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1100b4cdc8f6SHuang Shijie ret = -EINVAL; 1101b4cdc8f6SHuang Shijie goto err; 1102b4cdc8f6SHuang Shijie } 1103b4cdc8f6SHuang Shijie 1104b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1105b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1106b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1107184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1108184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1109b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1110b4cdc8f6SHuang Shijie if (ret) { 1111b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1112b4cdc8f6SHuang Shijie goto err; 1113b4cdc8f6SHuang Shijie } 1114b4cdc8f6SHuang Shijie 1115f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1116b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1117b4cdc8f6SHuang Shijie ret = -ENOMEM; 1118b4cdc8f6SHuang Shijie goto err; 1119b4cdc8f6SHuang Shijie } 11209d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1121b4cdc8f6SHuang Shijie 1122b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1123b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1124b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1125b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1126b4cdc8f6SHuang Shijie ret = -EINVAL; 1127b4cdc8f6SHuang Shijie goto err; 1128b4cdc8f6SHuang Shijie } 1129b4cdc8f6SHuang Shijie 1130b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1131b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1132b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1133184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1134b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1135b4cdc8f6SHuang Shijie if (ret) { 1136b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1137b4cdc8f6SHuang Shijie goto err; 1138b4cdc8f6SHuang Shijie } 1139b4cdc8f6SHuang Shijie 1140b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1141b4cdc8f6SHuang Shijie 1142b4cdc8f6SHuang Shijie return 0; 1143b4cdc8f6SHuang Shijie err: 1144b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1145b4cdc8f6SHuang Shijie return ret; 1146b4cdc8f6SHuang Shijie } 1147b4cdc8f6SHuang Shijie 1148b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1149b4cdc8f6SHuang Shijie { 1150b4cdc8f6SHuang Shijie unsigned long temp; 1151b4cdc8f6SHuang Shijie 1152b4cdc8f6SHuang Shijie /* set UCR1 */ 1153b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1154905c0decSLucas Stach temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN; 1155b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1156b4cdc8f6SHuang Shijie 1157184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1158184bd70bSLucas Stach 1159b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1160b4cdc8f6SHuang Shijie } 1161b4cdc8f6SHuang Shijie 1162b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1163b4cdc8f6SHuang Shijie { 1164b4cdc8f6SHuang Shijie unsigned long temp; 1165b4cdc8f6SHuang Shijie 1166b4cdc8f6SHuang Shijie /* clear UCR1 */ 1167b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1168b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1169b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1170b4cdc8f6SHuang Shijie 1171b4cdc8f6SHuang Shijie /* clear UCR2 */ 1172b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 117386a04ba6SLucas Stach temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN); 1174b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1175b4cdc8f6SHuang Shijie 1176184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1177184bd70bSLucas Stach 1178b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1179b4cdc8f6SHuang Shijie } 1180b4cdc8f6SHuang Shijie 1181ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1182ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1183ab4382d2SGreg Kroah-Hartman 1184ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1185ab4382d2SGreg Kroah-Hartman { 1186ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1187458e2c82SFabio Estevam int retval, i; 1188ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1189ab4382d2SGreg Kroah-Hartman 119028eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 119128eb4274SHuang Shijie if (retval) 1192cb0f0a5fSFabio Estevam return retval; 119328eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 11940c375501SHuang Shijie if (retval) { 11950c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1196cb0f0a5fSFabio Estevam return retval; 11970c375501SHuang Shijie } 119828eb4274SHuang Shijie 1199cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1200ab4382d2SGreg Kroah-Hartman 1201ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1202ab4382d2SGreg Kroah-Hartman * requesting IRQs 1203ab4382d2SGreg Kroah-Hartman */ 1204ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1205ab4382d2SGreg Kroah-Hartman 1206ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1207ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1208ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1209ab4382d2SGreg Kroah-Hartman 1210ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1211ab4382d2SGreg Kroah-Hartman 12127e11577eSLucas Stach /* Can we enable the DMA support? */ 12131c06bde6SMartyn Welch if (!uart_console(port) && !sport->dma_is_inited) 12147e11577eSLucas Stach imx_uart_dma_init(sport); 12157e11577eSLucas Stach 121653794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1217772f8991SHuang Shijie /* Reset fifo's and state machines */ 1218458e2c82SFabio Estevam i = 100; 1219458e2c82SFabio Estevam 1220458e2c82SFabio Estevam temp = readl(sport->port.membase + UCR2); 1221458e2c82SFabio Estevam temp &= ~UCR2_SRST; 1222458e2c82SFabio Estevam writel(temp, sport->port.membase + UCR2); 1223458e2c82SFabio Estevam 1224458e2c82SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1225458e2c82SFabio Estevam udelay(1); 1226ab4382d2SGreg Kroah-Hartman 1227ab4382d2SGreg Kroah-Hartman /* 1228ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1229ab4382d2SGreg Kroah-Hartman */ 123027e16501SUwe Kleine-König writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1); 123191555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 1232ab4382d2SGreg Kroah-Hartman 12337e11577eSLucas Stach if (sport->dma_is_inited && !sport->dma_is_enabled) 12347e11577eSLucas Stach imx_enable_dma(sport); 12357e11577eSLucas Stach 12361f043572STroy Kisky temp = readl(sport->port.membase + UCR1) & ~UCR1_RRDYEN; 12371f043572STroy Kisky if (!sport->dma_is_enabled) 12381f043572STroy Kisky temp |= UCR1_RRDYEN; 12391f043572STroy Kisky temp |= UCR1_UARTEN; 12406376cd39SNandor Han if (sport->have_rtscts) 12416376cd39SNandor Han temp |= UCR1_RTSDEN; 1242ab4382d2SGreg Kroah-Hartman 1243ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1244ab4382d2SGreg Kroah-Hartman 12451f043572STroy Kisky temp = readl(sport->port.membase + UCR4) & ~UCR4_OREN; 12461f043572STroy Kisky if (!sport->dma_is_enabled) 12476f026d6bSJiada Wang temp |= UCR4_OREN; 12486f026d6bSJiada Wang writel(temp, sport->port.membase + UCR4); 12496f026d6bSJiada Wang 12501f043572STroy Kisky temp = readl(sport->port.membase + UCR2) & ~UCR2_ATEN; 1251ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1252bff09b09SLucas Stach if (!sport->have_rtscts) 1253bff09b09SLucas Stach temp |= UCR2_IRTS; 125416804d68SUwe Kleine-König /* 125516804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 125616804d68SUwe Kleine-König * we're using RTSD instead. 125716804d68SUwe Kleine-König */ 125816804d68SUwe Kleine-König if (!is_imx1_uart(sport)) 125916804d68SUwe Kleine-König temp &= ~UCR2_RTSEN; 1260ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1261ab4382d2SGreg Kroah-Hartman 1262a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1263ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 126416804d68SUwe Kleine-König 1265e61c38d8SUwe Kleine-König temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 126616804d68SUwe Kleine-König 126716804d68SUwe Kleine-König if (sport->dte_mode) 1268e61c38d8SUwe Kleine-König /* disable broken interrupts */ 126916804d68SUwe Kleine-König temp &= ~(UCR3_RI | UCR3_DCD); 127016804d68SUwe Kleine-König 1271ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1272ab4382d2SGreg Kroah-Hartman } 1273ab4382d2SGreg Kroah-Hartman 1274ab4382d2SGreg Kroah-Hartman /* 1275ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1276ab4382d2SGreg Kroah-Hartman */ 1277ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 127818a42088SPeter Senna Tschudin 127918a42088SPeter Senna Tschudin /* 12804dec2f11SPeter Senna Tschudin * Start RX DMA immediately instead of waiting for RX FIFO interrupts. 12814dec2f11SPeter Senna Tschudin * In our iMX53 the average delay for the first reception dropped from 12824dec2f11SPeter Senna Tschudin * approximately 35000 microseconds to 1000 microseconds. 128318a42088SPeter Senna Tschudin */ 12841f043572STroy Kisky if (sport->dma_is_enabled) 128518a42088SPeter Senna Tschudin start_rx_dma(sport); 128618a42088SPeter Senna Tschudin 1287ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1288ab4382d2SGreg Kroah-Hartman 1289ab4382d2SGreg Kroah-Hartman return 0; 1290ab4382d2SGreg Kroah-Hartman } 1291ab4382d2SGreg Kroah-Hartman 1292ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1293ab4382d2SGreg Kroah-Hartman { 1294ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1295ab4382d2SGreg Kroah-Hartman unsigned long temp; 12969ec1882dSXinyu Chen unsigned long flags; 1297ab4382d2SGreg Kroah-Hartman 1298b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1299a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1300a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1301e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1302e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 13039d297239SNandor Han 130473631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1305a4688bcdSHuang Shijie imx_stop_tx(port); 1306b4cdc8f6SHuang Shijie imx_stop_rx(port); 1307b4cdc8f6SHuang Shijie imx_disable_dma(sport); 130873631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1309b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1310b4cdc8f6SHuang Shijie } 1311b4cdc8f6SHuang Shijie 131258362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 131358362d5bSUwe Kleine-König 13149ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1315ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1316ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1317ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 13189ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1319ab4382d2SGreg Kroah-Hartman 1320ab4382d2SGreg Kroah-Hartman /* 1321ab4382d2SGreg Kroah-Hartman * Stop our timer. 1322ab4382d2SGreg Kroah-Hartman */ 1323ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1324ab4382d2SGreg Kroah-Hartman 1325ab4382d2SGreg Kroah-Hartman /* 1326ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1327ab4382d2SGreg Kroah-Hartman */ 1328ab4382d2SGreg Kroah-Hartman 13299ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1330ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1331ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1332ab4382d2SGreg Kroah-Hartman 1333ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 13349ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 133528eb4274SHuang Shijie 133628eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 133728eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1338ab4382d2SGreg Kroah-Hartman } 1339ab4382d2SGreg Kroah-Hartman 1340eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1341eb56b7edSHuang Shijie { 1342eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 134382e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1344a2c718ceSDirk Behme unsigned long temp; 13454f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1346eb56b7edSHuang Shijie 134782e86ae9SDirk Behme if (!sport->dma_chan_tx) 134882e86ae9SDirk Behme return; 134982e86ae9SDirk Behme 1350eb56b7edSHuang Shijie sport->tx_bytes = 0; 1351eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 135282e86ae9SDirk Behme if (sport->dma_is_txing) { 135382e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 135482e86ae9SDirk Behme DMA_TO_DEVICE); 1355a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 1356a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 1357a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 13580f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1359eb56b7edSHuang Shijie } 1360934084a9SFabio Estevam 1361934084a9SFabio Estevam /* 1362934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1363263763c1SMartyn Welch * 1364934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1365934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1366263763c1SMartyn Welch * and UTS[6-3]". 1367263763c1SMartyn Welch * 1368263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1369263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1370263763c1SMartyn Welch * registers. 1371934084a9SFabio Estevam */ 1372934084a9SFabio Estevam ubir = readl(sport->port.membase + UBIR); 1373934084a9SFabio Estevam ubmr = readl(sport->port.membase + UBMR); 1374934084a9SFabio Estevam uts = readl(sport->port.membase + IMX21_UTS); 1375934084a9SFabio Estevam 1376934084a9SFabio Estevam temp = readl(sport->port.membase + UCR2); 1377934084a9SFabio Estevam temp &= ~UCR2_SRST; 1378934084a9SFabio Estevam writel(temp, sport->port.membase + UCR2); 1379934084a9SFabio Estevam 1380934084a9SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1381934084a9SFabio Estevam udelay(1); 1382934084a9SFabio Estevam 1383934084a9SFabio Estevam /* Restore the registers */ 1384934084a9SFabio Estevam writel(ubir, sport->port.membase + UBIR); 1385934084a9SFabio Estevam writel(ubmr, sport->port.membase + UBMR); 1386934084a9SFabio Estevam writel(uts, sport->port.membase + IMX21_UTS); 1387eb56b7edSHuang Shijie } 1388eb56b7edSHuang Shijie 1389ab4382d2SGreg Kroah-Hartman static void 1390ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1391ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1392ab4382d2SGreg Kroah-Hartman { 1393ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1394ab4382d2SGreg Kroah-Hartman unsigned long flags; 139558362d5bSUwe Kleine-König unsigned long ucr2, old_ucr1, old_ucr2; 139658362d5bSUwe Kleine-König unsigned int baud, quot; 1397ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 139858362d5bSUwe Kleine-König unsigned long div, ufcr; 1399ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1400ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1401ab4382d2SGreg Kroah-Hartman 1402ab4382d2SGreg Kroah-Hartman /* 1403ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1404ab4382d2SGreg Kroah-Hartman */ 1405ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1406ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1407ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1408ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1409ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1410ab4382d2SGreg Kroah-Hartman } 1411ab4382d2SGreg Kroah-Hartman 1412ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1413ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1414ab4382d2SGreg Kroah-Hartman else 1415ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1416ab4382d2SGreg Kroah-Hartman 1417ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1418ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1419ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 142017b8f2a3SUwe Kleine-König 142112fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 142217b8f2a3SUwe Kleine-König /* 142317b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 142417b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 142517b8f2a3SUwe Kleine-König * disabled. 142617b8f2a3SUwe Kleine-König */ 142758362d5bSUwe Kleine-König if (port->rs485.flags & 142858362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 142958362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 14301a613626SFabio Estevam else 14311a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 143212fe59f9SFabio Estevam } else { 143358362d5bSUwe Kleine-König imx_port_rts_auto(sport, &ucr2); 143412fe59f9SFabio Estevam } 1435ab4382d2SGreg Kroah-Hartman } else { 1436ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1437ab4382d2SGreg Kroah-Hartman } 143858362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 143917b8f2a3SUwe Kleine-König /* disable transmitter */ 144058362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 144158362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 14421a613626SFabio Estevam else 14431a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 144458362d5bSUwe Kleine-König } 144558362d5bSUwe Kleine-König 1446ab4382d2SGreg Kroah-Hartman 1447ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1448ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1449ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1450ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1451ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1452ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1453ab4382d2SGreg Kroah-Hartman } 1454ab4382d2SGreg Kroah-Hartman 1455995234daSEric Miao del_timer_sync(&sport->timer); 1456995234daSEric Miao 1457ab4382d2SGreg Kroah-Hartman /* 1458ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1459ab4382d2SGreg Kroah-Hartman */ 1460ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1461ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1462ab4382d2SGreg Kroah-Hartman 1463ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1464ab4382d2SGreg Kroah-Hartman 1465ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1466ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1467ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1468ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1469ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1470ab4382d2SGreg Kroah-Hartman 1471ab4382d2SGreg Kroah-Hartman /* 1472ab4382d2SGreg Kroah-Hartman * Characters to ignore 1473ab4382d2SGreg Kroah-Hartman */ 1474ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1475ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1476865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1477ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1478ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1479ab4382d2SGreg Kroah-Hartman /* 1480ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1481ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1482ab4382d2SGreg Kroah-Hartman */ 1483ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1484ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1485ab4382d2SGreg Kroah-Hartman } 1486ab4382d2SGreg Kroah-Hartman 148755d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 148855d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 148955d8693aSJiada Wang 1490ab4382d2SGreg Kroah-Hartman /* 1491ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1492ab4382d2SGreg Kroah-Hartman */ 1493ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1494ab4382d2SGreg Kroah-Hartman 1495ab4382d2SGreg Kroah-Hartman /* 1496ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1497ab4382d2SGreg Kroah-Hartman */ 1498ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1499ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1500ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1501ab4382d2SGreg Kroah-Hartman 1502ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1503ab4382d2SGreg Kroah-Hartman barrier(); 1504ab4382d2SGreg Kroah-Hartman 1505ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 150686a04ba6SLucas Stach old_ucr2 = readl(sport->port.membase + UCR2); 150786a04ba6SLucas Stach writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN), 1508ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 150986a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1510ab4382d2SGreg Kroah-Hartman 151109bd00f6SHubert Feurstein /* custom-baudrate handling */ 151209bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 151309bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 151409bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 151509bd00f6SHubert Feurstein 1516ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1517ab4382d2SGreg Kroah-Hartman if (div > 7) 1518ab4382d2SGreg Kroah-Hartman div = 7; 1519ab4382d2SGreg Kroah-Hartman if (!div) 1520ab4382d2SGreg Kroah-Hartman div = 1; 1521ab4382d2SGreg Kroah-Hartman 1522ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1523ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1524ab4382d2SGreg Kroah-Hartman 1525ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1526ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1527ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1528ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1529ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1530ab4382d2SGreg Kroah-Hartman 1531ab4382d2SGreg Kroah-Hartman num -= 1; 1532ab4382d2SGreg Kroah-Hartman denom -= 1; 1533ab4382d2SGreg Kroah-Hartman 1534ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1535ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1536ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1537ab4382d2SGreg Kroah-Hartman 1538ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1539ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1540ab4382d2SGreg Kroah-Hartman 1541a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1542ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1543fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1544ab4382d2SGreg Kroah-Hartman 1545ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1546ab4382d2SGreg Kroah-Hartman 1547ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 154886a04ba6SLucas Stach writel(ucr2 | old_ucr2, sport->port.membase + UCR2); 1549ab4382d2SGreg Kroah-Hartman 1550ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1551ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1552ab4382d2SGreg Kroah-Hartman 1553ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1554ab4382d2SGreg Kroah-Hartman } 1555ab4382d2SGreg Kroah-Hartman 1556ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1557ab4382d2SGreg Kroah-Hartman { 1558ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1559ab4382d2SGreg Kroah-Hartman 1560ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1561ab4382d2SGreg Kroah-Hartman } 1562ab4382d2SGreg Kroah-Hartman 1563ab4382d2SGreg Kroah-Hartman /* 1564ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1565ab4382d2SGreg Kroah-Hartman */ 1566ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1567ab4382d2SGreg Kroah-Hartman { 1568ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1569ab4382d2SGreg Kroah-Hartman 1570da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1571ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1572ab4382d2SGreg Kroah-Hartman } 1573ab4382d2SGreg Kroah-Hartman 1574ab4382d2SGreg Kroah-Hartman /* 1575ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1576ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1577ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1578ab4382d2SGreg Kroah-Hartman */ 1579ab4382d2SGreg Kroah-Hartman static int 1580ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1581ab4382d2SGreg Kroah-Hartman { 1582ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1583ab4382d2SGreg Kroah-Hartman int ret = 0; 1584ab4382d2SGreg Kroah-Hartman 1585ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1586ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1587ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1588ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1589ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1590ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1591ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1592ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1593a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1594ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1595ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1596ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1597ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1598ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1599ab4382d2SGreg Kroah-Hartman return ret; 1600ab4382d2SGreg Kroah-Hartman } 1601ab4382d2SGreg Kroah-Hartman 160201f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 16036b8bdad9SDaniel Thompson 16046b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 16056b8bdad9SDaniel Thompson { 16066b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 16076b8bdad9SDaniel Thompson unsigned long flags; 16086b8bdad9SDaniel Thompson unsigned long temp; 16096b8bdad9SDaniel Thompson int retval; 16106b8bdad9SDaniel Thompson 16116b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 16126b8bdad9SDaniel Thompson if (retval) 16136b8bdad9SDaniel Thompson return retval; 16146b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 16156b8bdad9SDaniel Thompson if (retval) 16166b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 16176b8bdad9SDaniel Thompson 1618cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 16196b8bdad9SDaniel Thompson 16206b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 16216b8bdad9SDaniel Thompson 16226b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR1); 16236b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 16246b8bdad9SDaniel Thompson temp |= IMX1_UCR1_UARTCLKEN; 16256b8bdad9SDaniel Thompson temp |= UCR1_UARTEN | UCR1_RRDYEN; 16266b8bdad9SDaniel Thompson temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 16276b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR1); 16286b8bdad9SDaniel Thompson 16296b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR2); 16306b8bdad9SDaniel Thompson temp |= UCR2_RXEN; 16316b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR2); 16326b8bdad9SDaniel Thompson 16336b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 16346b8bdad9SDaniel Thompson 16356b8bdad9SDaniel Thompson return 0; 16366b8bdad9SDaniel Thompson } 16376b8bdad9SDaniel Thompson 163801f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 163901f56abdSSaleem Abdulrasool { 1640f968ef34SDaniel Thompson if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 164126c47412SDirk Behme return NO_POLL_CHAR; 164201f56abdSSaleem Abdulrasool 1643f968ef34SDaniel Thompson return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 164401f56abdSSaleem Abdulrasool } 164501f56abdSSaleem Abdulrasool 164601f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 164701f56abdSSaleem Abdulrasool { 164801f56abdSSaleem Abdulrasool unsigned int status; 164901f56abdSSaleem Abdulrasool 165001f56abdSSaleem Abdulrasool /* drain */ 165101f56abdSSaleem Abdulrasool do { 1652f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR1); 165301f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 165401f56abdSSaleem Abdulrasool 165501f56abdSSaleem Abdulrasool /* write */ 1656f968ef34SDaniel Thompson writel_relaxed(c, port->membase + URTX0); 165701f56abdSSaleem Abdulrasool 165801f56abdSSaleem Abdulrasool /* flush */ 165901f56abdSSaleem Abdulrasool do { 1660f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR2); 166101f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 166201f56abdSSaleem Abdulrasool } 166301f56abdSSaleem Abdulrasool #endif 166401f56abdSSaleem Abdulrasool 166517b8f2a3SUwe Kleine-König static int imx_rs485_config(struct uart_port *port, 166617b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 166717b8f2a3SUwe Kleine-König { 166817b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 16697d1cadcaSBaruch Siach unsigned long temp; 167017b8f2a3SUwe Kleine-König 167117b8f2a3SUwe Kleine-König /* unimplemented */ 167217b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 167317b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 167417b8f2a3SUwe Kleine-König 167517b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 16767b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 167717b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 167817b8f2a3SUwe Kleine-König 167917b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 168017b8f2a3SUwe Kleine-König /* disable transmitter */ 168117b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 168217b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 168358362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 16841a613626SFabio Estevam else 16851a613626SFabio Estevam imx_port_rts_inactive(sport, &temp); 168617b8f2a3SUwe Kleine-König writel(temp, sport->port.membase + UCR2); 168717b8f2a3SUwe Kleine-König } 168817b8f2a3SUwe Kleine-König 16897d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 16907d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 16917d1cadcaSBaruch Siach rs485conf->flags & SER_RS485_RX_DURING_TX) { 16927d1cadcaSBaruch Siach temp = readl(sport->port.membase + UCR2); 16937d1cadcaSBaruch Siach temp |= UCR2_RXEN; 16947d1cadcaSBaruch Siach writel(temp, sport->port.membase + UCR2); 16957d1cadcaSBaruch Siach } 16967d1cadcaSBaruch Siach 169717b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 169817b8f2a3SUwe Kleine-König 169917b8f2a3SUwe Kleine-König return 0; 170017b8f2a3SUwe Kleine-König } 170117b8f2a3SUwe Kleine-König 1702069a47e5SJulia Lawall static const struct uart_ops imx_pops = { 1703ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1704ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1705ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1706ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1707ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1708ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1709ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1710ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1711ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1712ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1713eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1714ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1715ab4382d2SGreg Kroah-Hartman .type = imx_type, 1716ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1717ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 171801f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17196b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 172001f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 172101f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 172201f56abdSSaleem Abdulrasool #endif 1723ab4382d2SGreg Kroah-Hartman }; 1724ab4382d2SGreg Kroah-Hartman 1725ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1726ab4382d2SGreg Kroah-Hartman 1727ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1728ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1729ab4382d2SGreg Kroah-Hartman { 1730ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1731ab4382d2SGreg Kroah-Hartman 1732fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1733ab4382d2SGreg Kroah-Hartman barrier(); 1734ab4382d2SGreg Kroah-Hartman 1735ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1736ab4382d2SGreg Kroah-Hartman } 1737ab4382d2SGreg Kroah-Hartman 1738ab4382d2SGreg Kroah-Hartman /* 1739ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1740ab4382d2SGreg Kroah-Hartman */ 1741ab4382d2SGreg Kroah-Hartman static void 1742ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1743ab4382d2SGreg Kroah-Hartman { 1744ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 17450ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 17460ad5a814SDirk Behme unsigned int ucr1; 1747f30e8260SShawn Guo unsigned long flags = 0; 1748677fe555SThomas Gleixner int locked = 1; 17491cf93e0dSHuang Shijie int retval; 17501cf93e0dSHuang Shijie 17510c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 17521cf93e0dSHuang Shijie if (retval) 17531cf93e0dSHuang Shijie return; 17540c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 17551cf93e0dSHuang Shijie if (retval) { 17560c727a42SFabio Estevam clk_disable(sport->clk_per); 17571cf93e0dSHuang Shijie return; 17581cf93e0dSHuang Shijie } 17599ec1882dSXinyu Chen 1760677fe555SThomas Gleixner if (sport->port.sysrq) 1761677fe555SThomas Gleixner locked = 0; 1762677fe555SThomas Gleixner else if (oops_in_progress) 1763677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1764677fe555SThomas Gleixner else 17659ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1766ab4382d2SGreg Kroah-Hartman 1767ab4382d2SGreg Kroah-Hartman /* 17680ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1769ab4382d2SGreg Kroah-Hartman */ 17700ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 17710ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1772ab4382d2SGreg Kroah-Hartman 1773fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1774fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1775ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1776ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1777ab4382d2SGreg Kroah-Hartman 1778ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1779ab4382d2SGreg Kroah-Hartman 17800ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1781ab4382d2SGreg Kroah-Hartman 1782ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1783ab4382d2SGreg Kroah-Hartman 1784ab4382d2SGreg Kroah-Hartman /* 1785ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 17860ad5a814SDirk Behme * and restore UCR1/2/3 1787ab4382d2SGreg Kroah-Hartman */ 1788ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1789ab4382d2SGreg Kroah-Hartman 17900ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 17919ec1882dSXinyu Chen 1792677fe555SThomas Gleixner if (locked) 17939ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 17941cf93e0dSHuang Shijie 17950c727a42SFabio Estevam clk_disable(sport->clk_ipg); 17960c727a42SFabio Estevam clk_disable(sport->clk_per); 1797ab4382d2SGreg Kroah-Hartman } 1798ab4382d2SGreg Kroah-Hartman 1799ab4382d2SGreg Kroah-Hartman /* 1800ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1801ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1802ab4382d2SGreg Kroah-Hartman */ 1803ab4382d2SGreg Kroah-Hartman static void __init 1804ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1805ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1806ab4382d2SGreg Kroah-Hartman { 1807ab4382d2SGreg Kroah-Hartman 1808ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1809ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1810ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1811ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1812ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1813ab4382d2SGreg Kroah-Hartman 1814ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1815ab4382d2SGreg Kroah-Hartman 1816ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1817ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1818ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1819ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1820ab4382d2SGreg Kroah-Hartman else 1821ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1822ab4382d2SGreg Kroah-Hartman } 1823ab4382d2SGreg Kroah-Hartman 1824ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1825ab4382d2SGreg Kroah-Hartman *bits = 8; 1826ab4382d2SGreg Kroah-Hartman else 1827ab4382d2SGreg Kroah-Hartman *bits = 7; 1828ab4382d2SGreg Kroah-Hartman 1829ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1830ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1831ab4382d2SGreg Kroah-Hartman 1832ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1833ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1834ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1835ab4382d2SGreg Kroah-Hartman else 1836ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1837ab4382d2SGreg Kroah-Hartman 18383a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1839ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1840ab4382d2SGreg Kroah-Hartman 1841ab4382d2SGreg Kroah-Hartman { /* 1842ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1843ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1844ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1845ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1846ab4382d2SGreg Kroah-Hartman */ 1847ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1848ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1849ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1850ab4382d2SGreg Kroah-Hartman 1851ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1852ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1853ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1854ab4382d2SGreg Kroah-Hartman } 1855ab4382d2SGreg Kroah-Hartman 1856ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 185750bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1858ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1859ab4382d2SGreg Kroah-Hartman } 1860ab4382d2SGreg Kroah-Hartman } 1861ab4382d2SGreg Kroah-Hartman 1862ab4382d2SGreg Kroah-Hartman static int __init 1863ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1864ab4382d2SGreg Kroah-Hartman { 1865ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1866ab4382d2SGreg Kroah-Hartman int baud = 9600; 1867ab4382d2SGreg Kroah-Hartman int bits = 8; 1868ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1869ab4382d2SGreg Kroah-Hartman int flow = 'n'; 18701cf93e0dSHuang Shijie int retval; 1871ab4382d2SGreg Kroah-Hartman 1872ab4382d2SGreg Kroah-Hartman /* 1873ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1874ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1875ab4382d2SGreg Kroah-Hartman * console support. 1876ab4382d2SGreg Kroah-Hartman */ 1877ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1878ab4382d2SGreg Kroah-Hartman co->index = 0; 1879ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1880ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1881ab4382d2SGreg Kroah-Hartman return -ENODEV; 1882ab4382d2SGreg Kroah-Hartman 18831cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 18841cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 18851cf93e0dSHuang Shijie if (retval) 18861cf93e0dSHuang Shijie goto error_console; 18871cf93e0dSHuang Shijie 1888ab4382d2SGreg Kroah-Hartman if (options) 1889ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1890ab4382d2SGreg Kroah-Hartman else 1891ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1892ab4382d2SGreg Kroah-Hartman 1893cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1894ab4382d2SGreg Kroah-Hartman 18951cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 18961cf93e0dSHuang Shijie 18970c727a42SFabio Estevam clk_disable(sport->clk_ipg); 18980c727a42SFabio Estevam if (retval) { 18990c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 19000c727a42SFabio Estevam goto error_console; 19010c727a42SFabio Estevam } 19020c727a42SFabio Estevam 19030c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 19040c727a42SFabio Estevam if (retval) 19051cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 19061cf93e0dSHuang Shijie 19071cf93e0dSHuang Shijie error_console: 19081cf93e0dSHuang Shijie return retval; 1909ab4382d2SGreg Kroah-Hartman } 1910ab4382d2SGreg Kroah-Hartman 1911ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1912ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1913ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1914ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1915ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1916ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1917ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1918ab4382d2SGreg Kroah-Hartman .index = -1, 1919ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1920ab4382d2SGreg Kroah-Hartman }; 1921ab4382d2SGreg Kroah-Hartman 1922ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1923913c6c0eSLucas Stach 1924913c6c0eSLucas Stach #ifdef CONFIG_OF 1925913c6c0eSLucas Stach static void imx_console_early_putchar(struct uart_port *port, int ch) 1926913c6c0eSLucas Stach { 1927913c6c0eSLucas Stach while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL) 1928913c6c0eSLucas Stach cpu_relax(); 1929913c6c0eSLucas Stach 1930913c6c0eSLucas Stach writel_relaxed(ch, port->membase + URTX0); 1931913c6c0eSLucas Stach } 1932913c6c0eSLucas Stach 1933913c6c0eSLucas Stach static void imx_console_early_write(struct console *con, const char *s, 1934913c6c0eSLucas Stach unsigned count) 1935913c6c0eSLucas Stach { 1936913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 1937913c6c0eSLucas Stach 1938913c6c0eSLucas Stach uart_console_write(&dev->port, s, count, imx_console_early_putchar); 1939913c6c0eSLucas Stach } 1940913c6c0eSLucas Stach 1941913c6c0eSLucas Stach static int __init 1942913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 1943913c6c0eSLucas Stach { 1944913c6c0eSLucas Stach if (!dev->port.membase) 1945913c6c0eSLucas Stach return -ENODEV; 1946913c6c0eSLucas Stach 1947913c6c0eSLucas Stach dev->con->write = imx_console_early_write; 1948913c6c0eSLucas Stach 1949913c6c0eSLucas Stach return 0; 1950913c6c0eSLucas Stach } 1951913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 1952913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 1953913c6c0eSLucas Stach #endif 1954913c6c0eSLucas Stach 1955ab4382d2SGreg Kroah-Hartman #else 1956ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1957ab4382d2SGreg Kroah-Hartman #endif 1958ab4382d2SGreg Kroah-Hartman 1959ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1960ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1961ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 1962ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 1963ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 1964ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 1965ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 1966ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 1967ab4382d2SGreg Kroah-Hartman }; 1968ab4382d2SGreg Kroah-Hartman 196922698aa2SShawn Guo #ifdef CONFIG_OF 197020bb8095SUwe Kleine-König /* 197120bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 197220bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 197320bb8095SUwe Kleine-König */ 197422698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 197522698aa2SShawn Guo struct platform_device *pdev) 197622698aa2SShawn Guo { 197722698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 1978ff05967aSShawn Guo int ret; 197922698aa2SShawn Guo 19805f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 19815f8b9043SLABBE Corentin if (!sport->devdata) 198220bb8095SUwe Kleine-König /* no device tree device */ 198320bb8095SUwe Kleine-König return 1; 198422698aa2SShawn Guo 1985ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 1986ff05967aSShawn Guo if (ret < 0) { 1987ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1988a197a191SUwe Kleine-König return ret; 1989ff05967aSShawn Guo } 1990ff05967aSShawn Guo sport->port.line = ret; 199122698aa2SShawn Guo 19921006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 19931006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 199422698aa2SShawn Guo sport->have_rtscts = 1; 199522698aa2SShawn Guo 199620ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 199720ff2fe6SHuang Shijie sport->dte_mode = 1; 199820ff2fe6SHuang Shijie 19997b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 20007b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 20017b7e8e8eSFabio Estevam 200222698aa2SShawn Guo return 0; 200322698aa2SShawn Guo } 200422698aa2SShawn Guo #else 200522698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 200622698aa2SShawn Guo struct platform_device *pdev) 200722698aa2SShawn Guo { 200820bb8095SUwe Kleine-König return 1; 200922698aa2SShawn Guo } 201022698aa2SShawn Guo #endif 201122698aa2SShawn Guo 201222698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 201322698aa2SShawn Guo struct platform_device *pdev) 201422698aa2SShawn Guo { 2015574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 201622698aa2SShawn Guo 201722698aa2SShawn Guo sport->port.line = pdev->id; 201822698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 201922698aa2SShawn Guo 202022698aa2SShawn Guo if (!pdata) 202122698aa2SShawn Guo return; 202222698aa2SShawn Guo 202322698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 202422698aa2SShawn Guo sport->have_rtscts = 1; 202522698aa2SShawn Guo } 202622698aa2SShawn Guo 2027ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 2028ab4382d2SGreg Kroah-Hartman { 2029ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2030ab4382d2SGreg Kroah-Hartman void __iomem *base; 20318a61f0c7SFabio Estevam int ret = 0, reg; 2032ab4382d2SGreg Kroah-Hartman struct resource *res; 2033842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2034ab4382d2SGreg Kroah-Hartman 203542d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2036ab4382d2SGreg Kroah-Hartman if (!sport) 2037ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2038ab4382d2SGreg Kroah-Hartman 203922698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 204020bb8095SUwe Kleine-König if (ret > 0) 204122698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 204220bb8095SUwe Kleine-König else if (ret < 0) 204342d34191SSachin Kamat return ret; 204422698aa2SShawn Guo 2045ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2046da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2047da82f997SAlexander Shiyan if (IS_ERR(base)) 2048da82f997SAlexander Shiyan return PTR_ERR(base); 2049ab4382d2SGreg Kroah-Hartman 2050842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2051842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2052842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2053842633bdSUwe Kleine-König 2054ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2055ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2056ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2057ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2058ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2059842633bdSUwe Kleine-König sport->port.irq = rxirq; 2060ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2061ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 206217b8f2a3SUwe Kleine-König sport->port.rs485_config = imx_rs485_config; 2063ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 2064e99e88a9SKees Cook timer_setup(&sport->timer, imx_timeout, 0); 2065ab4382d2SGreg Kroah-Hartman 206658362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 206758362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 206858362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 206958362d5bSUwe Kleine-König 20703a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 20713a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 20723a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2073833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 207442d34191SSachin Kamat return ret; 2075ab4382d2SGreg Kroah-Hartman } 2076ab4382d2SGreg Kroah-Hartman 20773a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 20783a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 20793a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2080833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 208142d34191SSachin Kamat return ret; 20823a9465faSSascha Hauer } 20833a9465faSSascha Hauer 20843a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2085ab4382d2SGreg Kroah-Hartman 20868a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 20878a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 20881e512d45SUwe Kleine-König if (ret) { 20891e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 20908a61f0c7SFabio Estevam return ret; 20911e512d45SUwe Kleine-König } 20928a61f0c7SFabio Estevam 2093743f93f8SLukas Wunner uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2094743f93f8SLukas Wunner 2095b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 2096b8f3bff0SLukas Wunner (!sport->have_rtscts || !sport->have_rtsgpio)) 2097b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2098b8f3bff0SLukas Wunner 2099b8f3bff0SLukas Wunner imx_rs485_config(&sport->port, &sport->port.rs485); 2100b8f3bff0SLukas Wunner 21018a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 21028a61f0c7SFabio Estevam reg = readl_relaxed(sport->port.membase + UCR1); 21038a61f0c7SFabio Estevam reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 21048a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 21058a61f0c7SFabio Estevam writel_relaxed(reg, sport->port.membase + UCR1); 21068a61f0c7SFabio Estevam 2107e61c38d8SUwe Kleine-König if (!is_imx1_uart(sport) && sport->dte_mode) { 2108e61c38d8SUwe Kleine-König /* 2109e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2110e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2111e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2112e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2113e61c38d8SUwe Kleine-König */ 21146df765dcSUwe Kleine-König reg = readl(sport->port.membase + UFCR); 21156df765dcSUwe Kleine-König if (!(reg & UFCR_DCEDTE)) 21166df765dcSUwe Kleine-König writel(reg | UFCR_DCEDTE, sport->port.membase + UFCR); 2117e61c38d8SUwe Kleine-König 2118e61c38d8SUwe Kleine-König /* 2119e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2120e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2121e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2122e61c38d8SUwe Kleine-König */ 2123e61c38d8SUwe Kleine-König writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2124e61c38d8SUwe Kleine-König sport->port.membase + UCR3); 2125e61c38d8SUwe Kleine-König 2126e61c38d8SUwe Kleine-König } else { 21276df765dcSUwe Kleine-König unsigned long ucr3 = UCR3_DSR; 21286df765dcSUwe Kleine-König 21296df765dcSUwe Kleine-König reg = readl(sport->port.membase + UFCR); 21306df765dcSUwe Kleine-König if (reg & UFCR_DCEDTE) 21316df765dcSUwe Kleine-König writel(reg & ~UFCR_DCEDTE, sport->port.membase + UFCR); 21326df765dcSUwe Kleine-König 21336df765dcSUwe Kleine-König if (!is_imx1_uart(sport)) 21346df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 21356df765dcSUwe Kleine-König writel(ucr3, sport->port.membase + UCR3); 2136e61c38d8SUwe Kleine-König } 2137e61c38d8SUwe Kleine-König 21388a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 21398a61f0c7SFabio Estevam 2140c0d1c6b0SFabio Estevam /* 2141c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2142c0d1c6b0SFabio Estevam * chips only have one interrupt. 2143c0d1c6b0SFabio Estevam */ 2144842633bdSUwe Kleine-König if (txirq > 0) { 2145842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2146c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 21471e512d45SUwe Kleine-König if (ret) { 21481e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 21491e512d45SUwe Kleine-König ret); 2150c0d1c6b0SFabio Estevam return ret; 21511e512d45SUwe Kleine-König } 2152c0d1c6b0SFabio Estevam 2153842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2154c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 21551e512d45SUwe Kleine-König if (ret) { 21561e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 21571e512d45SUwe Kleine-König ret); 2158c0d1c6b0SFabio Estevam return ret; 21591e512d45SUwe Kleine-König } 2160c0d1c6b0SFabio Estevam } else { 2161842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2162c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 21631e512d45SUwe Kleine-König if (ret) { 21641e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2165c0d1c6b0SFabio Estevam return ret; 2166c0d1c6b0SFabio Estevam } 21671e512d45SUwe Kleine-König } 2168c0d1c6b0SFabio Estevam 216922698aa2SShawn Guo imx_ports[sport->port.line] = sport; 2170ab4382d2SGreg Kroah-Hartman 21710a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2172ab4382d2SGreg Kroah-Hartman 217345af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2174ab4382d2SGreg Kroah-Hartman } 2175ab4382d2SGreg Kroah-Hartman 2176ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2177ab4382d2SGreg Kroah-Hartman { 2178ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2179ab4382d2SGreg Kroah-Hartman 218045af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2181ab4382d2SGreg Kroah-Hartman } 2182ab4382d2SGreg Kroah-Hartman 2183c868cbb7SEduardo Valentin static void serial_imx_restore_context(struct imx_port *sport) 2184c868cbb7SEduardo Valentin { 2185c868cbb7SEduardo Valentin if (!sport->context_saved) 2186c868cbb7SEduardo Valentin return; 2187c868cbb7SEduardo Valentin 2188c868cbb7SEduardo Valentin writel(sport->saved_reg[4], sport->port.membase + UFCR); 2189c868cbb7SEduardo Valentin writel(sport->saved_reg[5], sport->port.membase + UESC); 2190c868cbb7SEduardo Valentin writel(sport->saved_reg[6], sport->port.membase + UTIM); 2191c868cbb7SEduardo Valentin writel(sport->saved_reg[7], sport->port.membase + UBIR); 2192c868cbb7SEduardo Valentin writel(sport->saved_reg[8], sport->port.membase + UBMR); 2193c868cbb7SEduardo Valentin writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS); 2194c868cbb7SEduardo Valentin writel(sport->saved_reg[0], sport->port.membase + UCR1); 2195c868cbb7SEduardo Valentin writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2); 2196c868cbb7SEduardo Valentin writel(sport->saved_reg[2], sport->port.membase + UCR3); 2197c868cbb7SEduardo Valentin writel(sport->saved_reg[3], sport->port.membase + UCR4); 2198c868cbb7SEduardo Valentin sport->context_saved = false; 2199c868cbb7SEduardo Valentin } 2200c868cbb7SEduardo Valentin 2201c868cbb7SEduardo Valentin static void serial_imx_save_context(struct imx_port *sport) 2202c868cbb7SEduardo Valentin { 2203c868cbb7SEduardo Valentin /* Save necessary regs */ 2204c868cbb7SEduardo Valentin sport->saved_reg[0] = readl(sport->port.membase + UCR1); 2205c868cbb7SEduardo Valentin sport->saved_reg[1] = readl(sport->port.membase + UCR2); 2206c868cbb7SEduardo Valentin sport->saved_reg[2] = readl(sport->port.membase + UCR3); 2207c868cbb7SEduardo Valentin sport->saved_reg[3] = readl(sport->port.membase + UCR4); 2208c868cbb7SEduardo Valentin sport->saved_reg[4] = readl(sport->port.membase + UFCR); 2209c868cbb7SEduardo Valentin sport->saved_reg[5] = readl(sport->port.membase + UESC); 2210c868cbb7SEduardo Valentin sport->saved_reg[6] = readl(sport->port.membase + UTIM); 2211c868cbb7SEduardo Valentin sport->saved_reg[7] = readl(sport->port.membase + UBIR); 2212c868cbb7SEduardo Valentin sport->saved_reg[8] = readl(sport->port.membase + UBMR); 2213c868cbb7SEduardo Valentin sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS); 2214c868cbb7SEduardo Valentin sport->context_saved = true; 2215c868cbb7SEduardo Valentin } 2216c868cbb7SEduardo Valentin 2217189550b8SEduardo Valentin static void serial_imx_enable_wakeup(struct imx_port *sport, bool on) 2218189550b8SEduardo Valentin { 2219189550b8SEduardo Valentin unsigned int val; 2220189550b8SEduardo Valentin 2221189550b8SEduardo Valentin val = readl(sport->port.membase + UCR3); 2222189550b8SEduardo Valentin if (on) 2223189550b8SEduardo Valentin val |= UCR3_AWAKEN; 2224189550b8SEduardo Valentin else 2225189550b8SEduardo Valentin val &= ~UCR3_AWAKEN; 2226189550b8SEduardo Valentin writel(val, sport->port.membase + UCR3); 2227bc85734bSEduardo Valentin 2228bc85734bSEduardo Valentin val = readl(sport->port.membase + UCR1); 2229bc85734bSEduardo Valentin if (on) 2230bc85734bSEduardo Valentin val |= UCR1_RTSDEN; 2231bc85734bSEduardo Valentin else 2232bc85734bSEduardo Valentin val &= ~UCR1_RTSDEN; 2233bc85734bSEduardo Valentin writel(val, sport->port.membase + UCR1); 2234189550b8SEduardo Valentin } 2235189550b8SEduardo Valentin 223690bb6bd3SShenwei Wang static int imx_serial_port_suspend_noirq(struct device *dev) 223790bb6bd3SShenwei Wang { 223890bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 223990bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 224090bb6bd3SShenwei Wang int ret; 224190bb6bd3SShenwei Wang 224290bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 224390bb6bd3SShenwei Wang if (ret) 224490bb6bd3SShenwei Wang return ret; 224590bb6bd3SShenwei Wang 2246c868cbb7SEduardo Valentin serial_imx_save_context(sport); 224790bb6bd3SShenwei Wang 224890bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 224990bb6bd3SShenwei Wang 225090bb6bd3SShenwei Wang return 0; 225190bb6bd3SShenwei Wang } 225290bb6bd3SShenwei Wang 225390bb6bd3SShenwei Wang static int imx_serial_port_resume_noirq(struct device *dev) 225490bb6bd3SShenwei Wang { 225590bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 225690bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 225790bb6bd3SShenwei Wang int ret; 225890bb6bd3SShenwei Wang 225990bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 226090bb6bd3SShenwei Wang if (ret) 226190bb6bd3SShenwei Wang return ret; 226290bb6bd3SShenwei Wang 2263c868cbb7SEduardo Valentin serial_imx_restore_context(sport); 226490bb6bd3SShenwei Wang 226590bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 226690bb6bd3SShenwei Wang 226790bb6bd3SShenwei Wang return 0; 226890bb6bd3SShenwei Wang } 226990bb6bd3SShenwei Wang 227090bb6bd3SShenwei Wang static int imx_serial_port_suspend(struct device *dev) 227190bb6bd3SShenwei Wang { 227290bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 227390bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 227490bb6bd3SShenwei Wang 227590bb6bd3SShenwei Wang /* enable wakeup from i.MX UART */ 2276189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, true); 227790bb6bd3SShenwei Wang 227890bb6bd3SShenwei Wang uart_suspend_port(&imx_reg, &sport->port); 227981b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 228090bb6bd3SShenwei Wang 228129add68dSMartin Fuzzey /* Needed to enable clock in suspend_noirq */ 228229add68dSMartin Fuzzey return clk_prepare(sport->clk_ipg); 228390bb6bd3SShenwei Wang } 228490bb6bd3SShenwei Wang 228590bb6bd3SShenwei Wang static int imx_serial_port_resume(struct device *dev) 228690bb6bd3SShenwei Wang { 228790bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 228890bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 228990bb6bd3SShenwei Wang 229090bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 2291189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, false); 229290bb6bd3SShenwei Wang 229390bb6bd3SShenwei Wang uart_resume_port(&imx_reg, &sport->port); 229481b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 229590bb6bd3SShenwei Wang 229629add68dSMartin Fuzzey clk_unprepare(sport->clk_ipg); 229729add68dSMartin Fuzzey 229890bb6bd3SShenwei Wang return 0; 229990bb6bd3SShenwei Wang } 230090bb6bd3SShenwei Wang 230194be6d74SPhilipp Zabel static int imx_serial_port_freeze(struct device *dev) 230294be6d74SPhilipp Zabel { 230394be6d74SPhilipp Zabel struct platform_device *pdev = to_platform_device(dev); 230494be6d74SPhilipp Zabel struct imx_port *sport = platform_get_drvdata(pdev); 230594be6d74SPhilipp Zabel 230694be6d74SPhilipp Zabel uart_suspend_port(&imx_reg, &sport->port); 230794be6d74SPhilipp Zabel 230894be6d74SPhilipp Zabel /* Needed to enable clock in suspend_noirq */ 230994be6d74SPhilipp Zabel return clk_prepare(sport->clk_ipg); 231094be6d74SPhilipp Zabel } 231194be6d74SPhilipp Zabel 231294be6d74SPhilipp Zabel static int imx_serial_port_thaw(struct device *dev) 231394be6d74SPhilipp Zabel { 231494be6d74SPhilipp Zabel struct platform_device *pdev = to_platform_device(dev); 231594be6d74SPhilipp Zabel struct imx_port *sport = platform_get_drvdata(pdev); 231694be6d74SPhilipp Zabel 231794be6d74SPhilipp Zabel uart_resume_port(&imx_reg, &sport->port); 231894be6d74SPhilipp Zabel 231994be6d74SPhilipp Zabel clk_unprepare(sport->clk_ipg); 232094be6d74SPhilipp Zabel 232194be6d74SPhilipp Zabel return 0; 232294be6d74SPhilipp Zabel } 232394be6d74SPhilipp Zabel 232490bb6bd3SShenwei Wang static const struct dev_pm_ops imx_serial_port_pm_ops = { 232590bb6bd3SShenwei Wang .suspend_noirq = imx_serial_port_suspend_noirq, 232690bb6bd3SShenwei Wang .resume_noirq = imx_serial_port_resume_noirq, 232794be6d74SPhilipp Zabel .freeze_noirq = imx_serial_port_suspend_noirq, 232894be6d74SPhilipp Zabel .restore_noirq = imx_serial_port_resume_noirq, 232990bb6bd3SShenwei Wang .suspend = imx_serial_port_suspend, 233090bb6bd3SShenwei Wang .resume = imx_serial_port_resume, 233194be6d74SPhilipp Zabel .freeze = imx_serial_port_freeze, 233294be6d74SPhilipp Zabel .thaw = imx_serial_port_thaw, 233394be6d74SPhilipp Zabel .restore = imx_serial_port_thaw, 233490bb6bd3SShenwei Wang }; 233590bb6bd3SShenwei Wang 2336ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2337ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2338ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2339ab4382d2SGreg Kroah-Hartman 2340fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2341ab4382d2SGreg Kroah-Hartman .driver = { 2342ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 234322698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 234490bb6bd3SShenwei Wang .pm = &imx_serial_port_pm_ops, 2345ab4382d2SGreg Kroah-Hartman }, 2346ab4382d2SGreg Kroah-Hartman }; 2347ab4382d2SGreg Kroah-Hartman 2348ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2349ab4382d2SGreg Kroah-Hartman { 2350f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2351ab4382d2SGreg Kroah-Hartman 2352ab4382d2SGreg Kroah-Hartman if (ret) 2353ab4382d2SGreg Kroah-Hartman return ret; 2354ab4382d2SGreg Kroah-Hartman 2355ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2356ab4382d2SGreg Kroah-Hartman if (ret != 0) 2357ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2358ab4382d2SGreg Kroah-Hartman 2359f227824eSUwe Kleine-König return ret; 2360ab4382d2SGreg Kroah-Hartman } 2361ab4382d2SGreg Kroah-Hartman 2362ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2363ab4382d2SGreg Kroah-Hartman { 2364ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2365ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2366ab4382d2SGreg Kroah-Hartman } 2367ab4382d2SGreg Kroah-Hartman 2368ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2369ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2370ab4382d2SGreg Kroah-Hartman 2371ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2372ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2373ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2374ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2375