1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 12ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 13ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 14ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 15ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 23bd78ecd6SAhmad Fatoum #include <linux/ktime.h> 24fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2722698aa2SShawn Guo #include <linux/of.h> 2822698aa2SShawn Guo #include <linux/of_device.h> 29e32a9f8fSSachin Kamat #include <linux/io.h> 30b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 31ab4382d2SGreg Kroah-Hartman 32ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 33b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 34ab4382d2SGreg Kroah-Hartman 3558362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3658362d5bSUwe Kleine-König 37ab4382d2SGreg Kroah-Hartman /* Register definitions */ 38ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 39ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 40ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 41ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 42ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 43ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 44ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 45ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 46ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 47ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 48ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 49ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 50ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 51ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 52fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 53fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 54fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 55ab4382d2SGreg Kroah-Hartman 56ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 5755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 58ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 59ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 60ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 61ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 62ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 63ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 66ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 67ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 68ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 69b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 71302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 72ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 76302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 77fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 78b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 81ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 83ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 95ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 96ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 97ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 101b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10527e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 106fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 110ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 111ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 115b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1227be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 123ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 125ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 126ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 127ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 128ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 129ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 130ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 131ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13386a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13427e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 136ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 137ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 138ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 139ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 140ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14290ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14390ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14690ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 149ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 150ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 151ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 152ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 153ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 154ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 155ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 156ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 157ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 158ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 159ab4382d2SGreg Kroah-Hartman 160ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 161ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 162ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 163ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 164ab4382d2SGreg Kroah-Hartman 165ab4382d2SGreg Kroah-Hartman /* 166ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 167ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 168ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 169ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 170ab4382d2SGreg Kroah-Hartman */ 171ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 172ab4382d2SGreg Kroah-Hartman 173ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 174ab4382d2SGreg Kroah-Hartman 175ab4382d2SGreg Kroah-Hartman #define UART_NR 8 176ab4382d2SGreg Kroah-Hartman 177f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 178fe6b540aSShawn Guo enum imx_uart_type { 179fe6b540aSShawn Guo IMX1_UART, 180fe6b540aSShawn Guo IMX21_UART, 1811c06bde6SMartyn Welch IMX53_UART, 182a496e628SHuang Shijie IMX6Q_UART, 183fe6b540aSShawn Guo }; 184fe6b540aSShawn Guo 185fe6b540aSShawn Guo /* device type dependent stuff */ 186fe6b540aSShawn Guo struct imx_uart_data { 187fe6b540aSShawn Guo unsigned uts_reg; 188fe6b540aSShawn Guo enum imx_uart_type devtype; 189fe6b540aSShawn Guo }; 190fe6b540aSShawn Guo 191cb1a6092SUwe Kleine-König enum imx_tx_state { 192cb1a6092SUwe Kleine-König OFF, 193cb1a6092SUwe Kleine-König WAIT_AFTER_RTS, 194cb1a6092SUwe Kleine-König SEND, 195cb1a6092SUwe Kleine-König WAIT_AFTER_SEND, 196cb1a6092SUwe Kleine-König }; 197cb1a6092SUwe Kleine-König 198ab4382d2SGreg Kroah-Hartman struct imx_port { 199ab4382d2SGreg Kroah-Hartman struct uart_port port; 200ab4382d2SGreg Kroah-Hartman struct timer_list timer; 201ab4382d2SGreg Kroah-Hartman unsigned int old_status; 202ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2037b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20420ff2fe6SHuang Shijie unsigned int dte_mode:1; 2055a08a487SGeorge Hilliard unsigned int inverted_tx:1; 2065a08a487SGeorge Hilliard unsigned int inverted_rx:1; 2073a9465faSSascha Hauer struct clk *clk_ipg; 2083a9465faSSascha Hauer struct clk *clk_per; 2097d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 210b4cdc8f6SHuang Shijie 21158362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21258362d5bSUwe Kleine-König 2133a0ab62fSUwe Kleine-König /* shadow registers */ 2143a0ab62fSUwe Kleine-König unsigned int ucr1; 2153a0ab62fSUwe Kleine-König unsigned int ucr2; 2163a0ab62fSUwe Kleine-König unsigned int ucr3; 2173a0ab62fSUwe Kleine-König unsigned int ucr4; 2183a0ab62fSUwe Kleine-König unsigned int ufcr; 2193a0ab62fSUwe Kleine-König 220b4cdc8f6SHuang Shijie /* DMA fields */ 221b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 224b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 225b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 226b4cdc8f6SHuang Shijie void *rx_buf; 2279d297239SNandor Han struct circ_buf rx_ring; 2289d297239SNandor Han unsigned int rx_periods; 2299d297239SNandor Han dma_cookie_t rx_cookie; 2307cb92fd2SHuang Shijie unsigned int tx_bytes; 231b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 23290bb6bd3SShenwei Wang unsigned int saved_reg[10]; 233c868cbb7SEduardo Valentin bool context_saved; 234cb1a6092SUwe Kleine-König 235cb1a6092SUwe Kleine-König enum imx_tx_state tx_state; 236bd78ecd6SAhmad Fatoum struct hrtimer trigger_start_tx; 237bd78ecd6SAhmad Fatoum struct hrtimer trigger_stop_tx; 238ab4382d2SGreg Kroah-Hartman }; 239ab4382d2SGreg Kroah-Hartman 2400ad5a814SDirk Behme struct imx_port_ucrs { 2410ad5a814SDirk Behme unsigned int ucr1; 2420ad5a814SDirk Behme unsigned int ucr2; 2430ad5a814SDirk Behme unsigned int ucr3; 2440ad5a814SDirk Behme }; 2450ad5a814SDirk Behme 246fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 247fe6b540aSShawn Guo [IMX1_UART] = { 248fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 249fe6b540aSShawn Guo .devtype = IMX1_UART, 250fe6b540aSShawn Guo }, 251fe6b540aSShawn Guo [IMX21_UART] = { 252fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 253fe6b540aSShawn Guo .devtype = IMX21_UART, 254fe6b540aSShawn Guo }, 2551c06bde6SMartyn Welch [IMX53_UART] = { 2561c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2571c06bde6SMartyn Welch .devtype = IMX53_UART, 2581c06bde6SMartyn Welch }, 259a496e628SHuang Shijie [IMX6Q_UART] = { 260a496e628SHuang Shijie .uts_reg = IMX21_UTS, 261a496e628SHuang Shijie .devtype = IMX6Q_UART, 262a496e628SHuang Shijie }, 263fe6b540aSShawn Guo }; 264fe6b540aSShawn Guo 265ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 266a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2671c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 26822698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 26922698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27022698aa2SShawn Guo { /* sentinel */ } 27122698aa2SShawn Guo }; 27222698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27322698aa2SShawn Guo 27427c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 27527c84426SUwe Kleine-König { 2763a0ab62fSUwe Kleine-König switch (offset) { 2773a0ab62fSUwe Kleine-König case UCR1: 2783a0ab62fSUwe Kleine-König sport->ucr1 = val; 2793a0ab62fSUwe Kleine-König break; 2803a0ab62fSUwe Kleine-König case UCR2: 2813a0ab62fSUwe Kleine-König sport->ucr2 = val; 2823a0ab62fSUwe Kleine-König break; 2833a0ab62fSUwe Kleine-König case UCR3: 2843a0ab62fSUwe Kleine-König sport->ucr3 = val; 2853a0ab62fSUwe Kleine-König break; 2863a0ab62fSUwe Kleine-König case UCR4: 2873a0ab62fSUwe Kleine-König sport->ucr4 = val; 2883a0ab62fSUwe Kleine-König break; 2893a0ab62fSUwe Kleine-König case UFCR: 2903a0ab62fSUwe Kleine-König sport->ufcr = val; 2913a0ab62fSUwe Kleine-König break; 2923a0ab62fSUwe Kleine-König default: 2933a0ab62fSUwe Kleine-König break; 2943a0ab62fSUwe Kleine-König } 29527c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 29627c84426SUwe Kleine-König } 29727c84426SUwe Kleine-König 29827c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 29927c84426SUwe Kleine-König { 3003a0ab62fSUwe Kleine-König switch (offset) { 3013a0ab62fSUwe Kleine-König case UCR1: 3023a0ab62fSUwe Kleine-König return sport->ucr1; 3033a0ab62fSUwe Kleine-König break; 3043a0ab62fSUwe Kleine-König case UCR2: 3053a0ab62fSUwe Kleine-König /* 3063a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3073a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 308728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 309728e74a4SUwe Kleine-König * conditionally. 3103a0ab62fSUwe Kleine-König */ 3110aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3123a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3133a0ab62fSUwe Kleine-König return sport->ucr2; 3143a0ab62fSUwe Kleine-König break; 3153a0ab62fSUwe Kleine-König case UCR3: 3163a0ab62fSUwe Kleine-König return sport->ucr3; 3173a0ab62fSUwe Kleine-König break; 3183a0ab62fSUwe Kleine-König case UCR4: 3193a0ab62fSUwe Kleine-König return sport->ucr4; 3203a0ab62fSUwe Kleine-König break; 3213a0ab62fSUwe Kleine-König case UFCR: 3223a0ab62fSUwe Kleine-König return sport->ufcr; 3233a0ab62fSUwe Kleine-König break; 3243a0ab62fSUwe Kleine-König default: 32527c84426SUwe Kleine-König return readl(sport->port.membase + offset); 32627c84426SUwe Kleine-König } 3273a0ab62fSUwe Kleine-König } 32827c84426SUwe Kleine-König 3299d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 330fe6b540aSShawn Guo { 331fe6b540aSShawn Guo return sport->devdata->uts_reg; 332fe6b540aSShawn Guo } 333fe6b540aSShawn Guo 3349d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 335fe6b540aSShawn Guo { 336fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 337fe6b540aSShawn Guo } 338fe6b540aSShawn Guo 3399d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 340fe6b540aSShawn Guo { 341fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 342fe6b540aSShawn Guo } 343fe6b540aSShawn Guo 3449d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3451c06bde6SMartyn Welch { 3461c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3471c06bde6SMartyn Welch } 3481c06bde6SMartyn Welch 3499d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 350a496e628SHuang Shijie { 351a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 352a496e628SHuang Shijie } 353ab4382d2SGreg Kroah-Hartman /* 35444a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 35544a75411Sfabio.estevam@freescale.com */ 3560db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 3579d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 35844a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 35944a75411Sfabio.estevam@freescale.com { 36044a75411Sfabio.estevam@freescale.com /* save control registers */ 36127c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 36227c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 36327c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 36444a75411Sfabio.estevam@freescale.com } 36544a75411Sfabio.estevam@freescale.com 3669d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 36744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36844a75411Sfabio.estevam@freescale.com { 36944a75411Sfabio.estevam@freescale.com /* restore control registers */ 37027c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 37127c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 37227c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 37344a75411Sfabio.estevam@freescale.com } 374e8bfa760SFabio Estevam #endif 37544a75411Sfabio.estevam@freescale.com 3764e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3779d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 37858362d5bSUwe Kleine-König { 379bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38058362d5bSUwe Kleine-König 381a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 382a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 38358362d5bSUwe Kleine-König } 38458362d5bSUwe Kleine-König 3854e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3869d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 38758362d5bSUwe Kleine-König { 388bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 389bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39058362d5bSUwe Kleine-König 391a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 392a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39358362d5bSUwe Kleine-König } 39458362d5bSUwe Kleine-König 395bd78ecd6SAhmad Fatoum static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 396bd78ecd6SAhmad Fatoum { 397f751ae1cSJiri Slaby hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 398bd78ecd6SAhmad Fatoum } 399bd78ecd6SAhmad Fatoum 4006aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4019d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 40276821e22SUwe Kleine-König { 40376821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 40476821e22SUwe Kleine-König unsigned int ucr1, ucr2; 40576821e22SUwe Kleine-König 40676821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 40776821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 40876821e22SUwe Kleine-König 40976821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41076821e22SUwe Kleine-König 41176821e22SUwe Kleine-König if (sport->dma_is_enabled) { 41276821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 41376821e22SUwe Kleine-König } else { 41476821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 41581ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 41676821e22SUwe Kleine-König } 41776821e22SUwe Kleine-König 41876821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 41976821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42076821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42176821e22SUwe Kleine-König } 42276821e22SUwe Kleine-König 42376821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4249d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 425ab4382d2SGreg Kroah-Hartman { 426ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 427cb1a6092SUwe Kleine-König u32 ucr1, ucr4, usr2; 428cb1a6092SUwe Kleine-König 429cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) 430cb1a6092SUwe Kleine-König return; 431ab4382d2SGreg Kroah-Hartman 4329ce4f8f3SGreg Kroah-Hartman /* 4339ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4349ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4359ce4f8f3SGreg Kroah-Hartman */ 436686351f3SUwe Kleine-König if (sport->dma_is_txing) 4379ce4f8f3SGreg Kroah-Hartman return; 438b4cdc8f6SHuang Shijie 4394444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 440c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 44117b8f2a3SUwe Kleine-König 442cb1a6092SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 443cb1a6092SUwe Kleine-König if (!(usr2 & USR2_TXDC)) { 444cb1a6092SUwe Kleine-König /* The shifter is still busy, so retry once TC triggers */ 445cb1a6092SUwe Kleine-König return; 446cb1a6092SUwe Kleine-König } 447cb1a6092SUwe Kleine-König 448cb1a6092SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 449cb1a6092SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 450cb1a6092SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 451cb1a6092SUwe Kleine-König 452cb1a6092SUwe Kleine-König /* in rs485 mode disable transmitter */ 453cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 454cb1a6092SUwe Kleine-König if (sport->tx_state == SEND) { 455cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_SEND; 456bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_stop_tx, 457bd78ecd6SAhmad Fatoum port->rs485.delay_rts_after_send); 458bd78ecd6SAhmad Fatoum return; 459cb1a6092SUwe Kleine-König } 460cb1a6092SUwe Kleine-König 461cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS || 462bd78ecd6SAhmad Fatoum sport->tx_state == WAIT_AFTER_SEND) { 463cb1a6092SUwe Kleine-König u32 ucr2; 464cb1a6092SUwe Kleine-König 465bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_start_tx); 466cb1a6092SUwe Kleine-König 467cb1a6092SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 46817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4699d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4701a613626SFabio Estevam else 4719d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4724444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 47317b8f2a3SUwe Kleine-König 4749d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 47576821e22SUwe Kleine-König 476cb1a6092SUwe Kleine-König sport->tx_state = OFF; 477cb1a6092SUwe Kleine-König } 478cb1a6092SUwe Kleine-König } else { 479cb1a6092SUwe Kleine-König sport->tx_state = OFF; 48017b8f2a3SUwe Kleine-König } 481ab4382d2SGreg Kroah-Hartman } 482ab4382d2SGreg Kroah-Hartman 4836aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4849d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 485ab4382d2SGreg Kroah-Hartman { 486ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4874444dcf1SUwe Kleine-König u32 ucr1, ucr2; 488ab4382d2SGreg Kroah-Hartman 4894444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 49076821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 49176821e22SUwe Kleine-König 49276821e22SUwe Kleine-König if (sport->dma_is_enabled) { 49376821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 49476821e22SUwe Kleine-König } else { 49576821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 49681ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 49776821e22SUwe Kleine-König } 49876821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 49976821e22SUwe Kleine-König 50076821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 50176821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 502ab4382d2SGreg Kroah-Hartman } 503ab4382d2SGreg Kroah-Hartman 5046aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5059d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 506ab4382d2SGreg Kroah-Hartman { 507ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 508ab4382d2SGreg Kroah-Hartman 509ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 51058362d5bSUwe Kleine-König 51158362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 512ab4382d2SGreg Kroah-Hartman } 513ab4382d2SGreg Kroah-Hartman 5149d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 5156aed2a88SUwe Kleine-König 5166aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5179d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 518ab4382d2SGreg Kroah-Hartman { 519ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 520ab4382d2SGreg Kroah-Hartman 5215e42e9a3SPeter Hurley if (sport->port.x_char) { 5225e42e9a3SPeter Hurley /* Send next char */ 52327c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5247e2fb5aaSJiada Wang sport->port.icount.tx++; 5257e2fb5aaSJiada Wang sport->port.x_char = 0; 5265e42e9a3SPeter Hurley return; 5275e42e9a3SPeter Hurley } 5285e42e9a3SPeter Hurley 5295e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5309d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5315e42e9a3SPeter Hurley return; 5325e42e9a3SPeter Hurley } 5335e42e9a3SPeter Hurley 53491a1a909SJiada Wang if (sport->dma_is_enabled) { 5354444dcf1SUwe Kleine-König u32 ucr1; 53691a1a909SJiada Wang /* 53791a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 53891a1a909SJiada Wang * and the TX IRQ is disabled. 53991a1a909SJiada Wang **/ 5404444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 541c514a6f8SSergey Organov ucr1 &= ~UCR1_TRDYEN; 54291a1a909SJiada Wang if (sport->dma_is_txing) { 5434444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5444444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 54591a1a909SJiada Wang } else { 5464444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5479d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 54891a1a909SJiada Wang } 54991a1a909SJiada Wang 5505aabd3b0SIan Jamison return; 5510c549223SUwe Kleine-König } 5525aabd3b0SIan Jamison 5535aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5549d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 555ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 556ab4382d2SGreg Kroah-Hartman * out the port here */ 55727c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 558ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 559ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 560ab4382d2SGreg Kroah-Hartman } 561ab4382d2SGreg Kroah-Hartman 562ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 563ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 564ab4382d2SGreg Kroah-Hartman 565ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5669d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 567ab4382d2SGreg Kroah-Hartman } 568ab4382d2SGreg Kroah-Hartman 5699d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 570b4cdc8f6SHuang Shijie { 571b4cdc8f6SHuang Shijie struct imx_port *sport = data; 572b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 573b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 574b4cdc8f6SHuang Shijie unsigned long flags; 5754444dcf1SUwe Kleine-König u32 ucr1; 576b4cdc8f6SHuang Shijie 57742f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 57842f752b3SDirk Behme 579b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 580b4cdc8f6SHuang Shijie 5814444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5824444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 584a2c718ceSDirk Behme 58542f752b3SDirk Behme /* update the stat */ 58642f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 58742f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 58842f752b3SDirk Behme 58942f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 59042f752b3SDirk Behme 591b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 592b4cdc8f6SHuang Shijie 593d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 594b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5959ce4f8f3SGreg Kroah-Hartman 5960bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5979d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 59818665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 59918665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 60018665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 60118665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 60218665414SUwe Kleine-König } 60364432a85SUwe Kleine-König 6040bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 605b4cdc8f6SHuang Shijie } 606b4cdc8f6SHuang Shijie 6076aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6089d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 609b4cdc8f6SHuang Shijie { 610b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 611b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 612b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 613b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 614b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 61518665414SUwe Kleine-König u32 ucr1, ucr4; 616b4cdc8f6SHuang Shijie int ret; 617b4cdc8f6SHuang Shijie 61842f752b3SDirk Behme if (sport->dma_is_txing) 619b4cdc8f6SHuang Shijie return; 620b4cdc8f6SHuang Shijie 62118665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 62218665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 62318665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 62418665414SUwe Kleine-König 625b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 626b4cdc8f6SHuang Shijie 627f7670783SFugang Duan if (xmit->tail < xmit->head || xmit->head == 0) { 6287942f857SDirk Behme sport->dma_tx_nents = 1; 6297942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6307942f857SDirk Behme } else { 631b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 632b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 633b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 634b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 635b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 636b4cdc8f6SHuang Shijie } 637b4cdc8f6SHuang Shijie 638b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 639b4cdc8f6SHuang Shijie if (ret == 0) { 640b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 641b4cdc8f6SHuang Shijie return; 642b4cdc8f6SHuang Shijie } 643596fd8dfSPeng Fan desc = dmaengine_prep_slave_sg(chan, sgl, ret, 644b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 645b4cdc8f6SHuang Shijie if (!desc) { 64624649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 64724649821SDirk Behme DMA_TO_DEVICE); 648b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 649b4cdc8f6SHuang Shijie return; 650b4cdc8f6SHuang Shijie } 6519d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 652b4cdc8f6SHuang Shijie desc->callback_param = sport; 653b4cdc8f6SHuang Shijie 654b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 655b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 656a2c718ceSDirk Behme 6574444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6584444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 660a2c718ceSDirk Behme 661b4cdc8f6SHuang Shijie /* fire it */ 662b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 663b4cdc8f6SHuang Shijie dmaengine_submit(desc); 664b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 665b4cdc8f6SHuang Shijie return; 666b4cdc8f6SHuang Shijie } 667b4cdc8f6SHuang Shijie 6686aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6699d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 670ab4382d2SGreg Kroah-Hartman { 671ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6724444dcf1SUwe Kleine-König u32 ucr1; 673ab4382d2SGreg Kroah-Hartman 67448669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 67548669b69SUwe Kleine-König return; 67648669b69SUwe Kleine-König 677cb1a6092SUwe Kleine-König /* 678cb1a6092SUwe Kleine-König * We cannot simply do nothing here if sport->tx_state == SEND already 679cb1a6092SUwe Kleine-König * because UCR1_TXMPTYEN might already have been cleared in 680cb1a6092SUwe Kleine-König * imx_uart_stop_tx(), but tx_state is still SEND. 681cb1a6092SUwe Kleine-König */ 6824444dcf1SUwe Kleine-König 683cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 684cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) { 685cb1a6092SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2); 68617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6879d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 6881a613626SFabio Estevam else 6899d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 6904444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 69117b8f2a3SUwe Kleine-König 69276821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 6939d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 69476821e22SUwe Kleine-König 695cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_RTS; 696bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_start_tx, 697bd78ecd6SAhmad Fatoum port->rs485.delay_rts_before_send); 698bd78ecd6SAhmad Fatoum return; 699cb1a6092SUwe Kleine-König } 700cb1a6092SUwe Kleine-König 701bd78ecd6SAhmad Fatoum if (sport->tx_state == WAIT_AFTER_SEND 702bd78ecd6SAhmad Fatoum || sport->tx_state == WAIT_AFTER_RTS) { 703cb1a6092SUwe Kleine-König 704bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_stop_tx); 705bd78ecd6SAhmad Fatoum 70618665414SUwe Kleine-König /* 707cb1a6092SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA 708cb1a6092SUwe Kleine-König * is off. In the DMA case this is done in the 709cb1a6092SUwe Kleine-König * tx-callback. 71018665414SUwe Kleine-König */ 71118665414SUwe Kleine-König if (!sport->dma_is_enabled) { 71218665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 7134444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 7144444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 71517b8f2a3SUwe Kleine-König } 716cb1a6092SUwe Kleine-König 717cb1a6092SUwe Kleine-König sport->tx_state = SEND; 718cb1a6092SUwe Kleine-König } 719cb1a6092SUwe Kleine-König } else { 720cb1a6092SUwe Kleine-König sport->tx_state = SEND; 72118665414SUwe Kleine-König } 72217b8f2a3SUwe Kleine-König 723b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 7244444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 725c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 726b4cdc8f6SHuang Shijie } 727ab4382d2SGreg Kroah-Hartman 728b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 72991a1a909SJiada Wang if (sport->port.x_char) { 73091a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 73191a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 7324444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 7334444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 734c514a6f8SSergey Organov ucr1 |= UCR1_TRDYEN; 7354444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 73691a1a909SJiada Wang return; 73791a1a909SJiada Wang } 73891a1a909SJiada Wang 7395e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 7405e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7419d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 742b4cdc8f6SHuang Shijie return; 743b4cdc8f6SHuang Shijie } 744ab4382d2SGreg Kroah-Hartman } 745ab4382d2SGreg Kroah-Hartman 746101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 747ab4382d2SGreg Kroah-Hartman { 748ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7494444dcf1SUwe Kleine-König u32 usr1; 750ab4382d2SGreg Kroah-Hartman 75127c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7524444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7534444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 754ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 755ab4382d2SGreg Kroah-Hartman 756ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 757ab4382d2SGreg Kroah-Hartman } 758ab4382d2SGreg Kroah-Hartman 759101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 760101aa46bSUwe Kleine-König { 761101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 762101aa46bSUwe Kleine-König irqreturn_t ret; 763101aa46bSUwe Kleine-König 764101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 765101aa46bSUwe Kleine-König 766101aa46bSUwe Kleine-König ret = __imx_uart_rtsint(irq, dev_id); 767101aa46bSUwe Kleine-König 768101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 769101aa46bSUwe Kleine-König 770101aa46bSUwe Kleine-König return ret; 771101aa46bSUwe Kleine-König } 772101aa46bSUwe Kleine-König 7739d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 774ab4382d2SGreg Kroah-Hartman { 775ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 776ab4382d2SGreg Kroah-Hartman 777c974991dSjun qian spin_lock(&sport->port.lock); 7789d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 779c974991dSjun qian spin_unlock(&sport->port.lock); 780ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 781ab4382d2SGreg Kroah-Hartman } 782ab4382d2SGreg Kroah-Hartman 783101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 784ab4382d2SGreg Kroah-Hartman { 785ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 786ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 78792a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 788ab4382d2SGreg Kroah-Hartman 78927c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 7904444dcf1SUwe Kleine-König u32 usr2; 7914444dcf1SUwe Kleine-König 792ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 793ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 794ab4382d2SGreg Kroah-Hartman 79527c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 796ab4382d2SGreg Kroah-Hartman 7974444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 7984444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 79927c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 800ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 801ab4382d2SGreg Kroah-Hartman continue; 802ab4382d2SGreg Kroah-Hartman } 803ab4382d2SGreg Kroah-Hartman 804ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 805ab4382d2SGreg Kroah-Hartman continue; 806ab4382d2SGreg Kroah-Hartman 807019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 808019dc9eaSHui Wang if (rx & URXD_BRK) 809019dc9eaSHui Wang sport->port.icount.brk++; 810019dc9eaSHui Wang else if (rx & URXD_PRERR) 811ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 812ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 813ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 814ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 815ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 816ab4382d2SGreg Kroah-Hartman 817ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 818ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 819ab4382d2SGreg Kroah-Hartman goto out; 820ab4382d2SGreg Kroah-Hartman continue; 821ab4382d2SGreg Kroah-Hartman } 822ab4382d2SGreg Kroah-Hartman 8238d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 824ab4382d2SGreg Kroah-Hartman 825019dc9eaSHui Wang if (rx & URXD_BRK) 826019dc9eaSHui Wang flg = TTY_BREAK; 827019dc9eaSHui Wang else if (rx & URXD_PRERR) 828ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 829ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 830ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 831ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 832ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 833ab4382d2SGreg Kroah-Hartman 834ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 835ab4382d2SGreg Kroah-Hartman } 836ab4382d2SGreg Kroah-Hartman 83755d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 83855d8693aSJiada Wang goto out; 83955d8693aSJiada Wang 8409b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 8419b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 842ab4382d2SGreg Kroah-Hartman } 843ab4382d2SGreg Kroah-Hartman 844ab4382d2SGreg Kroah-Hartman out: 8452e124b4aSJiri Slaby tty_flip_buffer_push(port); 846101aa46bSUwe Kleine-König 847ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 848ab4382d2SGreg Kroah-Hartman } 849ab4382d2SGreg Kroah-Hartman 850101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 851101aa46bSUwe Kleine-König { 852101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 853101aa46bSUwe Kleine-König irqreturn_t ret; 854101aa46bSUwe Kleine-König 855101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 856101aa46bSUwe Kleine-König 857101aa46bSUwe Kleine-König ret = __imx_uart_rxint(irq, dev_id); 858101aa46bSUwe Kleine-König 859101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 860101aa46bSUwe Kleine-König 861101aa46bSUwe Kleine-König return ret; 862101aa46bSUwe Kleine-König } 863101aa46bSUwe Kleine-König 8649d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 865b4cdc8f6SHuang Shijie 86666f95884SUwe Kleine-König /* 86766f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 86866f95884SUwe Kleine-König */ 8699d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 87066f95884SUwe Kleine-König { 87166f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 87227c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 87327c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 87466f95884SUwe Kleine-König 87566f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 87666f95884SUwe Kleine-König tmp |= TIOCM_CTS; 87766f95884SUwe Kleine-König 87866f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 8794b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 88066f95884SUwe Kleine-König tmp |= TIOCM_CAR; 88166f95884SUwe Kleine-König 88266f95884SUwe Kleine-König if (sport->dte_mode) 88327c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 88466f95884SUwe Kleine-König tmp |= TIOCM_RI; 88566f95884SUwe Kleine-König 88666f95884SUwe Kleine-König return tmp; 88766f95884SUwe Kleine-König } 88866f95884SUwe Kleine-König 88966f95884SUwe Kleine-König /* 89066f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 89166f95884SUwe Kleine-König */ 8929d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 89366f95884SUwe Kleine-König { 89466f95884SUwe Kleine-König unsigned int status, changed; 89566f95884SUwe Kleine-König 8969d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 89766f95884SUwe Kleine-König changed = status ^ sport->old_status; 89866f95884SUwe Kleine-König 89966f95884SUwe Kleine-König if (changed == 0) 90066f95884SUwe Kleine-König return; 90166f95884SUwe Kleine-König 90266f95884SUwe Kleine-König sport->old_status = status; 90366f95884SUwe Kleine-König 90466f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 90566f95884SUwe Kleine-König sport->port.icount.rng++; 90666f95884SUwe Kleine-König if (changed & TIOCM_DSR) 90766f95884SUwe Kleine-König sport->port.icount.dsr++; 90866f95884SUwe Kleine-König if (changed & TIOCM_CAR) 90966f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 91066f95884SUwe Kleine-König if (changed & TIOCM_CTS) 91166f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 91266f95884SUwe Kleine-König 91366f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 91466f95884SUwe Kleine-König } 91566f95884SUwe Kleine-König 9169d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 917ab4382d2SGreg Kroah-Hartman { 918ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 91943776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 9204d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 921ab4382d2SGreg Kroah-Hartman 922*9baedb7bSJohan Hovold spin_lock(&sport->port.lock); 923101aa46bSUwe Kleine-König 92427c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 92527c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 92627c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 92727c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 92827c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 92927c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 930ab4382d2SGreg Kroah-Hartman 93143776896SUwe Kleine-König /* 93243776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 93343776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 93443776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 93543776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 93643776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 93743776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 93843776896SUwe Kleine-König */ 93943776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 94043776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 94143776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 94243776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 943c514a6f8SSergey Organov if ((ucr1 & UCR1_TRDYEN) == 0) 94443776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 94543776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 94643776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 94743776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 94843776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 94943776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 95043776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 95143776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 95243776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 95343776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 95443776896SUwe Kleine-König usr2 &= ~USR2_ORE; 95543776896SUwe Kleine-König 95643776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 957d1d996afSMatthias Schiffer imx_uart_writel(sport, USR1_AGTIM, USR1); 958d1d996afSMatthias Schiffer 959101aa46bSUwe Kleine-König __imx_uart_rxint(irq, dev_id); 9604d845a62SUwe Kleine-König ret = IRQ_HANDLED; 961b4cdc8f6SHuang Shijie } 962ab4382d2SGreg Kroah-Hartman 96343776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 964101aa46bSUwe Kleine-König imx_uart_transmit_buffer(sport); 9654d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9664d845a62SUwe Kleine-König } 967ab4382d2SGreg Kroah-Hartman 9680399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 96927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 97027e16501SUwe Kleine-König 9719d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 97227e16501SUwe Kleine-König 97327e16501SUwe Kleine-König ret = IRQ_HANDLED; 97427e16501SUwe Kleine-König } 97527e16501SUwe Kleine-König 9760399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 977101aa46bSUwe Kleine-König __imx_uart_rtsint(irq, dev_id); 9784d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9794d845a62SUwe Kleine-König } 980ab4382d2SGreg Kroah-Hartman 9810399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 98227c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 9834d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9844d845a62SUwe Kleine-König } 985db1a9b55SFabio Estevam 9860399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 987f1f836e4SAlexander Stein sport->port.icount.overrun++; 98827c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 9894d845a62SUwe Kleine-König ret = IRQ_HANDLED; 990f1f836e4SAlexander Stein } 991f1f836e4SAlexander Stein 992*9baedb7bSJohan Hovold spin_unlock(&sport->port.lock); 993101aa46bSUwe Kleine-König 9944d845a62SUwe Kleine-König return ret; 995ab4382d2SGreg Kroah-Hartman } 996ab4382d2SGreg Kroah-Hartman 997ab4382d2SGreg Kroah-Hartman /* 998ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 999ab4382d2SGreg Kroah-Hartman */ 10009d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 1001ab4382d2SGreg Kroah-Hartman { 1002ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10031ce43e58SHuang Shijie unsigned int ret; 1004ab4382d2SGreg Kroah-Hartman 100527c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 10061ce43e58SHuang Shijie 10071ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 1008686351f3SUwe Kleine-König if (sport->dma_is_txing) 10091ce43e58SHuang Shijie ret = 0; 10101ce43e58SHuang Shijie 10111ce43e58SHuang Shijie return ret; 1012ab4382d2SGreg Kroah-Hartman } 1013ab4382d2SGreg Kroah-Hartman 10146aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10159d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 101658362d5bSUwe Kleine-König { 101758362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 10189d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 101958362d5bSUwe Kleine-König 102058362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 102158362d5bSUwe Kleine-König 102258362d5bSUwe Kleine-König return ret; 102358362d5bSUwe Kleine-König } 102458362d5bSUwe Kleine-König 10256aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10269d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1027ab4382d2SGreg Kroah-Hartman { 1028ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10294444dcf1SUwe Kleine-König u32 ucr3, uts; 1030ab4382d2SGreg Kroah-Hartman 103117b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 10324444dcf1SUwe Kleine-König u32 ucr2; 10334444dcf1SUwe Kleine-König 1034197540dcSSergey Organov /* 1035197540dcSSergey Organov * Turn off autoRTS if RTS is lowered and restore autoRTS 1036197540dcSSergey Organov * setting if RTS is raised. 1037197540dcSSergey Organov */ 10384444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 10394444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1040197540dcSSergey Organov if (mctrl & TIOCM_RTS) { 1041197540dcSSergey Organov ucr2 |= UCR2_CTS; 1042197540dcSSergey Organov /* 1043197540dcSSergey Organov * UCR2_IRTS is unset if and only if the port is 1044197540dcSSergey Organov * configured for CRTSCTS, so we use inverted UCR2_IRTS 1045197540dcSSergey Organov * to get the state to restore to. 1046197540dcSSergey Organov */ 1047197540dcSSergey Organov if (!(ucr2 & UCR2_IRTS)) 1048197540dcSSergey Organov ucr2 |= UCR2_CTSC; 1049197540dcSSergey Organov } 10504444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 105117b8f2a3SUwe Kleine-König } 10526b471a98SHuang Shijie 10534444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 105490ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 10554444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 10564444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 105790ebc483SUwe Kleine-König 10589d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 10596b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 10604444dcf1SUwe Kleine-König uts |= UTS_LOOP; 10619d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 106258362d5bSUwe Kleine-König 106358362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 1064ab4382d2SGreg Kroah-Hartman } 1065ab4382d2SGreg Kroah-Hartman 1066ab4382d2SGreg Kroah-Hartman /* 1067ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 1068ab4382d2SGreg Kroah-Hartman */ 10699d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1070ab4382d2SGreg Kroah-Hartman { 1071ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10724444dcf1SUwe Kleine-König unsigned long flags; 10734444dcf1SUwe Kleine-König u32 ucr1; 1074ab4382d2SGreg Kroah-Hartman 1075ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1076ab4382d2SGreg Kroah-Hartman 10774444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1078ab4382d2SGreg Kroah-Hartman 1079ab4382d2SGreg Kroah-Hartman if (break_state != 0) 10804444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1081ab4382d2SGreg Kroah-Hartman 10824444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1083ab4382d2SGreg Kroah-Hartman 1084ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1085ab4382d2SGreg Kroah-Hartman } 1086ab4382d2SGreg Kroah-Hartman 1087cc568849SUwe Kleine-König /* 1088cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1089cc568849SUwe Kleine-König * modem status signals. 1090cc568849SUwe Kleine-König */ 10919d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1092cc568849SUwe Kleine-König { 1093e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1094cc568849SUwe Kleine-König unsigned long flags; 1095cc568849SUwe Kleine-König 1096cc568849SUwe Kleine-König if (sport->port.state) { 1097cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 10989d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1099cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1100cc568849SUwe Kleine-König 1101cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1102cc568849SUwe Kleine-König } 1103cc568849SUwe Kleine-König } 1104cc568849SUwe Kleine-König 1105b4cdc8f6SHuang Shijie /* 1106905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1107b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1108905c0decSLucas Stach * [2] the aging timer expires 1109b4cdc8f6SHuang Shijie * 1110905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1111905c0decSLucas Stach * for at least 8 byte durations. 1112b4cdc8f6SHuang Shijie */ 11139d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1114b4cdc8f6SHuang Shijie { 1115b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1116b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1117b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 11187cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1119b4cdc8f6SHuang Shijie struct dma_tx_state state; 11209d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1121b4cdc8f6SHuang Shijie enum dma_status status; 11229d297239SNandor Han unsigned int w_bytes = 0; 11239d297239SNandor Han unsigned int r_bytes; 11249d297239SNandor Han unsigned int bd_size; 1125b4cdc8f6SHuang Shijie 1126fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1127392bceedSPhilipp Zabel 11289d297239SNandor Han if (status == DMA_ERROR) { 11299d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 11309d297239SNandor Han return; 11319d297239SNandor Han } 1132b4cdc8f6SHuang Shijie 11339b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1134976b39cdSLucas Stach 1135976b39cdSLucas Stach /* 11369d297239SNandor Han * The state-residue variable represents the empty space 11379d297239SNandor Han * relative to the entire buffer. Taking this in consideration 11389d297239SNandor Han * the head is always calculated base on the buffer total 11399d297239SNandor Han * length - DMA transaction residue. The UART script from the 11409d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 11419d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 11429d297239SNandor Han * Taking this in consideration the tail is always at the 11439d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1144976b39cdSLucas Stach */ 11459d297239SNandor Han 11469d297239SNandor Han /* Calculate the head */ 11479d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 11489d297239SNandor Han 11499d297239SNandor Han /* Calculate the tail. */ 11509d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 11519d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 11529d297239SNandor Han 11539d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 11549d297239SNandor Han rx_ring->head > rx_ring->tail) { 11559d297239SNandor Han 11569d297239SNandor Han /* Move data from tail to head */ 11579d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 11589d297239SNandor Han 11599d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 11609d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 11619d297239SNandor Han DMA_FROM_DEVICE); 11629d297239SNandor Han 11639d297239SNandor Han w_bytes = tty_insert_flip_string(port, 11649d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 11659d297239SNandor Han 11669d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 11679d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 11689d297239SNandor Han DMA_FROM_DEVICE); 11699d297239SNandor Han 11709d297239SNandor Han if (w_bytes != r_bytes) 11719d297239SNandor Han sport->port.icount.buf_overrun++; 11729d297239SNandor Han 11739d297239SNandor Han sport->port.icount.rx += w_bytes; 11749d297239SNandor Han } else { 11759d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11769d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1177ee5e7c10SRobin Gong } 11789d297239SNandor Han } 11799d297239SNandor Han 11809d297239SNandor Han if (w_bytes) { 11819d297239SNandor Han tty_flip_buffer_push(port); 11829d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 11839d297239SNandor Han } 11849d297239SNandor Han } 11859d297239SNandor Han 1186351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 118776c38d30SPhilipp Puschmann #define RX_DMA_PERIODS 16 118876c38d30SPhilipp Puschmann #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4) 1189351ea50dSGreg Kroah-Hartman 11909d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1191b4cdc8f6SHuang Shijie { 1192b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1193b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1194b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1195b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1196b4cdc8f6SHuang Shijie int ret; 1197b4cdc8f6SHuang Shijie 11989d297239SNandor Han sport->rx_ring.head = 0; 11999d297239SNandor Han sport->rx_ring.tail = 0; 1200351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 12019d297239SNandor Han 1202351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1203b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1204b4cdc8f6SHuang Shijie if (ret == 0) { 1205b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1206b4cdc8f6SHuang Shijie return -EINVAL; 1207b4cdc8f6SHuang Shijie } 12089d297239SNandor Han 12099d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 12109d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 12119d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 12129d297239SNandor Han 1213b4cdc8f6SHuang Shijie if (!desc) { 121424649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1215b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1216b4cdc8f6SHuang Shijie return -EINVAL; 1217b4cdc8f6SHuang Shijie } 12189d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1219b4cdc8f6SHuang Shijie desc->callback_param = sport; 1220b4cdc8f6SHuang Shijie 1221b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 12224139fd76SRomain Perier sport->dma_is_rxing = 1; 12239d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1224b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1225b4cdc8f6SHuang Shijie return 0; 1226b4cdc8f6SHuang Shijie } 1227b4cdc8f6SHuang Shijie 12289d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 122941d98b5dSNandor Han { 123045ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 12314444dcf1SUwe Kleine-König u32 usr1, usr2; 123241d98b5dSNandor Han 12334444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 12344444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 123541d98b5dSNandor Han 12364444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 123741d98b5dSNandor Han sport->port.icount.brk++; 123827c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 123945ca673eSTroy Kisky uart_handle_break(&sport->port); 124045ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 124145ca673eSTroy Kisky sport->port.icount.buf_overrun++; 124245ca673eSTroy Kisky tty_flip_buffer_push(port); 124345ca673eSTroy Kisky } else { 12444444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 124541d98b5dSNandor Han sport->port.icount.frame++; 124627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 12474444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 124841d98b5dSNandor Han sport->port.icount.parity++; 124927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 125041d98b5dSNandor Han } 125145ca673eSTroy Kisky } 125241d98b5dSNandor Han 12534444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 125441d98b5dSNandor Han sport->port.icount.overrun++; 125527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 125641d98b5dSNandor Han } 125741d98b5dSNandor Han 125841d98b5dSNandor Han } 125941d98b5dSNandor Han 1260cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1261cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1262184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1263184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1264cc32382dSLucas Stach 12659d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1266cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1267cc32382dSLucas Stach { 1268cc32382dSLucas Stach unsigned int val; 1269cc32382dSLucas Stach 1270cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 127127c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1272cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 127327c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1274cc32382dSLucas Stach } 1275cc32382dSLucas Stach 1276b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1277b4cdc8f6SHuang Shijie { 1278b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1279e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1280b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1281b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 12829d297239SNandor Han sport->rx_cookie = -EINVAL; 1283b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1284b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1285b4cdc8f6SHuang Shijie } 1286b4cdc8f6SHuang Shijie 1287b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1288e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1289b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1290b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1291b4cdc8f6SHuang Shijie } 1292b4cdc8f6SHuang Shijie } 1293b4cdc8f6SHuang Shijie 1294b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1295b4cdc8f6SHuang Shijie { 1296b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1297b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1298b4cdc8f6SHuang Shijie int ret; 1299b4cdc8f6SHuang Shijie 1300b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1301b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1302b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1303b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1304b4cdc8f6SHuang Shijie ret = -EINVAL; 1305b4cdc8f6SHuang Shijie goto err; 1306b4cdc8f6SHuang Shijie } 1307b4cdc8f6SHuang Shijie 1308b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1309b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1310b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1311184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1312184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1313b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1314b4cdc8f6SHuang Shijie if (ret) { 1315b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1316b4cdc8f6SHuang Shijie goto err; 1317b4cdc8f6SHuang Shijie } 1318b4cdc8f6SHuang Shijie 1319f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1320b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1321b4cdc8f6SHuang Shijie ret = -ENOMEM; 1322b4cdc8f6SHuang Shijie goto err; 1323b4cdc8f6SHuang Shijie } 13249d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1325b4cdc8f6SHuang Shijie 1326b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1327b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1328b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1329b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1330b4cdc8f6SHuang Shijie ret = -EINVAL; 1331b4cdc8f6SHuang Shijie goto err; 1332b4cdc8f6SHuang Shijie } 1333b4cdc8f6SHuang Shijie 1334b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1335b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1336b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1337184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1338b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1339b4cdc8f6SHuang Shijie if (ret) { 1340b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1341b4cdc8f6SHuang Shijie goto err; 1342b4cdc8f6SHuang Shijie } 1343b4cdc8f6SHuang Shijie 1344b4cdc8f6SHuang Shijie return 0; 1345b4cdc8f6SHuang Shijie err: 1346b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1347b4cdc8f6SHuang Shijie return ret; 1348b4cdc8f6SHuang Shijie } 1349b4cdc8f6SHuang Shijie 13509d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1351b4cdc8f6SHuang Shijie { 13524444dcf1SUwe Kleine-König u32 ucr1; 1353b4cdc8f6SHuang Shijie 13549d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 135502b0abd3SUwe Kleine-König 1356b4cdc8f6SHuang Shijie /* set UCR1 */ 13574444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13584444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 13594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1360b4cdc8f6SHuang Shijie 1361b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1362b4cdc8f6SHuang Shijie } 1363b4cdc8f6SHuang Shijie 13649d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1365b4cdc8f6SHuang Shijie { 1366676a31d8SSebastian Reichel u32 ucr1; 1367b4cdc8f6SHuang Shijie 1368b4cdc8f6SHuang Shijie /* clear UCR1 */ 13694444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13704444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 13714444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1372b4cdc8f6SHuang Shijie 13739d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1374184bd70bSLucas Stach 1375b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1376b4cdc8f6SHuang Shijie } 1377b4cdc8f6SHuang Shijie 1378ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1379ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1380ab4382d2SGreg Kroah-Hartman 13819d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1382ab4382d2SGreg Kroah-Hartman { 1383ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1384458e2c82SFabio Estevam int retval, i; 13854444dcf1SUwe Kleine-König unsigned long flags; 13864238c00bSUwe Kleine-König int dma_is_inited = 0; 13875a08a487SGeorge Hilliard u32 ucr1, ucr2, ucr3, ucr4; 1388ab4382d2SGreg Kroah-Hartman 138928eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 139028eb4274SHuang Shijie if (retval) 1391cb0f0a5fSFabio Estevam return retval; 139228eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 13930c375501SHuang Shijie if (retval) { 13940c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1395cb0f0a5fSFabio Estevam return retval; 13960c375501SHuang Shijie } 139728eb4274SHuang Shijie 13989d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1399ab4382d2SGreg Kroah-Hartman 1400ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1401ab4382d2SGreg Kroah-Hartman * requesting IRQs 1402ab4382d2SGreg Kroah-Hartman */ 14034444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1404ab4382d2SGreg Kroah-Hartman 1405ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 14064444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 14074444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1408ab4382d2SGreg Kroah-Hartman 14094444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1410ab4382d2SGreg Kroah-Hartman 14117e11577eSLucas Stach /* Can we enable the DMA support? */ 14124238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 14134238c00bSUwe Kleine-König dma_is_inited = 1; 14147e11577eSLucas Stach 141553794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1416772f8991SHuang Shijie /* Reset fifo's and state machines */ 1417458e2c82SFabio Estevam i = 100; 1418458e2c82SFabio Estevam 14194444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14204444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 14214444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1422458e2c82SFabio Estevam 142327c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1424458e2c82SFabio Estevam udelay(1); 1425ab4382d2SGreg Kroah-Hartman 1426ab4382d2SGreg Kroah-Hartman /* 1427ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1428ab4382d2SGreg Kroah-Hartman */ 142927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 143027c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1431ab4382d2SGreg Kroah-Hartman 14324444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 14334444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 14346376cd39SNandor Han if (sport->have_rtscts) 14354444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1436ab4382d2SGreg Kroah-Hartman 14374444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1438ab4382d2SGreg Kroah-Hartman 14395a08a487SGeorge Hilliard ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 14401f043572STroy Kisky if (!sport->dma_is_enabled) 14414444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 14425a08a487SGeorge Hilliard if (sport->inverted_rx) 14435a08a487SGeorge Hilliard ucr4 |= UCR4_INVR; 14444444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 14456f026d6bSJiada Wang 14465a08a487SGeorge Hilliard ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 14475a08a487SGeorge Hilliard /* 14485a08a487SGeorge Hilliard * configure tx polarity before enabling tx 14495a08a487SGeorge Hilliard */ 14505a08a487SGeorge Hilliard if (sport->inverted_tx) 14515a08a487SGeorge Hilliard ucr3 |= UCR3_INVT; 14525a08a487SGeorge Hilliard 14535a08a487SGeorge Hilliard if (!imx_uart_is_imx1(sport)) { 14545a08a487SGeorge Hilliard ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 14555a08a487SGeorge Hilliard 14565a08a487SGeorge Hilliard if (sport->dte_mode) 14575a08a487SGeorge Hilliard /* disable broken interrupts */ 14585a08a487SGeorge Hilliard ucr3 &= ~(UCR3_RI | UCR3_DCD); 14595a08a487SGeorge Hilliard } 14605a08a487SGeorge Hilliard imx_uart_writel(sport, ucr3, UCR3); 14615a08a487SGeorge Hilliard 14624444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 14634444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1464bff09b09SLucas Stach if (!sport->have_rtscts) 14654444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 146616804d68SUwe Kleine-König /* 146716804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 146816804d68SUwe Kleine-König * we're using RTSD instead. 146916804d68SUwe Kleine-König */ 14709d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 14714444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 14724444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1473ab4382d2SGreg Kroah-Hartman 1474ab4382d2SGreg Kroah-Hartman /* 1475ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1476ab4382d2SGreg Kroah-Hartman */ 14779d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 147818a42088SPeter Senna Tschudin 147976821e22SUwe Kleine-König if (dma_is_inited) { 14809d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 14819d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 148276821e22SUwe Kleine-König } else { 148376821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 148476821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 148576821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 148681ca8e82SUwe Kleine-König 148781ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 148881ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 148981ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 149076821e22SUwe Kleine-König } 149118a42088SPeter Senna Tschudin 1492ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1493ab4382d2SGreg Kroah-Hartman 1494ab4382d2SGreg Kroah-Hartman return 0; 1495ab4382d2SGreg Kroah-Hartman } 1496ab4382d2SGreg Kroah-Hartman 14979d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1498ab4382d2SGreg Kroah-Hartman { 1499ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 15009ec1882dSXinyu Chen unsigned long flags; 1501339c7a87SSebastian Reichel u32 ucr1, ucr2, ucr4; 1502ab4382d2SGreg Kroah-Hartman 1503b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1504e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 15057722c240SSebastian Reichel if (sport->dma_is_txing) { 15067722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 15077722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 15087722c240SSebastian Reichel sport->dma_is_txing = 0; 15097722c240SSebastian Reichel } 1510e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 15117722c240SSebastian Reichel if (sport->dma_is_rxing) { 15127722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 15137722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 15147722c240SSebastian Reichel sport->dma_is_rxing = 0; 15157722c240SSebastian Reichel } 15169d297239SNandor Han 151773631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 15189d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 15199d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 15209d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 152173631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1522b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1523b4cdc8f6SHuang Shijie } 1524b4cdc8f6SHuang Shijie 152558362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 152658362d5bSUwe Kleine-König 15279ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 15284444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15290fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 15304444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 15319ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1532ab4382d2SGreg Kroah-Hartman 1533ab4382d2SGreg Kroah-Hartman /* 1534ab4382d2SGreg Kroah-Hartman * Stop our timer. 1535ab4382d2SGreg Kroah-Hartman */ 1536ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1537ab4382d2SGreg Kroah-Hartman 1538ab4382d2SGreg Kroah-Hartman /* 1539ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1540ab4382d2SGreg Kroah-Hartman */ 1541ab4382d2SGreg Kroah-Hartman 15429ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1543edd64f30SMatthias Schiffer 15444444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 1545c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 15464444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1547edd64f30SMatthias Schiffer 1548edd64f30SMatthias Schiffer ucr4 = imx_uart_readl(sport, UCR4); 1549edd64f30SMatthias Schiffer ucr4 &= ~(UCR4_OREN | UCR4_TCEN); 1550edd64f30SMatthias Schiffer imx_uart_writel(sport, ucr4, UCR4); 1551edd64f30SMatthias Schiffer 15529ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 155328eb4274SHuang Shijie 155428eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 155528eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1556ab4382d2SGreg Kroah-Hartman } 1557ab4382d2SGreg Kroah-Hartman 15586aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 15599d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1560eb56b7edSHuang Shijie { 1561eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 156282e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 15634444dcf1SUwe Kleine-König u32 ucr2; 15644f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1565eb56b7edSHuang Shijie 156682e86ae9SDirk Behme if (!sport->dma_chan_tx) 156782e86ae9SDirk Behme return; 156882e86ae9SDirk Behme 1569eb56b7edSHuang Shijie sport->tx_bytes = 0; 1570eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 157182e86ae9SDirk Behme if (sport->dma_is_txing) { 15724444dcf1SUwe Kleine-König u32 ucr1; 15734444dcf1SUwe Kleine-König 157482e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 157582e86ae9SDirk Behme DMA_TO_DEVICE); 15764444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 15774444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 15784444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 15790f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1580eb56b7edSHuang Shijie } 1581934084a9SFabio Estevam 1582934084a9SFabio Estevam /* 1583934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1584263763c1SMartyn Welch * 1585934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1586934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1587263763c1SMartyn Welch * and UTS[6-3]". 1588263763c1SMartyn Welch * 1589263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1590263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1591263763c1SMartyn Welch * registers. 1592934084a9SFabio Estevam */ 159327c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 159427c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 159527c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1596934084a9SFabio Estevam 15974444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15984444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 15994444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1600934084a9SFabio Estevam 160127c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1602934084a9SFabio Estevam udelay(1); 1603934084a9SFabio Estevam 1604934084a9SFabio Estevam /* Restore the registers */ 160527c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 160627c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 160727c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1608eb56b7edSHuang Shijie } 1609eb56b7edSHuang Shijie 1610ab4382d2SGreg Kroah-Hartman static void 16119d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1612ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1613ab4382d2SGreg Kroah-Hartman { 1614ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1615ab4382d2SGreg Kroah-Hartman unsigned long flags; 161685f30fbfSSergey Organov u32 ucr2, old_ucr2, ufcr; 161758362d5bSUwe Kleine-König unsigned int baud, quot; 1618ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 16194444dcf1SUwe Kleine-König unsigned long div; 1620d47bcb4aSSergey Organov unsigned long num, denom, old_ubir, old_ubmr; 1621ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1622ab4382d2SGreg Kroah-Hartman 1623ab4382d2SGreg Kroah-Hartman /* 1624ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1625ab4382d2SGreg Kroah-Hartman */ 1626ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1627ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1628ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1629ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1630ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1631ab4382d2SGreg Kroah-Hartman } 1632ab4382d2SGreg Kroah-Hartman 16334e828c3eSSergey Organov del_timer_sync(&sport->timer); 16344e828c3eSSergey Organov 16354e828c3eSSergey Organov /* 16364e828c3eSSergey Organov * Ask the core to calculate the divisor for us. 16374e828c3eSSergey Organov */ 16384e828c3eSSergey Organov baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 16394e828c3eSSergey Organov quot = uart_get_divisor(port, baud); 16404e828c3eSSergey Organov 16414e828c3eSSergey Organov spin_lock_irqsave(&sport->port.lock, flags); 16424e828c3eSSergey Organov 1643011bd05dSSergey Organov /* 1644011bd05dSSergey Organov * Read current UCR2 and save it for future use, then clear all the bits 1645011bd05dSSergey Organov * except those we will or may need to preserve. 1646011bd05dSSergey Organov */ 1647011bd05dSSergey Organov old_ucr2 = imx_uart_readl(sport, UCR2); 1648011bd05dSSergey Organov ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1649011bd05dSSergey Organov 1650011bd05dSSergey Organov ucr2 |= UCR2_SRST | UCR2_IRTS; 165141ffa48eSSergey Organov if ((termios->c_cflag & CSIZE) == CS8) 165241ffa48eSSergey Organov ucr2 |= UCR2_WS; 1653ab4382d2SGreg Kroah-Hartman 1654ddf89e75SSergey Organov if (!sport->have_rtscts) 1655ddf89e75SSergey Organov termios->c_cflag &= ~CRTSCTS; 165617b8f2a3SUwe Kleine-König 165712fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 165817b8f2a3SUwe Kleine-König /* 165917b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 166017b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 166117b8f2a3SUwe Kleine-König * disabled. 166217b8f2a3SUwe Kleine-König */ 166358362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 16649d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 16651a613626SFabio Estevam else 16669d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 166758362d5bSUwe Kleine-König 1668b777b5deSSergey Organov } else if (termios->c_cflag & CRTSCTS) { 1669b777b5deSSergey Organov /* 1670b777b5deSSergey Organov * Only let receiver control RTS output if we were not requested 1671b777b5deSSergey Organov * to have RTS inactive (which then should take precedence). 1672b777b5deSSergey Organov */ 1673b777b5deSSergey Organov if (ucr2 & UCR2_CTS) 1674b777b5deSSergey Organov ucr2 |= UCR2_CTSC; 1675b777b5deSSergey Organov } 1676ddf89e75SSergey Organov 1677ddf89e75SSergey Organov if (termios->c_cflag & CRTSCTS) 1678ddf89e75SSergey Organov ucr2 &= ~UCR2_IRTS; 1679ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1680ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1681ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1682ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1683ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1684ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1685ab4382d2SGreg Kroah-Hartman } 1686ab4382d2SGreg Kroah-Hartman 1687ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1688ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1689ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1690ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1691ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1692ab4382d2SGreg Kroah-Hartman 1693ab4382d2SGreg Kroah-Hartman /* 1694ab4382d2SGreg Kroah-Hartman * Characters to ignore 1695ab4382d2SGreg Kroah-Hartman */ 1696ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1697ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1698865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1699ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1700ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1701ab4382d2SGreg Kroah-Hartman /* 1702ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1703ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1704ab4382d2SGreg Kroah-Hartman */ 1705ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1706ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1707ab4382d2SGreg Kroah-Hartman } 1708ab4382d2SGreg Kroah-Hartman 170955d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 171055d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 171155d8693aSJiada Wang 1712ab4382d2SGreg Kroah-Hartman /* 1713ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1714ab4382d2SGreg Kroah-Hartman */ 1715ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1716ab4382d2SGreg Kroah-Hartman 171709bd00f6SHubert Feurstein /* custom-baudrate handling */ 171809bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 171909bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 172009bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 172109bd00f6SHubert Feurstein 1722ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1723ab4382d2SGreg Kroah-Hartman if (div > 7) 1724ab4382d2SGreg Kroah-Hartman div = 7; 1725ab4382d2SGreg Kroah-Hartman if (!div) 1726ab4382d2SGreg Kroah-Hartman div = 1; 1727ab4382d2SGreg Kroah-Hartman 1728ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1729ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1730ab4382d2SGreg Kroah-Hartman 1731ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1732ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1733ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1734ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1735ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1736ab4382d2SGreg Kroah-Hartman 1737ab4382d2SGreg Kroah-Hartman num -= 1; 1738ab4382d2SGreg Kroah-Hartman denom -= 1; 1739ab4382d2SGreg Kroah-Hartman 174027c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1741ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 174227c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1743ab4382d2SGreg Kroah-Hartman 1744d47bcb4aSSergey Organov /* 1745d47bcb4aSSergey Organov * Two registers below should always be written both and in this 1746d47bcb4aSSergey Organov * particular order. One consequence is that we need to check if any of 1747d47bcb4aSSergey Organov * them changes and then update both. We do need the check for change 1748d47bcb4aSSergey Organov * as even writing the same values seem to "restart" 1749d47bcb4aSSergey Organov * transmission/receiving logic in the hardware, that leads to data 1750d47bcb4aSSergey Organov * breakage even when rate doesn't in fact change. E.g., user switches 1751d47bcb4aSSergey Organov * RTS/CTS handshake and suddenly gets broken bytes. 1752d47bcb4aSSergey Organov */ 1753d47bcb4aSSergey Organov old_ubir = imx_uart_readl(sport, UBIR); 1754d47bcb4aSSergey Organov old_ubmr = imx_uart_readl(sport, UBMR); 1755d47bcb4aSSergey Organov if (old_ubir != num || old_ubmr != denom) { 175627c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 175727c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1758d47bcb4aSSergey Organov } 1759ab4382d2SGreg Kroah-Hartman 17609d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 176127c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 176227c84426SUwe Kleine-König IMX21_ONEMS); 1763ab4382d2SGreg Kroah-Hartman 1764011bd05dSSergey Organov imx_uart_writel(sport, ucr2, UCR2); 1765ab4382d2SGreg Kroah-Hartman 1766ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 17679d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1768ab4382d2SGreg Kroah-Hartman 1769ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1770ab4382d2SGreg Kroah-Hartman } 1771ab4382d2SGreg Kroah-Hartman 17729d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1773ab4382d2SGreg Kroah-Hartman { 1774ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1775ab4382d2SGreg Kroah-Hartman 1776ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1777ab4382d2SGreg Kroah-Hartman } 1778ab4382d2SGreg Kroah-Hartman 1779ab4382d2SGreg Kroah-Hartman /* 1780ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1781ab4382d2SGreg Kroah-Hartman */ 17829d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1783ab4382d2SGreg Kroah-Hartman { 1784ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1785ab4382d2SGreg Kroah-Hartman 1786da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1787ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1788ab4382d2SGreg Kroah-Hartman } 1789ab4382d2SGreg Kroah-Hartman 1790ab4382d2SGreg Kroah-Hartman /* 1791ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1792ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1793ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1794ab4382d2SGreg Kroah-Hartman */ 1795ab4382d2SGreg Kroah-Hartman static int 17969d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1797ab4382d2SGreg Kroah-Hartman { 1798ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1799ab4382d2SGreg Kroah-Hartman int ret = 0; 1800ab4382d2SGreg Kroah-Hartman 1801ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1802ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1803ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1804ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1805ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1806ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1807ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1808ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1809a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1810ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1811ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1812ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1813ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1814ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1815ab4382d2SGreg Kroah-Hartman return ret; 1816ab4382d2SGreg Kroah-Hartman } 1817ab4382d2SGreg Kroah-Hartman 181801f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18196b8bdad9SDaniel Thompson 18209d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 18216b8bdad9SDaniel Thompson { 18226b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 18236b8bdad9SDaniel Thompson unsigned long flags; 18244444dcf1SUwe Kleine-König u32 ucr1, ucr2; 18256b8bdad9SDaniel Thompson int retval; 18266b8bdad9SDaniel Thompson 18276b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 18286b8bdad9SDaniel Thompson if (retval) 18296b8bdad9SDaniel Thompson return retval; 18306b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 18316b8bdad9SDaniel Thompson if (retval) 18326b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 18336b8bdad9SDaniel Thompson 18349d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 18356b8bdad9SDaniel Thompson 18366b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 18376b8bdad9SDaniel Thompson 183876821e22SUwe Kleine-König /* 183976821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 184076821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 184176821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 184276821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 184376821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 184476821e22SUwe Kleine-König */ 18454444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 184676821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 184776821e22SUwe Kleine-König 18489d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 18494444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 18506b8bdad9SDaniel Thompson 185176821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 1852c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 185376821e22SUwe Kleine-König 1854aef1b6a2SMingrui Ren ucr2 |= UCR2_RXEN | UCR2_TXEN; 185581ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 185676821e22SUwe Kleine-König 185776821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 18584444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 18596b8bdad9SDaniel Thompson 186076821e22SUwe Kleine-König /* now enable irqs */ 186176821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 186281ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 186376821e22SUwe Kleine-König 18646b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 18656b8bdad9SDaniel Thompson 18666b8bdad9SDaniel Thompson return 0; 18676b8bdad9SDaniel Thompson } 18686b8bdad9SDaniel Thompson 18699d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 187001f56abdSSaleem Abdulrasool { 187127c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 187227c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 187326c47412SDirk Behme return NO_POLL_CHAR; 187401f56abdSSaleem Abdulrasool 187527c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 187601f56abdSSaleem Abdulrasool } 187701f56abdSSaleem Abdulrasool 18789d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 187901f56abdSSaleem Abdulrasool { 188027c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 188101f56abdSSaleem Abdulrasool unsigned int status; 188201f56abdSSaleem Abdulrasool 188301f56abdSSaleem Abdulrasool /* drain */ 188401f56abdSSaleem Abdulrasool do { 188527c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 188601f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 188701f56abdSSaleem Abdulrasool 188801f56abdSSaleem Abdulrasool /* write */ 188927c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 189001f56abdSSaleem Abdulrasool 189101f56abdSSaleem Abdulrasool /* flush */ 189201f56abdSSaleem Abdulrasool do { 189327c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 189401f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 189501f56abdSSaleem Abdulrasool } 189601f56abdSSaleem Abdulrasool #endif 189701f56abdSSaleem Abdulrasool 18986aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 18999d1a50a2SUwe Kleine-König static int imx_uart_rs485_config(struct uart_port *port, 190017b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 190117b8f2a3SUwe Kleine-König { 190217b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 19034444dcf1SUwe Kleine-König u32 ucr2; 190417b8f2a3SUwe Kleine-König 190517b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 19067b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 190717b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 190817b8f2a3SUwe Kleine-König 190917b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 19106d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 19116d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 19126d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 19136d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 19146d215f83SStefan Agner 191517b8f2a3SUwe Kleine-König /* disable transmitter */ 19164444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 191717b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 19189d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 19191a613626SFabio Estevam else 19209d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 19214444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 192217b8f2a3SUwe Kleine-König } 192317b8f2a3SUwe Kleine-König 19247d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 19257d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 192676821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 19279d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 19287d1cadcaSBaruch Siach 192917b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 193017b8f2a3SUwe Kleine-König 193117b8f2a3SUwe Kleine-König return 0; 193217b8f2a3SUwe Kleine-König } 193317b8f2a3SUwe Kleine-König 19349d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 19359d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 19369d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 19379d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 19389d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 19399d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 19409d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 19419d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 19429d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 19439d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 19449d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 19459d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 19469d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 19479d1a50a2SUwe Kleine-König .type = imx_uart_type, 19489d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 19499d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 195001f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 19519d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 19529d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 19539d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 195401f56abdSSaleem Abdulrasool #endif 1955ab4382d2SGreg Kroah-Hartman }; 1956ab4382d2SGreg Kroah-Hartman 19579d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1958ab4382d2SGreg Kroah-Hartman 19590db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 19609d1a50a2SUwe Kleine-König static void imx_uart_console_putchar(struct uart_port *port, int ch) 1961ab4382d2SGreg Kroah-Hartman { 1962ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1963ab4382d2SGreg Kroah-Hartman 19649d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1965ab4382d2SGreg Kroah-Hartman barrier(); 1966ab4382d2SGreg Kroah-Hartman 196727c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1968ab4382d2SGreg Kroah-Hartman } 1969ab4382d2SGreg Kroah-Hartman 1970ab4382d2SGreg Kroah-Hartman /* 1971ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1972ab4382d2SGreg Kroah-Hartman */ 1973ab4382d2SGreg Kroah-Hartman static void 19749d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1975ab4382d2SGreg Kroah-Hartman { 19769d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 19770ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 19780ad5a814SDirk Behme unsigned int ucr1; 1979f30e8260SShawn Guo unsigned long flags = 0; 1980677fe555SThomas Gleixner int locked = 1; 19819ec1882dSXinyu Chen 1982677fe555SThomas Gleixner if (sport->port.sysrq) 1983677fe555SThomas Gleixner locked = 0; 1984677fe555SThomas Gleixner else if (oops_in_progress) 1985677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1986677fe555SThomas Gleixner else 19879ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1988ab4382d2SGreg Kroah-Hartman 1989ab4382d2SGreg Kroah-Hartman /* 19900ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1991ab4382d2SGreg Kroah-Hartman */ 19929d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 19930ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1994ab4382d2SGreg Kroah-Hartman 19959d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 1996fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1997ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1998c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1999ab4382d2SGreg Kroah-Hartman 200027c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2001ab4382d2SGreg Kroah-Hartman 200227c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2003ab4382d2SGreg Kroah-Hartman 20049d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2005ab4382d2SGreg Kroah-Hartman 2006ab4382d2SGreg Kroah-Hartman /* 2007ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 20080ad5a814SDirk Behme * and restore UCR1/2/3 2009ab4382d2SGreg Kroah-Hartman */ 201027c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2011ab4382d2SGreg Kroah-Hartman 20129d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 20139ec1882dSXinyu Chen 2014677fe555SThomas Gleixner if (locked) 20159ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 2016ab4382d2SGreg Kroah-Hartman } 2017ab4382d2SGreg Kroah-Hartman 2018ab4382d2SGreg Kroah-Hartman /* 2019ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 2020ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 2021ab4382d2SGreg Kroah-Hartman */ 2022ab4382d2SGreg Kroah-Hartman static void __init 20239d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 2024ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 2025ab4382d2SGreg Kroah-Hartman { 2026ab4382d2SGreg Kroah-Hartman 202727c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2028ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 2029ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 2030ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 2031ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 2032ab4382d2SGreg Kroah-Hartman 203327c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 2034ab4382d2SGreg Kroah-Hartman 2035ab4382d2SGreg Kroah-Hartman *parity = 'n'; 2036ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 2037ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 2038ab4382d2SGreg Kroah-Hartman *parity = 'o'; 2039ab4382d2SGreg Kroah-Hartman else 2040ab4382d2SGreg Kroah-Hartman *parity = 'e'; 2041ab4382d2SGreg Kroah-Hartman } 2042ab4382d2SGreg Kroah-Hartman 2043ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 2044ab4382d2SGreg Kroah-Hartman *bits = 8; 2045ab4382d2SGreg Kroah-Hartman else 2046ab4382d2SGreg Kroah-Hartman *bits = 7; 2047ab4382d2SGreg Kroah-Hartman 204827c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 204927c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2050ab4382d2SGreg Kroah-Hartman 205127c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2052ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 2053ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 2054ab4382d2SGreg Kroah-Hartman else 2055ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 2056ab4382d2SGreg Kroah-Hartman 20573a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2058ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2059ab4382d2SGreg Kroah-Hartman 2060ab4382d2SGreg Kroah-Hartman { /* 2061ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2062ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2063ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2064ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2065ab4382d2SGreg Kroah-Hartman */ 2066ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2067ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2068ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2069ab4382d2SGreg Kroah-Hartman 2070ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2071ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2072ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2073ab4382d2SGreg Kroah-Hartman } 2074ab4382d2SGreg Kroah-Hartman 2075ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 2076f5a9e5f7SFabio Estevam dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2077ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2078ab4382d2SGreg Kroah-Hartman } 2079ab4382d2SGreg Kroah-Hartman } 2080ab4382d2SGreg Kroah-Hartman 2081ab4382d2SGreg Kroah-Hartman static int __init 20829d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2083ab4382d2SGreg Kroah-Hartman { 2084ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2085ab4382d2SGreg Kroah-Hartman int baud = 9600; 2086ab4382d2SGreg Kroah-Hartman int bits = 8; 2087ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2088ab4382d2SGreg Kroah-Hartman int flow = 'n'; 20891cf93e0dSHuang Shijie int retval; 2090ab4382d2SGreg Kroah-Hartman 2091ab4382d2SGreg Kroah-Hartman /* 2092ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2093ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2094ab4382d2SGreg Kroah-Hartman * console support. 2095ab4382d2SGreg Kroah-Hartman */ 20969d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2097ab4382d2SGreg Kroah-Hartman co->index = 0; 20989d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2099ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2100ab4382d2SGreg Kroah-Hartman return -ENODEV; 2101ab4382d2SGreg Kroah-Hartman 21021cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 21031cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 21041cf93e0dSHuang Shijie if (retval) 21051cf93e0dSHuang Shijie goto error_console; 21061cf93e0dSHuang Shijie 2107ab4382d2SGreg Kroah-Hartman if (options) 2108ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2109ab4382d2SGreg Kroah-Hartman else 21109d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2111ab4382d2SGreg Kroah-Hartman 21129d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2113ab4382d2SGreg Kroah-Hartman 21141cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 21151cf93e0dSHuang Shijie 21160c727a42SFabio Estevam if (retval) { 2117e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21180c727a42SFabio Estevam goto error_console; 21190c727a42SFabio Estevam } 21200c727a42SFabio Estevam 2121e67c139cSFugang Duan retval = clk_prepare_enable(sport->clk_per); 21220c727a42SFabio Estevam if (retval) 2123e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21241cf93e0dSHuang Shijie 21251cf93e0dSHuang Shijie error_console: 21261cf93e0dSHuang Shijie return retval; 2127ab4382d2SGreg Kroah-Hartman } 2128ab4382d2SGreg Kroah-Hartman 21299d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 21309d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2131ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 21329d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2133ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 21349d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 2135ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2136ab4382d2SGreg Kroah-Hartman .index = -1, 21379d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2138ab4382d2SGreg Kroah-Hartman }; 2139ab4382d2SGreg Kroah-Hartman 21409d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2141913c6c0eSLucas Stach 2142ab4382d2SGreg Kroah-Hartman #else 2143ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2144ab4382d2SGreg Kroah-Hartman #endif 2145ab4382d2SGreg Kroah-Hartman 21469d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2147ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2148ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2149ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2150ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2151ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21529d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2153ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2154ab4382d2SGreg Kroah-Hartman }; 2155ab4382d2SGreg Kroah-Hartman 2156bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2157cb1a6092SUwe Kleine-König { 2158bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2159cb1a6092SUwe Kleine-König unsigned long flags; 2160cb1a6092SUwe Kleine-König 2161cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2162cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS) 2163cb1a6092SUwe Kleine-König imx_uart_start_tx(&sport->port); 2164cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2165bd78ecd6SAhmad Fatoum 2166bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2167cb1a6092SUwe Kleine-König } 2168cb1a6092SUwe Kleine-König 2169bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2170cb1a6092SUwe Kleine-König { 2171bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2172cb1a6092SUwe Kleine-König unsigned long flags; 2173cb1a6092SUwe Kleine-König 2174cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2175cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_SEND) 2176cb1a6092SUwe Kleine-König imx_uart_stop_tx(&sport->port); 2177cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2178bd78ecd6SAhmad Fatoum 2179bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2180cb1a6092SUwe Kleine-König } 2181cb1a6092SUwe Kleine-König 21829d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2183ab4382d2SGreg Kroah-Hartman { 21844661f46eSFabio Estevam struct device_node *np = pdev->dev.of_node; 2185ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2186ab4382d2SGreg Kroah-Hartman void __iomem *base; 21874444dcf1SUwe Kleine-König int ret = 0; 21884444dcf1SUwe Kleine-König u32 ucr1; 2189ab4382d2SGreg Kroah-Hartman struct resource *res; 2190842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2191ab4382d2SGreg Kroah-Hartman 219242d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2193ab4382d2SGreg Kroah-Hartman if (!sport) 2194ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2195ab4382d2SGreg Kroah-Hartman 21964661f46eSFabio Estevam sport->devdata = of_device_get_match_data(&pdev->dev); 21974661f46eSFabio Estevam 21984661f46eSFabio Estevam ret = of_alias_get_id(np, "serial"); 21994661f46eSFabio Estevam if (ret < 0) { 22004661f46eSFabio Estevam dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 220142d34191SSachin Kamat return ret; 22024661f46eSFabio Estevam } 22034661f46eSFabio Estevam sport->port.line = ret; 22044661f46eSFabio Estevam 22054661f46eSFabio Estevam if (of_get_property(np, "uart-has-rtscts", NULL) || 22064661f46eSFabio Estevam of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 22074661f46eSFabio Estevam sport->have_rtscts = 1; 22084661f46eSFabio Estevam 22094661f46eSFabio Estevam if (of_get_property(np, "fsl,dte-mode", NULL)) 22104661f46eSFabio Estevam sport->dte_mode = 1; 22114661f46eSFabio Estevam 22124661f46eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 22134661f46eSFabio Estevam sport->have_rtsgpio = 1; 22144661f46eSFabio Estevam 22154661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-tx", NULL)) 22164661f46eSFabio Estevam sport->inverted_tx = 1; 22174661f46eSFabio Estevam 22184661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-rx", NULL)) 22194661f46eSFabio Estevam sport->inverted_rx = 1; 222022698aa2SShawn Guo 22219d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 222256734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 222356734448SGeert Uytterhoeven sport->port.line); 222456734448SGeert Uytterhoeven return -EINVAL; 222556734448SGeert Uytterhoeven } 222656734448SGeert Uytterhoeven 2227ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2228da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2229da82f997SAlexander Shiyan if (IS_ERR(base)) 2230da82f997SAlexander Shiyan return PTR_ERR(base); 2231ab4382d2SGreg Kroah-Hartman 2232842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2233aa49d8e8SAnson Huang if (rxirq < 0) 2234aa49d8e8SAnson Huang return rxirq; 223531a8d8faSAnson Huang txirq = platform_get_irq_optional(pdev, 1); 223631a8d8faSAnson Huang rtsirq = platform_get_irq_optional(pdev, 2); 2237842633bdSUwe Kleine-König 2238ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2239ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2240ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 22415b109564SZheng Yongjun sport->port.type = PORT_IMX; 2242ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2243842633bdSUwe Kleine-König sport->port.irq = rxirq; 2244ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2245aa3479d2SDmitry Safonov sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 22469d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 22479d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 2248ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 22499d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2250ab4382d2SGreg Kroah-Hartman 225158362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 225258362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 225358362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 225458362d5bSUwe Kleine-König 22553a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 22563a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 22573a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2258833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 225942d34191SSachin Kamat return ret; 2260ab4382d2SGreg Kroah-Hartman } 2261ab4382d2SGreg Kroah-Hartman 22623a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 22633a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 22643a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2265833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 226642d34191SSachin Kamat return ret; 22673a9465faSSascha Hauer } 22683a9465faSSascha Hauer 22693a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2270ab4382d2SGreg Kroah-Hartman 22718a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 22728a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 22731e512d45SUwe Kleine-König if (ret) { 22741e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 22758a61f0c7SFabio Estevam return ret; 22761e512d45SUwe Kleine-König } 22778a61f0c7SFabio Estevam 22783a0ab62fSUwe Kleine-König /* initialize shadow register values */ 22793a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 22803a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 22813a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 22823a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 22833a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 22843a0ab62fSUwe Kleine-König 2285c150c0f3SLukas Wunner ret = uart_get_rs485_mode(&sport->port); 2286c150c0f3SLukas Wunner if (ret) { 2287c150c0f3SLukas Wunner clk_disable_unprepare(sport->clk_ipg); 2288c150c0f3SLukas Wunner return ret; 2289c150c0f3SLukas Wunner } 2290743f93f8SLukas Wunner 2291b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 22925d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2293b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2294b8f3bff0SLukas Wunner 22956d215f83SStefan Agner /* 22966d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 22976d215f83SStefan Agner * signal cannot be set low during transmission in case the 22986d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 22996d215f83SStefan Agner */ 23006d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23016d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 23026d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 23036d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 23046d215f83SStefan Agner dev_err(&pdev->dev, 23056d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 23066d215f83SStefan Agner 23079d1a50a2SUwe Kleine-König imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2308b8f3bff0SLukas Wunner 23098a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 23104444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 23115f0e708cSYe Bin ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 23124444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 23138a61f0c7SFabio Estevam 23149d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2315e61c38d8SUwe Kleine-König /* 2316e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2317e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2318e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2319e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2320e61c38d8SUwe Kleine-König */ 23214444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23224444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 23234444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2324e61c38d8SUwe Kleine-König 2325e61c38d8SUwe Kleine-König /* 2326e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2327e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2328e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2329e61c38d8SUwe Kleine-König */ 233027c84426SUwe Kleine-König imx_uart_writel(sport, 233127c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 233227c84426SUwe Kleine-König UCR3); 2333e61c38d8SUwe Kleine-König 2334e61c38d8SUwe Kleine-König } else { 23354444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 23364444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23374444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 23384444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 23396df765dcSUwe Kleine-König 23409d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 23416df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 234227c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2343e61c38d8SUwe Kleine-König } 2344e61c38d8SUwe Kleine-König 23458a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 23468a61f0c7SFabio Estevam 2347bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2348bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2349bd78ecd6SAhmad Fatoum sport->trigger_start_tx.function = imx_trigger_start_tx; 2350bd78ecd6SAhmad Fatoum sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2351cb1a6092SUwe Kleine-König 2352c0d1c6b0SFabio Estevam /* 2353c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2354c0d1c6b0SFabio Estevam * chips only have one interrupt. 2355c0d1c6b0SFabio Estevam */ 2356842633bdSUwe Kleine-König if (txirq > 0) { 23579d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2358c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23591e512d45SUwe Kleine-König if (ret) { 23601e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 23611e512d45SUwe Kleine-König ret); 2362c0d1c6b0SFabio Estevam return ret; 23631e512d45SUwe Kleine-König } 2364c0d1c6b0SFabio Estevam 23659d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2366c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23671e512d45SUwe Kleine-König if (ret) { 23681e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 23691e512d45SUwe Kleine-König ret); 2370c0d1c6b0SFabio Estevam return ret; 23711e512d45SUwe Kleine-König } 23727e620984SUwe Kleine-König 23737e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 23747e620984SUwe Kleine-König dev_name(&pdev->dev), sport); 23757e620984SUwe Kleine-König if (ret) { 23767e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n", 23777e620984SUwe Kleine-König ret); 23787e620984SUwe Kleine-König return ret; 23797e620984SUwe Kleine-König } 2380c0d1c6b0SFabio Estevam } else { 23819d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2382c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23831e512d45SUwe Kleine-König if (ret) { 23841e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2385c0d1c6b0SFabio Estevam return ret; 2386c0d1c6b0SFabio Estevam } 23871e512d45SUwe Kleine-König } 2388c0d1c6b0SFabio Estevam 23899d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2390ab4382d2SGreg Kroah-Hartman 23910a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2392ab4382d2SGreg Kroah-Hartman 23939d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2394ab4382d2SGreg Kroah-Hartman } 2395ab4382d2SGreg Kroah-Hartman 23969d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2397ab4382d2SGreg Kroah-Hartman { 2398ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2399ab4382d2SGreg Kroah-Hartman 24009d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2401ab4382d2SGreg Kroah-Hartman } 2402ab4382d2SGreg Kroah-Hartman 24039d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2404c868cbb7SEduardo Valentin { 240507b5e16eSAnson Huang unsigned long flags; 240607b5e16eSAnson Huang 240707b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 240807b5e16eSAnson Huang if (!sport->context_saved) { 240907b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2410c868cbb7SEduardo Valentin return; 241107b5e16eSAnson Huang } 2412c868cbb7SEduardo Valentin 241327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 241427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 241527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 241627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 241727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 241827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 241927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 242027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 242127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 242227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2423c868cbb7SEduardo Valentin sport->context_saved = false; 242407b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2425c868cbb7SEduardo Valentin } 2426c868cbb7SEduardo Valentin 24279d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2428c868cbb7SEduardo Valentin { 242907b5e16eSAnson Huang unsigned long flags; 243007b5e16eSAnson Huang 2431c868cbb7SEduardo Valentin /* Save necessary regs */ 243207b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 243327c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 243427c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 243527c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 243627c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 243727c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 243827c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 243927c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 244027c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 244127c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 244227c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2443c868cbb7SEduardo Valentin sport->context_saved = true; 244407b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2445c868cbb7SEduardo Valentin } 2446c868cbb7SEduardo Valentin 24479d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2448189550b8SEduardo Valentin { 24494444dcf1SUwe Kleine-König u32 ucr3; 2450189550b8SEduardo Valentin 24514444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 245209df0b34SMartin Kaiser if (on) { 245327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 24544444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 24554444dcf1SUwe Kleine-König } else { 24564444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 245709df0b34SMartin Kaiser } 24584444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2459bc85734bSEduardo Valentin 246038b1f0fbSFabio Estevam if (sport->have_rtscts) { 24614444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2462bc85734bSEduardo Valentin if (on) 24634444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2464bc85734bSEduardo Valentin else 24654444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 24664444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2467189550b8SEduardo Valentin } 246838b1f0fbSFabio Estevam } 2469189550b8SEduardo Valentin 24709d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 247190bb6bd3SShenwei Wang { 2472a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 247390bb6bd3SShenwei Wang 24749d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 247590bb6bd3SShenwei Wang 247690bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 247790bb6bd3SShenwei Wang 2478fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev); 2479fcfed1beSAnson Huang 248090bb6bd3SShenwei Wang return 0; 248190bb6bd3SShenwei Wang } 248290bb6bd3SShenwei Wang 24839d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 248490bb6bd3SShenwei Wang { 2485a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 248690bb6bd3SShenwei Wang int ret; 248790bb6bd3SShenwei Wang 2488fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev); 2489fcfed1beSAnson Huang 249090bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 249190bb6bd3SShenwei Wang if (ret) 249290bb6bd3SShenwei Wang return ret; 249390bb6bd3SShenwei Wang 24949d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 249590bb6bd3SShenwei Wang 249690bb6bd3SShenwei Wang return 0; 249790bb6bd3SShenwei Wang } 249890bb6bd3SShenwei Wang 24999d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 250090bb6bd3SShenwei Wang { 2501a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 250209df0b34SMartin Kaiser int ret; 250390bb6bd3SShenwei Wang 25049d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 250581b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 250690bb6bd3SShenwei Wang 250709df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 250809df0b34SMartin Kaiser if (ret) 250909df0b34SMartin Kaiser return ret; 251009df0b34SMartin Kaiser 251109df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 25129d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 251309df0b34SMartin Kaiser 251409df0b34SMartin Kaiser return 0; 251590bb6bd3SShenwei Wang } 251690bb6bd3SShenwei Wang 25179d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 251890bb6bd3SShenwei Wang { 2519a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 252090bb6bd3SShenwei Wang 252190bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 25229d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 252390bb6bd3SShenwei Wang 25249d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 252581b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 252690bb6bd3SShenwei Wang 252709df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 252829add68dSMartin Fuzzey 252990bb6bd3SShenwei Wang return 0; 253090bb6bd3SShenwei Wang } 253190bb6bd3SShenwei Wang 25329d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 253394be6d74SPhilipp Zabel { 2534a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 253594be6d74SPhilipp Zabel 25369d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 253794be6d74SPhilipp Zabel 253809df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 253994be6d74SPhilipp Zabel } 254094be6d74SPhilipp Zabel 25419d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 254294be6d74SPhilipp Zabel { 2543a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 254494be6d74SPhilipp Zabel 25459d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 254694be6d74SPhilipp Zabel 254709df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 254894be6d74SPhilipp Zabel 254994be6d74SPhilipp Zabel return 0; 255094be6d74SPhilipp Zabel } 255194be6d74SPhilipp Zabel 25529d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 25539d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 25549d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 25559d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 25569d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 25579d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 25589d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 25599d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 25609d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 25619d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 256290bb6bd3SShenwei Wang }; 256390bb6bd3SShenwei Wang 25649d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 25659d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 25669d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2567ab4382d2SGreg Kroah-Hartman 2568ab4382d2SGreg Kroah-Hartman .driver = { 2569ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 257022698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 25719d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2572ab4382d2SGreg Kroah-Hartman }, 2573ab4382d2SGreg Kroah-Hartman }; 2574ab4382d2SGreg Kroah-Hartman 25759d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2576ab4382d2SGreg Kroah-Hartman { 25779d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2578ab4382d2SGreg Kroah-Hartman 2579ab4382d2SGreg Kroah-Hartman if (ret) 2580ab4382d2SGreg Kroah-Hartman return ret; 2581ab4382d2SGreg Kroah-Hartman 25829d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2583ab4382d2SGreg Kroah-Hartman if (ret != 0) 25849d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2585ab4382d2SGreg Kroah-Hartman 2586f227824eSUwe Kleine-König return ret; 2587ab4382d2SGreg Kroah-Hartman } 2588ab4382d2SGreg Kroah-Hartman 25899d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2590ab4382d2SGreg Kroah-Hartman { 25919d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 25929d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2593ab4382d2SGreg Kroah-Hartman } 2594ab4382d2SGreg Kroah-Hartman 25959d1a50a2SUwe Kleine-König module_init(imx_uart_init); 25969d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2597ab4382d2SGreg Kroah-Hartman 2598ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2599ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2600ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2601ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2602