1ab4382d2SGreg Kroah-Hartman /* 2ab4382d2SGreg Kroah-Hartman * Driver for Motorola IMX serial ports 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 7ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 8ab4382d2SGreg Kroah-Hartman * 9ab4382d2SGreg Kroah-Hartman * Copyright (C) 2009 emlix GmbH 10ab4382d2SGreg Kroah-Hartman * Author: Fabian Godehardt (added IrDA support for iMX) 11ab4382d2SGreg Kroah-Hartman * 12ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 13ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 14ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2 of the License, or 15ab4382d2SGreg Kroah-Hartman * (at your option) any later version. 16ab4382d2SGreg Kroah-Hartman * 17ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 18ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY; without even the implied warranty of 19ab4382d2SGreg Kroah-Hartman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20ab4382d2SGreg Kroah-Hartman * GNU General Public License for more details. 21ab4382d2SGreg Kroah-Hartman * 22ab4382d2SGreg Kroah-Hartman * You should have received a copy of the GNU General Public License 23ab4382d2SGreg Kroah-Hartman * along with this program; if not, write to the Free Software 24ab4382d2SGreg Kroah-Hartman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25ab4382d2SGreg Kroah-Hartman * 26ab4382d2SGreg Kroah-Hartman * [29-Mar-2005] Mike Lee 27ab4382d2SGreg Kroah-Hartman * Added hardware handshake 28ab4382d2SGreg Kroah-Hartman */ 29ab4382d2SGreg Kroah-Hartman 30ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 32ab4382d2SGreg Kroah-Hartman #endif 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 35ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 36ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 37ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 38ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 39ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 40ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 41ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 42ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 43ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 44ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 45ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 46ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 47ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 4822698aa2SShawn Guo #include <linux/of.h> 4922698aa2SShawn Guo #include <linux/of_device.h> 50e32a9f8fSSachin Kamat #include <linux/io.h> 51b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 52ab4382d2SGreg Kroah-Hartman 53ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 5482906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 55b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 56ab4382d2SGreg Kroah-Hartman 57ab4382d2SGreg Kroah-Hartman /* Register definitions */ 58ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 59ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 60ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 61ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 62ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 63ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 64ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 65ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 66ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 67ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 68ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 69ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 70ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 71ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 72fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 73fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 74fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 75ab4382d2SGreg Kroah-Hartman 76ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 7755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 78ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 79ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 80ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 81ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 82ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 83ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 8426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 8525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 86ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 87ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 88ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 89b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 90ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 91ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 93ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 94ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 95ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 96ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 97fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 98b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 100ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 101ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 102ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 103ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 104ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 105ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 108ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 109ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 110ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 11101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 112ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 113ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 114ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 115ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 119ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 120ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 121b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 122ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 125fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 126ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 127ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 128ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 129ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 130ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 131ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 132ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 133ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 134b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 135ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 136ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 137ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 138ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 139ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 140ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1417be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 142ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 143ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 144ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 145ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 146ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 147ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 148ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 149ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 150ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 151ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 152ab4382d2SGreg Kroah-Hartman #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 153ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 154ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 155ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 156ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 157ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 158ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 159ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 160ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 161ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 162ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 163ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 164ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 165ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 166ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 167ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 168ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 169ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 170ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 171ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 172ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 173ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 174ab4382d2SGreg Kroah-Hartman 175ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 176ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 177ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 178ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 179ab4382d2SGreg Kroah-Hartman 180ab4382d2SGreg Kroah-Hartman /* 181ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 182ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 183ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 184ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 185ab4382d2SGreg Kroah-Hartman */ 186ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 187ab4382d2SGreg Kroah-Hartman 188ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 189ab4382d2SGreg Kroah-Hartman 190ab4382d2SGreg Kroah-Hartman #define UART_NR 8 191ab4382d2SGreg Kroah-Hartman 192fe6b540aSShawn Guo /* i.mx21 type uart runs on all i.mx except i.mx1 */ 193fe6b540aSShawn Guo enum imx_uart_type { 194fe6b540aSShawn Guo IMX1_UART, 195fe6b540aSShawn Guo IMX21_UART, 196a496e628SHuang Shijie IMX6Q_UART, 197fe6b540aSShawn Guo }; 198fe6b540aSShawn Guo 199fe6b540aSShawn Guo /* device type dependent stuff */ 200fe6b540aSShawn Guo struct imx_uart_data { 201fe6b540aSShawn Guo unsigned uts_reg; 202fe6b540aSShawn Guo enum imx_uart_type devtype; 203fe6b540aSShawn Guo }; 204fe6b540aSShawn Guo 205ab4382d2SGreg Kroah-Hartman struct imx_port { 206ab4382d2SGreg Kroah-Hartman struct uart_port port; 207ab4382d2SGreg Kroah-Hartman struct timer_list timer; 208ab4382d2SGreg Kroah-Hartman unsigned int old_status; 209ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 21020ff2fe6SHuang Shijie unsigned int dte_mode:1; 211ab4382d2SGreg Kroah-Hartman unsigned int use_irda:1; 212ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_rx:1; 213ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_tx:1; 214ab4382d2SGreg Kroah-Hartman unsigned short trcv_delay; /* transceiver delay */ 2153a9465faSSascha Hauer struct clk *clk_ipg; 2163a9465faSSascha Hauer struct clk *clk_per; 2177d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 218b4cdc8f6SHuang Shijie 219b4cdc8f6SHuang Shijie /* DMA fields */ 220b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 221b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 224b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 225b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 226b4cdc8f6SHuang Shijie void *rx_buf; 2277cb92fd2SHuang Shijie unsigned int tx_bytes; 228b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 2299ce4f8f3SGreg Kroah-Hartman wait_queue_head_t dma_wait; 230ab4382d2SGreg Kroah-Hartman }; 231ab4382d2SGreg Kroah-Hartman 2320ad5a814SDirk Behme struct imx_port_ucrs { 2330ad5a814SDirk Behme unsigned int ucr1; 2340ad5a814SDirk Behme unsigned int ucr2; 2350ad5a814SDirk Behme unsigned int ucr3; 2360ad5a814SDirk Behme }; 2370ad5a814SDirk Behme 238ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_IRDA 239ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) ((sport)->use_irda) 240ab4382d2SGreg Kroah-Hartman #else 241ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) (0) 242ab4382d2SGreg Kroah-Hartman #endif 243ab4382d2SGreg Kroah-Hartman 244fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 245fe6b540aSShawn Guo [IMX1_UART] = { 246fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 247fe6b540aSShawn Guo .devtype = IMX1_UART, 248fe6b540aSShawn Guo }, 249fe6b540aSShawn Guo [IMX21_UART] = { 250fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 251fe6b540aSShawn Guo .devtype = IMX21_UART, 252fe6b540aSShawn Guo }, 253a496e628SHuang Shijie [IMX6Q_UART] = { 254a496e628SHuang Shijie .uts_reg = IMX21_UTS, 255a496e628SHuang Shijie .devtype = IMX6Q_UART, 256a496e628SHuang Shijie }, 257fe6b540aSShawn Guo }; 258fe6b540aSShawn Guo 259fe6b540aSShawn Guo static struct platform_device_id imx_uart_devtype[] = { 260fe6b540aSShawn Guo { 261fe6b540aSShawn Guo .name = "imx1-uart", 262fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 263fe6b540aSShawn Guo }, { 264fe6b540aSShawn Guo .name = "imx21-uart", 265fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 266fe6b540aSShawn Guo }, { 267a496e628SHuang Shijie .name = "imx6q-uart", 268a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 269a496e628SHuang Shijie }, { 270fe6b540aSShawn Guo /* sentinel */ 271fe6b540aSShawn Guo } 272fe6b540aSShawn Guo }; 273fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 274fe6b540aSShawn Guo 275ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 276a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 27722698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27822698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27922698aa2SShawn Guo { /* sentinel */ } 28022698aa2SShawn Guo }; 28122698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28222698aa2SShawn Guo 283fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 284fe6b540aSShawn Guo { 285fe6b540aSShawn Guo return sport->devdata->uts_reg; 286fe6b540aSShawn Guo } 287fe6b540aSShawn Guo 288fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 289fe6b540aSShawn Guo { 290fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 291fe6b540aSShawn Guo } 292fe6b540aSShawn Guo 293fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 294fe6b540aSShawn Guo { 295fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 296fe6b540aSShawn Guo } 297fe6b540aSShawn Guo 298a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 299a496e628SHuang Shijie { 300a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 301a496e628SHuang Shijie } 302ab4382d2SGreg Kroah-Hartman /* 30344a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 30444a75411Sfabio.estevam@freescale.com */ 30593d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 30644a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 30744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30844a75411Sfabio.estevam@freescale.com { 30944a75411Sfabio.estevam@freescale.com /* save control registers */ 31044a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 31144a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 31244a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 31344a75411Sfabio.estevam@freescale.com } 31444a75411Sfabio.estevam@freescale.com 31544a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 31644a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 31744a75411Sfabio.estevam@freescale.com { 31844a75411Sfabio.estevam@freescale.com /* restore control registers */ 31944a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 32044a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 32144a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 32244a75411Sfabio.estevam@freescale.com } 323e8bfa760SFabio Estevam #endif 32444a75411Sfabio.estevam@freescale.com 32544a75411Sfabio.estevam@freescale.com /* 326ab4382d2SGreg Kroah-Hartman * Handle any change of modem status signal since we were last called. 327ab4382d2SGreg Kroah-Hartman */ 328ab4382d2SGreg Kroah-Hartman static void imx_mctrl_check(struct imx_port *sport) 329ab4382d2SGreg Kroah-Hartman { 330ab4382d2SGreg Kroah-Hartman unsigned int status, changed; 331ab4382d2SGreg Kroah-Hartman 332ab4382d2SGreg Kroah-Hartman status = sport->port.ops->get_mctrl(&sport->port); 333ab4382d2SGreg Kroah-Hartman changed = status ^ sport->old_status; 334ab4382d2SGreg Kroah-Hartman 335ab4382d2SGreg Kroah-Hartman if (changed == 0) 336ab4382d2SGreg Kroah-Hartman return; 337ab4382d2SGreg Kroah-Hartman 338ab4382d2SGreg Kroah-Hartman sport->old_status = status; 339ab4382d2SGreg Kroah-Hartman 340ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_RI) 341ab4382d2SGreg Kroah-Hartman sport->port.icount.rng++; 342ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_DSR) 343ab4382d2SGreg Kroah-Hartman sport->port.icount.dsr++; 344ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CAR) 345ab4382d2SGreg Kroah-Hartman uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 346ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CTS) 347ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 348ab4382d2SGreg Kroah-Hartman 349ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 350ab4382d2SGreg Kroah-Hartman } 351ab4382d2SGreg Kroah-Hartman 352ab4382d2SGreg Kroah-Hartman /* 353ab4382d2SGreg Kroah-Hartman * This is our per-port timeout handler, for checking the 354ab4382d2SGreg Kroah-Hartman * modem status signals. 355ab4382d2SGreg Kroah-Hartman */ 356ab4382d2SGreg Kroah-Hartman static void imx_timeout(unsigned long data) 357ab4382d2SGreg Kroah-Hartman { 358ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)data; 359ab4382d2SGreg Kroah-Hartman unsigned long flags; 360ab4382d2SGreg Kroah-Hartman 361ab4382d2SGreg Kroah-Hartman if (sport->port.state) { 362ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 363ab4382d2SGreg Kroah-Hartman imx_mctrl_check(sport); 364ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 365ab4382d2SGreg Kroah-Hartman 366ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 367ab4382d2SGreg Kroah-Hartman } 368ab4382d2SGreg Kroah-Hartman } 369ab4382d2SGreg Kroah-Hartman 370ab4382d2SGreg Kroah-Hartman /* 371ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 372ab4382d2SGreg Kroah-Hartman */ 373ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 374ab4382d2SGreg Kroah-Hartman { 375ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 376ab4382d2SGreg Kroah-Hartman unsigned long temp; 377ab4382d2SGreg Kroah-Hartman 378ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 379ab4382d2SGreg Kroah-Hartman /* half duplex - wait for end of transmission */ 380ab4382d2SGreg Kroah-Hartman int n = 256; 381ab4382d2SGreg Kroah-Hartman while ((--n > 0) && 382ab4382d2SGreg Kroah-Hartman !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 383ab4382d2SGreg Kroah-Hartman udelay(5); 384ab4382d2SGreg Kroah-Hartman barrier(); 385ab4382d2SGreg Kroah-Hartman } 386ab4382d2SGreg Kroah-Hartman /* 387ab4382d2SGreg Kroah-Hartman * irda transceiver - wait a bit more to avoid 388ab4382d2SGreg Kroah-Hartman * cutoff, hardware dependent 389ab4382d2SGreg Kroah-Hartman */ 390ab4382d2SGreg Kroah-Hartman udelay(sport->trcv_delay); 391ab4382d2SGreg Kroah-Hartman 392ab4382d2SGreg Kroah-Hartman /* 393ab4382d2SGreg Kroah-Hartman * half duplex - reactivate receive mode, 394ab4382d2SGreg Kroah-Hartman * flush receive pipe echo crap 395ab4382d2SGreg Kroah-Hartman */ 396ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR2) & USR2_TXDC) { 397ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 398ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 399ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 400ab4382d2SGreg Kroah-Hartman 401ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 402ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_TCEN); 403ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 404ab4382d2SGreg Kroah-Hartman 405ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + URXD0) & 406ab4382d2SGreg Kroah-Hartman URXD_CHARRDY) 407ab4382d2SGreg Kroah-Hartman barrier(); 408ab4382d2SGreg Kroah-Hartman 409ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 410ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN; 411ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 412ab4382d2SGreg Kroah-Hartman 413ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 414ab4382d2SGreg Kroah-Hartman temp |= UCR4_DREN; 415ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 416ab4382d2SGreg Kroah-Hartman } 417ab4382d2SGreg Kroah-Hartman return; 418ab4382d2SGreg Kroah-Hartman } 419ab4382d2SGreg Kroah-Hartman 4209ce4f8f3SGreg Kroah-Hartman /* 4219ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4229ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4239ce4f8f3SGreg Kroah-Hartman */ 4249ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 4259ce4f8f3SGreg Kroah-Hartman return; 426b4cdc8f6SHuang Shijie 427ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 428ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 429ab4382d2SGreg Kroah-Hartman } 430ab4382d2SGreg Kroah-Hartman 431ab4382d2SGreg Kroah-Hartman /* 432ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 433ab4382d2SGreg Kroah-Hartman */ 434ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 435ab4382d2SGreg Kroah-Hartman { 436ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 437ab4382d2SGreg Kroah-Hartman unsigned long temp; 438ab4382d2SGreg Kroah-Hartman 43945564a66SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) { 44045564a66SHuang Shijie if (sport->port.suspended) { 44145564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 44245564a66SHuang Shijie sport->dma_is_rxing = 0; 44345564a66SHuang Shijie } else { 4449ce4f8f3SGreg Kroah-Hartman return; 44545564a66SHuang Shijie } 44645564a66SHuang Shijie } 447b4cdc8f6SHuang Shijie 448ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 449ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 45085878399SHuang Shijie 45185878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 45285878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 45385878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 454ab4382d2SGreg Kroah-Hartman } 455ab4382d2SGreg Kroah-Hartman 456ab4382d2SGreg Kroah-Hartman /* 457ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 458ab4382d2SGreg Kroah-Hartman */ 459ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 460ab4382d2SGreg Kroah-Hartman { 461ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 462ab4382d2SGreg Kroah-Hartman 463ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 464ab4382d2SGreg Kroah-Hartman } 465ab4382d2SGreg Kroah-Hartman 46691a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 467ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 468ab4382d2SGreg Kroah-Hartman { 469ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 47091a1a909SJiada Wang unsigned long temp; 471ab4382d2SGreg Kroah-Hartman 4725e42e9a3SPeter Hurley if (sport->port.x_char) { 4735e42e9a3SPeter Hurley /* Send next char */ 4745e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4757e2fb5aaSJiada Wang sport->port.icount.tx++; 4767e2fb5aaSJiada Wang sport->port.x_char = 0; 4775e42e9a3SPeter Hurley return; 4785e42e9a3SPeter Hurley } 4795e42e9a3SPeter Hurley 4805e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4815e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4825e42e9a3SPeter Hurley return; 4835e42e9a3SPeter Hurley } 4845e42e9a3SPeter Hurley 48591a1a909SJiada Wang if (sport->dma_is_enabled) { 48691a1a909SJiada Wang /* 48791a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 48891a1a909SJiada Wang * and the TX IRQ is disabled. 48991a1a909SJiada Wang **/ 49091a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 49191a1a909SJiada Wang temp &= ~UCR1_TXMPTYEN; 49291a1a909SJiada Wang if (sport->dma_is_txing) { 49391a1a909SJiada Wang temp |= UCR1_TDMAEN; 49491a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 49591a1a909SJiada Wang } else { 49691a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 49791a1a909SJiada Wang imx_dma_tx(sport); 49891a1a909SJiada Wang } 49991a1a909SJiada Wang } 50091a1a909SJiada Wang 501ab4382d2SGreg Kroah-Hartman while (!uart_circ_empty(xmit) && 5025e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 503ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 504ab4382d2SGreg Kroah-Hartman * out the port here */ 505ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 506ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 507ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 508ab4382d2SGreg Kroah-Hartman } 509ab4382d2SGreg Kroah-Hartman 510ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 511ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 512ab4382d2SGreg Kroah-Hartman 513ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 514ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 515ab4382d2SGreg Kroah-Hartman } 516ab4382d2SGreg Kroah-Hartman 517b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 518b4cdc8f6SHuang Shijie { 519b4cdc8f6SHuang Shijie struct imx_port *sport = data; 520b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 521b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 522b4cdc8f6SHuang Shijie unsigned long flags; 523a2c718ceSDirk Behme unsigned long temp; 524b4cdc8f6SHuang Shijie 52542f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 52642f752b3SDirk Behme 527b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 528b4cdc8f6SHuang Shijie 529a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 530a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 531a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 532a2c718ceSDirk Behme 53342f752b3SDirk Behme /* update the stat */ 53442f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 53542f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 53642f752b3SDirk Behme 53742f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 53842f752b3SDirk Behme 539b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 540b4cdc8f6SHuang Shijie 541b4cdc8f6SHuang Shijie spin_unlock_irqrestore(&sport->port.lock, flags); 542b4cdc8f6SHuang Shijie 543d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 544b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5459ce4f8f3SGreg Kroah-Hartman 5469ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) { 5479ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 5489ce4f8f3SGreg Kroah-Hartman dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 5499ce4f8f3SGreg Kroah-Hartman return; 5509ce4f8f3SGreg Kroah-Hartman } 5510bbc9b81SJiada Wang 5520bbc9b81SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 5530bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5540bbc9b81SJiada Wang imx_dma_tx(sport); 5550bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 556b4cdc8f6SHuang Shijie } 557b4cdc8f6SHuang Shijie 5587cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 559b4cdc8f6SHuang Shijie { 560b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 561b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 562b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 563b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 564b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 565a2c718ceSDirk Behme unsigned long temp; 566b4cdc8f6SHuang Shijie int ret; 567b4cdc8f6SHuang Shijie 56842f752b3SDirk Behme if (sport->dma_is_txing) 569b4cdc8f6SHuang Shijie return; 570b4cdc8f6SHuang Shijie 571b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 572b4cdc8f6SHuang Shijie 5737942f857SDirk Behme if (xmit->tail < xmit->head) { 5747942f857SDirk Behme sport->dma_tx_nents = 1; 5757942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5767942f857SDirk Behme } else { 577b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 578b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 579b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 580b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 581b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 582b4cdc8f6SHuang Shijie } 583b4cdc8f6SHuang Shijie 584b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 585b4cdc8f6SHuang Shijie if (ret == 0) { 586b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 587b4cdc8f6SHuang Shijie return; 588b4cdc8f6SHuang Shijie } 589b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 590b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 591b4cdc8f6SHuang Shijie if (!desc) { 59224649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 59324649821SDirk Behme DMA_TO_DEVICE); 594b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 595b4cdc8f6SHuang Shijie return; 596b4cdc8f6SHuang Shijie } 597b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 598b4cdc8f6SHuang Shijie desc->callback_param = sport; 599b4cdc8f6SHuang Shijie 600b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 601b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 602a2c718ceSDirk Behme 603a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 604a2c718ceSDirk Behme temp |= UCR1_TDMAEN; 605a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 606a2c718ceSDirk Behme 607b4cdc8f6SHuang Shijie /* fire it */ 608b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 609b4cdc8f6SHuang Shijie dmaengine_submit(desc); 610b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 611b4cdc8f6SHuang Shijie return; 612b4cdc8f6SHuang Shijie } 613b4cdc8f6SHuang Shijie 614ab4382d2SGreg Kroah-Hartman /* 615ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 616ab4382d2SGreg Kroah-Hartman */ 617ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 618ab4382d2SGreg Kroah-Hartman { 619ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 620ab4382d2SGreg Kroah-Hartman unsigned long temp; 621ab4382d2SGreg Kroah-Hartman 622ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 623ab4382d2SGreg Kroah-Hartman /* half duplex in IrDA mode; have to disable receive mode */ 624ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 625ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_DREN); 626ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 627ab4382d2SGreg Kroah-Hartman 628ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 629ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RRDYEN); 630ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 631ab4382d2SGreg Kroah-Hartman } 632ab4382d2SGreg Kroah-Hartman 633b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 634ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 635ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 636b4cdc8f6SHuang Shijie } 637ab4382d2SGreg Kroah-Hartman 638ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 639ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 640ab4382d2SGreg Kroah-Hartman temp |= UCR1_TRDYEN; 641ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 642ab4382d2SGreg Kroah-Hartman 643ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 644ab4382d2SGreg Kroah-Hartman temp |= UCR4_TCEN; 645ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 646ab4382d2SGreg Kroah-Hartman } 647ab4382d2SGreg Kroah-Hartman 648b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 64991a1a909SJiada Wang if (sport->port.x_char) { 65091a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 65191a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 65291a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 65391a1a909SJiada Wang temp &= ~UCR1_TDMAEN; 65491a1a909SJiada Wang temp |= UCR1_TXMPTYEN; 65591a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 65691a1a909SJiada Wang return; 65791a1a909SJiada Wang } 65891a1a909SJiada Wang 6595e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6605e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6617cb92fd2SHuang Shijie imx_dma_tx(sport); 662b4cdc8f6SHuang Shijie return; 663b4cdc8f6SHuang Shijie } 664ab4382d2SGreg Kroah-Hartman } 665ab4382d2SGreg Kroah-Hartman 666ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 667ab4382d2SGreg Kroah-Hartman { 668ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6695680e941SUwe Kleine-König unsigned int val; 670ab4382d2SGreg Kroah-Hartman unsigned long flags; 671ab4382d2SGreg Kroah-Hartman 672ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 673ab4382d2SGreg Kroah-Hartman 674ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6755680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 676ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 677ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 678ab4382d2SGreg Kroah-Hartman 679ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 680ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 681ab4382d2SGreg Kroah-Hartman } 682ab4382d2SGreg Kroah-Hartman 683ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 684ab4382d2SGreg Kroah-Hartman { 685ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 686ab4382d2SGreg Kroah-Hartman unsigned long flags; 687ab4382d2SGreg Kroah-Hartman 688ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 689ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 690ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 691ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 692ab4382d2SGreg Kroah-Hartman } 693ab4382d2SGreg Kroah-Hartman 694ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 695ab4382d2SGreg Kroah-Hartman { 696ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 697ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 69892a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 699ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 700ab4382d2SGreg Kroah-Hartman 701ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 702ab4382d2SGreg Kroah-Hartman 703ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 704ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 705ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 706ab4382d2SGreg Kroah-Hartman 707ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 708ab4382d2SGreg Kroah-Hartman 709ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 710ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 711ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 712ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 713ab4382d2SGreg Kroah-Hartman continue; 714ab4382d2SGreg Kroah-Hartman } 715ab4382d2SGreg Kroah-Hartman 716ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 717ab4382d2SGreg Kroah-Hartman continue; 718ab4382d2SGreg Kroah-Hartman 719019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 720019dc9eaSHui Wang if (rx & URXD_BRK) 721019dc9eaSHui Wang sport->port.icount.brk++; 722019dc9eaSHui Wang else if (rx & URXD_PRERR) 723ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 724ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 725ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 726ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 727ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 728ab4382d2SGreg Kroah-Hartman 729ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 730ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 731ab4382d2SGreg Kroah-Hartman goto out; 732ab4382d2SGreg Kroah-Hartman continue; 733ab4382d2SGreg Kroah-Hartman } 734ab4382d2SGreg Kroah-Hartman 7358d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 736ab4382d2SGreg Kroah-Hartman 737019dc9eaSHui Wang if (rx & URXD_BRK) 738019dc9eaSHui Wang flg = TTY_BREAK; 739019dc9eaSHui Wang else if (rx & URXD_PRERR) 740ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 741ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 742ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 743ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 744ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 745ab4382d2SGreg Kroah-Hartman 746ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 747ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 748ab4382d2SGreg Kroah-Hartman #endif 749ab4382d2SGreg Kroah-Hartman } 750ab4382d2SGreg Kroah-Hartman 75155d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 75255d8693aSJiada Wang goto out; 75355d8693aSJiada Wang 75492a19f9cSJiri Slaby tty_insert_flip_char(port, rx, flg); 755ab4382d2SGreg Kroah-Hartman } 756ab4382d2SGreg Kroah-Hartman 757ab4382d2SGreg Kroah-Hartman out: 758ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7592e124b4aSJiri Slaby tty_flip_buffer_push(port); 760ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 761ab4382d2SGreg Kroah-Hartman } 762ab4382d2SGreg Kroah-Hartman 7637cb92fd2SHuang Shijie static int start_rx_dma(struct imx_port *sport); 764b4cdc8f6SHuang Shijie /* 765b4cdc8f6SHuang Shijie * If the RXFIFO is filled with some data, and then we 766b4cdc8f6SHuang Shijie * arise a DMA operation to receive them. 767b4cdc8f6SHuang Shijie */ 768b4cdc8f6SHuang Shijie static void imx_dma_rxint(struct imx_port *sport) 769b4cdc8f6SHuang Shijie { 770b4cdc8f6SHuang Shijie unsigned long temp; 77173631813SJiada Wang unsigned long flags; 77273631813SJiada Wang 77373631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 774b4cdc8f6SHuang Shijie 775b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + USR2); 776b4cdc8f6SHuang Shijie if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 777b4cdc8f6SHuang Shijie sport->dma_is_rxing = 1; 778b4cdc8f6SHuang Shijie 779b4cdc8f6SHuang Shijie /* disable the `Recerver Ready Interrrupt` */ 780b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 781b4cdc8f6SHuang Shijie temp &= ~(UCR1_RRDYEN); 782b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 783b4cdc8f6SHuang Shijie 784b4cdc8f6SHuang Shijie /* tell the DMA to receive the data. */ 7857cb92fd2SHuang Shijie start_rx_dma(sport); 786b4cdc8f6SHuang Shijie } 78773631813SJiada Wang 78873631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 789b4cdc8f6SHuang Shijie } 790b4cdc8f6SHuang Shijie 791ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 792ab4382d2SGreg Kroah-Hartman { 793ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 794ab4382d2SGreg Kroah-Hartman unsigned int sts; 795f1f836e4SAlexander Stein unsigned int sts2; 796ab4382d2SGreg Kroah-Hartman 797ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 798ab4382d2SGreg Kroah-Hartman 799b4cdc8f6SHuang Shijie if (sts & USR1_RRDY) { 800b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) 801b4cdc8f6SHuang Shijie imx_dma_rxint(sport); 802b4cdc8f6SHuang Shijie else 803ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 804b4cdc8f6SHuang Shijie } 805ab4382d2SGreg Kroah-Hartman 806ab4382d2SGreg Kroah-Hartman if (sts & USR1_TRDY && 807ab4382d2SGreg Kroah-Hartman readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 808ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 809ab4382d2SGreg Kroah-Hartman 810ab4382d2SGreg Kroah-Hartman if (sts & USR1_RTSD) 811ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 812ab4382d2SGreg Kroah-Hartman 813db1a9b55SFabio Estevam if (sts & USR1_AWAKE) 814db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 815db1a9b55SFabio Estevam 816f1f836e4SAlexander Stein sts2 = readl(sport->port.membase + USR2); 817f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 818f1f836e4SAlexander Stein dev_err(sport->port.dev, "Rx FIFO overrun\n"); 819f1f836e4SAlexander Stein sport->port.icount.overrun++; 82091555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 821f1f836e4SAlexander Stein } 822f1f836e4SAlexander Stein 823ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 824ab4382d2SGreg Kroah-Hartman } 825ab4382d2SGreg Kroah-Hartman 826ab4382d2SGreg Kroah-Hartman /* 827ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 828ab4382d2SGreg Kroah-Hartman */ 829ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 830ab4382d2SGreg Kroah-Hartman { 831ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 8321ce43e58SHuang Shijie unsigned int ret; 833ab4382d2SGreg Kroah-Hartman 8341ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 8351ce43e58SHuang Shijie 8361ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 8371ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 8381ce43e58SHuang Shijie ret = 0; 8391ce43e58SHuang Shijie 8401ce43e58SHuang Shijie return ret; 841ab4382d2SGreg Kroah-Hartman } 842ab4382d2SGreg Kroah-Hartman 843ab4382d2SGreg Kroah-Hartman /* 844ab4382d2SGreg Kroah-Hartman * We have a modem side uart, so the meanings of RTS and CTS are inverted. 845ab4382d2SGreg Kroah-Hartman */ 846ab4382d2SGreg Kroah-Hartman static unsigned int imx_get_mctrl(struct uart_port *port) 847ab4382d2SGreg Kroah-Hartman { 848ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 849ab4382d2SGreg Kroah-Hartman unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 850ab4382d2SGreg Kroah-Hartman 851ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR1) & USR1_RTSS) 852ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_CTS; 853ab4382d2SGreg Kroah-Hartman 854ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR2) & UCR2_CTS) 855ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_RTS; 856ab4382d2SGreg Kroah-Hartman 8576b471a98SHuang Shijie if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 8586b471a98SHuang Shijie tmp |= TIOCM_LOOP; 8596b471a98SHuang Shijie 860ab4382d2SGreg Kroah-Hartman return tmp; 861ab4382d2SGreg Kroah-Hartman } 862ab4382d2SGreg Kroah-Hartman 863ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 864ab4382d2SGreg Kroah-Hartman { 865ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 866ab4382d2SGreg Kroah-Hartman unsigned long temp; 867ab4382d2SGreg Kroah-Hartman 868bb2f861aSFugang Duan temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC); 869ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 870bb2f861aSFugang Duan temp |= UCR2_CTS | UCR2_CTSC; 871ab4382d2SGreg Kroah-Hartman 872ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 8736b471a98SHuang Shijie 8746b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8756b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8766b471a98SHuang Shijie temp |= UTS_LOOP; 8776b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 878ab4382d2SGreg Kroah-Hartman } 879ab4382d2SGreg Kroah-Hartman 880ab4382d2SGreg Kroah-Hartman /* 881ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 882ab4382d2SGreg Kroah-Hartman */ 883ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 884ab4382d2SGreg Kroah-Hartman { 885ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 886ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 887ab4382d2SGreg Kroah-Hartman 888ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 889ab4382d2SGreg Kroah-Hartman 890ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 891ab4382d2SGreg Kroah-Hartman 892ab4382d2SGreg Kroah-Hartman if (break_state != 0) 893ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 894ab4382d2SGreg Kroah-Hartman 895ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 896ab4382d2SGreg Kroah-Hartman 897ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 898ab4382d2SGreg Kroah-Hartman } 899ab4382d2SGreg Kroah-Hartman 900ab4382d2SGreg Kroah-Hartman #define TXTL 2 /* reset default */ 901ab4382d2SGreg Kroah-Hartman #define RXTL 1 /* reset default */ 902ab4382d2SGreg Kroah-Hartman 903ab4382d2SGreg Kroah-Hartman static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 904ab4382d2SGreg Kroah-Hartman { 905ab4382d2SGreg Kroah-Hartman unsigned int val; 906ab4382d2SGreg Kroah-Hartman 9077be0670fSDirk Behme /* set receiver / transmitter trigger level */ 9087be0670fSDirk Behme val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 9097be0670fSDirk Behme val |= TXTL << UFCR_TXTL_SHF | RXTL; 910ab4382d2SGreg Kroah-Hartman writel(val, sport->port.membase + UFCR); 911ab4382d2SGreg Kroah-Hartman return 0; 912ab4382d2SGreg Kroah-Hartman } 913ab4382d2SGreg Kroah-Hartman 914b4cdc8f6SHuang Shijie #define RX_BUF_SIZE (PAGE_SIZE) 915b4cdc8f6SHuang Shijie static void imx_rx_dma_done(struct imx_port *sport) 916b4cdc8f6SHuang Shijie { 917b4cdc8f6SHuang Shijie unsigned long temp; 91873631813SJiada Wang unsigned long flags; 91973631813SJiada Wang 92073631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 921b4cdc8f6SHuang Shijie 922b4cdc8f6SHuang Shijie /* Enable this interrupt when the RXFIFO is empty. */ 923b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 924b4cdc8f6SHuang Shijie temp |= UCR1_RRDYEN; 925b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 926b4cdc8f6SHuang Shijie 927b4cdc8f6SHuang Shijie sport->dma_is_rxing = 0; 9289ce4f8f3SGreg Kroah-Hartman 9299ce4f8f3SGreg Kroah-Hartman /* Is the shutdown waiting for us? */ 9309ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) 9319ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 93273631813SJiada Wang 93373631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 934b4cdc8f6SHuang Shijie } 935b4cdc8f6SHuang Shijie 936b4cdc8f6SHuang Shijie /* 937b4cdc8f6SHuang Shijie * There are three kinds of RX DMA interrupts(such as in the MX6Q): 938b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 939b4cdc8f6SHuang Shijie * [2] the Aging timer expires(wait for 8 bytes long) 940b4cdc8f6SHuang Shijie * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 941b4cdc8f6SHuang Shijie * 942b4cdc8f6SHuang Shijie * The [2] is trigger when a character was been sitting in the FIFO 943b4cdc8f6SHuang Shijie * meanwhile [3] can wait for 32 bytes long when the RX line is 944b4cdc8f6SHuang Shijie * on IDLE state and RxFIFO is empty. 945b4cdc8f6SHuang Shijie */ 946b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 947b4cdc8f6SHuang Shijie { 948b4cdc8f6SHuang Shijie struct imx_port *sport = data; 949b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 950b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9517cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 952b4cdc8f6SHuang Shijie struct dma_tx_state state; 953b4cdc8f6SHuang Shijie enum dma_status status; 954b4cdc8f6SHuang Shijie unsigned int count; 955b4cdc8f6SHuang Shijie 956b4cdc8f6SHuang Shijie /* unmap it first */ 957b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 958b4cdc8f6SHuang Shijie 959f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 960b4cdc8f6SHuang Shijie count = RX_BUF_SIZE - state.residue; 961b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 962b4cdc8f6SHuang Shijie 963b4cdc8f6SHuang Shijie if (count) { 96455d8693aSJiada Wang if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) 9657cb92fd2SHuang Shijie tty_insert_flip_string(port, sport->rx_buf, count); 9667cb92fd2SHuang Shijie tty_flip_buffer_push(port); 9677cb92fd2SHuang Shijie 9687cb92fd2SHuang Shijie start_rx_dma(sport); 969ee5e7c10SRobin Gong } else if (readl(sport->port.membase + USR2) & USR2_RDR) { 970ee5e7c10SRobin Gong /* 971ee5e7c10SRobin Gong * start rx_dma directly once data in RXFIFO, more efficient 972ee5e7c10SRobin Gong * than before: 973ee5e7c10SRobin Gong * 1. call imx_rx_dma_done to stop dma if no data received 974ee5e7c10SRobin Gong * 2. wait next RDR interrupt to start dma transfer. 975ee5e7c10SRobin Gong */ 976ee5e7c10SRobin Gong start_rx_dma(sport); 977ee5e7c10SRobin Gong } else { 978ee5e7c10SRobin Gong /* 979ee5e7c10SRobin Gong * stop dma to prevent too many IDLE event trigged if no data 980ee5e7c10SRobin Gong * in RXFIFO 981ee5e7c10SRobin Gong */ 982b4cdc8f6SHuang Shijie imx_rx_dma_done(sport); 983b4cdc8f6SHuang Shijie } 984ee5e7c10SRobin Gong } 985b4cdc8f6SHuang Shijie 986b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 987b4cdc8f6SHuang Shijie { 988b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 989b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 990b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 991b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 992b4cdc8f6SHuang Shijie int ret; 993b4cdc8f6SHuang Shijie 994b4cdc8f6SHuang Shijie sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 995b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 996b4cdc8f6SHuang Shijie if (ret == 0) { 997b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 998b4cdc8f6SHuang Shijie return -EINVAL; 999b4cdc8f6SHuang Shijie } 1000b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 1001b4cdc8f6SHuang Shijie DMA_PREP_INTERRUPT); 1002b4cdc8f6SHuang Shijie if (!desc) { 100324649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1004b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1005b4cdc8f6SHuang Shijie return -EINVAL; 1006b4cdc8f6SHuang Shijie } 1007b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 1008b4cdc8f6SHuang Shijie desc->callback_param = sport; 1009b4cdc8f6SHuang Shijie 1010b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 1011b4cdc8f6SHuang Shijie dmaengine_submit(desc); 1012b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1013b4cdc8f6SHuang Shijie return 0; 1014b4cdc8f6SHuang Shijie } 1015b4cdc8f6SHuang Shijie 1016b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1017b4cdc8f6SHuang Shijie { 1018b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1019b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1020b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 1021b4cdc8f6SHuang Shijie 1022b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1023b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1024b4cdc8f6SHuang Shijie } 1025b4cdc8f6SHuang Shijie 1026b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1027b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1028b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1029b4cdc8f6SHuang Shijie } 1030b4cdc8f6SHuang Shijie 1031b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 1032b4cdc8f6SHuang Shijie } 1033b4cdc8f6SHuang Shijie 1034b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1035b4cdc8f6SHuang Shijie { 1036b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1037b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1038b4cdc8f6SHuang Shijie int ret; 1039b4cdc8f6SHuang Shijie 1040b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1041b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1042b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1043b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1044b4cdc8f6SHuang Shijie ret = -EINVAL; 1045b4cdc8f6SHuang Shijie goto err; 1046b4cdc8f6SHuang Shijie } 1047b4cdc8f6SHuang Shijie 1048b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1049b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1050b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1051b4cdc8f6SHuang Shijie slave_config.src_maxburst = RXTL; 1052b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1053b4cdc8f6SHuang Shijie if (ret) { 1054b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1055b4cdc8f6SHuang Shijie goto err; 1056b4cdc8f6SHuang Shijie } 1057b4cdc8f6SHuang Shijie 1058b4cdc8f6SHuang Shijie sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1059b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1060b4cdc8f6SHuang Shijie ret = -ENOMEM; 1061b4cdc8f6SHuang Shijie goto err; 1062b4cdc8f6SHuang Shijie } 1063b4cdc8f6SHuang Shijie 1064b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1065b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1066b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1067b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1068b4cdc8f6SHuang Shijie ret = -EINVAL; 1069b4cdc8f6SHuang Shijie goto err; 1070b4cdc8f6SHuang Shijie } 1071b4cdc8f6SHuang Shijie 1072b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1073b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1074b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1075b4cdc8f6SHuang Shijie slave_config.dst_maxburst = TXTL; 1076b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1077b4cdc8f6SHuang Shijie if (ret) { 1078b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1079b4cdc8f6SHuang Shijie goto err; 1080b4cdc8f6SHuang Shijie } 1081b4cdc8f6SHuang Shijie 1082b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1083b4cdc8f6SHuang Shijie 1084b4cdc8f6SHuang Shijie return 0; 1085b4cdc8f6SHuang Shijie err: 1086b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1087b4cdc8f6SHuang Shijie return ret; 1088b4cdc8f6SHuang Shijie } 1089b4cdc8f6SHuang Shijie 1090b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1091b4cdc8f6SHuang Shijie { 1092b4cdc8f6SHuang Shijie unsigned long temp; 1093b4cdc8f6SHuang Shijie 10949ce4f8f3SGreg Kroah-Hartman init_waitqueue_head(&sport->dma_wait); 10959ce4f8f3SGreg Kroah-Hartman 1096b4cdc8f6SHuang Shijie /* set UCR1 */ 1097b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1098b4cdc8f6SHuang Shijie temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1099b4cdc8f6SHuang Shijie /* wait for 32 idle frames for IDDMA interrupt */ 1100b4cdc8f6SHuang Shijie UCR1_ICD_REG(3); 1101b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1102b4cdc8f6SHuang Shijie 1103b4cdc8f6SHuang Shijie /* set UCR4 */ 1104b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1105b4cdc8f6SHuang Shijie temp |= UCR4_IDDMAEN; 1106b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1107b4cdc8f6SHuang Shijie 1108b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1109b4cdc8f6SHuang Shijie } 1110b4cdc8f6SHuang Shijie 1111b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1112b4cdc8f6SHuang Shijie { 1113b4cdc8f6SHuang Shijie unsigned long temp; 1114b4cdc8f6SHuang Shijie 1115b4cdc8f6SHuang Shijie /* clear UCR1 */ 1116b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1117b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1118b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1119b4cdc8f6SHuang Shijie 1120b4cdc8f6SHuang Shijie /* clear UCR2 */ 1121b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 1122b4cdc8f6SHuang Shijie temp &= ~(UCR2_CTSC | UCR2_CTS); 1123b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1124b4cdc8f6SHuang Shijie 1125b4cdc8f6SHuang Shijie /* clear UCR4 */ 1126b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1127b4cdc8f6SHuang Shijie temp &= ~UCR4_IDDMAEN; 1128b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1129b4cdc8f6SHuang Shijie 1130b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1131b4cdc8f6SHuang Shijie } 1132b4cdc8f6SHuang Shijie 1133ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1134ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1135ab4382d2SGreg Kroah-Hartman 1136ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1137ab4382d2SGreg Kroah-Hartman { 1138ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1139772f8991SHuang Shijie int retval, i; 1140ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1141ab4382d2SGreg Kroah-Hartman 114228eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 114328eb4274SHuang Shijie if (retval) 1144cb0f0a5fSFabio Estevam return retval; 114528eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 11460c375501SHuang Shijie if (retval) { 11470c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1148cb0f0a5fSFabio Estevam return retval; 11490c375501SHuang Shijie } 115028eb4274SHuang Shijie 1151ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1152ab4382d2SGreg Kroah-Hartman 1153ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1154ab4382d2SGreg Kroah-Hartman * requesting IRQs 1155ab4382d2SGreg Kroah-Hartman */ 1156ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1157ab4382d2SGreg Kroah-Hartman 1158ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1159ab4382d2SGreg Kroah-Hartman temp |= UCR4_IRSC; 1160ab4382d2SGreg Kroah-Hartman 1161ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1162ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1163ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1164ab4382d2SGreg Kroah-Hartman 1165ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1166ab4382d2SGreg Kroah-Hartman 1167772f8991SHuang Shijie /* Reset fifo's and state machines */ 1168772f8991SHuang Shijie i = 100; 1169772f8991SHuang Shijie 1170ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1171ab4382d2SGreg Kroah-Hartman temp &= ~UCR2_SRST; 1172ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1173772f8991SHuang Shijie 1174772f8991SHuang Shijie while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1175ab4382d2SGreg Kroah-Hartman udelay(1); 1176ab4382d2SGreg Kroah-Hartman 1177068500e0SAnton Bondarenko /* Can we enable the DMA support? */ 1178068500e0SAnton Bondarenko if (is_imx6q_uart(sport) && !uart_console(port) && 1179068500e0SAnton Bondarenko !sport->dma_is_inited) 1180068500e0SAnton Bondarenko imx_uart_dma_init(sport); 1181068500e0SAnton Bondarenko 11829ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 118391555ce9SUwe Kleine-König 1184ab4382d2SGreg Kroah-Hartman /* 1185ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1186ab4382d2SGreg Kroah-Hartman */ 1187ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 118891555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 1189ab4382d2SGreg Kroah-Hartman 1190068500e0SAnton Bondarenko if (sport->dma_is_inited && !sport->dma_is_enabled) 1191068500e0SAnton Bondarenko imx_enable_dma(sport); 1192068500e0SAnton Bondarenko 1193ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1194ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1195ab4382d2SGreg Kroah-Hartman 1196ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1197ab4382d2SGreg Kroah-Hartman temp |= UCR1_IREN; 1198ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RTSDEN); 1199ab4382d2SGreg Kroah-Hartman } 1200ab4382d2SGreg Kroah-Hartman 1201ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1202ab4382d2SGreg Kroah-Hartman 12036f026d6bSJiada Wang temp = readl(sport->port.membase + UCR4); 12046f026d6bSJiada Wang temp |= UCR4_OREN; 12056f026d6bSJiada Wang writel(temp, sport->port.membase + UCR4); 12066f026d6bSJiada Wang 1207ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1208ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1209bff09b09SLucas Stach if (!sport->have_rtscts) 1210bff09b09SLucas Stach temp |= UCR2_IRTS; 1211ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1212ab4382d2SGreg Kroah-Hartman 1213a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1214ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1215b38cb7d2SFabio Estevam temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1216ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1217ab4382d2SGreg Kroah-Hartman } 1218ab4382d2SGreg Kroah-Hartman 1219ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1220ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1221ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_rx) 1222ab4382d2SGreg Kroah-Hartman temp |= UCR4_INVR; 1223ab4382d2SGreg Kroah-Hartman else 1224ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_INVR); 1225ab4382d2SGreg Kroah-Hartman writel(temp | UCR4_DREN, sport->port.membase + UCR4); 1226ab4382d2SGreg Kroah-Hartman 1227ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1228ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_tx) 1229ab4382d2SGreg Kroah-Hartman temp |= UCR3_INVT; 1230ab4382d2SGreg Kroah-Hartman else 1231ab4382d2SGreg Kroah-Hartman temp &= ~(UCR3_INVT); 1232ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1233ab4382d2SGreg Kroah-Hartman } 1234ab4382d2SGreg Kroah-Hartman 1235ab4382d2SGreg Kroah-Hartman /* 1236ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1237ab4382d2SGreg Kroah-Hartman */ 1238ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1239ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1240ab4382d2SGreg Kroah-Hartman 1241ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1242ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1243574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1244ab4382d2SGreg Kroah-Hartman sport->irda_inv_rx = pdata->irda_inv_rx; 1245ab4382d2SGreg Kroah-Hartman sport->irda_inv_tx = pdata->irda_inv_tx; 1246ab4382d2SGreg Kroah-Hartman sport->trcv_delay = pdata->transceiver_delay; 1247ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1248ab4382d2SGreg Kroah-Hartman pdata->irda_enable(1); 1249ab4382d2SGreg Kroah-Hartman } 1250ab4382d2SGreg Kroah-Hartman 1251ab4382d2SGreg Kroah-Hartman return 0; 1252ab4382d2SGreg Kroah-Hartman } 1253ab4382d2SGreg Kroah-Hartman 1254ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1255ab4382d2SGreg Kroah-Hartman { 1256ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1257ab4382d2SGreg Kroah-Hartman unsigned long temp; 12589ec1882dSXinyu Chen unsigned long flags; 1259ab4382d2SGreg Kroah-Hartman 1260b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1261a4688bcdSHuang Shijie int ret; 1262a4688bcdSHuang Shijie 12639ce4f8f3SGreg Kroah-Hartman /* We have to wait for the DMA to finish. */ 1264a4688bcdSHuang Shijie ret = wait_event_interruptible(sport->dma_wait, 12659ce4f8f3SGreg Kroah-Hartman !sport->dma_is_rxing && !sport->dma_is_txing); 1266a4688bcdSHuang Shijie if (ret != 0) { 1267a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1268a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1269a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 1270a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 1271a4688bcdSHuang Shijie } 127273631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1273a4688bcdSHuang Shijie imx_stop_tx(port); 1274b4cdc8f6SHuang Shijie imx_stop_rx(port); 1275b4cdc8f6SHuang Shijie imx_disable_dma(sport); 127673631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1277b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1278b4cdc8f6SHuang Shijie } 1279b4cdc8f6SHuang Shijie 12809ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1281ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1282ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1283ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 12849ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1285ab4382d2SGreg Kroah-Hartman 1286ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1287ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1288574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1289ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1290ab4382d2SGreg Kroah-Hartman pdata->irda_enable(0); 1291ab4382d2SGreg Kroah-Hartman } 1292ab4382d2SGreg Kroah-Hartman 1293ab4382d2SGreg Kroah-Hartman /* 1294ab4382d2SGreg Kroah-Hartman * Stop our timer. 1295ab4382d2SGreg Kroah-Hartman */ 1296ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1297ab4382d2SGreg Kroah-Hartman 1298ab4382d2SGreg Kroah-Hartman /* 1299ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1300ab4382d2SGreg Kroah-Hartman */ 1301ab4382d2SGreg Kroah-Hartman 13029ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1303ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1304ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1305ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1306ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_IREN); 1307ab4382d2SGreg Kroah-Hartman 1308ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 13099ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 131028eb4274SHuang Shijie 131128eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 131228eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1313ab4382d2SGreg Kroah-Hartman } 1314ab4382d2SGreg Kroah-Hartman 1315eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1316eb56b7edSHuang Shijie { 1317eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 131882e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1319a2c718ceSDirk Behme unsigned long temp; 13204f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1321eb56b7edSHuang Shijie 132282e86ae9SDirk Behme if (!sport->dma_chan_tx) 132382e86ae9SDirk Behme return; 132482e86ae9SDirk Behme 1325eb56b7edSHuang Shijie sport->tx_bytes = 0; 1326eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 132782e86ae9SDirk Behme if (sport->dma_is_txing) { 132882e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 132982e86ae9SDirk Behme DMA_TO_DEVICE); 1330a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 1331a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 1332a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 133382e86ae9SDirk Behme sport->dma_is_txing = false; 1334eb56b7edSHuang Shijie } 1335934084a9SFabio Estevam 1336934084a9SFabio Estevam /* 1337934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1338934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1339934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1340934084a9SFabio Estevam * and UTS[6-3]". As we don't need to restore the old values from 1341934084a9SFabio Estevam * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1342934084a9SFabio Estevam */ 1343934084a9SFabio Estevam ubir = readl(sport->port.membase + UBIR); 1344934084a9SFabio Estevam ubmr = readl(sport->port.membase + UBMR); 1345934084a9SFabio Estevam uts = readl(sport->port.membase + IMX21_UTS); 1346934084a9SFabio Estevam 1347934084a9SFabio Estevam temp = readl(sport->port.membase + UCR2); 1348934084a9SFabio Estevam temp &= ~UCR2_SRST; 1349934084a9SFabio Estevam writel(temp, sport->port.membase + UCR2); 1350934084a9SFabio Estevam 1351934084a9SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1352934084a9SFabio Estevam udelay(1); 1353934084a9SFabio Estevam 1354934084a9SFabio Estevam /* Restore the registers */ 1355934084a9SFabio Estevam writel(ubir, sport->port.membase + UBIR); 1356934084a9SFabio Estevam writel(ubmr, sport->port.membase + UBMR); 1357934084a9SFabio Estevam writel(uts, sport->port.membase + IMX21_UTS); 1358eb56b7edSHuang Shijie } 1359eb56b7edSHuang Shijie 1360ab4382d2SGreg Kroah-Hartman static void 1361ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1362ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1363ab4382d2SGreg Kroah-Hartman { 1364ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1365ab4382d2SGreg Kroah-Hartman unsigned long flags; 1366ab4382d2SGreg Kroah-Hartman unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1367ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1368ab4382d2SGreg Kroah-Hartman unsigned int div, ufcr; 1369ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1370ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1371ab4382d2SGreg Kroah-Hartman 1372ab4382d2SGreg Kroah-Hartman /* 1373ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1374ab4382d2SGreg Kroah-Hartman */ 1375ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1376ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1377ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1378ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1379ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1380ab4382d2SGreg Kroah-Hartman } 1381ab4382d2SGreg Kroah-Hartman 1382ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1383ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1384ab4382d2SGreg Kroah-Hartman else 1385ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1386ab4382d2SGreg Kroah-Hartman 1387ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1388ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1389ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 1390ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_CTSC; 1391ab4382d2SGreg Kroah-Hartman } else { 1392ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1393ab4382d2SGreg Kroah-Hartman } 1394ab4382d2SGreg Kroah-Hartman } 1395ab4382d2SGreg Kroah-Hartman 1396ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1397ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1398ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1399ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1400ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1401ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1402ab4382d2SGreg Kroah-Hartman } 1403ab4382d2SGreg Kroah-Hartman 1404995234daSEric Miao del_timer_sync(&sport->timer); 1405995234daSEric Miao 1406ab4382d2SGreg Kroah-Hartman /* 1407ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1408ab4382d2SGreg Kroah-Hartman */ 1409ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1410ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1411ab4382d2SGreg Kroah-Hartman 1412ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1413ab4382d2SGreg Kroah-Hartman 1414ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1415ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1416ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1417ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1418ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1419ab4382d2SGreg Kroah-Hartman 1420ab4382d2SGreg Kroah-Hartman /* 1421ab4382d2SGreg Kroah-Hartman * Characters to ignore 1422ab4382d2SGreg Kroah-Hartman */ 1423ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1424ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1425865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1426ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1427ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1428ab4382d2SGreg Kroah-Hartman /* 1429ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1430ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1431ab4382d2SGreg Kroah-Hartman */ 1432ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1433ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1434ab4382d2SGreg Kroah-Hartman } 1435ab4382d2SGreg Kroah-Hartman 143655d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 143755d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 143855d8693aSJiada Wang 1439ab4382d2SGreg Kroah-Hartman /* 1440ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1441ab4382d2SGreg Kroah-Hartman */ 1442ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1443ab4382d2SGreg Kroah-Hartman 1444ab4382d2SGreg Kroah-Hartman /* 1445ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1446ab4382d2SGreg Kroah-Hartman */ 1447ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1448ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1449ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1450ab4382d2SGreg Kroah-Hartman 1451ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1452ab4382d2SGreg Kroah-Hartman barrier(); 1453ab4382d2SGreg Kroah-Hartman 1454ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 1455ab4382d2SGreg Kroah-Hartman old_txrxen = readl(sport->port.membase + UCR2); 1456ab4382d2SGreg Kroah-Hartman writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1457ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 1458ab4382d2SGreg Kroah-Hartman old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1459ab4382d2SGreg Kroah-Hartman 1460ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1461ab4382d2SGreg Kroah-Hartman /* 1462ab4382d2SGreg Kroah-Hartman * use maximum available submodule frequency to 1463ab4382d2SGreg Kroah-Hartman * avoid missing short pulses due to low sampling rate 1464ab4382d2SGreg Kroah-Hartman */ 1465ab4382d2SGreg Kroah-Hartman div = 1; 1466ab4382d2SGreg Kroah-Hartman } else { 146709bd00f6SHubert Feurstein /* custom-baudrate handling */ 146809bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 146909bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 147009bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 147109bd00f6SHubert Feurstein 1472ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1473ab4382d2SGreg Kroah-Hartman if (div > 7) 1474ab4382d2SGreg Kroah-Hartman div = 7; 1475ab4382d2SGreg Kroah-Hartman if (!div) 1476ab4382d2SGreg Kroah-Hartman div = 1; 1477ab4382d2SGreg Kroah-Hartman } 1478ab4382d2SGreg Kroah-Hartman 1479ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1480ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1481ab4382d2SGreg Kroah-Hartman 1482ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1483ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1484ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1485ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1486ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1487ab4382d2SGreg Kroah-Hartman 1488ab4382d2SGreg Kroah-Hartman num -= 1; 1489ab4382d2SGreg Kroah-Hartman denom -= 1; 1490ab4382d2SGreg Kroah-Hartman 1491ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1492ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 149320ff2fe6SHuang Shijie if (sport->dte_mode) 149420ff2fe6SHuang Shijie ufcr |= UFCR_DCEDTE; 1495ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1496ab4382d2SGreg Kroah-Hartman 1497ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1498ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1499ab4382d2SGreg Kroah-Hartman 1500a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1501ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1502fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1503ab4382d2SGreg Kroah-Hartman 1504ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1505ab4382d2SGreg Kroah-Hartman 1506ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 1507ab4382d2SGreg Kroah-Hartman writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1508ab4382d2SGreg Kroah-Hartman 1509ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1510ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1511ab4382d2SGreg Kroah-Hartman 1512ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1513ab4382d2SGreg Kroah-Hartman } 1514ab4382d2SGreg Kroah-Hartman 1515ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1516ab4382d2SGreg Kroah-Hartman { 1517ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1518ab4382d2SGreg Kroah-Hartman 1519ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1520ab4382d2SGreg Kroah-Hartman } 1521ab4382d2SGreg Kroah-Hartman 1522ab4382d2SGreg Kroah-Hartman /* 1523ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1524ab4382d2SGreg Kroah-Hartman */ 1525ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1526ab4382d2SGreg Kroah-Hartman { 1527ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1528ab4382d2SGreg Kroah-Hartman 1529da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1530ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1531ab4382d2SGreg Kroah-Hartman } 1532ab4382d2SGreg Kroah-Hartman 1533ab4382d2SGreg Kroah-Hartman /* 1534ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1535ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1536ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1537ab4382d2SGreg Kroah-Hartman */ 1538ab4382d2SGreg Kroah-Hartman static int 1539ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1540ab4382d2SGreg Kroah-Hartman { 1541ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1542ab4382d2SGreg Kroah-Hartman int ret = 0; 1543ab4382d2SGreg Kroah-Hartman 1544ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1545ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1546ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1547ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1548ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1549ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1550ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1551ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1552a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1553ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1554ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1555ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1556ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1557ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1558ab4382d2SGreg Kroah-Hartman return ret; 1559ab4382d2SGreg Kroah-Hartman } 1560ab4382d2SGreg Kroah-Hartman 156101f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 15626b8bdad9SDaniel Thompson 15636b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 15646b8bdad9SDaniel Thompson { 15656b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 15666b8bdad9SDaniel Thompson unsigned long flags; 15676b8bdad9SDaniel Thompson unsigned long temp; 15686b8bdad9SDaniel Thompson int retval; 15696b8bdad9SDaniel Thompson 15706b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 15716b8bdad9SDaniel Thompson if (retval) 15726b8bdad9SDaniel Thompson return retval; 15736b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 15746b8bdad9SDaniel Thompson if (retval) 15756b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 15766b8bdad9SDaniel Thompson 15776b8bdad9SDaniel Thompson imx_setup_ufcr(sport, 0); 15786b8bdad9SDaniel Thompson 15796b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 15806b8bdad9SDaniel Thompson 15816b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR1); 15826b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 15836b8bdad9SDaniel Thompson temp |= IMX1_UCR1_UARTCLKEN; 15846b8bdad9SDaniel Thompson temp |= UCR1_UARTEN | UCR1_RRDYEN; 15856b8bdad9SDaniel Thompson temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 15866b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR1); 15876b8bdad9SDaniel Thompson 15886b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR2); 15896b8bdad9SDaniel Thompson temp |= UCR2_RXEN; 15906b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR2); 15916b8bdad9SDaniel Thompson 15926b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 15936b8bdad9SDaniel Thompson 15946b8bdad9SDaniel Thompson return 0; 15956b8bdad9SDaniel Thompson } 15966b8bdad9SDaniel Thompson 159701f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 159801f56abdSSaleem Abdulrasool { 1599f968ef34SDaniel Thompson if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 160026c47412SDirk Behme return NO_POLL_CHAR; 160101f56abdSSaleem Abdulrasool 1602f968ef34SDaniel Thompson return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 160301f56abdSSaleem Abdulrasool } 160401f56abdSSaleem Abdulrasool 160501f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 160601f56abdSSaleem Abdulrasool { 160701f56abdSSaleem Abdulrasool unsigned int status; 160801f56abdSSaleem Abdulrasool 160901f56abdSSaleem Abdulrasool /* drain */ 161001f56abdSSaleem Abdulrasool do { 1611f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR1); 161201f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 161301f56abdSSaleem Abdulrasool 161401f56abdSSaleem Abdulrasool /* write */ 1615f968ef34SDaniel Thompson writel_relaxed(c, port->membase + URTX0); 161601f56abdSSaleem Abdulrasool 161701f56abdSSaleem Abdulrasool /* flush */ 161801f56abdSSaleem Abdulrasool do { 1619f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR2); 162001f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 162101f56abdSSaleem Abdulrasool } 162201f56abdSSaleem Abdulrasool #endif 162301f56abdSSaleem Abdulrasool 1624ab4382d2SGreg Kroah-Hartman static struct uart_ops imx_pops = { 1625ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1626ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1627ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1628ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1629ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1630ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1631ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1632ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1633ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1634ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1635eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1636ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1637ab4382d2SGreg Kroah-Hartman .type = imx_type, 1638ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1639ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 164001f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 16416b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 164201f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 164301f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 164401f56abdSSaleem Abdulrasool #endif 1645ab4382d2SGreg Kroah-Hartman }; 1646ab4382d2SGreg Kroah-Hartman 1647ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1648ab4382d2SGreg Kroah-Hartman 1649ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1650ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1651ab4382d2SGreg Kroah-Hartman { 1652ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1653ab4382d2SGreg Kroah-Hartman 1654fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1655ab4382d2SGreg Kroah-Hartman barrier(); 1656ab4382d2SGreg Kroah-Hartman 1657ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1658ab4382d2SGreg Kroah-Hartman } 1659ab4382d2SGreg Kroah-Hartman 1660ab4382d2SGreg Kroah-Hartman /* 1661ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1662ab4382d2SGreg Kroah-Hartman */ 1663ab4382d2SGreg Kroah-Hartman static void 1664ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1665ab4382d2SGreg Kroah-Hartman { 1666ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 16670ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 16680ad5a814SDirk Behme unsigned int ucr1; 1669f30e8260SShawn Guo unsigned long flags = 0; 1670677fe555SThomas Gleixner int locked = 1; 16711cf93e0dSHuang Shijie int retval; 16721cf93e0dSHuang Shijie 16731cf93e0dSHuang Shijie retval = clk_enable(sport->clk_per); 16741cf93e0dSHuang Shijie if (retval) 16751cf93e0dSHuang Shijie return; 16761cf93e0dSHuang Shijie retval = clk_enable(sport->clk_ipg); 16771cf93e0dSHuang Shijie if (retval) { 16781cf93e0dSHuang Shijie clk_disable(sport->clk_per); 16791cf93e0dSHuang Shijie return; 16801cf93e0dSHuang Shijie } 16819ec1882dSXinyu Chen 1682677fe555SThomas Gleixner if (sport->port.sysrq) 1683677fe555SThomas Gleixner locked = 0; 1684677fe555SThomas Gleixner else if (oops_in_progress) 1685677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1686677fe555SThomas Gleixner else 16879ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1688ab4382d2SGreg Kroah-Hartman 1689ab4382d2SGreg Kroah-Hartman /* 16900ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1691ab4382d2SGreg Kroah-Hartman */ 16920ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 16930ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1694ab4382d2SGreg Kroah-Hartman 1695fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1696fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1697ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1698ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1699ab4382d2SGreg Kroah-Hartman 1700ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1701ab4382d2SGreg Kroah-Hartman 17020ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1703ab4382d2SGreg Kroah-Hartman 1704ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1705ab4382d2SGreg Kroah-Hartman 1706ab4382d2SGreg Kroah-Hartman /* 1707ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 17080ad5a814SDirk Behme * and restore UCR1/2/3 1709ab4382d2SGreg Kroah-Hartman */ 1710ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1711ab4382d2SGreg Kroah-Hartman 17120ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 17139ec1882dSXinyu Chen 1714677fe555SThomas Gleixner if (locked) 17159ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 17161cf93e0dSHuang Shijie 17171cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 17181cf93e0dSHuang Shijie clk_disable(sport->clk_per); 1719ab4382d2SGreg Kroah-Hartman } 1720ab4382d2SGreg Kroah-Hartman 1721ab4382d2SGreg Kroah-Hartman /* 1722ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1723ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1724ab4382d2SGreg Kroah-Hartman */ 1725ab4382d2SGreg Kroah-Hartman static void __init 1726ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1727ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1728ab4382d2SGreg Kroah-Hartman { 1729ab4382d2SGreg Kroah-Hartman 1730ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1731ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1732ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1733ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1734ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1735ab4382d2SGreg Kroah-Hartman 1736ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1737ab4382d2SGreg Kroah-Hartman 1738ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1739ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1740ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1741ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1742ab4382d2SGreg Kroah-Hartman else 1743ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1744ab4382d2SGreg Kroah-Hartman } 1745ab4382d2SGreg Kroah-Hartman 1746ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1747ab4382d2SGreg Kroah-Hartman *bits = 8; 1748ab4382d2SGreg Kroah-Hartman else 1749ab4382d2SGreg Kroah-Hartman *bits = 7; 1750ab4382d2SGreg Kroah-Hartman 1751ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1752ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1753ab4382d2SGreg Kroah-Hartman 1754ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1755ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1756ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1757ab4382d2SGreg Kroah-Hartman else 1758ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1759ab4382d2SGreg Kroah-Hartman 17603a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1761ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1762ab4382d2SGreg Kroah-Hartman 1763ab4382d2SGreg Kroah-Hartman { /* 1764ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1765ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1766ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1767ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1768ab4382d2SGreg Kroah-Hartman */ 1769ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1770ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1771ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1772ab4382d2SGreg Kroah-Hartman 1773ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1774ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1775ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1776ab4382d2SGreg Kroah-Hartman } 1777ab4382d2SGreg Kroah-Hartman 1778ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 177950bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1780ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1781ab4382d2SGreg Kroah-Hartman } 1782ab4382d2SGreg Kroah-Hartman } 1783ab4382d2SGreg Kroah-Hartman 1784ab4382d2SGreg Kroah-Hartman static int __init 1785ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1786ab4382d2SGreg Kroah-Hartman { 1787ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1788ab4382d2SGreg Kroah-Hartman int baud = 9600; 1789ab4382d2SGreg Kroah-Hartman int bits = 8; 1790ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1791ab4382d2SGreg Kroah-Hartman int flow = 'n'; 17921cf93e0dSHuang Shijie int retval; 1793ab4382d2SGreg Kroah-Hartman 1794ab4382d2SGreg Kroah-Hartman /* 1795ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1796ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1797ab4382d2SGreg Kroah-Hartman * console support. 1798ab4382d2SGreg Kroah-Hartman */ 1799ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1800ab4382d2SGreg Kroah-Hartman co->index = 0; 1801ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1802ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1803ab4382d2SGreg Kroah-Hartman return -ENODEV; 1804ab4382d2SGreg Kroah-Hartman 18051cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 18061cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 18071cf93e0dSHuang Shijie if (retval) 18081cf93e0dSHuang Shijie goto error_console; 18091cf93e0dSHuang Shijie 1810ab4382d2SGreg Kroah-Hartman if (options) 1811ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1812ab4382d2SGreg Kroah-Hartman else 1813ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1814ab4382d2SGreg Kroah-Hartman 1815ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1816ab4382d2SGreg Kroah-Hartman 18171cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 18181cf93e0dSHuang Shijie 18191cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 18201cf93e0dSHuang Shijie if (retval) { 18211cf93e0dSHuang Shijie clk_unprepare(sport->clk_ipg); 18221cf93e0dSHuang Shijie goto error_console; 18231cf93e0dSHuang Shijie } 18241cf93e0dSHuang Shijie 18251cf93e0dSHuang Shijie retval = clk_prepare(sport->clk_per); 18261cf93e0dSHuang Shijie if (retval) 18271cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 18281cf93e0dSHuang Shijie 18291cf93e0dSHuang Shijie error_console: 18301cf93e0dSHuang Shijie return retval; 1831ab4382d2SGreg Kroah-Hartman } 1832ab4382d2SGreg Kroah-Hartman 1833ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1834ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1835ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1836ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1837ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1838ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1839ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1840ab4382d2SGreg Kroah-Hartman .index = -1, 1841ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1842ab4382d2SGreg Kroah-Hartman }; 1843ab4382d2SGreg Kroah-Hartman 1844ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1845ab4382d2SGreg Kroah-Hartman #else 1846ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1847ab4382d2SGreg Kroah-Hartman #endif 1848ab4382d2SGreg Kroah-Hartman 1849ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1850ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1851ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 1852ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 1853ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 1854ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 1855ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 1856ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 1857ab4382d2SGreg Kroah-Hartman }; 1858ab4382d2SGreg Kroah-Hartman 1859ab4382d2SGreg Kroah-Hartman static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1860ab4382d2SGreg Kroah-Hartman { 1861ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1862db1a9b55SFabio Estevam unsigned int val; 1863db1a9b55SFabio Estevam 1864db1a9b55SFabio Estevam /* enable wakeup from i.MX UART */ 1865db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1866db1a9b55SFabio Estevam val |= UCR3_AWAKEN; 1867db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1868ab4382d2SGreg Kroah-Hartman 1869ab4382d2SGreg Kroah-Hartman uart_suspend_port(&imx_reg, &sport->port); 1870ab4382d2SGreg Kroah-Hartman 1871ab4382d2SGreg Kroah-Hartman return 0; 1872ab4382d2SGreg Kroah-Hartman } 1873ab4382d2SGreg Kroah-Hartman 1874ab4382d2SGreg Kroah-Hartman static int serial_imx_resume(struct platform_device *dev) 1875ab4382d2SGreg Kroah-Hartman { 1876ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1877db1a9b55SFabio Estevam unsigned int val; 1878db1a9b55SFabio Estevam 1879db1a9b55SFabio Estevam /* disable wakeup from i.MX UART */ 1880db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1881db1a9b55SFabio Estevam val &= ~UCR3_AWAKEN; 1882db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1883ab4382d2SGreg Kroah-Hartman 1884ab4382d2SGreg Kroah-Hartman uart_resume_port(&imx_reg, &sport->port); 1885ab4382d2SGreg Kroah-Hartman 1886ab4382d2SGreg Kroah-Hartman return 0; 1887ab4382d2SGreg Kroah-Hartman } 1888ab4382d2SGreg Kroah-Hartman 188922698aa2SShawn Guo #ifdef CONFIG_OF 189020bb8095SUwe Kleine-König /* 189120bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 189220bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 189320bb8095SUwe Kleine-König */ 189422698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 189522698aa2SShawn Guo struct platform_device *pdev) 189622698aa2SShawn Guo { 189722698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 189822698aa2SShawn Guo const struct of_device_id *of_id = 189922698aa2SShawn Guo of_match_device(imx_uart_dt_ids, &pdev->dev); 1900ff05967aSShawn Guo int ret; 190122698aa2SShawn Guo 190222698aa2SShawn Guo if (!np) 190320bb8095SUwe Kleine-König /* no device tree device */ 190420bb8095SUwe Kleine-König return 1; 190522698aa2SShawn Guo 1906ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 1907ff05967aSShawn Guo if (ret < 0) { 1908ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1909a197a191SUwe Kleine-König return ret; 1910ff05967aSShawn Guo } 1911ff05967aSShawn Guo sport->port.line = ret; 191222698aa2SShawn Guo 191322698aa2SShawn Guo if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 191422698aa2SShawn Guo sport->have_rtscts = 1; 191522698aa2SShawn Guo 191622698aa2SShawn Guo if (of_get_property(np, "fsl,irda-mode", NULL)) 191722698aa2SShawn Guo sport->use_irda = 1; 191822698aa2SShawn Guo 191920ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 192020ff2fe6SHuang Shijie sport->dte_mode = 1; 192120ff2fe6SHuang Shijie 192222698aa2SShawn Guo sport->devdata = of_id->data; 192322698aa2SShawn Guo 192422698aa2SShawn Guo return 0; 192522698aa2SShawn Guo } 192622698aa2SShawn Guo #else 192722698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 192822698aa2SShawn Guo struct platform_device *pdev) 192922698aa2SShawn Guo { 193020bb8095SUwe Kleine-König return 1; 193122698aa2SShawn Guo } 193222698aa2SShawn Guo #endif 193322698aa2SShawn Guo 193422698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 193522698aa2SShawn Guo struct platform_device *pdev) 193622698aa2SShawn Guo { 1937574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 193822698aa2SShawn Guo 193922698aa2SShawn Guo sport->port.line = pdev->id; 194022698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 194122698aa2SShawn Guo 194222698aa2SShawn Guo if (!pdata) 194322698aa2SShawn Guo return; 194422698aa2SShawn Guo 194522698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 194622698aa2SShawn Guo sport->have_rtscts = 1; 194722698aa2SShawn Guo 194822698aa2SShawn Guo if (pdata->flags & IMXUART_IRDA) 194922698aa2SShawn Guo sport->use_irda = 1; 195022698aa2SShawn Guo } 195122698aa2SShawn Guo 1952ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 1953ab4382d2SGreg Kroah-Hartman { 1954ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1955ab4382d2SGreg Kroah-Hartman void __iomem *base; 1956ab4382d2SGreg Kroah-Hartman int ret = 0; 1957ab4382d2SGreg Kroah-Hartman struct resource *res; 1958*842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 1959ab4382d2SGreg Kroah-Hartman 196042d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1961ab4382d2SGreg Kroah-Hartman if (!sport) 1962ab4382d2SGreg Kroah-Hartman return -ENOMEM; 1963ab4382d2SGreg Kroah-Hartman 196422698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 196520bb8095SUwe Kleine-König if (ret > 0) 196622698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 196720bb8095SUwe Kleine-König else if (ret < 0) 196842d34191SSachin Kamat return ret; 196922698aa2SShawn Guo 1970ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1971da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 1972da82f997SAlexander Shiyan if (IS_ERR(base)) 1973da82f997SAlexander Shiyan return PTR_ERR(base); 1974ab4382d2SGreg Kroah-Hartman 1975*842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 1976*842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 1977*842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 1978*842633bdSUwe Kleine-König 1979ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 1980ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 1981ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 1982ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 1983ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 1984*842633bdSUwe Kleine-König sport->port.irq = rxirq; 1985ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 1986ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 1987ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 1988ab4382d2SGreg Kroah-Hartman init_timer(&sport->timer); 1989ab4382d2SGreg Kroah-Hartman sport->timer.function = imx_timeout; 1990ab4382d2SGreg Kroah-Hartman sport->timer.data = (unsigned long)sport; 1991ab4382d2SGreg Kroah-Hartman 19923a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 19933a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 19943a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 1995833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 199642d34191SSachin Kamat return ret; 1997ab4382d2SGreg Kroah-Hartman } 1998ab4382d2SGreg Kroah-Hartman 19993a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 20003a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 20013a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2002833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 200342d34191SSachin Kamat return ret; 20043a9465faSSascha Hauer } 20053a9465faSSascha Hauer 20063a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2007ab4382d2SGreg Kroah-Hartman 2008c0d1c6b0SFabio Estevam /* 2009c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2010c0d1c6b0SFabio Estevam * chips only have one interrupt. 2011c0d1c6b0SFabio Estevam */ 2012*842633bdSUwe Kleine-König if (txirq > 0) { 2013*842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2014c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2015c0d1c6b0SFabio Estevam if (ret) 2016c0d1c6b0SFabio Estevam return ret; 2017c0d1c6b0SFabio Estevam 2018*842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2019c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2020c0d1c6b0SFabio Estevam if (ret) 2021c0d1c6b0SFabio Estevam return ret; 2022c0d1c6b0SFabio Estevam 2023c0d1c6b0SFabio Estevam /* do not use RTS IRQ on IrDA */ 2024c0d1c6b0SFabio Estevam if (!USE_IRDA(sport)) { 2025*842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, 2026c0d1c6b0SFabio Estevam imx_rtsint, 0, 2027c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2028c0d1c6b0SFabio Estevam if (ret) 2029c0d1c6b0SFabio Estevam return ret; 2030c0d1c6b0SFabio Estevam } 2031c0d1c6b0SFabio Estevam } else { 2032*842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2033c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2034c0d1c6b0SFabio Estevam if (ret) 2035c0d1c6b0SFabio Estevam return ret; 2036c0d1c6b0SFabio Estevam } 2037c0d1c6b0SFabio Estevam 203822698aa2SShawn Guo imx_ports[sport->port.line] = sport; 2039ab4382d2SGreg Kroah-Hartman 20400a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2041ab4382d2SGreg Kroah-Hartman 204245af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2043ab4382d2SGreg Kroah-Hartman } 2044ab4382d2SGreg Kroah-Hartman 2045ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2046ab4382d2SGreg Kroah-Hartman { 2047ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2048ab4382d2SGreg Kroah-Hartman 204945af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2050ab4382d2SGreg Kroah-Hartman } 2051ab4382d2SGreg Kroah-Hartman 2052ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2053ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2054ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2055ab4382d2SGreg Kroah-Hartman 2056ab4382d2SGreg Kroah-Hartman .suspend = serial_imx_suspend, 2057ab4382d2SGreg Kroah-Hartman .resume = serial_imx_resume, 2058fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2059ab4382d2SGreg Kroah-Hartman .driver = { 2060ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 206122698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 2062ab4382d2SGreg Kroah-Hartman }, 2063ab4382d2SGreg Kroah-Hartman }; 2064ab4382d2SGreg Kroah-Hartman 2065ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2066ab4382d2SGreg Kroah-Hartman { 2067f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2068ab4382d2SGreg Kroah-Hartman 2069ab4382d2SGreg Kroah-Hartman if (ret) 2070ab4382d2SGreg Kroah-Hartman return ret; 2071ab4382d2SGreg Kroah-Hartman 2072ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2073ab4382d2SGreg Kroah-Hartman if (ret != 0) 2074ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2075ab4382d2SGreg Kroah-Hartman 2076f227824eSUwe Kleine-König return ret; 2077ab4382d2SGreg Kroah-Hartman } 2078ab4382d2SGreg Kroah-Hartman 2079ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2080ab4382d2SGreg Kroah-Hartman { 2081ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2082ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2083ab4382d2SGreg Kroah-Hartman } 2084ab4382d2SGreg Kroah-Hartman 2085ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2086ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2087ab4382d2SGreg Kroah-Hartman 2088ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2089ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2090ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2091ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2092