1ab4382d2SGreg Kroah-Hartman /* 2f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 7ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 8ab4382d2SGreg Kroah-Hartman * 9ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 10ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 11ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2 of the License, or 12ab4382d2SGreg Kroah-Hartman * (at your option) any later version. 13ab4382d2SGreg Kroah-Hartman * 14ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 15ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY; without even the implied warranty of 16ab4382d2SGreg Kroah-Hartman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17ab4382d2SGreg Kroah-Hartman * GNU General Public License for more details. 18ab4382d2SGreg Kroah-Hartman */ 19ab4382d2SGreg Kroah-Hartman 20ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 22ab4382d2SGreg Kroah-Hartman #endif 23ab4382d2SGreg Kroah-Hartman 24ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 29ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 30ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 31ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 32ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 33ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 34ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 35ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 36ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 37ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 3822698aa2SShawn Guo #include <linux/of.h> 3922698aa2SShawn Guo #include <linux/of_device.h> 40e32a9f8fSSachin Kamat #include <linux/io.h> 41b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 42ab4382d2SGreg Kroah-Hartman 43ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 4482906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 45b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 46ab4382d2SGreg Kroah-Hartman 4758362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 4858362d5bSUwe Kleine-König 49ab4382d2SGreg Kroah-Hartman /* Register definitions */ 50ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 51ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 52ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 53ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 54ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 55ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 56ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 57ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 58ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 59ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 60ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 61ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 62ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 63ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 64fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 65fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 66fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 67ab4382d2SGreg Kroah-Hartman 68ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6955d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 70ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 71ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 72ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 73ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 74ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 75ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 7626c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 7725985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 81b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 84ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 88ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 89fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 90b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 91ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 92ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 100ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 101ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 102ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 10301f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 105ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 106ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 112ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 113b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 114ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 115ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 117fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 118ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 119ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 125ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 126b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 127ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 128ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 129ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 130ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 131ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 132ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1337be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 134ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 135ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 136ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 137ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 138ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 139ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 141ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 142ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 143ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 14486a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 146ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 147ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 150ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 151ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 152ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 15390ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 15490ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 155ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 156ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 15790ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 158ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 159ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 160ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 161ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 162ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 163ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 164ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 165ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 166ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 167ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 168ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 169ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 170ab4382d2SGreg Kroah-Hartman 171ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 172ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 173ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 174ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 175ab4382d2SGreg Kroah-Hartman 176ab4382d2SGreg Kroah-Hartman /* 177ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 178ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 179ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 180ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 181ab4382d2SGreg Kroah-Hartman */ 182ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 183ab4382d2SGreg Kroah-Hartman 184ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 185ab4382d2SGreg Kroah-Hartman 186ab4382d2SGreg Kroah-Hartman #define UART_NR 8 187ab4382d2SGreg Kroah-Hartman 188f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 189fe6b540aSShawn Guo enum imx_uart_type { 190fe6b540aSShawn Guo IMX1_UART, 191fe6b540aSShawn Guo IMX21_UART, 192a496e628SHuang Shijie IMX6Q_UART, 193fe6b540aSShawn Guo }; 194fe6b540aSShawn Guo 195fe6b540aSShawn Guo /* device type dependent stuff */ 196fe6b540aSShawn Guo struct imx_uart_data { 197fe6b540aSShawn Guo unsigned uts_reg; 198fe6b540aSShawn Guo enum imx_uart_type devtype; 199fe6b540aSShawn Guo }; 200fe6b540aSShawn Guo 201ab4382d2SGreg Kroah-Hartman struct imx_port { 202ab4382d2SGreg Kroah-Hartman struct uart_port port; 203ab4382d2SGreg Kroah-Hartman struct timer_list timer; 204ab4382d2SGreg Kroah-Hartman unsigned int old_status; 205ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 20620ff2fe6SHuang Shijie unsigned int dte_mode:1; 207ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_rx:1; 208ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_tx:1; 209ab4382d2SGreg Kroah-Hartman unsigned short trcv_delay; /* transceiver delay */ 2103a9465faSSascha Hauer struct clk *clk_ipg; 2113a9465faSSascha Hauer struct clk *clk_per; 2127d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 213b4cdc8f6SHuang Shijie 21458362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21558362d5bSUwe Kleine-König 216b4cdc8f6SHuang Shijie /* DMA fields */ 217b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 218b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 219b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 220b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 221b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 222b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 223b4cdc8f6SHuang Shijie void *rx_buf; 2247cb92fd2SHuang Shijie unsigned int tx_bytes; 225b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 2269ce4f8f3SGreg Kroah-Hartman wait_queue_head_t dma_wait; 22790bb6bd3SShenwei Wang unsigned int saved_reg[10]; 228c868cbb7SEduardo Valentin bool context_saved; 229ab4382d2SGreg Kroah-Hartman }; 230ab4382d2SGreg Kroah-Hartman 2310ad5a814SDirk Behme struct imx_port_ucrs { 2320ad5a814SDirk Behme unsigned int ucr1; 2330ad5a814SDirk Behme unsigned int ucr2; 2340ad5a814SDirk Behme unsigned int ucr3; 2350ad5a814SDirk Behme }; 2360ad5a814SDirk Behme 237fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 238fe6b540aSShawn Guo [IMX1_UART] = { 239fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 240fe6b540aSShawn Guo .devtype = IMX1_UART, 241fe6b540aSShawn Guo }, 242fe6b540aSShawn Guo [IMX21_UART] = { 243fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 244fe6b540aSShawn Guo .devtype = IMX21_UART, 245fe6b540aSShawn Guo }, 246a496e628SHuang Shijie [IMX6Q_UART] = { 247a496e628SHuang Shijie .uts_reg = IMX21_UTS, 248a496e628SHuang Shijie .devtype = IMX6Q_UART, 249a496e628SHuang Shijie }, 250fe6b540aSShawn Guo }; 251fe6b540aSShawn Guo 25231ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 253fe6b540aSShawn Guo { 254fe6b540aSShawn Guo .name = "imx1-uart", 255fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 256fe6b540aSShawn Guo }, { 257fe6b540aSShawn Guo .name = "imx21-uart", 258fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 259fe6b540aSShawn Guo }, { 260a496e628SHuang Shijie .name = "imx6q-uart", 261a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 262a496e628SHuang Shijie }, { 263fe6b540aSShawn Guo /* sentinel */ 264fe6b540aSShawn Guo } 265fe6b540aSShawn Guo }; 266fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 267fe6b540aSShawn Guo 268ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 269a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 27022698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27122698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27222698aa2SShawn Guo { /* sentinel */ } 27322698aa2SShawn Guo }; 27422698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27522698aa2SShawn Guo 276fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 277fe6b540aSShawn Guo { 278fe6b540aSShawn Guo return sport->devdata->uts_reg; 279fe6b540aSShawn Guo } 280fe6b540aSShawn Guo 281fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 282fe6b540aSShawn Guo { 283fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 284fe6b540aSShawn Guo } 285fe6b540aSShawn Guo 286fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 287fe6b540aSShawn Guo { 288fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 289fe6b540aSShawn Guo } 290fe6b540aSShawn Guo 291a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 292a496e628SHuang Shijie { 293a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 294a496e628SHuang Shijie } 295ab4382d2SGreg Kroah-Hartman /* 29644a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 29744a75411Sfabio.estevam@freescale.com */ 29893d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 29944a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 30044a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30144a75411Sfabio.estevam@freescale.com { 30244a75411Sfabio.estevam@freescale.com /* save control registers */ 30344a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 30444a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 30544a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 30644a75411Sfabio.estevam@freescale.com } 30744a75411Sfabio.estevam@freescale.com 30844a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 30944a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 31044a75411Sfabio.estevam@freescale.com { 31144a75411Sfabio.estevam@freescale.com /* restore control registers */ 31244a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 31344a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 31444a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 31544a75411Sfabio.estevam@freescale.com } 316e8bfa760SFabio Estevam #endif 31744a75411Sfabio.estevam@freescale.com 31858362d5bSUwe Kleine-König static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2) 31958362d5bSUwe Kleine-König { 32058362d5bSUwe Kleine-König *ucr2 &= ~UCR2_CTSC; 32158362d5bSUwe Kleine-König *ucr2 |= UCR2_CTS; 32258362d5bSUwe Kleine-König 32358362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); 32458362d5bSUwe Kleine-König } 32558362d5bSUwe Kleine-König 32658362d5bSUwe Kleine-König static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2) 32758362d5bSUwe Kleine-König { 32858362d5bSUwe Kleine-König *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 32958362d5bSUwe Kleine-König 33058362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); 33158362d5bSUwe Kleine-König } 33258362d5bSUwe Kleine-König 33358362d5bSUwe Kleine-König static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2) 33458362d5bSUwe Kleine-König { 33558362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 33658362d5bSUwe Kleine-König } 33758362d5bSUwe Kleine-König 33844a75411Sfabio.estevam@freescale.com /* 339ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 340ab4382d2SGreg Kroah-Hartman */ 341ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 342ab4382d2SGreg Kroah-Hartman { 343ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 344ab4382d2SGreg Kroah-Hartman unsigned long temp; 345ab4382d2SGreg Kroah-Hartman 3469ce4f8f3SGreg Kroah-Hartman /* 3479ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 3489ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 3499ce4f8f3SGreg Kroah-Hartman */ 3509ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 3519ce4f8f3SGreg Kroah-Hartman return; 352b4cdc8f6SHuang Shijie 35317b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR1); 35417b8f2a3SUwe Kleine-König writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); 35517b8f2a3SUwe Kleine-König 35617b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 35717b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 35817b8f2a3SUwe Kleine-König readl(port->membase + USR2) & USR2_TXDC) { 35917b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 36017b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 36158362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &temp); 36217b8f2a3SUwe Kleine-König else 36358362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 3647d1cadcaSBaruch Siach temp |= UCR2_RXEN; 36517b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 36617b8f2a3SUwe Kleine-König 36717b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 36817b8f2a3SUwe Kleine-König temp &= ~UCR4_TCEN; 36917b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 37017b8f2a3SUwe Kleine-König } 371ab4382d2SGreg Kroah-Hartman } 372ab4382d2SGreg Kroah-Hartman 373ab4382d2SGreg Kroah-Hartman /* 374ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 375ab4382d2SGreg Kroah-Hartman */ 376ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 377ab4382d2SGreg Kroah-Hartman { 378ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 379ab4382d2SGreg Kroah-Hartman unsigned long temp; 380ab4382d2SGreg Kroah-Hartman 38145564a66SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) { 38245564a66SHuang Shijie if (sport->port.suspended) { 38345564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 38445564a66SHuang Shijie sport->dma_is_rxing = 0; 38545564a66SHuang Shijie } else { 3869ce4f8f3SGreg Kroah-Hartman return; 38745564a66SHuang Shijie } 38845564a66SHuang Shijie } 389b4cdc8f6SHuang Shijie 390ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 391ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 39285878399SHuang Shijie 39385878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 39485878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 39585878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 396ab4382d2SGreg Kroah-Hartman } 397ab4382d2SGreg Kroah-Hartman 398ab4382d2SGreg Kroah-Hartman /* 399ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 400ab4382d2SGreg Kroah-Hartman */ 401ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 402ab4382d2SGreg Kroah-Hartman { 403ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 404ab4382d2SGreg Kroah-Hartman 405ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 40658362d5bSUwe Kleine-König 40758362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 408ab4382d2SGreg Kroah-Hartman } 409ab4382d2SGreg Kroah-Hartman 41091a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 411ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 412ab4382d2SGreg Kroah-Hartman { 413ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 41491a1a909SJiada Wang unsigned long temp; 415ab4382d2SGreg Kroah-Hartman 4165e42e9a3SPeter Hurley if (sport->port.x_char) { 4175e42e9a3SPeter Hurley /* Send next char */ 4185e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4197e2fb5aaSJiada Wang sport->port.icount.tx++; 4207e2fb5aaSJiada Wang sport->port.x_char = 0; 4215e42e9a3SPeter Hurley return; 4225e42e9a3SPeter Hurley } 4235e42e9a3SPeter Hurley 4245e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4255e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4265e42e9a3SPeter Hurley return; 4275e42e9a3SPeter Hurley } 4285e42e9a3SPeter Hurley 42991a1a909SJiada Wang if (sport->dma_is_enabled) { 43091a1a909SJiada Wang /* 43191a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 43291a1a909SJiada Wang * and the TX IRQ is disabled. 43391a1a909SJiada Wang **/ 43491a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 43591a1a909SJiada Wang temp &= ~UCR1_TXMPTYEN; 43691a1a909SJiada Wang if (sport->dma_is_txing) { 43791a1a909SJiada Wang temp |= UCR1_TDMAEN; 43891a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 43991a1a909SJiada Wang } else { 44091a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 44191a1a909SJiada Wang imx_dma_tx(sport); 44291a1a909SJiada Wang } 44391a1a909SJiada Wang } 44491a1a909SJiada Wang 445ab4382d2SGreg Kroah-Hartman while (!uart_circ_empty(xmit) && 4465e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 447ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 448ab4382d2SGreg Kroah-Hartman * out the port here */ 449ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 450ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 451ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 452ab4382d2SGreg Kroah-Hartman } 453ab4382d2SGreg Kroah-Hartman 454ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 455ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 456ab4382d2SGreg Kroah-Hartman 457ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 458ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 459ab4382d2SGreg Kroah-Hartman } 460ab4382d2SGreg Kroah-Hartman 461b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 462b4cdc8f6SHuang Shijie { 463b4cdc8f6SHuang Shijie struct imx_port *sport = data; 464b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 465b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 466b4cdc8f6SHuang Shijie unsigned long flags; 467a2c718ceSDirk Behme unsigned long temp; 468b4cdc8f6SHuang Shijie 46942f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 47042f752b3SDirk Behme 471b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 472b4cdc8f6SHuang Shijie 473a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 474a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 475a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 476a2c718ceSDirk Behme 47742f752b3SDirk Behme /* update the stat */ 47842f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 47942f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 48042f752b3SDirk Behme 48142f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 48242f752b3SDirk Behme 483b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 484b4cdc8f6SHuang Shijie 485b4cdc8f6SHuang Shijie spin_unlock_irqrestore(&sport->port.lock, flags); 486b4cdc8f6SHuang Shijie 487d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 488b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 4899ce4f8f3SGreg Kroah-Hartman 4909ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) { 4919ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 4929ce4f8f3SGreg Kroah-Hartman dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 4939ce4f8f3SGreg Kroah-Hartman return; 4949ce4f8f3SGreg Kroah-Hartman } 4950bbc9b81SJiada Wang 4960bbc9b81SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 4970bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 4980bbc9b81SJiada Wang imx_dma_tx(sport); 4990bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 500b4cdc8f6SHuang Shijie } 501b4cdc8f6SHuang Shijie 5027cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 503b4cdc8f6SHuang Shijie { 504b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 505b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 506b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 507b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 508b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 509a2c718ceSDirk Behme unsigned long temp; 510b4cdc8f6SHuang Shijie int ret; 511b4cdc8f6SHuang Shijie 51242f752b3SDirk Behme if (sport->dma_is_txing) 513b4cdc8f6SHuang Shijie return; 514b4cdc8f6SHuang Shijie 515b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 516b4cdc8f6SHuang Shijie 5177942f857SDirk Behme if (xmit->tail < xmit->head) { 5187942f857SDirk Behme sport->dma_tx_nents = 1; 5197942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5207942f857SDirk Behme } else { 521b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 522b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 523b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 524b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 525b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 526b4cdc8f6SHuang Shijie } 527b4cdc8f6SHuang Shijie 528b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 529b4cdc8f6SHuang Shijie if (ret == 0) { 530b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 531b4cdc8f6SHuang Shijie return; 532b4cdc8f6SHuang Shijie } 533b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 534b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 535b4cdc8f6SHuang Shijie if (!desc) { 53624649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 53724649821SDirk Behme DMA_TO_DEVICE); 538b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 539b4cdc8f6SHuang Shijie return; 540b4cdc8f6SHuang Shijie } 541b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 542b4cdc8f6SHuang Shijie desc->callback_param = sport; 543b4cdc8f6SHuang Shijie 544b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 545b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 546a2c718ceSDirk Behme 547a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 548a2c718ceSDirk Behme temp |= UCR1_TDMAEN; 549a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 550a2c718ceSDirk Behme 551b4cdc8f6SHuang Shijie /* fire it */ 552b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 553b4cdc8f6SHuang Shijie dmaengine_submit(desc); 554b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 555b4cdc8f6SHuang Shijie return; 556b4cdc8f6SHuang Shijie } 557b4cdc8f6SHuang Shijie 558ab4382d2SGreg Kroah-Hartman /* 559ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 560ab4382d2SGreg Kroah-Hartman */ 561ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 562ab4382d2SGreg Kroah-Hartman { 563ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 564ab4382d2SGreg Kroah-Hartman unsigned long temp; 565ab4382d2SGreg Kroah-Hartman 56617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 56717b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 56817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 56958362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &temp); 57017b8f2a3SUwe Kleine-König else 57158362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 5727d1cadcaSBaruch Siach if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 5737d1cadcaSBaruch Siach temp &= ~UCR2_RXEN; 57417b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 57517b8f2a3SUwe Kleine-König 57658362d5bSUwe Kleine-König /* enable transmitter and shifter empty irq */ 57717b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 57817b8f2a3SUwe Kleine-König temp |= UCR4_TCEN; 57917b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 58017b8f2a3SUwe Kleine-König } 58117b8f2a3SUwe Kleine-König 582b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 583ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 584ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 585b4cdc8f6SHuang Shijie } 586ab4382d2SGreg Kroah-Hartman 587b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 58891a1a909SJiada Wang if (sport->port.x_char) { 58991a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 59091a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 59191a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 59291a1a909SJiada Wang temp &= ~UCR1_TDMAEN; 59391a1a909SJiada Wang temp |= UCR1_TXMPTYEN; 59491a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 59591a1a909SJiada Wang return; 59691a1a909SJiada Wang } 59791a1a909SJiada Wang 5985e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 5995e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6007cb92fd2SHuang Shijie imx_dma_tx(sport); 601b4cdc8f6SHuang Shijie return; 602b4cdc8f6SHuang Shijie } 603ab4382d2SGreg Kroah-Hartman } 604ab4382d2SGreg Kroah-Hartman 605ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 606ab4382d2SGreg Kroah-Hartman { 607ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6085680e941SUwe Kleine-König unsigned int val; 609ab4382d2SGreg Kroah-Hartman unsigned long flags; 610ab4382d2SGreg Kroah-Hartman 611ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 612ab4382d2SGreg Kroah-Hartman 613ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6145680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 615ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 616ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 617ab4382d2SGreg Kroah-Hartman 618ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 619ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 620ab4382d2SGreg Kroah-Hartman } 621ab4382d2SGreg Kroah-Hartman 622ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 623ab4382d2SGreg Kroah-Hartman { 624ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 625ab4382d2SGreg Kroah-Hartman unsigned long flags; 626ab4382d2SGreg Kroah-Hartman 627ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 628ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 629ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 630ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 631ab4382d2SGreg Kroah-Hartman } 632ab4382d2SGreg Kroah-Hartman 633ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 634ab4382d2SGreg Kroah-Hartman { 635ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 636ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 63792a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 638ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 639ab4382d2SGreg Kroah-Hartman 640ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 641ab4382d2SGreg Kroah-Hartman 642ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 643ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 644ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 645ab4382d2SGreg Kroah-Hartman 646ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 647ab4382d2SGreg Kroah-Hartman 648ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 649ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 650ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 651ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 652ab4382d2SGreg Kroah-Hartman continue; 653ab4382d2SGreg Kroah-Hartman } 654ab4382d2SGreg Kroah-Hartman 655ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 656ab4382d2SGreg Kroah-Hartman continue; 657ab4382d2SGreg Kroah-Hartman 658019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 659019dc9eaSHui Wang if (rx & URXD_BRK) 660019dc9eaSHui Wang sport->port.icount.brk++; 661019dc9eaSHui Wang else if (rx & URXD_PRERR) 662ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 663ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 664ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 665ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 666ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 667ab4382d2SGreg Kroah-Hartman 668ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 669ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 670ab4382d2SGreg Kroah-Hartman goto out; 671ab4382d2SGreg Kroah-Hartman continue; 672ab4382d2SGreg Kroah-Hartman } 673ab4382d2SGreg Kroah-Hartman 6748d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 675ab4382d2SGreg Kroah-Hartman 676019dc9eaSHui Wang if (rx & URXD_BRK) 677019dc9eaSHui Wang flg = TTY_BREAK; 678019dc9eaSHui Wang else if (rx & URXD_PRERR) 679ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 680ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 681ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 682ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 683ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 684ab4382d2SGreg Kroah-Hartman 685ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 686ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 687ab4382d2SGreg Kroah-Hartman #endif 688ab4382d2SGreg Kroah-Hartman } 689ab4382d2SGreg Kroah-Hartman 69055d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 69155d8693aSJiada Wang goto out; 69255d8693aSJiada Wang 6939b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 6949b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 695ab4382d2SGreg Kroah-Hartman } 696ab4382d2SGreg Kroah-Hartman 697ab4382d2SGreg Kroah-Hartman out: 698ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 6992e124b4aSJiri Slaby tty_flip_buffer_push(port); 700ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 701ab4382d2SGreg Kroah-Hartman } 702ab4382d2SGreg Kroah-Hartman 7037cb92fd2SHuang Shijie static int start_rx_dma(struct imx_port *sport); 704b4cdc8f6SHuang Shijie /* 705b4cdc8f6SHuang Shijie * If the RXFIFO is filled with some data, and then we 706b4cdc8f6SHuang Shijie * arise a DMA operation to receive them. 707b4cdc8f6SHuang Shijie */ 708b4cdc8f6SHuang Shijie static void imx_dma_rxint(struct imx_port *sport) 709b4cdc8f6SHuang Shijie { 710b4cdc8f6SHuang Shijie unsigned long temp; 71173631813SJiada Wang unsigned long flags; 71273631813SJiada Wang 71373631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 714b4cdc8f6SHuang Shijie 715b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + USR2); 716b4cdc8f6SHuang Shijie if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 717b4cdc8f6SHuang Shijie sport->dma_is_rxing = 1; 718b4cdc8f6SHuang Shijie 71986a04ba6SLucas Stach /* disable the receiver ready and aging timer interrupts */ 720b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 721b4cdc8f6SHuang Shijie temp &= ~(UCR1_RRDYEN); 722b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 723b4cdc8f6SHuang Shijie 72486a04ba6SLucas Stach temp = readl(sport->port.membase + UCR2); 72586a04ba6SLucas Stach temp &= ~(UCR2_ATEN); 72686a04ba6SLucas Stach writel(temp, sport->port.membase + UCR2); 72786a04ba6SLucas Stach 728b4cdc8f6SHuang Shijie /* tell the DMA to receive the data. */ 7297cb92fd2SHuang Shijie start_rx_dma(sport); 730b4cdc8f6SHuang Shijie } 73173631813SJiada Wang 73273631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 733b4cdc8f6SHuang Shijie } 734b4cdc8f6SHuang Shijie 735ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 736ab4382d2SGreg Kroah-Hartman { 737ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 738ab4382d2SGreg Kroah-Hartman unsigned int sts; 739f1f836e4SAlexander Stein unsigned int sts2; 740ab4382d2SGreg Kroah-Hartman 741ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 74217b8f2a3SUwe Kleine-König sts2 = readl(sport->port.membase + USR2); 743ab4382d2SGreg Kroah-Hartman 74486a04ba6SLucas Stach if (sts & (USR1_RRDY | USR1_AGTIM)) { 745b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) 746b4cdc8f6SHuang Shijie imx_dma_rxint(sport); 747b4cdc8f6SHuang Shijie else 748ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 749b4cdc8f6SHuang Shijie } 750ab4382d2SGreg Kroah-Hartman 75117b8f2a3SUwe Kleine-König if ((sts & USR1_TRDY && 75217b8f2a3SUwe Kleine-König readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || 75317b8f2a3SUwe Kleine-König (sts2 & USR2_TXDC && 75417b8f2a3SUwe Kleine-König readl(sport->port.membase + UCR4) & UCR4_TCEN)) 755ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 756ab4382d2SGreg Kroah-Hartman 757ab4382d2SGreg Kroah-Hartman if (sts & USR1_RTSD) 758ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 759ab4382d2SGreg Kroah-Hartman 760db1a9b55SFabio Estevam if (sts & USR1_AWAKE) 761db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 762db1a9b55SFabio Estevam 763f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 764f1f836e4SAlexander Stein sport->port.icount.overrun++; 76591555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 766f1f836e4SAlexander Stein } 767f1f836e4SAlexander Stein 768ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 769ab4382d2SGreg Kroah-Hartman } 770ab4382d2SGreg Kroah-Hartman 771ab4382d2SGreg Kroah-Hartman /* 772ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 773ab4382d2SGreg Kroah-Hartman */ 774ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 775ab4382d2SGreg Kroah-Hartman { 776ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 7771ce43e58SHuang Shijie unsigned int ret; 778ab4382d2SGreg Kroah-Hartman 7791ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 7801ce43e58SHuang Shijie 7811ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 7821ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 7831ce43e58SHuang Shijie ret = 0; 7841ce43e58SHuang Shijie 7851ce43e58SHuang Shijie return ret; 786ab4382d2SGreg Kroah-Hartman } 787ab4382d2SGreg Kroah-Hartman 788ab4382d2SGreg Kroah-Hartman /* 789ab4382d2SGreg Kroah-Hartman * We have a modem side uart, so the meanings of RTS and CTS are inverted. 790ab4382d2SGreg Kroah-Hartman */ 79158362d5bSUwe Kleine-König static unsigned int imx_get_hwmctrl(struct imx_port *sport) 792ab4382d2SGreg Kroah-Hartman { 79390ebc483SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 79490ebc483SUwe Kleine-König unsigned usr1 = readl(sport->port.membase + USR1); 795ab4382d2SGreg Kroah-Hartman 79690ebc483SUwe Kleine-König if (usr1 & USR1_RTSS) 797ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_CTS; 798ab4382d2SGreg Kroah-Hartman 79990ebc483SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 80090ebc483SUwe Kleine-König if (!(usr1 & USR2_DCDIN)) 80190ebc483SUwe Kleine-König tmp |= TIOCM_CAR; 802ab4382d2SGreg Kroah-Hartman 80390ebc483SUwe Kleine-König /* in DCE mode RIIN is always 0 */ 80490ebc483SUwe Kleine-König if (readl(sport->port.membase + USR2) & USR2_RIIN) 80590ebc483SUwe Kleine-König tmp |= TIOCM_RI; 8066b471a98SHuang Shijie 807ab4382d2SGreg Kroah-Hartman return tmp; 808ab4382d2SGreg Kroah-Hartman } 809ab4382d2SGreg Kroah-Hartman 81058362d5bSUwe Kleine-König static unsigned int imx_get_mctrl(struct uart_port *port) 81158362d5bSUwe Kleine-König { 81258362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 81358362d5bSUwe Kleine-König unsigned int ret = imx_get_hwmctrl(sport); 81458362d5bSUwe Kleine-König 81558362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 81658362d5bSUwe Kleine-König 81758362d5bSUwe Kleine-König return ret; 81858362d5bSUwe Kleine-König } 81958362d5bSUwe Kleine-König 820ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 821ab4382d2SGreg Kroah-Hartman { 822ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 823ab4382d2SGreg Kroah-Hartman unsigned long temp; 824ab4382d2SGreg Kroah-Hartman 82517b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 82617b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 82717b8f2a3SUwe Kleine-König temp &= ~(UCR2_CTS | UCR2_CTSC); 828ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 829bb2f861aSFugang Duan temp |= UCR2_CTS | UCR2_CTSC; 830ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 83117b8f2a3SUwe Kleine-König } 8326b471a98SHuang Shijie 83390ebc483SUwe Kleine-König temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR; 83490ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 83590ebc483SUwe Kleine-König temp |= UCR3_DSR; 83690ebc483SUwe Kleine-König writel(temp, sport->port.membase + UCR3); 83790ebc483SUwe Kleine-König 8386b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8396b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8406b471a98SHuang Shijie temp |= UTS_LOOP; 8416b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 84258362d5bSUwe Kleine-König 84358362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 844ab4382d2SGreg Kroah-Hartman } 845ab4382d2SGreg Kroah-Hartman 846ab4382d2SGreg Kroah-Hartman /* 847ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 848ab4382d2SGreg Kroah-Hartman */ 849ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 850ab4382d2SGreg Kroah-Hartman { 851ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 852ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 853ab4382d2SGreg Kroah-Hartman 854ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 855ab4382d2SGreg Kroah-Hartman 856ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 857ab4382d2SGreg Kroah-Hartman 858ab4382d2SGreg Kroah-Hartman if (break_state != 0) 859ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 860ab4382d2SGreg Kroah-Hartman 861ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 862ab4382d2SGreg Kroah-Hartman 863ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 864ab4382d2SGreg Kroah-Hartman } 865ab4382d2SGreg Kroah-Hartman 866cc568849SUwe Kleine-König /* 867cc568849SUwe Kleine-König * Handle any change of modem status signal since we were last called. 868cc568849SUwe Kleine-König */ 869cc568849SUwe Kleine-König static void imx_mctrl_check(struct imx_port *sport) 870cc568849SUwe Kleine-König { 871cc568849SUwe Kleine-König unsigned int status, changed; 872cc568849SUwe Kleine-König 87358362d5bSUwe Kleine-König status = imx_get_hwmctrl(sport); 874cc568849SUwe Kleine-König changed = status ^ sport->old_status; 875cc568849SUwe Kleine-König 876cc568849SUwe Kleine-König if (changed == 0) 877cc568849SUwe Kleine-König return; 878cc568849SUwe Kleine-König 879cc568849SUwe Kleine-König sport->old_status = status; 880cc568849SUwe Kleine-König 881cc568849SUwe Kleine-König if (changed & TIOCM_RI) 882cc568849SUwe Kleine-König sport->port.icount.rng++; 883cc568849SUwe Kleine-König if (changed & TIOCM_DSR) 884cc568849SUwe Kleine-König sport->port.icount.dsr++; 885cc568849SUwe Kleine-König if (changed & TIOCM_CAR) 886cc568849SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 887cc568849SUwe Kleine-König if (changed & TIOCM_CTS) 888cc568849SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 889cc568849SUwe Kleine-König 890cc568849SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 891cc568849SUwe Kleine-König } 892cc568849SUwe Kleine-König 893cc568849SUwe Kleine-König /* 894cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 895cc568849SUwe Kleine-König * modem status signals. 896cc568849SUwe Kleine-König */ 897cc568849SUwe Kleine-König static void imx_timeout(unsigned long data) 898cc568849SUwe Kleine-König { 899cc568849SUwe Kleine-König struct imx_port *sport = (struct imx_port *)data; 900cc568849SUwe Kleine-König unsigned long flags; 901cc568849SUwe Kleine-König 902cc568849SUwe Kleine-König if (sport->port.state) { 903cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 904cc568849SUwe Kleine-König imx_mctrl_check(sport); 905cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 906cc568849SUwe Kleine-König 907cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 908cc568849SUwe Kleine-König } 909cc568849SUwe Kleine-König } 910cc568849SUwe Kleine-König 911b4cdc8f6SHuang Shijie #define RX_BUF_SIZE (PAGE_SIZE) 912b4cdc8f6SHuang Shijie static void imx_rx_dma_done(struct imx_port *sport) 913b4cdc8f6SHuang Shijie { 914b4cdc8f6SHuang Shijie unsigned long temp; 91573631813SJiada Wang unsigned long flags; 91673631813SJiada Wang 91773631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 918b4cdc8f6SHuang Shijie 91986a04ba6SLucas Stach /* re-enable interrupts to get notified when new symbols are incoming */ 920b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 921b4cdc8f6SHuang Shijie temp |= UCR1_RRDYEN; 922b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 923b4cdc8f6SHuang Shijie 92486a04ba6SLucas Stach temp = readl(sport->port.membase + UCR2); 92586a04ba6SLucas Stach temp |= UCR2_ATEN; 92686a04ba6SLucas Stach writel(temp, sport->port.membase + UCR2); 92786a04ba6SLucas Stach 928b4cdc8f6SHuang Shijie sport->dma_is_rxing = 0; 9299ce4f8f3SGreg Kroah-Hartman 9309ce4f8f3SGreg Kroah-Hartman /* Is the shutdown waiting for us? */ 9319ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) 9329ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 93373631813SJiada Wang 93473631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 935b4cdc8f6SHuang Shijie } 936b4cdc8f6SHuang Shijie 937b4cdc8f6SHuang Shijie /* 938905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 939b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 940905c0decSLucas Stach * [2] the aging timer expires 941b4cdc8f6SHuang Shijie * 942905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 943905c0decSLucas Stach * for at least 8 byte durations. 944b4cdc8f6SHuang Shijie */ 945b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 946b4cdc8f6SHuang Shijie { 947b4cdc8f6SHuang Shijie struct imx_port *sport = data; 948b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 949b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9507cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 951b4cdc8f6SHuang Shijie struct dma_tx_state state; 952b4cdc8f6SHuang Shijie enum dma_status status; 953b4cdc8f6SHuang Shijie unsigned int count; 954b4cdc8f6SHuang Shijie 955b4cdc8f6SHuang Shijie /* unmap it first */ 956b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 957b4cdc8f6SHuang Shijie 958f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 959b4cdc8f6SHuang Shijie count = RX_BUF_SIZE - state.residue; 960392bceedSPhilipp Zabel 961b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 962b4cdc8f6SHuang Shijie 963b4cdc8f6SHuang Shijie if (count) { 9649b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 9659b289932SManfred Schlaegl int bytes = tty_insert_flip_string(port, sport->rx_buf, 9669b289932SManfred Schlaegl count); 9679b289932SManfred Schlaegl 9689b289932SManfred Schlaegl if (bytes != count) 9699b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 9709b289932SManfred Schlaegl } 9717cb92fd2SHuang Shijie tty_flip_buffer_push(port); 972abc7882aSLucas Stach sport->port.icount.rx += count; 973b4cdc8f6SHuang Shijie } 974976b39cdSLucas Stach 975976b39cdSLucas Stach /* 976976b39cdSLucas Stach * Restart RX DMA directly if more data is available in order to skip 977976b39cdSLucas Stach * the roundtrip through the IRQ handler. If there is some data already 978976b39cdSLucas Stach * in the FIFO, DMA needs to be restarted soon anyways. 979976b39cdSLucas Stach * 980976b39cdSLucas Stach * Otherwise stop the DMA and reactivate FIFO IRQs to restart DMA once 981976b39cdSLucas Stach * data starts to arrive again. 982976b39cdSLucas Stach */ 983976b39cdSLucas Stach if (readl(sport->port.membase + USR2) & USR2_RDR) 984976b39cdSLucas Stach start_rx_dma(sport); 985976b39cdSLucas Stach else 986976b39cdSLucas Stach imx_rx_dma_done(sport); 987ee5e7c10SRobin Gong } 988b4cdc8f6SHuang Shijie 989b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 990b4cdc8f6SHuang Shijie { 991b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 992b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 993b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 994b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 995b4cdc8f6SHuang Shijie int ret; 996b4cdc8f6SHuang Shijie 997b4cdc8f6SHuang Shijie sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 998b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 999b4cdc8f6SHuang Shijie if (ret == 0) { 1000b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1001b4cdc8f6SHuang Shijie return -EINVAL; 1002b4cdc8f6SHuang Shijie } 1003b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 1004b4cdc8f6SHuang Shijie DMA_PREP_INTERRUPT); 1005b4cdc8f6SHuang Shijie if (!desc) { 100624649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1007b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1008b4cdc8f6SHuang Shijie return -EINVAL; 1009b4cdc8f6SHuang Shijie } 1010b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 1011b4cdc8f6SHuang Shijie desc->callback_param = sport; 1012b4cdc8f6SHuang Shijie 1013b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 1014b4cdc8f6SHuang Shijie dmaengine_submit(desc); 1015b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1016b4cdc8f6SHuang Shijie return 0; 1017b4cdc8f6SHuang Shijie } 1018b4cdc8f6SHuang Shijie 1019cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1020cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1021184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1022184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1023cc32382dSLucas Stach 1024cc32382dSLucas Stach static void imx_setup_ufcr(struct imx_port *sport, 1025cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1026cc32382dSLucas Stach { 1027cc32382dSLucas Stach unsigned int val; 1028cc32382dSLucas Stach 1029cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 1030cc32382dSLucas Stach val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1031cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 1032cc32382dSLucas Stach writel(val, sport->port.membase + UFCR); 1033cc32382dSLucas Stach } 1034cc32382dSLucas Stach 1035b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1036b4cdc8f6SHuang Shijie { 1037b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1038b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1039b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 1040b4cdc8f6SHuang Shijie 1041b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1042b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1043b4cdc8f6SHuang Shijie } 1044b4cdc8f6SHuang Shijie 1045b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1046b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1047b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1048b4cdc8f6SHuang Shijie } 1049b4cdc8f6SHuang Shijie 1050b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 1051b4cdc8f6SHuang Shijie } 1052b4cdc8f6SHuang Shijie 1053b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1054b4cdc8f6SHuang Shijie { 1055b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1056b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1057b4cdc8f6SHuang Shijie int ret; 1058b4cdc8f6SHuang Shijie 1059b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1060b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1061b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1062b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1063b4cdc8f6SHuang Shijie ret = -EINVAL; 1064b4cdc8f6SHuang Shijie goto err; 1065b4cdc8f6SHuang Shijie } 1066b4cdc8f6SHuang Shijie 1067b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1068b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1069b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1070184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1071184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1072b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1073b4cdc8f6SHuang Shijie if (ret) { 1074b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1075b4cdc8f6SHuang Shijie goto err; 1076b4cdc8f6SHuang Shijie } 1077b4cdc8f6SHuang Shijie 1078b4cdc8f6SHuang Shijie sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1079b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1080b4cdc8f6SHuang Shijie ret = -ENOMEM; 1081b4cdc8f6SHuang Shijie goto err; 1082b4cdc8f6SHuang Shijie } 1083b4cdc8f6SHuang Shijie 1084b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1085b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1086b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1087b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1088b4cdc8f6SHuang Shijie ret = -EINVAL; 1089b4cdc8f6SHuang Shijie goto err; 1090b4cdc8f6SHuang Shijie } 1091b4cdc8f6SHuang Shijie 1092b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1093b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1094b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1095184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1096b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1097b4cdc8f6SHuang Shijie if (ret) { 1098b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1099b4cdc8f6SHuang Shijie goto err; 1100b4cdc8f6SHuang Shijie } 1101b4cdc8f6SHuang Shijie 1102b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1103b4cdc8f6SHuang Shijie 1104b4cdc8f6SHuang Shijie return 0; 1105b4cdc8f6SHuang Shijie err: 1106b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1107b4cdc8f6SHuang Shijie return ret; 1108b4cdc8f6SHuang Shijie } 1109b4cdc8f6SHuang Shijie 1110b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1111b4cdc8f6SHuang Shijie { 1112b4cdc8f6SHuang Shijie unsigned long temp; 1113b4cdc8f6SHuang Shijie 11149ce4f8f3SGreg Kroah-Hartman init_waitqueue_head(&sport->dma_wait); 11159ce4f8f3SGreg Kroah-Hartman 1116b4cdc8f6SHuang Shijie /* set UCR1 */ 1117b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1118905c0decSLucas Stach temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN; 1119b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1120b4cdc8f6SHuang Shijie 112186a04ba6SLucas Stach temp = readl(sport->port.membase + UCR2); 112286a04ba6SLucas Stach temp |= UCR2_ATEN; 112386a04ba6SLucas Stach writel(temp, sport->port.membase + UCR2); 112486a04ba6SLucas Stach 1125184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1126184bd70bSLucas Stach 1127b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1128b4cdc8f6SHuang Shijie } 1129b4cdc8f6SHuang Shijie 1130b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1131b4cdc8f6SHuang Shijie { 1132b4cdc8f6SHuang Shijie unsigned long temp; 1133b4cdc8f6SHuang Shijie 1134b4cdc8f6SHuang Shijie /* clear UCR1 */ 1135b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1136b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1137b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1138b4cdc8f6SHuang Shijie 1139b4cdc8f6SHuang Shijie /* clear UCR2 */ 1140b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 114186a04ba6SLucas Stach temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN); 1142b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1143b4cdc8f6SHuang Shijie 1144184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1145184bd70bSLucas Stach 1146b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1147b4cdc8f6SHuang Shijie } 1148b4cdc8f6SHuang Shijie 1149ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1150ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1151ab4382d2SGreg Kroah-Hartman 1152ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1153ab4382d2SGreg Kroah-Hartman { 1154ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1155458e2c82SFabio Estevam int retval, i; 1156ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1157ab4382d2SGreg Kroah-Hartman 115828eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 115928eb4274SHuang Shijie if (retval) 1160cb0f0a5fSFabio Estevam return retval; 116128eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 11620c375501SHuang Shijie if (retval) { 11630c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1164cb0f0a5fSFabio Estevam return retval; 11650c375501SHuang Shijie } 116628eb4274SHuang Shijie 1167cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1168ab4382d2SGreg Kroah-Hartman 1169ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1170ab4382d2SGreg Kroah-Hartman * requesting IRQs 1171ab4382d2SGreg Kroah-Hartman */ 1172ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1173ab4382d2SGreg Kroah-Hartman 1174ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1175ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1176ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1177ab4382d2SGreg Kroah-Hartman 1178ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1179ab4382d2SGreg Kroah-Hartman 11807e11577eSLucas Stach /* Can we enable the DMA support? */ 11817e11577eSLucas Stach if (is_imx6q_uart(sport) && !uart_console(port) && 11827e11577eSLucas Stach !sport->dma_is_inited) 11837e11577eSLucas Stach imx_uart_dma_init(sport); 11847e11577eSLucas Stach 118553794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1186772f8991SHuang Shijie /* Reset fifo's and state machines */ 1187458e2c82SFabio Estevam i = 100; 1188458e2c82SFabio Estevam 1189458e2c82SFabio Estevam temp = readl(sport->port.membase + UCR2); 1190458e2c82SFabio Estevam temp &= ~UCR2_SRST; 1191458e2c82SFabio Estevam writel(temp, sport->port.membase + UCR2); 1192458e2c82SFabio Estevam 1193458e2c82SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1194458e2c82SFabio Estevam udelay(1); 1195ab4382d2SGreg Kroah-Hartman 1196ab4382d2SGreg Kroah-Hartman /* 1197ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1198ab4382d2SGreg Kroah-Hartman */ 1199ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 120091555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 1201ab4382d2SGreg Kroah-Hartman 12027e11577eSLucas Stach if (sport->dma_is_inited && !sport->dma_is_enabled) 12037e11577eSLucas Stach imx_enable_dma(sport); 12047e11577eSLucas Stach 1205ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1206ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1207ab4382d2SGreg Kroah-Hartman 1208ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1209ab4382d2SGreg Kroah-Hartman 12106f026d6bSJiada Wang temp = readl(sport->port.membase + UCR4); 12116f026d6bSJiada Wang temp |= UCR4_OREN; 12126f026d6bSJiada Wang writel(temp, sport->port.membase + UCR4); 12136f026d6bSJiada Wang 1214ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1215ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1216bff09b09SLucas Stach if (!sport->have_rtscts) 1217bff09b09SLucas Stach temp |= UCR2_IRTS; 1218ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1219ab4382d2SGreg Kroah-Hartman 1220a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1221ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1222b38cb7d2SFabio Estevam temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1223ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1224ab4382d2SGreg Kroah-Hartman } 1225ab4382d2SGreg Kroah-Hartman 1226ab4382d2SGreg Kroah-Hartman /* 1227ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1228ab4382d2SGreg Kroah-Hartman */ 1229ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1230ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1231ab4382d2SGreg Kroah-Hartman 1232ab4382d2SGreg Kroah-Hartman return 0; 1233ab4382d2SGreg Kroah-Hartman } 1234ab4382d2SGreg Kroah-Hartman 1235ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1236ab4382d2SGreg Kroah-Hartman { 1237ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1238ab4382d2SGreg Kroah-Hartman unsigned long temp; 12399ec1882dSXinyu Chen unsigned long flags; 1240ab4382d2SGreg Kroah-Hartman 1241b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1242a4688bcdSHuang Shijie int ret; 1243a4688bcdSHuang Shijie 12449ce4f8f3SGreg Kroah-Hartman /* We have to wait for the DMA to finish. */ 1245a4688bcdSHuang Shijie ret = wait_event_interruptible(sport->dma_wait, 12469ce4f8f3SGreg Kroah-Hartman !sport->dma_is_rxing && !sport->dma_is_txing); 1247a4688bcdSHuang Shijie if (ret != 0) { 1248a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1249a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1250a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 1251a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 1252a4688bcdSHuang Shijie } 125373631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1254a4688bcdSHuang Shijie imx_stop_tx(port); 1255b4cdc8f6SHuang Shijie imx_stop_rx(port); 1256b4cdc8f6SHuang Shijie imx_disable_dma(sport); 125773631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1258b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1259b4cdc8f6SHuang Shijie } 1260b4cdc8f6SHuang Shijie 126158362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 126258362d5bSUwe Kleine-König 12639ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1264ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1265ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1266ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 12679ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1268ab4382d2SGreg Kroah-Hartman 1269ab4382d2SGreg Kroah-Hartman /* 1270ab4382d2SGreg Kroah-Hartman * Stop our timer. 1271ab4382d2SGreg Kroah-Hartman */ 1272ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1273ab4382d2SGreg Kroah-Hartman 1274ab4382d2SGreg Kroah-Hartman /* 1275ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1276ab4382d2SGreg Kroah-Hartman */ 1277ab4382d2SGreg Kroah-Hartman 12789ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1279ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1280ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1281ab4382d2SGreg Kroah-Hartman 1282ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 12839ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 128428eb4274SHuang Shijie 128528eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 128628eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1287ab4382d2SGreg Kroah-Hartman } 1288ab4382d2SGreg Kroah-Hartman 1289eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1290eb56b7edSHuang Shijie { 1291eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 129282e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1293a2c718ceSDirk Behme unsigned long temp; 12944f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1295eb56b7edSHuang Shijie 129682e86ae9SDirk Behme if (!sport->dma_chan_tx) 129782e86ae9SDirk Behme return; 129882e86ae9SDirk Behme 1299eb56b7edSHuang Shijie sport->tx_bytes = 0; 1300eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 130182e86ae9SDirk Behme if (sport->dma_is_txing) { 130282e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 130382e86ae9SDirk Behme DMA_TO_DEVICE); 1304a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 1305a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 1306a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 130782e86ae9SDirk Behme sport->dma_is_txing = false; 1308eb56b7edSHuang Shijie } 1309934084a9SFabio Estevam 1310934084a9SFabio Estevam /* 1311934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1312934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1313934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1314934084a9SFabio Estevam * and UTS[6-3]". As we don't need to restore the old values from 1315934084a9SFabio Estevam * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1316934084a9SFabio Estevam */ 1317934084a9SFabio Estevam ubir = readl(sport->port.membase + UBIR); 1318934084a9SFabio Estevam ubmr = readl(sport->port.membase + UBMR); 1319934084a9SFabio Estevam uts = readl(sport->port.membase + IMX21_UTS); 1320934084a9SFabio Estevam 1321934084a9SFabio Estevam temp = readl(sport->port.membase + UCR2); 1322934084a9SFabio Estevam temp &= ~UCR2_SRST; 1323934084a9SFabio Estevam writel(temp, sport->port.membase + UCR2); 1324934084a9SFabio Estevam 1325934084a9SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1326934084a9SFabio Estevam udelay(1); 1327934084a9SFabio Estevam 1328934084a9SFabio Estevam /* Restore the registers */ 1329934084a9SFabio Estevam writel(ubir, sport->port.membase + UBIR); 1330934084a9SFabio Estevam writel(ubmr, sport->port.membase + UBMR); 1331934084a9SFabio Estevam writel(uts, sport->port.membase + IMX21_UTS); 1332eb56b7edSHuang Shijie } 1333eb56b7edSHuang Shijie 1334ab4382d2SGreg Kroah-Hartman static void 1335ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1336ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1337ab4382d2SGreg Kroah-Hartman { 1338ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1339ab4382d2SGreg Kroah-Hartman unsigned long flags; 134058362d5bSUwe Kleine-König unsigned long ucr2, old_ucr1, old_ucr2; 134158362d5bSUwe Kleine-König unsigned int baud, quot; 1342ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 134358362d5bSUwe Kleine-König unsigned long div, ufcr; 1344ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1345ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1346ab4382d2SGreg Kroah-Hartman 1347ab4382d2SGreg Kroah-Hartman /* 1348ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1349ab4382d2SGreg Kroah-Hartman */ 1350ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1351ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1352ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1353ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1354ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1355ab4382d2SGreg Kroah-Hartman } 1356ab4382d2SGreg Kroah-Hartman 1357ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1358ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1359ab4382d2SGreg Kroah-Hartman else 1360ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1361ab4382d2SGreg Kroah-Hartman 1362ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1363ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1364ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 136517b8f2a3SUwe Kleine-König 136612fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 136717b8f2a3SUwe Kleine-König /* 136817b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 136917b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 137017b8f2a3SUwe Kleine-König * disabled. 137117b8f2a3SUwe Kleine-König */ 137258362d5bSUwe Kleine-König if (port->rs485.flags & 137358362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 137458362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 137558362d5bSUwe Kleine-König else 137658362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 137712fe59f9SFabio Estevam } else { 137858362d5bSUwe Kleine-König imx_port_rts_auto(sport, &ucr2); 137912fe59f9SFabio Estevam } 1380ab4382d2SGreg Kroah-Hartman } else { 1381ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1382ab4382d2SGreg Kroah-Hartman } 138358362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 138417b8f2a3SUwe Kleine-König /* disable transmitter */ 138558362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 138658362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 138758362d5bSUwe Kleine-König else 138858362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 138958362d5bSUwe Kleine-König } 139058362d5bSUwe Kleine-König 1391ab4382d2SGreg Kroah-Hartman 1392ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1393ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1394ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1395ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1396ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1397ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1398ab4382d2SGreg Kroah-Hartman } 1399ab4382d2SGreg Kroah-Hartman 1400995234daSEric Miao del_timer_sync(&sport->timer); 1401995234daSEric Miao 1402ab4382d2SGreg Kroah-Hartman /* 1403ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1404ab4382d2SGreg Kroah-Hartman */ 1405ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1406ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1407ab4382d2SGreg Kroah-Hartman 1408ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1409ab4382d2SGreg Kroah-Hartman 1410ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1411ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1412ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1413ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1414ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1415ab4382d2SGreg Kroah-Hartman 1416ab4382d2SGreg Kroah-Hartman /* 1417ab4382d2SGreg Kroah-Hartman * Characters to ignore 1418ab4382d2SGreg Kroah-Hartman */ 1419ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1420ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1421865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1422ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1423ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1424ab4382d2SGreg Kroah-Hartman /* 1425ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1426ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1427ab4382d2SGreg Kroah-Hartman */ 1428ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1429ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1430ab4382d2SGreg Kroah-Hartman } 1431ab4382d2SGreg Kroah-Hartman 143255d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 143355d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 143455d8693aSJiada Wang 1435ab4382d2SGreg Kroah-Hartman /* 1436ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1437ab4382d2SGreg Kroah-Hartman */ 1438ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1439ab4382d2SGreg Kroah-Hartman 1440ab4382d2SGreg Kroah-Hartman /* 1441ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1442ab4382d2SGreg Kroah-Hartman */ 1443ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1444ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1445ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1446ab4382d2SGreg Kroah-Hartman 1447ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1448ab4382d2SGreg Kroah-Hartman barrier(); 1449ab4382d2SGreg Kroah-Hartman 1450ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 145186a04ba6SLucas Stach old_ucr2 = readl(sport->port.membase + UCR2); 145286a04ba6SLucas Stach writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN), 1453ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 145486a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1455ab4382d2SGreg Kroah-Hartman 145609bd00f6SHubert Feurstein /* custom-baudrate handling */ 145709bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 145809bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 145909bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 146009bd00f6SHubert Feurstein 1461ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1462ab4382d2SGreg Kroah-Hartman if (div > 7) 1463ab4382d2SGreg Kroah-Hartman div = 7; 1464ab4382d2SGreg Kroah-Hartman if (!div) 1465ab4382d2SGreg Kroah-Hartman div = 1; 1466ab4382d2SGreg Kroah-Hartman 1467ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1468ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1469ab4382d2SGreg Kroah-Hartman 1470ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1471ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1472ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1473ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1474ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1475ab4382d2SGreg Kroah-Hartman 1476ab4382d2SGreg Kroah-Hartman num -= 1; 1477ab4382d2SGreg Kroah-Hartman denom -= 1; 1478ab4382d2SGreg Kroah-Hartman 1479ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1480ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 148120ff2fe6SHuang Shijie if (sport->dte_mode) 148220ff2fe6SHuang Shijie ufcr |= UFCR_DCEDTE; 1483ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1484ab4382d2SGreg Kroah-Hartman 1485ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1486ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1487ab4382d2SGreg Kroah-Hartman 1488a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1489ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1490fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1491ab4382d2SGreg Kroah-Hartman 1492ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1493ab4382d2SGreg Kroah-Hartman 1494ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 149586a04ba6SLucas Stach writel(ucr2 | old_ucr2, sport->port.membase + UCR2); 1496ab4382d2SGreg Kroah-Hartman 1497ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1498ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1499ab4382d2SGreg Kroah-Hartman 1500ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1501ab4382d2SGreg Kroah-Hartman } 1502ab4382d2SGreg Kroah-Hartman 1503ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1504ab4382d2SGreg Kroah-Hartman { 1505ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1506ab4382d2SGreg Kroah-Hartman 1507ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1508ab4382d2SGreg Kroah-Hartman } 1509ab4382d2SGreg Kroah-Hartman 1510ab4382d2SGreg Kroah-Hartman /* 1511ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1512ab4382d2SGreg Kroah-Hartman */ 1513ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1514ab4382d2SGreg Kroah-Hartman { 1515ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1516ab4382d2SGreg Kroah-Hartman 1517da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1518ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1519ab4382d2SGreg Kroah-Hartman } 1520ab4382d2SGreg Kroah-Hartman 1521ab4382d2SGreg Kroah-Hartman /* 1522ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1523ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1524ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1525ab4382d2SGreg Kroah-Hartman */ 1526ab4382d2SGreg Kroah-Hartman static int 1527ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1528ab4382d2SGreg Kroah-Hartman { 1529ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1530ab4382d2SGreg Kroah-Hartman int ret = 0; 1531ab4382d2SGreg Kroah-Hartman 1532ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1533ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1534ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1535ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1536ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1537ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1538ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1539ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1540a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1541ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1542ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1543ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1544ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1545ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1546ab4382d2SGreg Kroah-Hartman return ret; 1547ab4382d2SGreg Kroah-Hartman } 1548ab4382d2SGreg Kroah-Hartman 154901f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 15506b8bdad9SDaniel Thompson 15516b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 15526b8bdad9SDaniel Thompson { 15536b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 15546b8bdad9SDaniel Thompson unsigned long flags; 15556b8bdad9SDaniel Thompson unsigned long temp; 15566b8bdad9SDaniel Thompson int retval; 15576b8bdad9SDaniel Thompson 15586b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 15596b8bdad9SDaniel Thompson if (retval) 15606b8bdad9SDaniel Thompson return retval; 15616b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 15626b8bdad9SDaniel Thompson if (retval) 15636b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 15646b8bdad9SDaniel Thompson 1565cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 15666b8bdad9SDaniel Thompson 15676b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 15686b8bdad9SDaniel Thompson 15696b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR1); 15706b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 15716b8bdad9SDaniel Thompson temp |= IMX1_UCR1_UARTCLKEN; 15726b8bdad9SDaniel Thompson temp |= UCR1_UARTEN | UCR1_RRDYEN; 15736b8bdad9SDaniel Thompson temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 15746b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR1); 15756b8bdad9SDaniel Thompson 15766b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR2); 15776b8bdad9SDaniel Thompson temp |= UCR2_RXEN; 15786b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR2); 15796b8bdad9SDaniel Thompson 15806b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 15816b8bdad9SDaniel Thompson 15826b8bdad9SDaniel Thompson return 0; 15836b8bdad9SDaniel Thompson } 15846b8bdad9SDaniel Thompson 158501f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 158601f56abdSSaleem Abdulrasool { 1587f968ef34SDaniel Thompson if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 158826c47412SDirk Behme return NO_POLL_CHAR; 158901f56abdSSaleem Abdulrasool 1590f968ef34SDaniel Thompson return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 159101f56abdSSaleem Abdulrasool } 159201f56abdSSaleem Abdulrasool 159301f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 159401f56abdSSaleem Abdulrasool { 159501f56abdSSaleem Abdulrasool unsigned int status; 159601f56abdSSaleem Abdulrasool 159701f56abdSSaleem Abdulrasool /* drain */ 159801f56abdSSaleem Abdulrasool do { 1599f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR1); 160001f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 160101f56abdSSaleem Abdulrasool 160201f56abdSSaleem Abdulrasool /* write */ 1603f968ef34SDaniel Thompson writel_relaxed(c, port->membase + URTX0); 160401f56abdSSaleem Abdulrasool 160501f56abdSSaleem Abdulrasool /* flush */ 160601f56abdSSaleem Abdulrasool do { 1607f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR2); 160801f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 160901f56abdSSaleem Abdulrasool } 161001f56abdSSaleem Abdulrasool #endif 161101f56abdSSaleem Abdulrasool 161217b8f2a3SUwe Kleine-König static int imx_rs485_config(struct uart_port *port, 161317b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 161417b8f2a3SUwe Kleine-König { 161517b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 16167d1cadcaSBaruch Siach unsigned long temp; 161717b8f2a3SUwe Kleine-König 161817b8f2a3SUwe Kleine-König /* unimplemented */ 161917b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 162017b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 162117b8f2a3SUwe Kleine-König 162217b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 162317b8f2a3SUwe Kleine-König if (!sport->have_rtscts) 162417b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 162517b8f2a3SUwe Kleine-König 162617b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 162717b8f2a3SUwe Kleine-König /* disable transmitter */ 162817b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 162917b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 163058362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &temp); 163117b8f2a3SUwe Kleine-König else 163258362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 163317b8f2a3SUwe Kleine-König writel(temp, sport->port.membase + UCR2); 163417b8f2a3SUwe Kleine-König } 163517b8f2a3SUwe Kleine-König 16367d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 16377d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 16387d1cadcaSBaruch Siach rs485conf->flags & SER_RS485_RX_DURING_TX) { 16397d1cadcaSBaruch Siach temp = readl(sport->port.membase + UCR2); 16407d1cadcaSBaruch Siach temp |= UCR2_RXEN; 16417d1cadcaSBaruch Siach writel(temp, sport->port.membase + UCR2); 16427d1cadcaSBaruch Siach } 16437d1cadcaSBaruch Siach 164417b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 164517b8f2a3SUwe Kleine-König 164617b8f2a3SUwe Kleine-König return 0; 164717b8f2a3SUwe Kleine-König } 164817b8f2a3SUwe Kleine-König 1649ab4382d2SGreg Kroah-Hartman static struct uart_ops imx_pops = { 1650ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1651ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1652ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1653ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1654ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1655ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1656ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1657ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1658ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1659ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1660eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1661ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1662ab4382d2SGreg Kroah-Hartman .type = imx_type, 1663ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1664ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 166501f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 16666b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 166701f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 166801f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 166901f56abdSSaleem Abdulrasool #endif 1670ab4382d2SGreg Kroah-Hartman }; 1671ab4382d2SGreg Kroah-Hartman 1672ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1673ab4382d2SGreg Kroah-Hartman 1674ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1675ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1676ab4382d2SGreg Kroah-Hartman { 1677ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1678ab4382d2SGreg Kroah-Hartman 1679fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1680ab4382d2SGreg Kroah-Hartman barrier(); 1681ab4382d2SGreg Kroah-Hartman 1682ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1683ab4382d2SGreg Kroah-Hartman } 1684ab4382d2SGreg Kroah-Hartman 1685ab4382d2SGreg Kroah-Hartman /* 1686ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1687ab4382d2SGreg Kroah-Hartman */ 1688ab4382d2SGreg Kroah-Hartman static void 1689ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1690ab4382d2SGreg Kroah-Hartman { 1691ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 16920ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 16930ad5a814SDirk Behme unsigned int ucr1; 1694f30e8260SShawn Guo unsigned long flags = 0; 1695677fe555SThomas Gleixner int locked = 1; 16961cf93e0dSHuang Shijie int retval; 16971cf93e0dSHuang Shijie 16980c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 16991cf93e0dSHuang Shijie if (retval) 17001cf93e0dSHuang Shijie return; 17010c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 17021cf93e0dSHuang Shijie if (retval) { 17030c727a42SFabio Estevam clk_disable(sport->clk_per); 17041cf93e0dSHuang Shijie return; 17051cf93e0dSHuang Shijie } 17069ec1882dSXinyu Chen 1707677fe555SThomas Gleixner if (sport->port.sysrq) 1708677fe555SThomas Gleixner locked = 0; 1709677fe555SThomas Gleixner else if (oops_in_progress) 1710677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1711677fe555SThomas Gleixner else 17129ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1713ab4382d2SGreg Kroah-Hartman 1714ab4382d2SGreg Kroah-Hartman /* 17150ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1716ab4382d2SGreg Kroah-Hartman */ 17170ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 17180ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1719ab4382d2SGreg Kroah-Hartman 1720fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1721fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1722ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1723ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1724ab4382d2SGreg Kroah-Hartman 1725ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1726ab4382d2SGreg Kroah-Hartman 17270ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1728ab4382d2SGreg Kroah-Hartman 1729ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1730ab4382d2SGreg Kroah-Hartman 1731ab4382d2SGreg Kroah-Hartman /* 1732ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 17330ad5a814SDirk Behme * and restore UCR1/2/3 1734ab4382d2SGreg Kroah-Hartman */ 1735ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1736ab4382d2SGreg Kroah-Hartman 17370ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 17389ec1882dSXinyu Chen 1739677fe555SThomas Gleixner if (locked) 17409ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 17411cf93e0dSHuang Shijie 17420c727a42SFabio Estevam clk_disable(sport->clk_ipg); 17430c727a42SFabio Estevam clk_disable(sport->clk_per); 1744ab4382d2SGreg Kroah-Hartman } 1745ab4382d2SGreg Kroah-Hartman 1746ab4382d2SGreg Kroah-Hartman /* 1747ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1748ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1749ab4382d2SGreg Kroah-Hartman */ 1750ab4382d2SGreg Kroah-Hartman static void __init 1751ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1752ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1753ab4382d2SGreg Kroah-Hartman { 1754ab4382d2SGreg Kroah-Hartman 1755ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1756ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1757ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1758ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1759ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1760ab4382d2SGreg Kroah-Hartman 1761ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1762ab4382d2SGreg Kroah-Hartman 1763ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1764ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1765ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1766ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1767ab4382d2SGreg Kroah-Hartman else 1768ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1769ab4382d2SGreg Kroah-Hartman } 1770ab4382d2SGreg Kroah-Hartman 1771ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1772ab4382d2SGreg Kroah-Hartman *bits = 8; 1773ab4382d2SGreg Kroah-Hartman else 1774ab4382d2SGreg Kroah-Hartman *bits = 7; 1775ab4382d2SGreg Kroah-Hartman 1776ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1777ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1778ab4382d2SGreg Kroah-Hartman 1779ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1780ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1781ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1782ab4382d2SGreg Kroah-Hartman else 1783ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1784ab4382d2SGreg Kroah-Hartman 17853a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1786ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1787ab4382d2SGreg Kroah-Hartman 1788ab4382d2SGreg Kroah-Hartman { /* 1789ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1790ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1791ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1792ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1793ab4382d2SGreg Kroah-Hartman */ 1794ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1795ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1796ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1797ab4382d2SGreg Kroah-Hartman 1798ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1799ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1800ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1801ab4382d2SGreg Kroah-Hartman } 1802ab4382d2SGreg Kroah-Hartman 1803ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 180450bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1805ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1806ab4382d2SGreg Kroah-Hartman } 1807ab4382d2SGreg Kroah-Hartman } 1808ab4382d2SGreg Kroah-Hartman 1809ab4382d2SGreg Kroah-Hartman static int __init 1810ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1811ab4382d2SGreg Kroah-Hartman { 1812ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1813ab4382d2SGreg Kroah-Hartman int baud = 9600; 1814ab4382d2SGreg Kroah-Hartman int bits = 8; 1815ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1816ab4382d2SGreg Kroah-Hartman int flow = 'n'; 18171cf93e0dSHuang Shijie int retval; 1818ab4382d2SGreg Kroah-Hartman 1819ab4382d2SGreg Kroah-Hartman /* 1820ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1821ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1822ab4382d2SGreg Kroah-Hartman * console support. 1823ab4382d2SGreg Kroah-Hartman */ 1824ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1825ab4382d2SGreg Kroah-Hartman co->index = 0; 1826ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1827ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1828ab4382d2SGreg Kroah-Hartman return -ENODEV; 1829ab4382d2SGreg Kroah-Hartman 18301cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 18311cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 18321cf93e0dSHuang Shijie if (retval) 18331cf93e0dSHuang Shijie goto error_console; 18341cf93e0dSHuang Shijie 1835ab4382d2SGreg Kroah-Hartman if (options) 1836ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1837ab4382d2SGreg Kroah-Hartman else 1838ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1839ab4382d2SGreg Kroah-Hartman 1840cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1841ab4382d2SGreg Kroah-Hartman 18421cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 18431cf93e0dSHuang Shijie 18440c727a42SFabio Estevam clk_disable(sport->clk_ipg); 18450c727a42SFabio Estevam if (retval) { 18460c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 18470c727a42SFabio Estevam goto error_console; 18480c727a42SFabio Estevam } 18490c727a42SFabio Estevam 18500c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 18510c727a42SFabio Estevam if (retval) 18521cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 18531cf93e0dSHuang Shijie 18541cf93e0dSHuang Shijie error_console: 18551cf93e0dSHuang Shijie return retval; 1856ab4382d2SGreg Kroah-Hartman } 1857ab4382d2SGreg Kroah-Hartman 1858ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1859ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1860ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1861ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1862ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1863ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1864ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1865ab4382d2SGreg Kroah-Hartman .index = -1, 1866ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1867ab4382d2SGreg Kroah-Hartman }; 1868ab4382d2SGreg Kroah-Hartman 1869ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1870913c6c0eSLucas Stach 1871913c6c0eSLucas Stach #ifdef CONFIG_OF 1872913c6c0eSLucas Stach static void imx_console_early_putchar(struct uart_port *port, int ch) 1873913c6c0eSLucas Stach { 1874913c6c0eSLucas Stach while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL) 1875913c6c0eSLucas Stach cpu_relax(); 1876913c6c0eSLucas Stach 1877913c6c0eSLucas Stach writel_relaxed(ch, port->membase + URTX0); 1878913c6c0eSLucas Stach } 1879913c6c0eSLucas Stach 1880913c6c0eSLucas Stach static void imx_console_early_write(struct console *con, const char *s, 1881913c6c0eSLucas Stach unsigned count) 1882913c6c0eSLucas Stach { 1883913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 1884913c6c0eSLucas Stach 1885913c6c0eSLucas Stach uart_console_write(&dev->port, s, count, imx_console_early_putchar); 1886913c6c0eSLucas Stach } 1887913c6c0eSLucas Stach 1888913c6c0eSLucas Stach static int __init 1889913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 1890913c6c0eSLucas Stach { 1891913c6c0eSLucas Stach if (!dev->port.membase) 1892913c6c0eSLucas Stach return -ENODEV; 1893913c6c0eSLucas Stach 1894913c6c0eSLucas Stach dev->con->write = imx_console_early_write; 1895913c6c0eSLucas Stach 1896913c6c0eSLucas Stach return 0; 1897913c6c0eSLucas Stach } 1898913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 1899913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 1900913c6c0eSLucas Stach #endif 1901913c6c0eSLucas Stach 1902ab4382d2SGreg Kroah-Hartman #else 1903ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1904ab4382d2SGreg Kroah-Hartman #endif 1905ab4382d2SGreg Kroah-Hartman 1906ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1907ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1908ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 1909ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 1910ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 1911ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 1912ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 1913ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 1914ab4382d2SGreg Kroah-Hartman }; 1915ab4382d2SGreg Kroah-Hartman 191622698aa2SShawn Guo #ifdef CONFIG_OF 191720bb8095SUwe Kleine-König /* 191820bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 191920bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 192020bb8095SUwe Kleine-König */ 192122698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 192222698aa2SShawn Guo struct platform_device *pdev) 192322698aa2SShawn Guo { 192422698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 1925ff05967aSShawn Guo int ret; 192622698aa2SShawn Guo 19275f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 19285f8b9043SLABBE Corentin if (!sport->devdata) 192920bb8095SUwe Kleine-König /* no device tree device */ 193020bb8095SUwe Kleine-König return 1; 193122698aa2SShawn Guo 1932ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 1933ff05967aSShawn Guo if (ret < 0) { 1934ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1935a197a191SUwe Kleine-König return ret; 1936ff05967aSShawn Guo } 1937ff05967aSShawn Guo sport->port.line = ret; 193822698aa2SShawn Guo 193922698aa2SShawn Guo if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 194022698aa2SShawn Guo sport->have_rtscts = 1; 194122698aa2SShawn Guo 194220ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 194320ff2fe6SHuang Shijie sport->dte_mode = 1; 194420ff2fe6SHuang Shijie 194522698aa2SShawn Guo return 0; 194622698aa2SShawn Guo } 194722698aa2SShawn Guo #else 194822698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 194922698aa2SShawn Guo struct platform_device *pdev) 195022698aa2SShawn Guo { 195120bb8095SUwe Kleine-König return 1; 195222698aa2SShawn Guo } 195322698aa2SShawn Guo #endif 195422698aa2SShawn Guo 195522698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 195622698aa2SShawn Guo struct platform_device *pdev) 195722698aa2SShawn Guo { 1958574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 195922698aa2SShawn Guo 196022698aa2SShawn Guo sport->port.line = pdev->id; 196122698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 196222698aa2SShawn Guo 196322698aa2SShawn Guo if (!pdata) 196422698aa2SShawn Guo return; 196522698aa2SShawn Guo 196622698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 196722698aa2SShawn Guo sport->have_rtscts = 1; 196822698aa2SShawn Guo } 196922698aa2SShawn Guo 1970ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 1971ab4382d2SGreg Kroah-Hartman { 1972ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1973ab4382d2SGreg Kroah-Hartman void __iomem *base; 19748a61f0c7SFabio Estevam int ret = 0, reg; 1975ab4382d2SGreg Kroah-Hartman struct resource *res; 1976842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 1977ab4382d2SGreg Kroah-Hartman 197842d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1979ab4382d2SGreg Kroah-Hartman if (!sport) 1980ab4382d2SGreg Kroah-Hartman return -ENOMEM; 1981ab4382d2SGreg Kroah-Hartman 198222698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 198320bb8095SUwe Kleine-König if (ret > 0) 198422698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 198520bb8095SUwe Kleine-König else if (ret < 0) 198642d34191SSachin Kamat return ret; 198722698aa2SShawn Guo 1988ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1989da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 1990da82f997SAlexander Shiyan if (IS_ERR(base)) 1991da82f997SAlexander Shiyan return PTR_ERR(base); 1992ab4382d2SGreg Kroah-Hartman 1993842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 1994842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 1995842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 1996842633bdSUwe Kleine-König 1997ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 1998ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 1999ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2000ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2001ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2002842633bdSUwe Kleine-König sport->port.irq = rxirq; 2003ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2004ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 200517b8f2a3SUwe Kleine-König sport->port.rs485_config = imx_rs485_config; 200617b8f2a3SUwe Kleine-König sport->port.rs485.flags = 200717b8f2a3SUwe Kleine-König SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX; 2008ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 2009ab4382d2SGreg Kroah-Hartman init_timer(&sport->timer); 2010ab4382d2SGreg Kroah-Hartman sport->timer.function = imx_timeout; 2011ab4382d2SGreg Kroah-Hartman sport->timer.data = (unsigned long)sport; 2012ab4382d2SGreg Kroah-Hartman 201358362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 201458362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 201558362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 201658362d5bSUwe Kleine-König 20173a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 20183a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 20193a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2020833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 202142d34191SSachin Kamat return ret; 2022ab4382d2SGreg Kroah-Hartman } 2023ab4382d2SGreg Kroah-Hartman 20243a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 20253a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 20263a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2027833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 202842d34191SSachin Kamat return ret; 20293a9465faSSascha Hauer } 20303a9465faSSascha Hauer 20313a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2032ab4382d2SGreg Kroah-Hartman 20338a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 20348a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 20358a61f0c7SFabio Estevam if (ret) 20368a61f0c7SFabio Estevam return ret; 20378a61f0c7SFabio Estevam 20388a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 20398a61f0c7SFabio Estevam reg = readl_relaxed(sport->port.membase + UCR1); 20408a61f0c7SFabio Estevam reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 20418a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 20428a61f0c7SFabio Estevam writel_relaxed(reg, sport->port.membase + UCR1); 20438a61f0c7SFabio Estevam 20448a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 20458a61f0c7SFabio Estevam 2046c0d1c6b0SFabio Estevam /* 2047c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2048c0d1c6b0SFabio Estevam * chips only have one interrupt. 2049c0d1c6b0SFabio Estevam */ 2050842633bdSUwe Kleine-König if (txirq > 0) { 2051842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2052c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2053c0d1c6b0SFabio Estevam if (ret) 2054c0d1c6b0SFabio Estevam return ret; 2055c0d1c6b0SFabio Estevam 2056842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2057c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2058c0d1c6b0SFabio Estevam if (ret) 2059c0d1c6b0SFabio Estevam return ret; 2060c0d1c6b0SFabio Estevam } else { 2061842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2062c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2063c0d1c6b0SFabio Estevam if (ret) 2064c0d1c6b0SFabio Estevam return ret; 2065c0d1c6b0SFabio Estevam } 2066c0d1c6b0SFabio Estevam 206722698aa2SShawn Guo imx_ports[sport->port.line] = sport; 2068ab4382d2SGreg Kroah-Hartman 20690a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2070ab4382d2SGreg Kroah-Hartman 207145af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2072ab4382d2SGreg Kroah-Hartman } 2073ab4382d2SGreg Kroah-Hartman 2074ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2075ab4382d2SGreg Kroah-Hartman { 2076ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2077ab4382d2SGreg Kroah-Hartman 207845af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2079ab4382d2SGreg Kroah-Hartman } 2080ab4382d2SGreg Kroah-Hartman 2081c868cbb7SEduardo Valentin static void serial_imx_restore_context(struct imx_port *sport) 2082c868cbb7SEduardo Valentin { 2083c868cbb7SEduardo Valentin if (!sport->context_saved) 2084c868cbb7SEduardo Valentin return; 2085c868cbb7SEduardo Valentin 2086c868cbb7SEduardo Valentin writel(sport->saved_reg[4], sport->port.membase + UFCR); 2087c868cbb7SEduardo Valentin writel(sport->saved_reg[5], sport->port.membase + UESC); 2088c868cbb7SEduardo Valentin writel(sport->saved_reg[6], sport->port.membase + UTIM); 2089c868cbb7SEduardo Valentin writel(sport->saved_reg[7], sport->port.membase + UBIR); 2090c868cbb7SEduardo Valentin writel(sport->saved_reg[8], sport->port.membase + UBMR); 2091c868cbb7SEduardo Valentin writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS); 2092c868cbb7SEduardo Valentin writel(sport->saved_reg[0], sport->port.membase + UCR1); 2093c868cbb7SEduardo Valentin writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2); 2094c868cbb7SEduardo Valentin writel(sport->saved_reg[2], sport->port.membase + UCR3); 2095c868cbb7SEduardo Valentin writel(sport->saved_reg[3], sport->port.membase + UCR4); 2096c868cbb7SEduardo Valentin sport->context_saved = false; 2097c868cbb7SEduardo Valentin } 2098c868cbb7SEduardo Valentin 2099c868cbb7SEduardo Valentin static void serial_imx_save_context(struct imx_port *sport) 2100c868cbb7SEduardo Valentin { 2101c868cbb7SEduardo Valentin /* Save necessary regs */ 2102c868cbb7SEduardo Valentin sport->saved_reg[0] = readl(sport->port.membase + UCR1); 2103c868cbb7SEduardo Valentin sport->saved_reg[1] = readl(sport->port.membase + UCR2); 2104c868cbb7SEduardo Valentin sport->saved_reg[2] = readl(sport->port.membase + UCR3); 2105c868cbb7SEduardo Valentin sport->saved_reg[3] = readl(sport->port.membase + UCR4); 2106c868cbb7SEduardo Valentin sport->saved_reg[4] = readl(sport->port.membase + UFCR); 2107c868cbb7SEduardo Valentin sport->saved_reg[5] = readl(sport->port.membase + UESC); 2108c868cbb7SEduardo Valentin sport->saved_reg[6] = readl(sport->port.membase + UTIM); 2109c868cbb7SEduardo Valentin sport->saved_reg[7] = readl(sport->port.membase + UBIR); 2110c868cbb7SEduardo Valentin sport->saved_reg[8] = readl(sport->port.membase + UBMR); 2111c868cbb7SEduardo Valentin sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS); 2112c868cbb7SEduardo Valentin sport->context_saved = true; 2113c868cbb7SEduardo Valentin } 2114c868cbb7SEduardo Valentin 2115189550b8SEduardo Valentin static void serial_imx_enable_wakeup(struct imx_port *sport, bool on) 2116189550b8SEduardo Valentin { 2117189550b8SEduardo Valentin unsigned int val; 2118189550b8SEduardo Valentin 2119189550b8SEduardo Valentin val = readl(sport->port.membase + UCR3); 2120189550b8SEduardo Valentin if (on) 2121189550b8SEduardo Valentin val |= UCR3_AWAKEN; 2122189550b8SEduardo Valentin else 2123189550b8SEduardo Valentin val &= ~UCR3_AWAKEN; 2124189550b8SEduardo Valentin writel(val, sport->port.membase + UCR3); 2125bc85734bSEduardo Valentin 2126bc85734bSEduardo Valentin val = readl(sport->port.membase + UCR1); 2127bc85734bSEduardo Valentin if (on) 2128bc85734bSEduardo Valentin val |= UCR1_RTSDEN; 2129bc85734bSEduardo Valentin else 2130bc85734bSEduardo Valentin val &= ~UCR1_RTSDEN; 2131bc85734bSEduardo Valentin writel(val, sport->port.membase + UCR1); 2132189550b8SEduardo Valentin } 2133189550b8SEduardo Valentin 213490bb6bd3SShenwei Wang static int imx_serial_port_suspend_noirq(struct device *dev) 213590bb6bd3SShenwei Wang { 213690bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 213790bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 213890bb6bd3SShenwei Wang int ret; 213990bb6bd3SShenwei Wang 214090bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 214190bb6bd3SShenwei Wang if (ret) 214290bb6bd3SShenwei Wang return ret; 214390bb6bd3SShenwei Wang 2144c868cbb7SEduardo Valentin serial_imx_save_context(sport); 214590bb6bd3SShenwei Wang 214690bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 214790bb6bd3SShenwei Wang 214890bb6bd3SShenwei Wang return 0; 214990bb6bd3SShenwei Wang } 215090bb6bd3SShenwei Wang 215190bb6bd3SShenwei Wang static int imx_serial_port_resume_noirq(struct device *dev) 215290bb6bd3SShenwei Wang { 215390bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 215490bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 215590bb6bd3SShenwei Wang int ret; 215690bb6bd3SShenwei Wang 215790bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 215890bb6bd3SShenwei Wang if (ret) 215990bb6bd3SShenwei Wang return ret; 216090bb6bd3SShenwei Wang 2161c868cbb7SEduardo Valentin serial_imx_restore_context(sport); 216290bb6bd3SShenwei Wang 216390bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 216490bb6bd3SShenwei Wang 216590bb6bd3SShenwei Wang return 0; 216690bb6bd3SShenwei Wang } 216790bb6bd3SShenwei Wang 216890bb6bd3SShenwei Wang static int imx_serial_port_suspend(struct device *dev) 216990bb6bd3SShenwei Wang { 217090bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 217190bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 217290bb6bd3SShenwei Wang 217390bb6bd3SShenwei Wang /* enable wakeup from i.MX UART */ 2174189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, true); 217590bb6bd3SShenwei Wang 217690bb6bd3SShenwei Wang uart_suspend_port(&imx_reg, &sport->port); 217790bb6bd3SShenwei Wang 217829add68dSMartin Fuzzey /* Needed to enable clock in suspend_noirq */ 217929add68dSMartin Fuzzey return clk_prepare(sport->clk_ipg); 218090bb6bd3SShenwei Wang } 218190bb6bd3SShenwei Wang 218290bb6bd3SShenwei Wang static int imx_serial_port_resume(struct device *dev) 218390bb6bd3SShenwei Wang { 218490bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 218590bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 218690bb6bd3SShenwei Wang 218790bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 2188189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, false); 218990bb6bd3SShenwei Wang 219090bb6bd3SShenwei Wang uart_resume_port(&imx_reg, &sport->port); 219190bb6bd3SShenwei Wang 219229add68dSMartin Fuzzey clk_unprepare(sport->clk_ipg); 219329add68dSMartin Fuzzey 219490bb6bd3SShenwei Wang return 0; 219590bb6bd3SShenwei Wang } 219690bb6bd3SShenwei Wang 219790bb6bd3SShenwei Wang static const struct dev_pm_ops imx_serial_port_pm_ops = { 219890bb6bd3SShenwei Wang .suspend_noirq = imx_serial_port_suspend_noirq, 219990bb6bd3SShenwei Wang .resume_noirq = imx_serial_port_resume_noirq, 220090bb6bd3SShenwei Wang .suspend = imx_serial_port_suspend, 220190bb6bd3SShenwei Wang .resume = imx_serial_port_resume, 220290bb6bd3SShenwei Wang }; 220390bb6bd3SShenwei Wang 2204ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2205ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2206ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2207ab4382d2SGreg Kroah-Hartman 2208fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2209ab4382d2SGreg Kroah-Hartman .driver = { 2210ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 221122698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 221290bb6bd3SShenwei Wang .pm = &imx_serial_port_pm_ops, 2213ab4382d2SGreg Kroah-Hartman }, 2214ab4382d2SGreg Kroah-Hartman }; 2215ab4382d2SGreg Kroah-Hartman 2216ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2217ab4382d2SGreg Kroah-Hartman { 2218f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2219ab4382d2SGreg Kroah-Hartman 2220ab4382d2SGreg Kroah-Hartman if (ret) 2221ab4382d2SGreg Kroah-Hartman return ret; 2222ab4382d2SGreg Kroah-Hartman 2223ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2224ab4382d2SGreg Kroah-Hartman if (ret != 0) 2225ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2226ab4382d2SGreg Kroah-Hartman 2227f227824eSUwe Kleine-König return ret; 2228ab4382d2SGreg Kroah-Hartman } 2229ab4382d2SGreg Kroah-Hartman 2230ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2231ab4382d2SGreg Kroah-Hartman { 2232ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2233ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2234ab4382d2SGreg Kroah-Hartman } 2235ab4382d2SGreg Kroah-Hartman 2236ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2237ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2238ab4382d2SGreg Kroah-Hartman 2239ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2240ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2241ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2242ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2243