1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 12ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 13ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 14ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 15ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 23bd78ecd6SAhmad Fatoum #include <linux/ktime.h> 24fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2722698aa2SShawn Guo #include <linux/of.h> 2822698aa2SShawn Guo #include <linux/of_device.h> 29e32a9f8fSSachin Kamat #include <linux/io.h> 30b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 31ab4382d2SGreg Kroah-Hartman 32ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 33b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 34ab4382d2SGreg Kroah-Hartman 3558362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3658362d5bSUwe Kleine-König 37ab4382d2SGreg Kroah-Hartman /* Register definitions */ 38ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 39ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 40ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 41ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 42ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 43ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 44ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 45ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 46ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 47ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 48ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 49ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 50ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 51ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 52fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 53fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 54fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 55ab4382d2SGreg Kroah-Hartman 56ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 5755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 58ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 59ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 60ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 61ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 62ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 63ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 66ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 67ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 68ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 69b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 71302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 72ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 76302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 77fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 78b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 81ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 83ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 95ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 96ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 97ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 101b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10527e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 106fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 110ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 111ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 115b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1227be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 123ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 125ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 126ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 127ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 128ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 129ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 130ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 131ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13386a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13427e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 136ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 137ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 138ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 139ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 140ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14290ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14390ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14690ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 149ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 150ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 151ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 152ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 153ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 154ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 155ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 156ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 157ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 158ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 159ab4382d2SGreg Kroah-Hartman 160ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 161ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 162ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 163ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 164ab4382d2SGreg Kroah-Hartman 165ab4382d2SGreg Kroah-Hartman /* 166ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 167ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 168ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 169ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 170ab4382d2SGreg Kroah-Hartman */ 171ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 172ab4382d2SGreg Kroah-Hartman 173ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 174ab4382d2SGreg Kroah-Hartman 175ab4382d2SGreg Kroah-Hartman #define UART_NR 8 176ab4382d2SGreg Kroah-Hartman 177f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 178fe6b540aSShawn Guo enum imx_uart_type { 179fe6b540aSShawn Guo IMX1_UART, 180fe6b540aSShawn Guo IMX21_UART, 1811c06bde6SMartyn Welch IMX53_UART, 182a496e628SHuang Shijie IMX6Q_UART, 183fe6b540aSShawn Guo }; 184fe6b540aSShawn Guo 185fe6b540aSShawn Guo /* device type dependent stuff */ 186fe6b540aSShawn Guo struct imx_uart_data { 187fe6b540aSShawn Guo unsigned uts_reg; 188fe6b540aSShawn Guo enum imx_uart_type devtype; 189fe6b540aSShawn Guo }; 190fe6b540aSShawn Guo 191cb1a6092SUwe Kleine-König enum imx_tx_state { 192cb1a6092SUwe Kleine-König OFF, 193cb1a6092SUwe Kleine-König WAIT_AFTER_RTS, 194cb1a6092SUwe Kleine-König SEND, 195cb1a6092SUwe Kleine-König WAIT_AFTER_SEND, 196cb1a6092SUwe Kleine-König }; 197cb1a6092SUwe Kleine-König 198ab4382d2SGreg Kroah-Hartman struct imx_port { 199ab4382d2SGreg Kroah-Hartman struct uart_port port; 200ab4382d2SGreg Kroah-Hartman struct timer_list timer; 201ab4382d2SGreg Kroah-Hartman unsigned int old_status; 202ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2037b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20420ff2fe6SHuang Shijie unsigned int dte_mode:1; 2055a08a487SGeorge Hilliard unsigned int inverted_tx:1; 2065a08a487SGeorge Hilliard unsigned int inverted_rx:1; 2073a9465faSSascha Hauer struct clk *clk_ipg; 2083a9465faSSascha Hauer struct clk *clk_per; 2097d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 210b4cdc8f6SHuang Shijie 21158362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21258362d5bSUwe Kleine-König 2133a0ab62fSUwe Kleine-König /* shadow registers */ 2143a0ab62fSUwe Kleine-König unsigned int ucr1; 2153a0ab62fSUwe Kleine-König unsigned int ucr2; 2163a0ab62fSUwe Kleine-König unsigned int ucr3; 2173a0ab62fSUwe Kleine-König unsigned int ucr4; 2183a0ab62fSUwe Kleine-König unsigned int ufcr; 2193a0ab62fSUwe Kleine-König 220b4cdc8f6SHuang Shijie /* DMA fields */ 221b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 224b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 225b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 226b4cdc8f6SHuang Shijie void *rx_buf; 2279d297239SNandor Han struct circ_buf rx_ring; 228db0a196bSFabien Lahoudere unsigned int rx_buf_size; 229db0a196bSFabien Lahoudere unsigned int rx_period_length; 2309d297239SNandor Han unsigned int rx_periods; 2319d297239SNandor Han dma_cookie_t rx_cookie; 2327cb92fd2SHuang Shijie unsigned int tx_bytes; 233b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 23490bb6bd3SShenwei Wang unsigned int saved_reg[10]; 235c868cbb7SEduardo Valentin bool context_saved; 236cb1a6092SUwe Kleine-König 237cb1a6092SUwe Kleine-König enum imx_tx_state tx_state; 238bd78ecd6SAhmad Fatoum struct hrtimer trigger_start_tx; 239bd78ecd6SAhmad Fatoum struct hrtimer trigger_stop_tx; 240ab4382d2SGreg Kroah-Hartman }; 241ab4382d2SGreg Kroah-Hartman 2420ad5a814SDirk Behme struct imx_port_ucrs { 2430ad5a814SDirk Behme unsigned int ucr1; 2440ad5a814SDirk Behme unsigned int ucr2; 2450ad5a814SDirk Behme unsigned int ucr3; 2460ad5a814SDirk Behme }; 2470ad5a814SDirk Behme 248fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 249fe6b540aSShawn Guo [IMX1_UART] = { 250fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 251fe6b540aSShawn Guo .devtype = IMX1_UART, 252fe6b540aSShawn Guo }, 253fe6b540aSShawn Guo [IMX21_UART] = { 254fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 255fe6b540aSShawn Guo .devtype = IMX21_UART, 256fe6b540aSShawn Guo }, 2571c06bde6SMartyn Welch [IMX53_UART] = { 2581c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2591c06bde6SMartyn Welch .devtype = IMX53_UART, 2601c06bde6SMartyn Welch }, 261a496e628SHuang Shijie [IMX6Q_UART] = { 262a496e628SHuang Shijie .uts_reg = IMX21_UTS, 263a496e628SHuang Shijie .devtype = IMX6Q_UART, 264a496e628SHuang Shijie }, 265fe6b540aSShawn Guo }; 266fe6b540aSShawn Guo 267ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 268a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2691c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27022698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27122698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27222698aa2SShawn Guo { /* sentinel */ } 27322698aa2SShawn Guo }; 27422698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27522698aa2SShawn Guo 27627c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 27727c84426SUwe Kleine-König { 2783a0ab62fSUwe Kleine-König switch (offset) { 2793a0ab62fSUwe Kleine-König case UCR1: 2803a0ab62fSUwe Kleine-König sport->ucr1 = val; 2813a0ab62fSUwe Kleine-König break; 2823a0ab62fSUwe Kleine-König case UCR2: 2833a0ab62fSUwe Kleine-König sport->ucr2 = val; 2843a0ab62fSUwe Kleine-König break; 2853a0ab62fSUwe Kleine-König case UCR3: 2863a0ab62fSUwe Kleine-König sport->ucr3 = val; 2873a0ab62fSUwe Kleine-König break; 2883a0ab62fSUwe Kleine-König case UCR4: 2893a0ab62fSUwe Kleine-König sport->ucr4 = val; 2903a0ab62fSUwe Kleine-König break; 2913a0ab62fSUwe Kleine-König case UFCR: 2923a0ab62fSUwe Kleine-König sport->ufcr = val; 2933a0ab62fSUwe Kleine-König break; 2943a0ab62fSUwe Kleine-König default: 2953a0ab62fSUwe Kleine-König break; 2963a0ab62fSUwe Kleine-König } 29727c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 29827c84426SUwe Kleine-König } 29927c84426SUwe Kleine-König 30027c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30127c84426SUwe Kleine-König { 3023a0ab62fSUwe Kleine-König switch (offset) { 3033a0ab62fSUwe Kleine-König case UCR1: 3043a0ab62fSUwe Kleine-König return sport->ucr1; 3053a0ab62fSUwe Kleine-König break; 3063a0ab62fSUwe Kleine-König case UCR2: 3073a0ab62fSUwe Kleine-König /* 3083a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3093a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 310728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 311728e74a4SUwe Kleine-König * conditionally. 3123a0ab62fSUwe Kleine-König */ 3130aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3143a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3153a0ab62fSUwe Kleine-König return sport->ucr2; 3163a0ab62fSUwe Kleine-König break; 3173a0ab62fSUwe Kleine-König case UCR3: 3183a0ab62fSUwe Kleine-König return sport->ucr3; 3193a0ab62fSUwe Kleine-König break; 3203a0ab62fSUwe Kleine-König case UCR4: 3213a0ab62fSUwe Kleine-König return sport->ucr4; 3223a0ab62fSUwe Kleine-König break; 3233a0ab62fSUwe Kleine-König case UFCR: 3243a0ab62fSUwe Kleine-König return sport->ufcr; 3253a0ab62fSUwe Kleine-König break; 3263a0ab62fSUwe Kleine-König default: 32727c84426SUwe Kleine-König return readl(sport->port.membase + offset); 32827c84426SUwe Kleine-König } 3293a0ab62fSUwe Kleine-König } 33027c84426SUwe Kleine-König 3319d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 332fe6b540aSShawn Guo { 333fe6b540aSShawn Guo return sport->devdata->uts_reg; 334fe6b540aSShawn Guo } 335fe6b540aSShawn Guo 3369d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 337fe6b540aSShawn Guo { 338fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 339fe6b540aSShawn Guo } 340fe6b540aSShawn Guo 3419d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 342fe6b540aSShawn Guo { 343fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 344fe6b540aSShawn Guo } 345fe6b540aSShawn Guo 3469d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3471c06bde6SMartyn Welch { 3481c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3491c06bde6SMartyn Welch } 3501c06bde6SMartyn Welch 3519d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 352a496e628SHuang Shijie { 353a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 354a496e628SHuang Shijie } 355ab4382d2SGreg Kroah-Hartman /* 35644a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 35744a75411Sfabio.estevam@freescale.com */ 3580db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 3599d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 36044a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36144a75411Sfabio.estevam@freescale.com { 36244a75411Sfabio.estevam@freescale.com /* save control registers */ 36327c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 36427c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 36527c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 36644a75411Sfabio.estevam@freescale.com } 36744a75411Sfabio.estevam@freescale.com 3689d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 36944a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37044a75411Sfabio.estevam@freescale.com { 37144a75411Sfabio.estevam@freescale.com /* restore control registers */ 37227c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 37327c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 37427c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 37544a75411Sfabio.estevam@freescale.com } 376e8bfa760SFabio Estevam #endif 37744a75411Sfabio.estevam@freescale.com 3784e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3799d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 38058362d5bSUwe Kleine-König { 381bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38258362d5bSUwe Kleine-König 383a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 384a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 38558362d5bSUwe Kleine-König } 38658362d5bSUwe Kleine-König 3874e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3889d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 38958362d5bSUwe Kleine-König { 390bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 391bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39258362d5bSUwe Kleine-König 393a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 394a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39558362d5bSUwe Kleine-König } 39658362d5bSUwe Kleine-König 397bd78ecd6SAhmad Fatoum static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 398bd78ecd6SAhmad Fatoum { 399f751ae1cSJiri Slaby hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 400bd78ecd6SAhmad Fatoum } 401bd78ecd6SAhmad Fatoum 4026aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4039d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 40476821e22SUwe Kleine-König { 40576821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 40676821e22SUwe Kleine-König unsigned int ucr1, ucr2; 40776821e22SUwe Kleine-König 40876821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 40976821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 41076821e22SUwe Kleine-König 41176821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41276821e22SUwe Kleine-König 41376821e22SUwe Kleine-König if (sport->dma_is_enabled) { 41476821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 41576821e22SUwe Kleine-König } else { 41676821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 41781ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 41876821e22SUwe Kleine-König } 41976821e22SUwe Kleine-König 42076821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 42176821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42376821e22SUwe Kleine-König } 42476821e22SUwe Kleine-König 42576821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4269d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 427ab4382d2SGreg Kroah-Hartman { 428ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 429cb1a6092SUwe Kleine-König u32 ucr1, ucr4, usr2; 430cb1a6092SUwe Kleine-König 431cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) 432cb1a6092SUwe Kleine-König return; 433ab4382d2SGreg Kroah-Hartman 4349ce4f8f3SGreg Kroah-Hartman /* 4359ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4369ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4379ce4f8f3SGreg Kroah-Hartman */ 438686351f3SUwe Kleine-König if (sport->dma_is_txing) 4399ce4f8f3SGreg Kroah-Hartman return; 440b4cdc8f6SHuang Shijie 4414444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 442c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 44317b8f2a3SUwe Kleine-König 444cb1a6092SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 445cb1a6092SUwe Kleine-König if (!(usr2 & USR2_TXDC)) { 446cb1a6092SUwe Kleine-König /* The shifter is still busy, so retry once TC triggers */ 447cb1a6092SUwe Kleine-König return; 448cb1a6092SUwe Kleine-König } 449cb1a6092SUwe Kleine-König 450cb1a6092SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 451cb1a6092SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 452cb1a6092SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 453cb1a6092SUwe Kleine-König 454cb1a6092SUwe Kleine-König /* in rs485 mode disable transmitter */ 455cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 456cb1a6092SUwe Kleine-König if (sport->tx_state == SEND) { 457cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_SEND; 458bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_stop_tx, 459bd78ecd6SAhmad Fatoum port->rs485.delay_rts_after_send); 460bd78ecd6SAhmad Fatoum return; 461cb1a6092SUwe Kleine-König } 462cb1a6092SUwe Kleine-König 463cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS || 464bd78ecd6SAhmad Fatoum sport->tx_state == WAIT_AFTER_SEND) { 465cb1a6092SUwe Kleine-König u32 ucr2; 466cb1a6092SUwe Kleine-König 467bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_start_tx); 468cb1a6092SUwe Kleine-König 469cb1a6092SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 47017b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4719d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4721a613626SFabio Estevam else 4739d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4744444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 47517b8f2a3SUwe Kleine-König 4769d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 47776821e22SUwe Kleine-König 478cb1a6092SUwe Kleine-König sport->tx_state = OFF; 479cb1a6092SUwe Kleine-König } 480cb1a6092SUwe Kleine-König } else { 481cb1a6092SUwe Kleine-König sport->tx_state = OFF; 48217b8f2a3SUwe Kleine-König } 483ab4382d2SGreg Kroah-Hartman } 484ab4382d2SGreg Kroah-Hartman 4856aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4869d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 487ab4382d2SGreg Kroah-Hartman { 488ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 489028e0838SFugang Duan u32 ucr1, ucr2, ucr4; 490ab4382d2SGreg Kroah-Hartman 4914444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 49276821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 493028e0838SFugang Duan ucr4 = imx_uart_readl(sport, UCR4); 49476821e22SUwe Kleine-König 49576821e22SUwe Kleine-König if (sport->dma_is_enabled) { 49676821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 49776821e22SUwe Kleine-König } else { 49876821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 49981ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 500028e0838SFugang Duan ucr4 &= ~UCR4_OREN; 50176821e22SUwe Kleine-König } 50276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 503028e0838SFugang Duan imx_uart_writel(sport, ucr4, UCR4); 50476821e22SUwe Kleine-König 50576821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 50676821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 507ab4382d2SGreg Kroah-Hartman } 508ab4382d2SGreg Kroah-Hartman 5096aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5109d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 511ab4382d2SGreg Kroah-Hartman { 512ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 513ab4382d2SGreg Kroah-Hartman 514ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 51558362d5bSUwe Kleine-König 51658362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 517ab4382d2SGreg Kroah-Hartman } 518ab4382d2SGreg Kroah-Hartman 5199d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 5206aed2a88SUwe Kleine-König 5216aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5229d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 523ab4382d2SGreg Kroah-Hartman { 524ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 525ab4382d2SGreg Kroah-Hartman 5265e42e9a3SPeter Hurley if (sport->port.x_char) { 5275e42e9a3SPeter Hurley /* Send next char */ 52827c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5297e2fb5aaSJiada Wang sport->port.icount.tx++; 5307e2fb5aaSJiada Wang sport->port.x_char = 0; 5315e42e9a3SPeter Hurley return; 5325e42e9a3SPeter Hurley } 5335e42e9a3SPeter Hurley 5345e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5359d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5365e42e9a3SPeter Hurley return; 5375e42e9a3SPeter Hurley } 5385e42e9a3SPeter Hurley 53991a1a909SJiada Wang if (sport->dma_is_enabled) { 5404444dcf1SUwe Kleine-König u32 ucr1; 54191a1a909SJiada Wang /* 54291a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 54391a1a909SJiada Wang * and the TX IRQ is disabled. 54491a1a909SJiada Wang **/ 5454444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 546c514a6f8SSergey Organov ucr1 &= ~UCR1_TRDYEN; 54791a1a909SJiada Wang if (sport->dma_is_txing) { 5484444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5494444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 55091a1a909SJiada Wang } else { 5514444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5529d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 55391a1a909SJiada Wang } 55491a1a909SJiada Wang 5555aabd3b0SIan Jamison return; 5560c549223SUwe Kleine-König } 5575aabd3b0SIan Jamison 5585aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5599d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 560ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 561ab4382d2SGreg Kroah-Hartman * out the port here */ 56227c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 563ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 564ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 565ab4382d2SGreg Kroah-Hartman } 566ab4382d2SGreg Kroah-Hartman 567ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 568ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 569ab4382d2SGreg Kroah-Hartman 570ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5719d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 572ab4382d2SGreg Kroah-Hartman } 573ab4382d2SGreg Kroah-Hartman 5749d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 575b4cdc8f6SHuang Shijie { 576b4cdc8f6SHuang Shijie struct imx_port *sport = data; 577b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 578b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 579b4cdc8f6SHuang Shijie unsigned long flags; 5804444dcf1SUwe Kleine-König u32 ucr1; 581b4cdc8f6SHuang Shijie 58242f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 58342f752b3SDirk Behme 584b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 585b4cdc8f6SHuang Shijie 5864444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5874444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5884444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 589a2c718ceSDirk Behme 59042f752b3SDirk Behme /* update the stat */ 59142f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 59242f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 59342f752b3SDirk Behme 59442f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 59542f752b3SDirk Behme 596b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 597b4cdc8f6SHuang Shijie 598d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 599b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 6009ce4f8f3SGreg Kroah-Hartman 6010bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 6029d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 60318665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 60418665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 60518665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 60618665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 60718665414SUwe Kleine-König } 60864432a85SUwe Kleine-König 6090bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 610b4cdc8f6SHuang Shijie } 611b4cdc8f6SHuang Shijie 6126aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6139d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 614b4cdc8f6SHuang Shijie { 615b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 616b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 617b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 618b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 619b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 62018665414SUwe Kleine-König u32 ucr1, ucr4; 621b4cdc8f6SHuang Shijie int ret; 622b4cdc8f6SHuang Shijie 62342f752b3SDirk Behme if (sport->dma_is_txing) 624b4cdc8f6SHuang Shijie return; 625b4cdc8f6SHuang Shijie 62618665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 62718665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 62818665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 62918665414SUwe Kleine-König 630b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 631b4cdc8f6SHuang Shijie 632f7670783SFugang Duan if (xmit->tail < xmit->head || xmit->head == 0) { 6337942f857SDirk Behme sport->dma_tx_nents = 1; 6347942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6357942f857SDirk Behme } else { 636b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 637b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 638b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 639b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 640b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 641b4cdc8f6SHuang Shijie } 642b4cdc8f6SHuang Shijie 643b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 644b4cdc8f6SHuang Shijie if (ret == 0) { 645b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 646b4cdc8f6SHuang Shijie return; 647b4cdc8f6SHuang Shijie } 648596fd8dfSPeng Fan desc = dmaengine_prep_slave_sg(chan, sgl, ret, 649b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 650b4cdc8f6SHuang Shijie if (!desc) { 65124649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 65224649821SDirk Behme DMA_TO_DEVICE); 653b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 654b4cdc8f6SHuang Shijie return; 655b4cdc8f6SHuang Shijie } 6569d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 657b4cdc8f6SHuang Shijie desc->callback_param = sport; 658b4cdc8f6SHuang Shijie 659b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 660b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 661a2c718ceSDirk Behme 6624444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6634444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6644444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 665a2c718ceSDirk Behme 666b4cdc8f6SHuang Shijie /* fire it */ 667b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 668b4cdc8f6SHuang Shijie dmaengine_submit(desc); 669b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 670b4cdc8f6SHuang Shijie return; 671b4cdc8f6SHuang Shijie } 672b4cdc8f6SHuang Shijie 6736aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6749d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 675ab4382d2SGreg Kroah-Hartman { 676ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6774444dcf1SUwe Kleine-König u32 ucr1; 678ab4382d2SGreg Kroah-Hartman 67948669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 68048669b69SUwe Kleine-König return; 68148669b69SUwe Kleine-König 682cb1a6092SUwe Kleine-König /* 683cb1a6092SUwe Kleine-König * We cannot simply do nothing here if sport->tx_state == SEND already 684cb1a6092SUwe Kleine-König * because UCR1_TXMPTYEN might already have been cleared in 685cb1a6092SUwe Kleine-König * imx_uart_stop_tx(), but tx_state is still SEND. 686cb1a6092SUwe Kleine-König */ 6874444dcf1SUwe Kleine-König 688cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 689cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) { 690cb1a6092SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2); 69117b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6929d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 6931a613626SFabio Estevam else 6949d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 6954444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 69617b8f2a3SUwe Kleine-König 69776821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 6989d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 69976821e22SUwe Kleine-König 700cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_RTS; 701bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_start_tx, 702bd78ecd6SAhmad Fatoum port->rs485.delay_rts_before_send); 703bd78ecd6SAhmad Fatoum return; 704cb1a6092SUwe Kleine-König } 705cb1a6092SUwe Kleine-König 706bd78ecd6SAhmad Fatoum if (sport->tx_state == WAIT_AFTER_SEND 707bd78ecd6SAhmad Fatoum || sport->tx_state == WAIT_AFTER_RTS) { 708cb1a6092SUwe Kleine-König 709bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_stop_tx); 710bd78ecd6SAhmad Fatoum 71118665414SUwe Kleine-König /* 712cb1a6092SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA 713cb1a6092SUwe Kleine-König * is off. In the DMA case this is done in the 714cb1a6092SUwe Kleine-König * tx-callback. 71518665414SUwe Kleine-König */ 71618665414SUwe Kleine-König if (!sport->dma_is_enabled) { 71718665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 7184444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 7194444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 72017b8f2a3SUwe Kleine-König } 721cb1a6092SUwe Kleine-König 722cb1a6092SUwe Kleine-König sport->tx_state = SEND; 723cb1a6092SUwe Kleine-König } 724cb1a6092SUwe Kleine-König } else { 725cb1a6092SUwe Kleine-König sport->tx_state = SEND; 72618665414SUwe Kleine-König } 72717b8f2a3SUwe Kleine-König 728b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 7294444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 730c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 731b4cdc8f6SHuang Shijie } 732ab4382d2SGreg Kroah-Hartman 733b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 73491a1a909SJiada Wang if (sport->port.x_char) { 73591a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 73691a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 7374444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 7384444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 739c514a6f8SSergey Organov ucr1 |= UCR1_TRDYEN; 7404444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 74191a1a909SJiada Wang return; 74291a1a909SJiada Wang } 74391a1a909SJiada Wang 7445e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 7455e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7469d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 747b4cdc8f6SHuang Shijie return; 748b4cdc8f6SHuang Shijie } 749ab4382d2SGreg Kroah-Hartman } 750ab4382d2SGreg Kroah-Hartman 751101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 752ab4382d2SGreg Kroah-Hartman { 753ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7544444dcf1SUwe Kleine-König u32 usr1; 755ab4382d2SGreg Kroah-Hartman 75627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7574444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7584444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 759ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 760ab4382d2SGreg Kroah-Hartman 761ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 762ab4382d2SGreg Kroah-Hartman } 763ab4382d2SGreg Kroah-Hartman 764101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 765101aa46bSUwe Kleine-König { 766101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 767101aa46bSUwe Kleine-König irqreturn_t ret; 768101aa46bSUwe Kleine-König 769101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 770101aa46bSUwe Kleine-König 771101aa46bSUwe Kleine-König ret = __imx_uart_rtsint(irq, dev_id); 772101aa46bSUwe Kleine-König 773101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 774101aa46bSUwe Kleine-König 775101aa46bSUwe Kleine-König return ret; 776101aa46bSUwe Kleine-König } 777101aa46bSUwe Kleine-König 7789d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 779ab4382d2SGreg Kroah-Hartman { 780ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 781ab4382d2SGreg Kroah-Hartman 782c974991dSjun qian spin_lock(&sport->port.lock); 7839d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 784c974991dSjun qian spin_unlock(&sport->port.lock); 785ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 786ab4382d2SGreg Kroah-Hartman } 787ab4382d2SGreg Kroah-Hartman 788101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 789ab4382d2SGreg Kroah-Hartman { 790ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 791ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 79292a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 793ab4382d2SGreg Kroah-Hartman 79427c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 7954444dcf1SUwe Kleine-König u32 usr2; 7964444dcf1SUwe Kleine-König 797ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 798ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 799ab4382d2SGreg Kroah-Hartman 80027c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 801ab4382d2SGreg Kroah-Hartman 8024444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 8034444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 80427c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 805ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 806ab4382d2SGreg Kroah-Hartman continue; 807ab4382d2SGreg Kroah-Hartman } 808ab4382d2SGreg Kroah-Hartman 809ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 810ab4382d2SGreg Kroah-Hartman continue; 811ab4382d2SGreg Kroah-Hartman 812019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 813019dc9eaSHui Wang if (rx & URXD_BRK) 814019dc9eaSHui Wang sport->port.icount.brk++; 815019dc9eaSHui Wang else if (rx & URXD_PRERR) 816ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 817ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 818ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 819ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 820ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 821ab4382d2SGreg Kroah-Hartman 822ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 823ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 824ab4382d2SGreg Kroah-Hartman goto out; 825ab4382d2SGreg Kroah-Hartman continue; 826ab4382d2SGreg Kroah-Hartman } 827ab4382d2SGreg Kroah-Hartman 8288d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 829ab4382d2SGreg Kroah-Hartman 830019dc9eaSHui Wang if (rx & URXD_BRK) 831019dc9eaSHui Wang flg = TTY_BREAK; 832019dc9eaSHui Wang else if (rx & URXD_PRERR) 833ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 834ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 835ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 836ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 837ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 838ab4382d2SGreg Kroah-Hartman 839ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 840ab4382d2SGreg Kroah-Hartman } 841ab4382d2SGreg Kroah-Hartman 84255d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 84355d8693aSJiada Wang goto out; 84455d8693aSJiada Wang 8459b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 8469b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 847ab4382d2SGreg Kroah-Hartman } 848ab4382d2SGreg Kroah-Hartman 849ab4382d2SGreg Kroah-Hartman out: 8502e124b4aSJiri Slaby tty_flip_buffer_push(port); 851101aa46bSUwe Kleine-König 852ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 853ab4382d2SGreg Kroah-Hartman } 854ab4382d2SGreg Kroah-Hartman 855101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 856101aa46bSUwe Kleine-König { 857101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 858101aa46bSUwe Kleine-König irqreturn_t ret; 859101aa46bSUwe Kleine-König 860101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 861101aa46bSUwe Kleine-König 862101aa46bSUwe Kleine-König ret = __imx_uart_rxint(irq, dev_id); 863101aa46bSUwe Kleine-König 864101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 865101aa46bSUwe Kleine-König 866101aa46bSUwe Kleine-König return ret; 867101aa46bSUwe Kleine-König } 868101aa46bSUwe Kleine-König 8699d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 870b4cdc8f6SHuang Shijie 87166f95884SUwe Kleine-König /* 87266f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 87366f95884SUwe Kleine-König */ 8749d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 87566f95884SUwe Kleine-König { 87666f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 87727c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 87827c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 87966f95884SUwe Kleine-König 88066f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 88166f95884SUwe Kleine-König tmp |= TIOCM_CTS; 88266f95884SUwe Kleine-König 88366f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 8844b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 88566f95884SUwe Kleine-König tmp |= TIOCM_CAR; 88666f95884SUwe Kleine-König 88766f95884SUwe Kleine-König if (sport->dte_mode) 88827c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 88966f95884SUwe Kleine-König tmp |= TIOCM_RI; 89066f95884SUwe Kleine-König 89166f95884SUwe Kleine-König return tmp; 89266f95884SUwe Kleine-König } 89366f95884SUwe Kleine-König 89466f95884SUwe Kleine-König /* 89566f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 89666f95884SUwe Kleine-König */ 8979d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 89866f95884SUwe Kleine-König { 89966f95884SUwe Kleine-König unsigned int status, changed; 90066f95884SUwe Kleine-König 9019d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 90266f95884SUwe Kleine-König changed = status ^ sport->old_status; 90366f95884SUwe Kleine-König 90466f95884SUwe Kleine-König if (changed == 0) 90566f95884SUwe Kleine-König return; 90666f95884SUwe Kleine-König 90766f95884SUwe Kleine-König sport->old_status = status; 90866f95884SUwe Kleine-König 90966f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 91066f95884SUwe Kleine-König sport->port.icount.rng++; 91166f95884SUwe Kleine-König if (changed & TIOCM_DSR) 91266f95884SUwe Kleine-König sport->port.icount.dsr++; 91366f95884SUwe Kleine-König if (changed & TIOCM_CAR) 91466f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 91566f95884SUwe Kleine-König if (changed & TIOCM_CTS) 91666f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 91766f95884SUwe Kleine-König 91866f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 91966f95884SUwe Kleine-König } 92066f95884SUwe Kleine-König 9219d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 922ab4382d2SGreg Kroah-Hartman { 923ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 92443776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 9254d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 926ab4382d2SGreg Kroah-Hartman 9279baedb7bSJohan Hovold spin_lock(&sport->port.lock); 928101aa46bSUwe Kleine-König 92927c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 93027c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 93127c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 93227c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 93327c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 93427c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 935ab4382d2SGreg Kroah-Hartman 93643776896SUwe Kleine-König /* 93743776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 93843776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 93943776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 94043776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 94143776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 94243776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 94343776896SUwe Kleine-König */ 94443776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 94543776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 94643776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 94743776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 948c514a6f8SSergey Organov if ((ucr1 & UCR1_TRDYEN) == 0) 94943776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 95043776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 95143776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 95243776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 95343776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 95443776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 95543776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 95643776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 95743776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 95843776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 95943776896SUwe Kleine-König usr2 &= ~USR2_ORE; 96043776896SUwe Kleine-König 96143776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 962d1d996afSMatthias Schiffer imx_uart_writel(sport, USR1_AGTIM, USR1); 963d1d996afSMatthias Schiffer 964101aa46bSUwe Kleine-König __imx_uart_rxint(irq, dev_id); 9654d845a62SUwe Kleine-König ret = IRQ_HANDLED; 966b4cdc8f6SHuang Shijie } 967ab4382d2SGreg Kroah-Hartman 96843776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 969101aa46bSUwe Kleine-König imx_uart_transmit_buffer(sport); 9704d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9714d845a62SUwe Kleine-König } 972ab4382d2SGreg Kroah-Hartman 9730399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 97427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 97527e16501SUwe Kleine-König 9769d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 97727e16501SUwe Kleine-König 97827e16501SUwe Kleine-König ret = IRQ_HANDLED; 97927e16501SUwe Kleine-König } 98027e16501SUwe Kleine-König 9810399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 982101aa46bSUwe Kleine-König __imx_uart_rtsint(irq, dev_id); 9834d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9844d845a62SUwe Kleine-König } 985ab4382d2SGreg Kroah-Hartman 9860399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 98727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 9884d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9894d845a62SUwe Kleine-König } 990db1a9b55SFabio Estevam 9910399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 992f1f836e4SAlexander Stein sport->port.icount.overrun++; 99327c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 9944d845a62SUwe Kleine-König ret = IRQ_HANDLED; 995f1f836e4SAlexander Stein } 996f1f836e4SAlexander Stein 9979baedb7bSJohan Hovold spin_unlock(&sport->port.lock); 998101aa46bSUwe Kleine-König 9994d845a62SUwe Kleine-König return ret; 1000ab4382d2SGreg Kroah-Hartman } 1001ab4382d2SGreg Kroah-Hartman 1002ab4382d2SGreg Kroah-Hartman /* 1003ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 1004ab4382d2SGreg Kroah-Hartman */ 10059d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 1006ab4382d2SGreg Kroah-Hartman { 1007ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10081ce43e58SHuang Shijie unsigned int ret; 1009ab4382d2SGreg Kroah-Hartman 101027c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 10111ce43e58SHuang Shijie 10121ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 1013686351f3SUwe Kleine-König if (sport->dma_is_txing) 10141ce43e58SHuang Shijie ret = 0; 10151ce43e58SHuang Shijie 10161ce43e58SHuang Shijie return ret; 1017ab4382d2SGreg Kroah-Hartman } 1018ab4382d2SGreg Kroah-Hartman 10196aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10209d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 102158362d5bSUwe Kleine-König { 102258362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 10239d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 102458362d5bSUwe Kleine-König 102558362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 102658362d5bSUwe Kleine-König 102758362d5bSUwe Kleine-König return ret; 102858362d5bSUwe Kleine-König } 102958362d5bSUwe Kleine-König 10306aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10319d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1032ab4382d2SGreg Kroah-Hartman { 1033ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10344444dcf1SUwe Kleine-König u32 ucr3, uts; 1035ab4382d2SGreg Kroah-Hartman 103617b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 10374444dcf1SUwe Kleine-König u32 ucr2; 10384444dcf1SUwe Kleine-König 1039197540dcSSergey Organov /* 1040197540dcSSergey Organov * Turn off autoRTS if RTS is lowered and restore autoRTS 1041197540dcSSergey Organov * setting if RTS is raised. 1042197540dcSSergey Organov */ 10434444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 10444444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1045197540dcSSergey Organov if (mctrl & TIOCM_RTS) { 1046197540dcSSergey Organov ucr2 |= UCR2_CTS; 1047197540dcSSergey Organov /* 1048197540dcSSergey Organov * UCR2_IRTS is unset if and only if the port is 1049197540dcSSergey Organov * configured for CRTSCTS, so we use inverted UCR2_IRTS 1050197540dcSSergey Organov * to get the state to restore to. 1051197540dcSSergey Organov */ 1052197540dcSSergey Organov if (!(ucr2 & UCR2_IRTS)) 1053197540dcSSergey Organov ucr2 |= UCR2_CTSC; 1054197540dcSSergey Organov } 10554444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 105617b8f2a3SUwe Kleine-König } 10576b471a98SHuang Shijie 10584444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 105990ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 10604444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 10614444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 106290ebc483SUwe Kleine-König 10639d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 10646b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 10654444dcf1SUwe Kleine-König uts |= UTS_LOOP; 10669d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 106758362d5bSUwe Kleine-König 106858362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 1069ab4382d2SGreg Kroah-Hartman } 1070ab4382d2SGreg Kroah-Hartman 1071ab4382d2SGreg Kroah-Hartman /* 1072ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 1073ab4382d2SGreg Kroah-Hartman */ 10749d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1075ab4382d2SGreg Kroah-Hartman { 1076ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10774444dcf1SUwe Kleine-König unsigned long flags; 10784444dcf1SUwe Kleine-König u32 ucr1; 1079ab4382d2SGreg Kroah-Hartman 1080ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1081ab4382d2SGreg Kroah-Hartman 10824444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1083ab4382d2SGreg Kroah-Hartman 1084ab4382d2SGreg Kroah-Hartman if (break_state != 0) 10854444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1086ab4382d2SGreg Kroah-Hartman 10874444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1088ab4382d2SGreg Kroah-Hartman 1089ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1090ab4382d2SGreg Kroah-Hartman } 1091ab4382d2SGreg Kroah-Hartman 1092cc568849SUwe Kleine-König /* 1093cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1094cc568849SUwe Kleine-König * modem status signals. 1095cc568849SUwe Kleine-König */ 10969d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1097cc568849SUwe Kleine-König { 1098e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1099cc568849SUwe Kleine-König unsigned long flags; 1100cc568849SUwe Kleine-König 1101cc568849SUwe Kleine-König if (sport->port.state) { 1102cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 11039d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1104cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1105cc568849SUwe Kleine-König 1106cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1107cc568849SUwe Kleine-König } 1108cc568849SUwe Kleine-König } 1109cc568849SUwe Kleine-König 1110b4cdc8f6SHuang Shijie /* 1111905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1112b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1113905c0decSLucas Stach * [2] the aging timer expires 1114b4cdc8f6SHuang Shijie * 1115905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1116905c0decSLucas Stach * for at least 8 byte durations. 1117b4cdc8f6SHuang Shijie */ 11189d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1119b4cdc8f6SHuang Shijie { 1120b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1121b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1122b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 11237cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1124b4cdc8f6SHuang Shijie struct dma_tx_state state; 11259d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1126b4cdc8f6SHuang Shijie enum dma_status status; 11279d297239SNandor Han unsigned int w_bytes = 0; 11289d297239SNandor Han unsigned int r_bytes; 11299d297239SNandor Han unsigned int bd_size; 1130b4cdc8f6SHuang Shijie 1131fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1132392bceedSPhilipp Zabel 11339d297239SNandor Han if (status == DMA_ERROR) { 11349d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 11359d297239SNandor Han return; 11369d297239SNandor Han } 1137b4cdc8f6SHuang Shijie 11389b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1139976b39cdSLucas Stach 1140976b39cdSLucas Stach /* 11419d297239SNandor Han * The state-residue variable represents the empty space 11429d297239SNandor Han * relative to the entire buffer. Taking this in consideration 11439d297239SNandor Han * the head is always calculated base on the buffer total 11449d297239SNandor Han * length - DMA transaction residue. The UART script from the 11459d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 11469d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 11479d297239SNandor Han * Taking this in consideration the tail is always at the 11489d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1149976b39cdSLucas Stach */ 11509d297239SNandor Han 11519d297239SNandor Han /* Calculate the head */ 11529d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 11539d297239SNandor Han 11549d297239SNandor Han /* Calculate the tail. */ 11559d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 11569d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 11579d297239SNandor Han 11589d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 11599d297239SNandor Han rx_ring->head > rx_ring->tail) { 11609d297239SNandor Han 11619d297239SNandor Han /* Move data from tail to head */ 11629d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 11639d297239SNandor Han 11649d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 11659d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 11669d297239SNandor Han DMA_FROM_DEVICE); 11679d297239SNandor Han 11689d297239SNandor Han w_bytes = tty_insert_flip_string(port, 11699d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 11709d297239SNandor Han 11719d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 11729d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 11739d297239SNandor Han DMA_FROM_DEVICE); 11749d297239SNandor Han 11759d297239SNandor Han if (w_bytes != r_bytes) 11769d297239SNandor Han sport->port.icount.buf_overrun++; 11779d297239SNandor Han 11789d297239SNandor Han sport->port.icount.rx += w_bytes; 11799d297239SNandor Han } else { 11809d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11819d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1182ee5e7c10SRobin Gong } 11839d297239SNandor Han } 11849d297239SNandor Han 11859d297239SNandor Han if (w_bytes) { 11869d297239SNandor Han tty_flip_buffer_push(port); 11879d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 11889d297239SNandor Han } 11899d297239SNandor Han } 11909d297239SNandor Han 11919d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1192b4cdc8f6SHuang Shijie { 1193b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1194b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1195b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1196b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1197b4cdc8f6SHuang Shijie int ret; 1198b4cdc8f6SHuang Shijie 11999d297239SNandor Han sport->rx_ring.head = 0; 12009d297239SNandor Han sport->rx_ring.tail = 0; 12019d297239SNandor Han 1202db0a196bSFabien Lahoudere sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); 1203b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1204b4cdc8f6SHuang Shijie if (ret == 0) { 1205b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1206b4cdc8f6SHuang Shijie return -EINVAL; 1207b4cdc8f6SHuang Shijie } 12089d297239SNandor Han 12099d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 12109d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 12119d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 12129d297239SNandor Han 1213b4cdc8f6SHuang Shijie if (!desc) { 121424649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1215b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1216b4cdc8f6SHuang Shijie return -EINVAL; 1217b4cdc8f6SHuang Shijie } 12189d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1219b4cdc8f6SHuang Shijie desc->callback_param = sport; 1220b4cdc8f6SHuang Shijie 1221b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 12224139fd76SRomain Perier sport->dma_is_rxing = 1; 12239d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1224b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1225b4cdc8f6SHuang Shijie return 0; 1226b4cdc8f6SHuang Shijie } 1227b4cdc8f6SHuang Shijie 12289d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 122941d98b5dSNandor Han { 123045ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 12314444dcf1SUwe Kleine-König u32 usr1, usr2; 123241d98b5dSNandor Han 12334444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 12344444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 123541d98b5dSNandor Han 12364444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 123741d98b5dSNandor Han sport->port.icount.brk++; 123827c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 123945ca673eSTroy Kisky uart_handle_break(&sport->port); 124045ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 124145ca673eSTroy Kisky sport->port.icount.buf_overrun++; 124245ca673eSTroy Kisky tty_flip_buffer_push(port); 124345ca673eSTroy Kisky } else { 12444444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 124541d98b5dSNandor Han sport->port.icount.frame++; 124627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 12474444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 124841d98b5dSNandor Han sport->port.icount.parity++; 124927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 125041d98b5dSNandor Han } 125145ca673eSTroy Kisky } 125241d98b5dSNandor Han 12534444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 125441d98b5dSNandor Han sport->port.icount.overrun++; 125527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 125641d98b5dSNandor Han } 125741d98b5dSNandor Han 125841d98b5dSNandor Han } 125941d98b5dSNandor Han 1260cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1261*7a637784STomasz Moń #define RXTL_DEFAULT 8 /* 8 characters or aging timer */ 1262184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1263184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1264cc32382dSLucas Stach 12659d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1266cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1267cc32382dSLucas Stach { 1268cc32382dSLucas Stach unsigned int val; 1269cc32382dSLucas Stach 1270cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 127127c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1272cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 127327c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1274cc32382dSLucas Stach } 1275cc32382dSLucas Stach 1276b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1277b4cdc8f6SHuang Shijie { 1278b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1279e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1280b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1281b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 12829d297239SNandor Han sport->rx_cookie = -EINVAL; 1283b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1284b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1285b4cdc8f6SHuang Shijie } 1286b4cdc8f6SHuang Shijie 1287b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1288e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1289b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1290b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1291b4cdc8f6SHuang Shijie } 1292b4cdc8f6SHuang Shijie } 1293b4cdc8f6SHuang Shijie 1294b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1295b4cdc8f6SHuang Shijie { 1296b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1297b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1298b4cdc8f6SHuang Shijie int ret; 1299b4cdc8f6SHuang Shijie 1300b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1301b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1302b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1303b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1304b4cdc8f6SHuang Shijie ret = -EINVAL; 1305b4cdc8f6SHuang Shijie goto err; 1306b4cdc8f6SHuang Shijie } 1307b4cdc8f6SHuang Shijie 1308b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1309b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1310b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1311184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1312184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1313b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1314b4cdc8f6SHuang Shijie if (ret) { 1315b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1316b4cdc8f6SHuang Shijie goto err; 1317b4cdc8f6SHuang Shijie } 1318b4cdc8f6SHuang Shijie 1319db0a196bSFabien Lahoudere sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; 1320db0a196bSFabien Lahoudere sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); 1321b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1322b4cdc8f6SHuang Shijie ret = -ENOMEM; 1323b4cdc8f6SHuang Shijie goto err; 1324b4cdc8f6SHuang Shijie } 13259d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1326b4cdc8f6SHuang Shijie 1327b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1328b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1329b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1330b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1331b4cdc8f6SHuang Shijie ret = -EINVAL; 1332b4cdc8f6SHuang Shijie goto err; 1333b4cdc8f6SHuang Shijie } 1334b4cdc8f6SHuang Shijie 1335b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1336b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1337b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1338184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1339b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1340b4cdc8f6SHuang Shijie if (ret) { 1341b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1342b4cdc8f6SHuang Shijie goto err; 1343b4cdc8f6SHuang Shijie } 1344b4cdc8f6SHuang Shijie 1345b4cdc8f6SHuang Shijie return 0; 1346b4cdc8f6SHuang Shijie err: 1347b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1348b4cdc8f6SHuang Shijie return ret; 1349b4cdc8f6SHuang Shijie } 1350b4cdc8f6SHuang Shijie 13519d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1352b4cdc8f6SHuang Shijie { 13534444dcf1SUwe Kleine-König u32 ucr1; 1354b4cdc8f6SHuang Shijie 13559d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 135602b0abd3SUwe Kleine-König 1357b4cdc8f6SHuang Shijie /* set UCR1 */ 13584444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13594444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 13604444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1361b4cdc8f6SHuang Shijie 1362b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1363b4cdc8f6SHuang Shijie } 1364b4cdc8f6SHuang Shijie 13659d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1366b4cdc8f6SHuang Shijie { 1367676a31d8SSebastian Reichel u32 ucr1; 1368b4cdc8f6SHuang Shijie 1369b4cdc8f6SHuang Shijie /* clear UCR1 */ 13704444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13714444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 13724444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1373b4cdc8f6SHuang Shijie 13749d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1375184bd70bSLucas Stach 1376b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1377b4cdc8f6SHuang Shijie } 1378b4cdc8f6SHuang Shijie 1379ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1380ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1381ab4382d2SGreg Kroah-Hartman 13829d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1383ab4382d2SGreg Kroah-Hartman { 1384ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1385458e2c82SFabio Estevam int retval, i; 13864444dcf1SUwe Kleine-König unsigned long flags; 13874238c00bSUwe Kleine-König int dma_is_inited = 0; 13885a08a487SGeorge Hilliard u32 ucr1, ucr2, ucr3, ucr4; 1389ab4382d2SGreg Kroah-Hartman 139028eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 139128eb4274SHuang Shijie if (retval) 1392cb0f0a5fSFabio Estevam return retval; 139328eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 13940c375501SHuang Shijie if (retval) { 13950c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1396cb0f0a5fSFabio Estevam return retval; 13970c375501SHuang Shijie } 139828eb4274SHuang Shijie 13999d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1400ab4382d2SGreg Kroah-Hartman 1401ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1402ab4382d2SGreg Kroah-Hartman * requesting IRQs 1403ab4382d2SGreg Kroah-Hartman */ 14044444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1405ab4382d2SGreg Kroah-Hartman 1406ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 14074444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 14084444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1409ab4382d2SGreg Kroah-Hartman 14104444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1411ab4382d2SGreg Kroah-Hartman 14127e11577eSLucas Stach /* Can we enable the DMA support? */ 14134238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 14144238c00bSUwe Kleine-König dma_is_inited = 1; 14157e11577eSLucas Stach 141653794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1417772f8991SHuang Shijie /* Reset fifo's and state machines */ 1418458e2c82SFabio Estevam i = 100; 1419458e2c82SFabio Estevam 14204444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14214444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 14224444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1423458e2c82SFabio Estevam 142427c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1425458e2c82SFabio Estevam udelay(1); 1426ab4382d2SGreg Kroah-Hartman 1427ab4382d2SGreg Kroah-Hartman /* 1428ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1429ab4382d2SGreg Kroah-Hartman */ 143027c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 143127c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1432ab4382d2SGreg Kroah-Hartman 14334444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 14344444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 14356376cd39SNandor Han if (sport->have_rtscts) 14364444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1437ab4382d2SGreg Kroah-Hartman 14384444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1439ab4382d2SGreg Kroah-Hartman 14405a08a487SGeorge Hilliard ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 14411f043572STroy Kisky if (!sport->dma_is_enabled) 14424444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 14435a08a487SGeorge Hilliard if (sport->inverted_rx) 14445a08a487SGeorge Hilliard ucr4 |= UCR4_INVR; 14454444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 14466f026d6bSJiada Wang 14475a08a487SGeorge Hilliard ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 14485a08a487SGeorge Hilliard /* 14495a08a487SGeorge Hilliard * configure tx polarity before enabling tx 14505a08a487SGeorge Hilliard */ 14515a08a487SGeorge Hilliard if (sport->inverted_tx) 14525a08a487SGeorge Hilliard ucr3 |= UCR3_INVT; 14535a08a487SGeorge Hilliard 14545a08a487SGeorge Hilliard if (!imx_uart_is_imx1(sport)) { 14555a08a487SGeorge Hilliard ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 14565a08a487SGeorge Hilliard 14575a08a487SGeorge Hilliard if (sport->dte_mode) 14585a08a487SGeorge Hilliard /* disable broken interrupts */ 14595a08a487SGeorge Hilliard ucr3 &= ~(UCR3_RI | UCR3_DCD); 14605a08a487SGeorge Hilliard } 14615a08a487SGeorge Hilliard imx_uart_writel(sport, ucr3, UCR3); 14625a08a487SGeorge Hilliard 14634444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 14644444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1465bff09b09SLucas Stach if (!sport->have_rtscts) 14664444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 146716804d68SUwe Kleine-König /* 146816804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 146916804d68SUwe Kleine-König * we're using RTSD instead. 147016804d68SUwe Kleine-König */ 14719d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 14724444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 14734444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1474ab4382d2SGreg Kroah-Hartman 1475ab4382d2SGreg Kroah-Hartman /* 1476ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1477ab4382d2SGreg Kroah-Hartman */ 14789d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 147918a42088SPeter Senna Tschudin 148076821e22SUwe Kleine-König if (dma_is_inited) { 14819d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 14829d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 148376821e22SUwe Kleine-König } else { 148476821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 148576821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 148676821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 148781ca8e82SUwe Kleine-König 148881ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 148981ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 149081ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 149176821e22SUwe Kleine-König } 149218a42088SPeter Senna Tschudin 1493ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1494ab4382d2SGreg Kroah-Hartman 1495ab4382d2SGreg Kroah-Hartman return 0; 1496ab4382d2SGreg Kroah-Hartman } 1497ab4382d2SGreg Kroah-Hartman 14989d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1499ab4382d2SGreg Kroah-Hartman { 1500ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 15019ec1882dSXinyu Chen unsigned long flags; 1502339c7a87SSebastian Reichel u32 ucr1, ucr2, ucr4; 1503ab4382d2SGreg Kroah-Hartman 1504b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1505e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 15067722c240SSebastian Reichel if (sport->dma_is_txing) { 15077722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 15087722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 15097722c240SSebastian Reichel sport->dma_is_txing = 0; 15107722c240SSebastian Reichel } 1511e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 15127722c240SSebastian Reichel if (sport->dma_is_rxing) { 15137722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 15147722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 15157722c240SSebastian Reichel sport->dma_is_rxing = 0; 15167722c240SSebastian Reichel } 15179d297239SNandor Han 151873631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 15199d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 15209d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 15219d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 152273631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1523b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1524b4cdc8f6SHuang Shijie } 1525b4cdc8f6SHuang Shijie 152658362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 152758362d5bSUwe Kleine-König 15289ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 15294444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15300fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 15314444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 15329ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1533ab4382d2SGreg Kroah-Hartman 1534ab4382d2SGreg Kroah-Hartman /* 1535ab4382d2SGreg Kroah-Hartman * Stop our timer. 1536ab4382d2SGreg Kroah-Hartman */ 1537ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1538ab4382d2SGreg Kroah-Hartman 1539ab4382d2SGreg Kroah-Hartman /* 1540ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1541ab4382d2SGreg Kroah-Hartman */ 1542ab4382d2SGreg Kroah-Hartman 15439ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1544edd64f30SMatthias Schiffer 15454444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 1546c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 15474444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1548edd64f30SMatthias Schiffer 1549edd64f30SMatthias Schiffer ucr4 = imx_uart_readl(sport, UCR4); 1550028e0838SFugang Duan ucr4 &= ~UCR4_TCEN; 1551edd64f30SMatthias Schiffer imx_uart_writel(sport, ucr4, UCR4); 1552edd64f30SMatthias Schiffer 15539ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 155428eb4274SHuang Shijie 155528eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 155628eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1557ab4382d2SGreg Kroah-Hartman } 1558ab4382d2SGreg Kroah-Hartman 15596aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 15609d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1561eb56b7edSHuang Shijie { 1562eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 156382e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 15644444dcf1SUwe Kleine-König u32 ucr2; 15654f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1566eb56b7edSHuang Shijie 156782e86ae9SDirk Behme if (!sport->dma_chan_tx) 156882e86ae9SDirk Behme return; 156982e86ae9SDirk Behme 1570eb56b7edSHuang Shijie sport->tx_bytes = 0; 1571eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 157282e86ae9SDirk Behme if (sport->dma_is_txing) { 15734444dcf1SUwe Kleine-König u32 ucr1; 15744444dcf1SUwe Kleine-König 157582e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 157682e86ae9SDirk Behme DMA_TO_DEVICE); 15774444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 15784444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 15794444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 15800f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1581eb56b7edSHuang Shijie } 1582934084a9SFabio Estevam 1583934084a9SFabio Estevam /* 1584934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1585263763c1SMartyn Welch * 1586934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1587934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1588263763c1SMartyn Welch * and UTS[6-3]". 1589263763c1SMartyn Welch * 1590263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1591263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1592263763c1SMartyn Welch * registers. 1593934084a9SFabio Estevam */ 159427c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 159527c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 159627c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1597934084a9SFabio Estevam 15984444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15994444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 16004444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1601934084a9SFabio Estevam 160227c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1603934084a9SFabio Estevam udelay(1); 1604934084a9SFabio Estevam 1605934084a9SFabio Estevam /* Restore the registers */ 160627c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 160727c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 160827c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1609eb56b7edSHuang Shijie } 1610eb56b7edSHuang Shijie 1611ab4382d2SGreg Kroah-Hartman static void 16129d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1613ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1614ab4382d2SGreg Kroah-Hartman { 1615ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1616ab4382d2SGreg Kroah-Hartman unsigned long flags; 161785f30fbfSSergey Organov u32 ucr2, old_ucr2, ufcr; 161858362d5bSUwe Kleine-König unsigned int baud, quot; 1619ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 16204444dcf1SUwe Kleine-König unsigned long div; 1621d47bcb4aSSergey Organov unsigned long num, denom, old_ubir, old_ubmr; 1622ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1623ab4382d2SGreg Kroah-Hartman 1624ab4382d2SGreg Kroah-Hartman /* 1625ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1626ab4382d2SGreg Kroah-Hartman */ 1627ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1628ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1629ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1630ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1631ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1632ab4382d2SGreg Kroah-Hartman } 1633ab4382d2SGreg Kroah-Hartman 16344e828c3eSSergey Organov del_timer_sync(&sport->timer); 16354e828c3eSSergey Organov 16364e828c3eSSergey Organov /* 16374e828c3eSSergey Organov * Ask the core to calculate the divisor for us. 16384e828c3eSSergey Organov */ 16394e828c3eSSergey Organov baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 16404e828c3eSSergey Organov quot = uart_get_divisor(port, baud); 16414e828c3eSSergey Organov 16424e828c3eSSergey Organov spin_lock_irqsave(&sport->port.lock, flags); 16434e828c3eSSergey Organov 1644011bd05dSSergey Organov /* 1645011bd05dSSergey Organov * Read current UCR2 and save it for future use, then clear all the bits 1646011bd05dSSergey Organov * except those we will or may need to preserve. 1647011bd05dSSergey Organov */ 1648011bd05dSSergey Organov old_ucr2 = imx_uart_readl(sport, UCR2); 1649011bd05dSSergey Organov ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1650011bd05dSSergey Organov 1651011bd05dSSergey Organov ucr2 |= UCR2_SRST | UCR2_IRTS; 165241ffa48eSSergey Organov if ((termios->c_cflag & CSIZE) == CS8) 165341ffa48eSSergey Organov ucr2 |= UCR2_WS; 1654ab4382d2SGreg Kroah-Hartman 1655ddf89e75SSergey Organov if (!sport->have_rtscts) 1656ddf89e75SSergey Organov termios->c_cflag &= ~CRTSCTS; 165717b8f2a3SUwe Kleine-König 165812fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 165917b8f2a3SUwe Kleine-König /* 166017b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 166117b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 166217b8f2a3SUwe Kleine-König * disabled. 166317b8f2a3SUwe Kleine-König */ 166458362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 16659d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 16661a613626SFabio Estevam else 16679d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 166858362d5bSUwe Kleine-König 1669b777b5deSSergey Organov } else if (termios->c_cflag & CRTSCTS) { 1670b777b5deSSergey Organov /* 1671b777b5deSSergey Organov * Only let receiver control RTS output if we were not requested 1672b777b5deSSergey Organov * to have RTS inactive (which then should take precedence). 1673b777b5deSSergey Organov */ 1674b777b5deSSergey Organov if (ucr2 & UCR2_CTS) 1675b777b5deSSergey Organov ucr2 |= UCR2_CTSC; 1676b777b5deSSergey Organov } 1677ddf89e75SSergey Organov 1678ddf89e75SSergey Organov if (termios->c_cflag & CRTSCTS) 1679ddf89e75SSergey Organov ucr2 &= ~UCR2_IRTS; 1680ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1681ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1682ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1683ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1684ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1685ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1686ab4382d2SGreg Kroah-Hartman } 1687ab4382d2SGreg Kroah-Hartman 1688ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1689ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1690ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1691ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1692ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1693ab4382d2SGreg Kroah-Hartman 1694ab4382d2SGreg Kroah-Hartman /* 1695ab4382d2SGreg Kroah-Hartman * Characters to ignore 1696ab4382d2SGreg Kroah-Hartman */ 1697ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1698ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1699865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1700ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1701ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1702ab4382d2SGreg Kroah-Hartman /* 1703ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1704ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1705ab4382d2SGreg Kroah-Hartman */ 1706ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1707ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1708ab4382d2SGreg Kroah-Hartman } 1709ab4382d2SGreg Kroah-Hartman 171055d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 171155d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 171255d8693aSJiada Wang 1713ab4382d2SGreg Kroah-Hartman /* 1714ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1715ab4382d2SGreg Kroah-Hartman */ 1716ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1717ab4382d2SGreg Kroah-Hartman 171809bd00f6SHubert Feurstein /* custom-baudrate handling */ 171909bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 172009bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 172109bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 172209bd00f6SHubert Feurstein 1723ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1724ab4382d2SGreg Kroah-Hartman if (div > 7) 1725ab4382d2SGreg Kroah-Hartman div = 7; 1726ab4382d2SGreg Kroah-Hartman if (!div) 1727ab4382d2SGreg Kroah-Hartman div = 1; 1728ab4382d2SGreg Kroah-Hartman 1729ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1730ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1731ab4382d2SGreg Kroah-Hartman 1732ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1733ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1734ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1735ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1736ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1737ab4382d2SGreg Kroah-Hartman 1738ab4382d2SGreg Kroah-Hartman num -= 1; 1739ab4382d2SGreg Kroah-Hartman denom -= 1; 1740ab4382d2SGreg Kroah-Hartman 174127c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1742ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 174327c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1744ab4382d2SGreg Kroah-Hartman 1745d47bcb4aSSergey Organov /* 1746d47bcb4aSSergey Organov * Two registers below should always be written both and in this 1747d47bcb4aSSergey Organov * particular order. One consequence is that we need to check if any of 1748d47bcb4aSSergey Organov * them changes and then update both. We do need the check for change 1749d47bcb4aSSergey Organov * as even writing the same values seem to "restart" 1750d47bcb4aSSergey Organov * transmission/receiving logic in the hardware, that leads to data 1751d47bcb4aSSergey Organov * breakage even when rate doesn't in fact change. E.g., user switches 1752d47bcb4aSSergey Organov * RTS/CTS handshake and suddenly gets broken bytes. 1753d47bcb4aSSergey Organov */ 1754d47bcb4aSSergey Organov old_ubir = imx_uart_readl(sport, UBIR); 1755d47bcb4aSSergey Organov old_ubmr = imx_uart_readl(sport, UBMR); 1756d47bcb4aSSergey Organov if (old_ubir != num || old_ubmr != denom) { 175727c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 175827c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1759d47bcb4aSSergey Organov } 1760ab4382d2SGreg Kroah-Hartman 17619d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 176227c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 176327c84426SUwe Kleine-König IMX21_ONEMS); 1764ab4382d2SGreg Kroah-Hartman 1765011bd05dSSergey Organov imx_uart_writel(sport, ucr2, UCR2); 1766ab4382d2SGreg Kroah-Hartman 1767ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 17689d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1769ab4382d2SGreg Kroah-Hartman 1770ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1771ab4382d2SGreg Kroah-Hartman } 1772ab4382d2SGreg Kroah-Hartman 17739d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1774ab4382d2SGreg Kroah-Hartman { 1775ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1776ab4382d2SGreg Kroah-Hartman 1777ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1778ab4382d2SGreg Kroah-Hartman } 1779ab4382d2SGreg Kroah-Hartman 1780ab4382d2SGreg Kroah-Hartman /* 1781ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1782ab4382d2SGreg Kroah-Hartman */ 17839d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1784ab4382d2SGreg Kroah-Hartman { 1785ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1786ab4382d2SGreg Kroah-Hartman 1787da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1788ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1789ab4382d2SGreg Kroah-Hartman } 1790ab4382d2SGreg Kroah-Hartman 1791ab4382d2SGreg Kroah-Hartman /* 1792ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1793ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1794ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1795ab4382d2SGreg Kroah-Hartman */ 1796ab4382d2SGreg Kroah-Hartman static int 17979d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1798ab4382d2SGreg Kroah-Hartman { 1799ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1800ab4382d2SGreg Kroah-Hartman int ret = 0; 1801ab4382d2SGreg Kroah-Hartman 1802ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1803ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1804ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1805ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1806ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1807ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1808ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1809ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1810a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1811ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1812ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1813ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1814ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1815ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1816ab4382d2SGreg Kroah-Hartman return ret; 1817ab4382d2SGreg Kroah-Hartman } 1818ab4382d2SGreg Kroah-Hartman 181901f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18206b8bdad9SDaniel Thompson 18219d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 18226b8bdad9SDaniel Thompson { 18236b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 18246b8bdad9SDaniel Thompson unsigned long flags; 18254444dcf1SUwe Kleine-König u32 ucr1, ucr2; 18266b8bdad9SDaniel Thompson int retval; 18276b8bdad9SDaniel Thompson 18286b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 18296b8bdad9SDaniel Thompson if (retval) 18306b8bdad9SDaniel Thompson return retval; 18316b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 18326b8bdad9SDaniel Thompson if (retval) 18336b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 18346b8bdad9SDaniel Thompson 18359d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 18366b8bdad9SDaniel Thompson 18376b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 18386b8bdad9SDaniel Thompson 183976821e22SUwe Kleine-König /* 184076821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 184176821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 184276821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 184376821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 184476821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 184576821e22SUwe Kleine-König */ 18464444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 184776821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 184876821e22SUwe Kleine-König 18499d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 18504444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 18516b8bdad9SDaniel Thompson 185276821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 1853c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 185476821e22SUwe Kleine-König 1855aef1b6a2SMingrui Ren ucr2 |= UCR2_RXEN | UCR2_TXEN; 185681ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 185776821e22SUwe Kleine-König 185876821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 18594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 18606b8bdad9SDaniel Thompson 186176821e22SUwe Kleine-König /* now enable irqs */ 186276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 186381ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 186476821e22SUwe Kleine-König 18656b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 18666b8bdad9SDaniel Thompson 18676b8bdad9SDaniel Thompson return 0; 18686b8bdad9SDaniel Thompson } 18696b8bdad9SDaniel Thompson 18709d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 187101f56abdSSaleem Abdulrasool { 187227c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 187327c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 187426c47412SDirk Behme return NO_POLL_CHAR; 187501f56abdSSaleem Abdulrasool 187627c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 187701f56abdSSaleem Abdulrasool } 187801f56abdSSaleem Abdulrasool 18799d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 188001f56abdSSaleem Abdulrasool { 188127c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 188201f56abdSSaleem Abdulrasool unsigned int status; 188301f56abdSSaleem Abdulrasool 188401f56abdSSaleem Abdulrasool /* drain */ 188501f56abdSSaleem Abdulrasool do { 188627c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 188701f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 188801f56abdSSaleem Abdulrasool 188901f56abdSSaleem Abdulrasool /* write */ 189027c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 189101f56abdSSaleem Abdulrasool 189201f56abdSSaleem Abdulrasool /* flush */ 189301f56abdSSaleem Abdulrasool do { 189427c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 189501f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 189601f56abdSSaleem Abdulrasool } 189701f56abdSSaleem Abdulrasool #endif 189801f56abdSSaleem Abdulrasool 18996aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 19009d1a50a2SUwe Kleine-König static int imx_uart_rs485_config(struct uart_port *port, 190117b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 190217b8f2a3SUwe Kleine-König { 190317b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 19044444dcf1SUwe Kleine-König u32 ucr2; 190517b8f2a3SUwe Kleine-König 190617b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 19077b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 190817b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 190917b8f2a3SUwe Kleine-König 191017b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 19116d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 19126d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 19136d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 19146d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 19156d215f83SStefan Agner 191617b8f2a3SUwe Kleine-König /* disable transmitter */ 19174444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 191817b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 19199d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 19201a613626SFabio Estevam else 19219d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 19224444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 192317b8f2a3SUwe Kleine-König } 192417b8f2a3SUwe Kleine-König 19257d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 19267d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 192776821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 19289d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 19297d1cadcaSBaruch Siach 193017b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 193117b8f2a3SUwe Kleine-König 193217b8f2a3SUwe Kleine-König return 0; 193317b8f2a3SUwe Kleine-König } 193417b8f2a3SUwe Kleine-König 19359d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 19369d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 19379d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 19389d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 19399d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 19409d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 19419d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 19429d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 19439d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 19449d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 19459d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 19469d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 19479d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 19489d1a50a2SUwe Kleine-König .type = imx_uart_type, 19499d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 19509d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 195101f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 19529d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 19539d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 19549d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 195501f56abdSSaleem Abdulrasool #endif 1956ab4382d2SGreg Kroah-Hartman }; 1957ab4382d2SGreg Kroah-Hartman 19589d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1959ab4382d2SGreg Kroah-Hartman 19600db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 19619d1a50a2SUwe Kleine-König static void imx_uart_console_putchar(struct uart_port *port, int ch) 1962ab4382d2SGreg Kroah-Hartman { 1963ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1964ab4382d2SGreg Kroah-Hartman 19659d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1966ab4382d2SGreg Kroah-Hartman barrier(); 1967ab4382d2SGreg Kroah-Hartman 196827c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1969ab4382d2SGreg Kroah-Hartman } 1970ab4382d2SGreg Kroah-Hartman 1971ab4382d2SGreg Kroah-Hartman /* 1972ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1973ab4382d2SGreg Kroah-Hartman */ 1974ab4382d2SGreg Kroah-Hartman static void 19759d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1976ab4382d2SGreg Kroah-Hartman { 19779d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 19780ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 197918ee37e1SJohan Hovold unsigned long flags; 19800ad5a814SDirk Behme unsigned int ucr1; 1981677fe555SThomas Gleixner int locked = 1; 19829ec1882dSXinyu Chen 1983677fe555SThomas Gleixner if (sport->port.sysrq) 1984677fe555SThomas Gleixner locked = 0; 1985677fe555SThomas Gleixner else if (oops_in_progress) 1986677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1987677fe555SThomas Gleixner else 19889ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1989ab4382d2SGreg Kroah-Hartman 1990ab4382d2SGreg Kroah-Hartman /* 19910ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1992ab4382d2SGreg Kroah-Hartman */ 19939d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 19940ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1995ab4382d2SGreg Kroah-Hartman 19969d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 1997fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1998ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1999c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 2000ab4382d2SGreg Kroah-Hartman 200127c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2002ab4382d2SGreg Kroah-Hartman 200327c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2004ab4382d2SGreg Kroah-Hartman 20059d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2006ab4382d2SGreg Kroah-Hartman 2007ab4382d2SGreg Kroah-Hartman /* 2008ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 20090ad5a814SDirk Behme * and restore UCR1/2/3 2010ab4382d2SGreg Kroah-Hartman */ 201127c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2012ab4382d2SGreg Kroah-Hartman 20139d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 20149ec1882dSXinyu Chen 2015677fe555SThomas Gleixner if (locked) 20169ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 2017ab4382d2SGreg Kroah-Hartman } 2018ab4382d2SGreg Kroah-Hartman 2019ab4382d2SGreg Kroah-Hartman /* 2020ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 2021ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 2022ab4382d2SGreg Kroah-Hartman */ 20236d0d1b5aSStefan Agner static void 20249d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 2025ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 2026ab4382d2SGreg Kroah-Hartman { 2027ab4382d2SGreg Kroah-Hartman 202827c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2029ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 2030ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 2031ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 2032ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 2033ab4382d2SGreg Kroah-Hartman 203427c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 2035ab4382d2SGreg Kroah-Hartman 2036ab4382d2SGreg Kroah-Hartman *parity = 'n'; 2037ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 2038ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 2039ab4382d2SGreg Kroah-Hartman *parity = 'o'; 2040ab4382d2SGreg Kroah-Hartman else 2041ab4382d2SGreg Kroah-Hartman *parity = 'e'; 2042ab4382d2SGreg Kroah-Hartman } 2043ab4382d2SGreg Kroah-Hartman 2044ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 2045ab4382d2SGreg Kroah-Hartman *bits = 8; 2046ab4382d2SGreg Kroah-Hartman else 2047ab4382d2SGreg Kroah-Hartman *bits = 7; 2048ab4382d2SGreg Kroah-Hartman 204927c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 205027c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2051ab4382d2SGreg Kroah-Hartman 205227c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2053ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 2054ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 2055ab4382d2SGreg Kroah-Hartman else 2056ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 2057ab4382d2SGreg Kroah-Hartman 20583a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2059ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2060ab4382d2SGreg Kroah-Hartman 2061ab4382d2SGreg Kroah-Hartman { /* 2062ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2063ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2064ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2065ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2066ab4382d2SGreg Kroah-Hartman */ 2067ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2068ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2069ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2070ab4382d2SGreg Kroah-Hartman 2071ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2072ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2073ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2074ab4382d2SGreg Kroah-Hartman } 2075ab4382d2SGreg Kroah-Hartman 2076ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 2077f5a9e5f7SFabio Estevam dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2078ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2079ab4382d2SGreg Kroah-Hartman } 2080ab4382d2SGreg Kroah-Hartman } 2081ab4382d2SGreg Kroah-Hartman 20826d0d1b5aSStefan Agner static int 20839d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2084ab4382d2SGreg Kroah-Hartman { 2085ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2086ab4382d2SGreg Kroah-Hartman int baud = 9600; 2087ab4382d2SGreg Kroah-Hartman int bits = 8; 2088ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2089ab4382d2SGreg Kroah-Hartman int flow = 'n'; 20901cf93e0dSHuang Shijie int retval; 2091ab4382d2SGreg Kroah-Hartman 2092ab4382d2SGreg Kroah-Hartman /* 2093ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2094ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2095ab4382d2SGreg Kroah-Hartman * console support. 2096ab4382d2SGreg Kroah-Hartman */ 20979d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2098ab4382d2SGreg Kroah-Hartman co->index = 0; 20999d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2100ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2101ab4382d2SGreg Kroah-Hartman return -ENODEV; 2102ab4382d2SGreg Kroah-Hartman 21031cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 21041cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 21051cf93e0dSHuang Shijie if (retval) 21061cf93e0dSHuang Shijie goto error_console; 21071cf93e0dSHuang Shijie 2108ab4382d2SGreg Kroah-Hartman if (options) 2109ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2110ab4382d2SGreg Kroah-Hartman else 21119d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2112ab4382d2SGreg Kroah-Hartman 21139d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2114ab4382d2SGreg Kroah-Hartman 21151cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 21161cf93e0dSHuang Shijie 21170c727a42SFabio Estevam if (retval) { 2118e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21190c727a42SFabio Estevam goto error_console; 21200c727a42SFabio Estevam } 21210c727a42SFabio Estevam 2122e67c139cSFugang Duan retval = clk_prepare_enable(sport->clk_per); 21230c727a42SFabio Estevam if (retval) 2124e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21251cf93e0dSHuang Shijie 21261cf93e0dSHuang Shijie error_console: 21271cf93e0dSHuang Shijie return retval; 2128ab4382d2SGreg Kroah-Hartman } 2129ab4382d2SGreg Kroah-Hartman 21309768a37cSFrancesco Dolcini static int 21319768a37cSFrancesco Dolcini imx_uart_console_exit(struct console *co) 21329768a37cSFrancesco Dolcini { 21339768a37cSFrancesco Dolcini struct imx_port *sport = imx_uart_ports[co->index]; 21349768a37cSFrancesco Dolcini 21359768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_per); 21369768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_ipg); 21379768a37cSFrancesco Dolcini 21389768a37cSFrancesco Dolcini return 0; 21399768a37cSFrancesco Dolcini } 21409768a37cSFrancesco Dolcini 21419d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 21429d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2143ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 21449d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2145ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 21469d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 21479768a37cSFrancesco Dolcini .exit = imx_uart_console_exit, 2148ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2149ab4382d2SGreg Kroah-Hartman .index = -1, 21509d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2151ab4382d2SGreg Kroah-Hartman }; 2152ab4382d2SGreg Kroah-Hartman 21539d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2154913c6c0eSLucas Stach 2155ab4382d2SGreg Kroah-Hartman #else 2156ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2157ab4382d2SGreg Kroah-Hartman #endif 2158ab4382d2SGreg Kroah-Hartman 21599d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2160ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2161ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2162ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2163ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2164ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21659d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2166ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2167ab4382d2SGreg Kroah-Hartman }; 2168ab4382d2SGreg Kroah-Hartman 2169bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2170cb1a6092SUwe Kleine-König { 2171bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2172cb1a6092SUwe Kleine-König unsigned long flags; 2173cb1a6092SUwe Kleine-König 2174cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2175cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS) 2176cb1a6092SUwe Kleine-König imx_uart_start_tx(&sport->port); 2177cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2178bd78ecd6SAhmad Fatoum 2179bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2180cb1a6092SUwe Kleine-König } 2181cb1a6092SUwe Kleine-König 2182bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2183cb1a6092SUwe Kleine-König { 2184bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2185cb1a6092SUwe Kleine-König unsigned long flags; 2186cb1a6092SUwe Kleine-König 2187cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2188cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_SEND) 2189cb1a6092SUwe Kleine-König imx_uart_stop_tx(&sport->port); 2190cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2191bd78ecd6SAhmad Fatoum 2192bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2193cb1a6092SUwe Kleine-König } 2194cb1a6092SUwe Kleine-König 2195db0a196bSFabien Lahoudere /* Default RX DMA buffer configuration */ 2196db0a196bSFabien Lahoudere #define RX_DMA_PERIODS 16 2197db0a196bSFabien Lahoudere #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4) 2198db0a196bSFabien Lahoudere 21999d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2200ab4382d2SGreg Kroah-Hartman { 22014661f46eSFabio Estevam struct device_node *np = pdev->dev.of_node; 2202ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2203ab4382d2SGreg Kroah-Hartman void __iomem *base; 2204db0a196bSFabien Lahoudere u32 dma_buf_conf[2]; 22054444dcf1SUwe Kleine-König int ret = 0; 22064444dcf1SUwe Kleine-König u32 ucr1; 2207ab4382d2SGreg Kroah-Hartman struct resource *res; 2208842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2209ab4382d2SGreg Kroah-Hartman 221042d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2211ab4382d2SGreg Kroah-Hartman if (!sport) 2212ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2213ab4382d2SGreg Kroah-Hartman 22144661f46eSFabio Estevam sport->devdata = of_device_get_match_data(&pdev->dev); 22154661f46eSFabio Estevam 22164661f46eSFabio Estevam ret = of_alias_get_id(np, "serial"); 22174661f46eSFabio Estevam if (ret < 0) { 22184661f46eSFabio Estevam dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 221942d34191SSachin Kamat return ret; 22204661f46eSFabio Estevam } 22214661f46eSFabio Estevam sport->port.line = ret; 22224661f46eSFabio Estevam 22234661f46eSFabio Estevam if (of_get_property(np, "uart-has-rtscts", NULL) || 22244661f46eSFabio Estevam of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 22254661f46eSFabio Estevam sport->have_rtscts = 1; 22264661f46eSFabio Estevam 22274661f46eSFabio Estevam if (of_get_property(np, "fsl,dte-mode", NULL)) 22284661f46eSFabio Estevam sport->dte_mode = 1; 22294661f46eSFabio Estevam 22304661f46eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 22314661f46eSFabio Estevam sport->have_rtsgpio = 1; 22324661f46eSFabio Estevam 22334661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-tx", NULL)) 22344661f46eSFabio Estevam sport->inverted_tx = 1; 22354661f46eSFabio Estevam 22364661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-rx", NULL)) 22374661f46eSFabio Estevam sport->inverted_rx = 1; 223822698aa2SShawn Guo 2239db0a196bSFabien Lahoudere if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { 2240db0a196bSFabien Lahoudere sport->rx_period_length = dma_buf_conf[0]; 2241db0a196bSFabien Lahoudere sport->rx_periods = dma_buf_conf[1]; 2242db0a196bSFabien Lahoudere } else { 2243db0a196bSFabien Lahoudere sport->rx_period_length = RX_DMA_PERIOD_LEN; 2244db0a196bSFabien Lahoudere sport->rx_periods = RX_DMA_PERIODS; 2245db0a196bSFabien Lahoudere } 2246db0a196bSFabien Lahoudere 22479d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 224856734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 224956734448SGeert Uytterhoeven sport->port.line); 225056734448SGeert Uytterhoeven return -EINVAL; 225156734448SGeert Uytterhoeven } 225256734448SGeert Uytterhoeven 2253ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2254da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2255da82f997SAlexander Shiyan if (IS_ERR(base)) 2256da82f997SAlexander Shiyan return PTR_ERR(base); 2257ab4382d2SGreg Kroah-Hartman 2258842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2259aa49d8e8SAnson Huang if (rxirq < 0) 2260aa49d8e8SAnson Huang return rxirq; 226131a8d8faSAnson Huang txirq = platform_get_irq_optional(pdev, 1); 226231a8d8faSAnson Huang rtsirq = platform_get_irq_optional(pdev, 2); 2263842633bdSUwe Kleine-König 2264ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2265ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2266ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 22675b109564SZheng Yongjun sport->port.type = PORT_IMX; 2268ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2269842633bdSUwe Kleine-König sport->port.irq = rxirq; 2270ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2271aa3479d2SDmitry Safonov sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 22729d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 22739d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 2274ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 22759d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2276ab4382d2SGreg Kroah-Hartman 227758362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 227858362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 227958362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 228058362d5bSUwe Kleine-König 22813a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 22823a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 22833a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2284833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 228542d34191SSachin Kamat return ret; 2286ab4382d2SGreg Kroah-Hartman } 2287ab4382d2SGreg Kroah-Hartman 22883a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 22893a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 22903a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2291833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 229242d34191SSachin Kamat return ret; 22933a9465faSSascha Hauer } 22943a9465faSSascha Hauer 22953a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2296ab4382d2SGreg Kroah-Hartman 22978a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 22988a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 22991e512d45SUwe Kleine-König if (ret) { 23001e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 23018a61f0c7SFabio Estevam return ret; 23021e512d45SUwe Kleine-König } 23038a61f0c7SFabio Estevam 23043a0ab62fSUwe Kleine-König /* initialize shadow register values */ 23053a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 23063a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 23073a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 23083a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 23093a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 23103a0ab62fSUwe Kleine-König 2311c150c0f3SLukas Wunner ret = uart_get_rs485_mode(&sport->port); 2312c150c0f3SLukas Wunner if (ret) { 2313c150c0f3SLukas Wunner clk_disable_unprepare(sport->clk_ipg); 2314c150c0f3SLukas Wunner return ret; 2315c150c0f3SLukas Wunner } 2316743f93f8SLukas Wunner 2317b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23185d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2319b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2320b8f3bff0SLukas Wunner 23216d215f83SStefan Agner /* 23226d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 23236d215f83SStefan Agner * signal cannot be set low during transmission in case the 23246d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 23256d215f83SStefan Agner */ 23266d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23276d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 23286d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 23296d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 23306d215f83SStefan Agner dev_err(&pdev->dev, 23316d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 23326d215f83SStefan Agner 23339d1a50a2SUwe Kleine-König imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2334b8f3bff0SLukas Wunner 23358a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 23364444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 23375f0e708cSYe Bin ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 23384444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 23398a61f0c7SFabio Estevam 23409d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2341e61c38d8SUwe Kleine-König /* 2342e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2343e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2344e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2345e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2346e61c38d8SUwe Kleine-König */ 23474444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23484444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 23494444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2350e61c38d8SUwe Kleine-König 2351e61c38d8SUwe Kleine-König /* 2352e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2353e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2354e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2355e61c38d8SUwe Kleine-König */ 235627c84426SUwe Kleine-König imx_uart_writel(sport, 235727c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 235827c84426SUwe Kleine-König UCR3); 2359e61c38d8SUwe Kleine-König 2360e61c38d8SUwe Kleine-König } else { 23614444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 23624444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23634444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 23644444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 23656df765dcSUwe Kleine-König 23669d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 23676df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 236827c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2369e61c38d8SUwe Kleine-König } 2370e61c38d8SUwe Kleine-König 23718a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 23728a61f0c7SFabio Estevam 2373bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2374bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2375bd78ecd6SAhmad Fatoum sport->trigger_start_tx.function = imx_trigger_start_tx; 2376bd78ecd6SAhmad Fatoum sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2377cb1a6092SUwe Kleine-König 2378c0d1c6b0SFabio Estevam /* 2379c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2380c0d1c6b0SFabio Estevam * chips only have one interrupt. 2381c0d1c6b0SFabio Estevam */ 2382842633bdSUwe Kleine-König if (txirq > 0) { 23839d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2384c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23851e512d45SUwe Kleine-König if (ret) { 23861e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 23871e512d45SUwe Kleine-König ret); 2388c0d1c6b0SFabio Estevam return ret; 23891e512d45SUwe Kleine-König } 2390c0d1c6b0SFabio Estevam 23919d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2392c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23931e512d45SUwe Kleine-König if (ret) { 23941e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 23951e512d45SUwe Kleine-König ret); 2396c0d1c6b0SFabio Estevam return ret; 23971e512d45SUwe Kleine-König } 23987e620984SUwe Kleine-König 23997e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 24007e620984SUwe Kleine-König dev_name(&pdev->dev), sport); 24017e620984SUwe Kleine-König if (ret) { 24027e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n", 24037e620984SUwe Kleine-König ret); 24047e620984SUwe Kleine-König return ret; 24057e620984SUwe Kleine-König } 2406c0d1c6b0SFabio Estevam } else { 24079d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2408c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24091e512d45SUwe Kleine-König if (ret) { 24101e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2411c0d1c6b0SFabio Estevam return ret; 2412c0d1c6b0SFabio Estevam } 24131e512d45SUwe Kleine-König } 2414c0d1c6b0SFabio Estevam 24159d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2416ab4382d2SGreg Kroah-Hartman 24170a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2418ab4382d2SGreg Kroah-Hartman 24199d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2420ab4382d2SGreg Kroah-Hartman } 2421ab4382d2SGreg Kroah-Hartman 24229d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2423ab4382d2SGreg Kroah-Hartman { 2424ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2425ab4382d2SGreg Kroah-Hartman 24269d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2427ab4382d2SGreg Kroah-Hartman } 2428ab4382d2SGreg Kroah-Hartman 24299d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2430c868cbb7SEduardo Valentin { 243107b5e16eSAnson Huang unsigned long flags; 243207b5e16eSAnson Huang 243307b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 243407b5e16eSAnson Huang if (!sport->context_saved) { 243507b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2436c868cbb7SEduardo Valentin return; 243707b5e16eSAnson Huang } 2438c868cbb7SEduardo Valentin 243927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 244027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 244127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 244227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 244327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 244427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 244527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 244627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 244727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 244827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2449c868cbb7SEduardo Valentin sport->context_saved = false; 245007b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2451c868cbb7SEduardo Valentin } 2452c868cbb7SEduardo Valentin 24539d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2454c868cbb7SEduardo Valentin { 245507b5e16eSAnson Huang unsigned long flags; 245607b5e16eSAnson Huang 2457c868cbb7SEduardo Valentin /* Save necessary regs */ 245807b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 245927c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 246027c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 246127c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 246227c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 246327c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 246427c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 246527c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 246627c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 246727c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 246827c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2469c868cbb7SEduardo Valentin sport->context_saved = true; 247007b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2471c868cbb7SEduardo Valentin } 2472c868cbb7SEduardo Valentin 24739d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2474189550b8SEduardo Valentin { 24754444dcf1SUwe Kleine-König u32 ucr3; 2476189550b8SEduardo Valentin 24774444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 247809df0b34SMartin Kaiser if (on) { 247927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 24804444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 24814444dcf1SUwe Kleine-König } else { 24824444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 248309df0b34SMartin Kaiser } 24844444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2485bc85734bSEduardo Valentin 248638b1f0fbSFabio Estevam if (sport->have_rtscts) { 24874444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2488c67643b4SFugang Duan if (on) { 2489c67643b4SFugang Duan imx_uart_writel(sport, USR1_RTSD, USR1); 24904444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2491c67643b4SFugang Duan } else { 24924444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 2493c67643b4SFugang Duan } 24944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2495189550b8SEduardo Valentin } 249638b1f0fbSFabio Estevam } 2497189550b8SEduardo Valentin 24989d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 249990bb6bd3SShenwei Wang { 2500a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 250190bb6bd3SShenwei Wang 25029d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 250390bb6bd3SShenwei Wang 250490bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 250590bb6bd3SShenwei Wang 2506fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev); 2507fcfed1beSAnson Huang 250890bb6bd3SShenwei Wang return 0; 250990bb6bd3SShenwei Wang } 251090bb6bd3SShenwei Wang 25119d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 251290bb6bd3SShenwei Wang { 2513a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 251490bb6bd3SShenwei Wang int ret; 251590bb6bd3SShenwei Wang 2516fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev); 2517fcfed1beSAnson Huang 251890bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 251990bb6bd3SShenwei Wang if (ret) 252090bb6bd3SShenwei Wang return ret; 252190bb6bd3SShenwei Wang 25229d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 252390bb6bd3SShenwei Wang 252490bb6bd3SShenwei Wang return 0; 252590bb6bd3SShenwei Wang } 252690bb6bd3SShenwei Wang 25279d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 252890bb6bd3SShenwei Wang { 2529a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 253009df0b34SMartin Kaiser int ret; 253190bb6bd3SShenwei Wang 25329d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 253381b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 253490bb6bd3SShenwei Wang 253509df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 253609df0b34SMartin Kaiser if (ret) 253709df0b34SMartin Kaiser return ret; 253809df0b34SMartin Kaiser 253909df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 25409d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 254109df0b34SMartin Kaiser 254209df0b34SMartin Kaiser return 0; 254390bb6bd3SShenwei Wang } 254490bb6bd3SShenwei Wang 25459d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 254690bb6bd3SShenwei Wang { 2547a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 254890bb6bd3SShenwei Wang 254990bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 25509d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 255190bb6bd3SShenwei Wang 25529d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 255381b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 255490bb6bd3SShenwei Wang 255509df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 255629add68dSMartin Fuzzey 255790bb6bd3SShenwei Wang return 0; 255890bb6bd3SShenwei Wang } 255990bb6bd3SShenwei Wang 25609d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 256194be6d74SPhilipp Zabel { 2562a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 256394be6d74SPhilipp Zabel 25649d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 256594be6d74SPhilipp Zabel 256609df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 256794be6d74SPhilipp Zabel } 256894be6d74SPhilipp Zabel 25699d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 257094be6d74SPhilipp Zabel { 2571a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 257294be6d74SPhilipp Zabel 25739d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 257494be6d74SPhilipp Zabel 257509df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 257694be6d74SPhilipp Zabel 257794be6d74SPhilipp Zabel return 0; 257894be6d74SPhilipp Zabel } 257994be6d74SPhilipp Zabel 25809d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 25819d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 25829d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 25839d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 25849d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 25859d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 25869d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 25879d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 25889d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 25899d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 259090bb6bd3SShenwei Wang }; 259190bb6bd3SShenwei Wang 25929d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 25939d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 25949d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2595ab4382d2SGreg Kroah-Hartman 2596ab4382d2SGreg Kroah-Hartman .driver = { 2597ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 259822698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 25999d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2600ab4382d2SGreg Kroah-Hartman }, 2601ab4382d2SGreg Kroah-Hartman }; 2602ab4382d2SGreg Kroah-Hartman 26039d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2604ab4382d2SGreg Kroah-Hartman { 26059d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2606ab4382d2SGreg Kroah-Hartman 2607ab4382d2SGreg Kroah-Hartman if (ret) 2608ab4382d2SGreg Kroah-Hartman return ret; 2609ab4382d2SGreg Kroah-Hartman 26109d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2611ab4382d2SGreg Kroah-Hartman if (ret != 0) 26129d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2613ab4382d2SGreg Kroah-Hartman 2614f227824eSUwe Kleine-König return ret; 2615ab4382d2SGreg Kroah-Hartman } 2616ab4382d2SGreg Kroah-Hartman 26179d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2618ab4382d2SGreg Kroah-Hartman { 26199d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 26209d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2621ab4382d2SGreg Kroah-Hartman } 2622ab4382d2SGreg Kroah-Hartman 26239d1a50a2SUwe Kleine-König module_init(imx_uart_init); 26249d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2625ab4382d2SGreg Kroah-Hartman 2626ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2627ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2628ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2629ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2630