1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 13ab4382d2SGreg Kroah-Hartman #endif 14ab4382d2SGreg Kroah-Hartman 15ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 23ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 24ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2922698aa2SShawn Guo #include <linux/of.h> 3022698aa2SShawn Guo #include <linux/of_device.h> 31e32a9f8fSSachin Kamat #include <linux/io.h> 32b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 3582906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 36b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 37ab4382d2SGreg Kroah-Hartman 3858362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3958362d5bSUwe Kleine-König 40ab4382d2SGreg Kroah-Hartman /* Register definitions */ 41ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 42ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 43ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 44ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 45ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 46ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 47ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 48ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 49ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 50ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 51ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 52ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 53ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 54ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 55fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 56fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 57fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 58ab4382d2SGreg Kroah-Hartman 59ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6055d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 61ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 62ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 63ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 64ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 65ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 66ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6726c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6825985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 69ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 71ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 72b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 74302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 77ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 79302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 80fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 81b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9401f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 101ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 104b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 105ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10827e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 109fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 115ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 118b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1257be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 126ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 127ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 128ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 129ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 130ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 131ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 133ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 134ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13686a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13727e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 138ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 142ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 143ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14590ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14690ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14990ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 150ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 151ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 152ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 153ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 154ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 155ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 156ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 157ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 158ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 159ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 160ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 161ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 162ab4382d2SGreg Kroah-Hartman 163ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 164ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 165ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 166ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 167ab4382d2SGreg Kroah-Hartman 168ab4382d2SGreg Kroah-Hartman /* 169ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 170ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 171ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 172ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 173ab4382d2SGreg Kroah-Hartman */ 174ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 175ab4382d2SGreg Kroah-Hartman 176ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 177ab4382d2SGreg Kroah-Hartman 178ab4382d2SGreg Kroah-Hartman #define UART_NR 8 179ab4382d2SGreg Kroah-Hartman 180f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 181fe6b540aSShawn Guo enum imx_uart_type { 182fe6b540aSShawn Guo IMX1_UART, 183fe6b540aSShawn Guo IMX21_UART, 1841c06bde6SMartyn Welch IMX53_UART, 185a496e628SHuang Shijie IMX6Q_UART, 186fe6b540aSShawn Guo }; 187fe6b540aSShawn Guo 188fe6b540aSShawn Guo /* device type dependent stuff */ 189fe6b540aSShawn Guo struct imx_uart_data { 190fe6b540aSShawn Guo unsigned uts_reg; 191fe6b540aSShawn Guo enum imx_uart_type devtype; 192fe6b540aSShawn Guo }; 193fe6b540aSShawn Guo 194ab4382d2SGreg Kroah-Hartman struct imx_port { 195ab4382d2SGreg Kroah-Hartman struct uart_port port; 196ab4382d2SGreg Kroah-Hartman struct timer_list timer; 197ab4382d2SGreg Kroah-Hartman unsigned int old_status; 198ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 1997b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20020ff2fe6SHuang Shijie unsigned int dte_mode:1; 2013a9465faSSascha Hauer struct clk *clk_ipg; 2023a9465faSSascha Hauer struct clk *clk_per; 2037d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 204b4cdc8f6SHuang Shijie 20558362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 20658362d5bSUwe Kleine-König 2073a0ab62fSUwe Kleine-König /* shadow registers */ 2083a0ab62fSUwe Kleine-König unsigned int ucr1; 2093a0ab62fSUwe Kleine-König unsigned int ucr2; 2103a0ab62fSUwe Kleine-König unsigned int ucr3; 2113a0ab62fSUwe Kleine-König unsigned int ucr4; 2123a0ab62fSUwe Kleine-König unsigned int ufcr; 2133a0ab62fSUwe Kleine-König 214b4cdc8f6SHuang Shijie /* DMA fields */ 215b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 216b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 217b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 218b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 219b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 220b4cdc8f6SHuang Shijie void *rx_buf; 2219d297239SNandor Han struct circ_buf rx_ring; 2229d297239SNandor Han unsigned int rx_periods; 2239d297239SNandor Han dma_cookie_t rx_cookie; 2247cb92fd2SHuang Shijie unsigned int tx_bytes; 225b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 22690bb6bd3SShenwei Wang unsigned int saved_reg[10]; 227c868cbb7SEduardo Valentin bool context_saved; 228ab4382d2SGreg Kroah-Hartman }; 229ab4382d2SGreg Kroah-Hartman 2300ad5a814SDirk Behme struct imx_port_ucrs { 2310ad5a814SDirk Behme unsigned int ucr1; 2320ad5a814SDirk Behme unsigned int ucr2; 2330ad5a814SDirk Behme unsigned int ucr3; 2340ad5a814SDirk Behme }; 2350ad5a814SDirk Behme 236fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 237fe6b540aSShawn Guo [IMX1_UART] = { 238fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 239fe6b540aSShawn Guo .devtype = IMX1_UART, 240fe6b540aSShawn Guo }, 241fe6b540aSShawn Guo [IMX21_UART] = { 242fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 243fe6b540aSShawn Guo .devtype = IMX21_UART, 244fe6b540aSShawn Guo }, 2451c06bde6SMartyn Welch [IMX53_UART] = { 2461c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2471c06bde6SMartyn Welch .devtype = IMX53_UART, 2481c06bde6SMartyn Welch }, 249a496e628SHuang Shijie [IMX6Q_UART] = { 250a496e628SHuang Shijie .uts_reg = IMX21_UTS, 251a496e628SHuang Shijie .devtype = IMX6Q_UART, 252a496e628SHuang Shijie }, 253fe6b540aSShawn Guo }; 254fe6b540aSShawn Guo 25531ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 256fe6b540aSShawn Guo { 257fe6b540aSShawn Guo .name = "imx1-uart", 258fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 259fe6b540aSShawn Guo }, { 260fe6b540aSShawn Guo .name = "imx21-uart", 261fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 262fe6b540aSShawn Guo }, { 2631c06bde6SMartyn Welch .name = "imx53-uart", 2641c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2651c06bde6SMartyn Welch }, { 266a496e628SHuang Shijie .name = "imx6q-uart", 267a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 268a496e628SHuang Shijie }, { 269fe6b540aSShawn Guo /* sentinel */ 270fe6b540aSShawn Guo } 271fe6b540aSShawn Guo }; 272fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 273fe6b540aSShawn Guo 274ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 275a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2761c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27722698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27822698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27922698aa2SShawn Guo { /* sentinel */ } 28022698aa2SShawn Guo }; 28122698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28222698aa2SShawn Guo 28327c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 28427c84426SUwe Kleine-König { 2853a0ab62fSUwe Kleine-König switch (offset) { 2863a0ab62fSUwe Kleine-König case UCR1: 2873a0ab62fSUwe Kleine-König sport->ucr1 = val; 2883a0ab62fSUwe Kleine-König break; 2893a0ab62fSUwe Kleine-König case UCR2: 2903a0ab62fSUwe Kleine-König sport->ucr2 = val; 2913a0ab62fSUwe Kleine-König break; 2923a0ab62fSUwe Kleine-König case UCR3: 2933a0ab62fSUwe Kleine-König sport->ucr3 = val; 2943a0ab62fSUwe Kleine-König break; 2953a0ab62fSUwe Kleine-König case UCR4: 2963a0ab62fSUwe Kleine-König sport->ucr4 = val; 2973a0ab62fSUwe Kleine-König break; 2983a0ab62fSUwe Kleine-König case UFCR: 2993a0ab62fSUwe Kleine-König sport->ufcr = val; 3003a0ab62fSUwe Kleine-König break; 3013a0ab62fSUwe Kleine-König default: 3023a0ab62fSUwe Kleine-König break; 3033a0ab62fSUwe Kleine-König } 30427c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 30527c84426SUwe Kleine-König } 30627c84426SUwe Kleine-König 30727c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30827c84426SUwe Kleine-König { 3093a0ab62fSUwe Kleine-König switch (offset) { 3103a0ab62fSUwe Kleine-König case UCR1: 3113a0ab62fSUwe Kleine-König return sport->ucr1; 3123a0ab62fSUwe Kleine-König break; 3133a0ab62fSUwe Kleine-König case UCR2: 3143a0ab62fSUwe Kleine-König /* 3153a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3163a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 317728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 318728e74a4SUwe Kleine-König * conditionally. 3193a0ab62fSUwe Kleine-König */ 3200aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3213a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3223a0ab62fSUwe Kleine-König return sport->ucr2; 3233a0ab62fSUwe Kleine-König break; 3243a0ab62fSUwe Kleine-König case UCR3: 3253a0ab62fSUwe Kleine-König return sport->ucr3; 3263a0ab62fSUwe Kleine-König break; 3273a0ab62fSUwe Kleine-König case UCR4: 3283a0ab62fSUwe Kleine-König return sport->ucr4; 3293a0ab62fSUwe Kleine-König break; 3303a0ab62fSUwe Kleine-König case UFCR: 3313a0ab62fSUwe Kleine-König return sport->ufcr; 3323a0ab62fSUwe Kleine-König break; 3333a0ab62fSUwe Kleine-König default: 33427c84426SUwe Kleine-König return readl(sport->port.membase + offset); 33527c84426SUwe Kleine-König } 3363a0ab62fSUwe Kleine-König } 33727c84426SUwe Kleine-König 3389d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 339fe6b540aSShawn Guo { 340fe6b540aSShawn Guo return sport->devdata->uts_reg; 341fe6b540aSShawn Guo } 342fe6b540aSShawn Guo 3439d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 344fe6b540aSShawn Guo { 345fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 346fe6b540aSShawn Guo } 347fe6b540aSShawn Guo 3489d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 349fe6b540aSShawn Guo { 350fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 351fe6b540aSShawn Guo } 352fe6b540aSShawn Guo 3539d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3541c06bde6SMartyn Welch { 3551c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3561c06bde6SMartyn Welch } 3571c06bde6SMartyn Welch 3589d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 359a496e628SHuang Shijie { 360a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 361a496e628SHuang Shijie } 362ab4382d2SGreg Kroah-Hartman /* 36344a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 36444a75411Sfabio.estevam@freescale.com */ 36593d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 3669d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 36744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36844a75411Sfabio.estevam@freescale.com { 36944a75411Sfabio.estevam@freescale.com /* save control registers */ 37027c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 37127c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 37227c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 37344a75411Sfabio.estevam@freescale.com } 37444a75411Sfabio.estevam@freescale.com 3759d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 37644a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37744a75411Sfabio.estevam@freescale.com { 37844a75411Sfabio.estevam@freescale.com /* restore control registers */ 37927c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 38027c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 38127c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 38244a75411Sfabio.estevam@freescale.com } 383e8bfa760SFabio Estevam #endif 38444a75411Sfabio.estevam@freescale.com 3859d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 38658362d5bSUwe Kleine-König { 387bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38858362d5bSUwe Kleine-König 389a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 390a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39158362d5bSUwe Kleine-König } 39258362d5bSUwe Kleine-König 3939d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 39458362d5bSUwe Kleine-König { 395bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 396bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39758362d5bSUwe Kleine-König 398a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 399a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 40058362d5bSUwe Kleine-König } 40158362d5bSUwe Kleine-König 4029d1a50a2SUwe Kleine-König static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2) 40358362d5bSUwe Kleine-König { 40458362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 40558362d5bSUwe Kleine-König } 40658362d5bSUwe Kleine-König 4076aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4089d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 40976821e22SUwe Kleine-König { 41076821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 41176821e22SUwe Kleine-König unsigned int ucr1, ucr2; 41276821e22SUwe Kleine-König 41376821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 41476821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 41576821e22SUwe Kleine-König 41676821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41776821e22SUwe Kleine-König 41876821e22SUwe Kleine-König if (sport->dma_is_enabled) { 41976821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 42076821e22SUwe Kleine-König } else { 42176821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 42281ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 42376821e22SUwe Kleine-König } 42476821e22SUwe Kleine-König 42576821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 42676821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42776821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42876821e22SUwe Kleine-König } 42976821e22SUwe Kleine-König 43076821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4319d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 432ab4382d2SGreg Kroah-Hartman { 433ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4344444dcf1SUwe Kleine-König u32 ucr1; 435ab4382d2SGreg Kroah-Hartman 4369ce4f8f3SGreg Kroah-Hartman /* 4379ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4389ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4399ce4f8f3SGreg Kroah-Hartman */ 440686351f3SUwe Kleine-König if (sport->dma_is_txing) 4419ce4f8f3SGreg Kroah-Hartman return; 442b4cdc8f6SHuang Shijie 4434444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 4444444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1); 44517b8f2a3SUwe Kleine-König 44617b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 44717b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 44827c84426SUwe Kleine-König imx_uart_readl(sport, USR2) & USR2_TXDC) { 4494444dcf1SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 45017b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4519d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4521a613626SFabio Estevam else 4539d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4544444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 45517b8f2a3SUwe Kleine-König 4569d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 45776821e22SUwe Kleine-König 4584444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 4594444dcf1SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 4604444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 46117b8f2a3SUwe Kleine-König } 462ab4382d2SGreg Kroah-Hartman } 463ab4382d2SGreg Kroah-Hartman 4646aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4659d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 466ab4382d2SGreg Kroah-Hartman { 467ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4684444dcf1SUwe Kleine-König u32 ucr1, ucr2; 469ab4382d2SGreg Kroah-Hartman 4704444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 47176821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 47276821e22SUwe Kleine-König 47376821e22SUwe Kleine-König if (sport->dma_is_enabled) { 47476821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 47576821e22SUwe Kleine-König } else { 47676821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 47781ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 47876821e22SUwe Kleine-König } 47976821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 48076821e22SUwe Kleine-König 48176821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 48276821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 483ab4382d2SGreg Kroah-Hartman } 484ab4382d2SGreg Kroah-Hartman 4856aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4869d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 487ab4382d2SGreg Kroah-Hartman { 488ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 489ab4382d2SGreg Kroah-Hartman 490ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 49158362d5bSUwe Kleine-König 49258362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 493ab4382d2SGreg Kroah-Hartman } 494ab4382d2SGreg Kroah-Hartman 4959d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 4966aed2a88SUwe Kleine-König 4976aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4989d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 499ab4382d2SGreg Kroah-Hartman { 500ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 501ab4382d2SGreg Kroah-Hartman 5025e42e9a3SPeter Hurley if (sport->port.x_char) { 5035e42e9a3SPeter Hurley /* Send next char */ 50427c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5057e2fb5aaSJiada Wang sport->port.icount.tx++; 5067e2fb5aaSJiada Wang sport->port.x_char = 0; 5075e42e9a3SPeter Hurley return; 5085e42e9a3SPeter Hurley } 5095e42e9a3SPeter Hurley 5105e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5119d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5125e42e9a3SPeter Hurley return; 5135e42e9a3SPeter Hurley } 5145e42e9a3SPeter Hurley 51591a1a909SJiada Wang if (sport->dma_is_enabled) { 5164444dcf1SUwe Kleine-König u32 ucr1; 51791a1a909SJiada Wang /* 51891a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 51991a1a909SJiada Wang * and the TX IRQ is disabled. 52091a1a909SJiada Wang **/ 5214444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5224444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXMPTYEN; 52391a1a909SJiada Wang if (sport->dma_is_txing) { 5244444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5254444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 52691a1a909SJiada Wang } else { 5274444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5289d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 52991a1a909SJiada Wang } 53091a1a909SJiada Wang 5315aabd3b0SIan Jamison return; 5320c549223SUwe Kleine-König } 5335aabd3b0SIan Jamison 5345aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5359d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 536ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 537ab4382d2SGreg Kroah-Hartman * out the port here */ 53827c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 539ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 540ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 541ab4382d2SGreg Kroah-Hartman } 542ab4382d2SGreg Kroah-Hartman 543ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 544ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 545ab4382d2SGreg Kroah-Hartman 546ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5479d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 548ab4382d2SGreg Kroah-Hartman } 549ab4382d2SGreg Kroah-Hartman 5509d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 551b4cdc8f6SHuang Shijie { 552b4cdc8f6SHuang Shijie struct imx_port *sport = data; 553b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 554b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 555b4cdc8f6SHuang Shijie unsigned long flags; 5564444dcf1SUwe Kleine-König u32 ucr1; 557b4cdc8f6SHuang Shijie 55842f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 55942f752b3SDirk Behme 560b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 561b4cdc8f6SHuang Shijie 5624444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5634444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5644444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 565a2c718ceSDirk Behme 56642f752b3SDirk Behme /* update the stat */ 56742f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 56842f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 56942f752b3SDirk Behme 57042f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 57142f752b3SDirk Behme 572b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 573b4cdc8f6SHuang Shijie 574d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 575b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5769ce4f8f3SGreg Kroah-Hartman 5770bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5789d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 57918665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 58018665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 58118665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 58218665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 58318665414SUwe Kleine-König } 58464432a85SUwe Kleine-König 5850bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 586b4cdc8f6SHuang Shijie } 587b4cdc8f6SHuang Shijie 5886aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5899d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 590b4cdc8f6SHuang Shijie { 591b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 592b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 593b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 594b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 595b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 59618665414SUwe Kleine-König u32 ucr1, ucr4; 597b4cdc8f6SHuang Shijie int ret; 598b4cdc8f6SHuang Shijie 59942f752b3SDirk Behme if (sport->dma_is_txing) 600b4cdc8f6SHuang Shijie return; 601b4cdc8f6SHuang Shijie 60218665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 60318665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 60418665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 60518665414SUwe Kleine-König 606b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 607b4cdc8f6SHuang Shijie 6087942f857SDirk Behme if (xmit->tail < xmit->head) { 6097942f857SDirk Behme sport->dma_tx_nents = 1; 6107942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6117942f857SDirk Behme } else { 612b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 613b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 614b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 615b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 616b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 617b4cdc8f6SHuang Shijie } 618b4cdc8f6SHuang Shijie 619b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 620b4cdc8f6SHuang Shijie if (ret == 0) { 621b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 622b4cdc8f6SHuang Shijie return; 623b4cdc8f6SHuang Shijie } 624b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 625b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 626b4cdc8f6SHuang Shijie if (!desc) { 62724649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 62824649821SDirk Behme DMA_TO_DEVICE); 629b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 630b4cdc8f6SHuang Shijie return; 631b4cdc8f6SHuang Shijie } 6329d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 633b4cdc8f6SHuang Shijie desc->callback_param = sport; 634b4cdc8f6SHuang Shijie 635b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 636b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 637a2c718ceSDirk Behme 6384444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6394444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6404444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 641a2c718ceSDirk Behme 642b4cdc8f6SHuang Shijie /* fire it */ 643b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 644b4cdc8f6SHuang Shijie dmaengine_submit(desc); 645b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 646b4cdc8f6SHuang Shijie return; 647b4cdc8f6SHuang Shijie } 648b4cdc8f6SHuang Shijie 6496aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6509d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 651ab4382d2SGreg Kroah-Hartman { 652ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6534444dcf1SUwe Kleine-König u32 ucr1; 654ab4382d2SGreg Kroah-Hartman 65548669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 65648669b69SUwe Kleine-König return; 65748669b69SUwe Kleine-König 65817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 65918665414SUwe Kleine-König u32 ucr2; 6604444dcf1SUwe Kleine-König 6614444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 66217b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6639d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 6641a613626SFabio Estevam else 6659d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 6664444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 66717b8f2a3SUwe Kleine-König 66876821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 6699d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 67076821e22SUwe Kleine-König 67118665414SUwe Kleine-König /* 67218665414SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA is off. 67318665414SUwe Kleine-König * In the DMA case this is done in the tx-callback. 67418665414SUwe Kleine-König */ 67518665414SUwe Kleine-König if (!sport->dma_is_enabled) { 67618665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 6774444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 6784444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 67917b8f2a3SUwe Kleine-König } 68018665414SUwe Kleine-König } 68117b8f2a3SUwe Kleine-König 682b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 6834444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6844444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1); 685b4cdc8f6SHuang Shijie } 686ab4382d2SGreg Kroah-Hartman 687b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 68891a1a909SJiada Wang if (sport->port.x_char) { 68991a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 69091a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 6914444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6924444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 6934444dcf1SUwe Kleine-König ucr1 |= UCR1_TXMPTYEN; 6944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 69591a1a909SJiada Wang return; 69691a1a909SJiada Wang } 69791a1a909SJiada Wang 6985e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6995e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7009d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 701b4cdc8f6SHuang Shijie return; 702b4cdc8f6SHuang Shijie } 703ab4382d2SGreg Kroah-Hartman } 704ab4382d2SGreg Kroah-Hartman 7059d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 706ab4382d2SGreg Kroah-Hartman { 707ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7084444dcf1SUwe Kleine-König u32 usr1; 709ab4382d2SGreg Kroah-Hartman unsigned long flags; 710ab4382d2SGreg Kroah-Hartman 711ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 712ab4382d2SGreg Kroah-Hartman 71327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7144444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7154444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 716ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 717ab4382d2SGreg Kroah-Hartman 718ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 719ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 720ab4382d2SGreg Kroah-Hartman } 721ab4382d2SGreg Kroah-Hartman 7229d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 723ab4382d2SGreg Kroah-Hartman { 724ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 725ab4382d2SGreg Kroah-Hartman unsigned long flags; 726ab4382d2SGreg Kroah-Hartman 727ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 7289d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 729ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 730ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 731ab4382d2SGreg Kroah-Hartman } 732ab4382d2SGreg Kroah-Hartman 7339d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 734ab4382d2SGreg Kroah-Hartman { 735ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 736ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 73792a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 7384444dcf1SUwe Kleine-König unsigned long flags; 739ab4382d2SGreg Kroah-Hartman 740ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 741ab4382d2SGreg Kroah-Hartman 74227c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 7434444dcf1SUwe Kleine-König u32 usr2; 7444444dcf1SUwe Kleine-König 745ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 746ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 747ab4382d2SGreg Kroah-Hartman 74827c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 749ab4382d2SGreg Kroah-Hartman 7504444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 7514444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 75227c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 753ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 754ab4382d2SGreg Kroah-Hartman continue; 755ab4382d2SGreg Kroah-Hartman } 756ab4382d2SGreg Kroah-Hartman 757ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 758ab4382d2SGreg Kroah-Hartman continue; 759ab4382d2SGreg Kroah-Hartman 760019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 761019dc9eaSHui Wang if (rx & URXD_BRK) 762019dc9eaSHui Wang sport->port.icount.brk++; 763019dc9eaSHui Wang else if (rx & URXD_PRERR) 764ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 765ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 766ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 767ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 768ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 769ab4382d2SGreg Kroah-Hartman 770ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 771ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 772ab4382d2SGreg Kroah-Hartman goto out; 773ab4382d2SGreg Kroah-Hartman continue; 774ab4382d2SGreg Kroah-Hartman } 775ab4382d2SGreg Kroah-Hartman 7768d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 777ab4382d2SGreg Kroah-Hartman 778019dc9eaSHui Wang if (rx & URXD_BRK) 779019dc9eaSHui Wang flg = TTY_BREAK; 780019dc9eaSHui Wang else if (rx & URXD_PRERR) 781ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 782ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 783ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 784ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 785ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 786ab4382d2SGreg Kroah-Hartman 787ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 788ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 789ab4382d2SGreg Kroah-Hartman #endif 790ab4382d2SGreg Kroah-Hartman } 791ab4382d2SGreg Kroah-Hartman 79255d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 79355d8693aSJiada Wang goto out; 79455d8693aSJiada Wang 7959b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 7969b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 797ab4382d2SGreg Kroah-Hartman } 798ab4382d2SGreg Kroah-Hartman 799ab4382d2SGreg Kroah-Hartman out: 800ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 8012e124b4aSJiri Slaby tty_flip_buffer_push(port); 802ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 803ab4382d2SGreg Kroah-Hartman } 804ab4382d2SGreg Kroah-Hartman 8059d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 806b4cdc8f6SHuang Shijie 80766f95884SUwe Kleine-König /* 80866f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 80966f95884SUwe Kleine-König */ 8109d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 81166f95884SUwe Kleine-König { 81266f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 81327c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 81427c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 81566f95884SUwe Kleine-König 81666f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 81766f95884SUwe Kleine-König tmp |= TIOCM_CTS; 81866f95884SUwe Kleine-König 81966f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 8204b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 82166f95884SUwe Kleine-König tmp |= TIOCM_CAR; 82266f95884SUwe Kleine-König 82366f95884SUwe Kleine-König if (sport->dte_mode) 82427c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 82566f95884SUwe Kleine-König tmp |= TIOCM_RI; 82666f95884SUwe Kleine-König 82766f95884SUwe Kleine-König return tmp; 82866f95884SUwe Kleine-König } 82966f95884SUwe Kleine-König 83066f95884SUwe Kleine-König /* 83166f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 83266f95884SUwe Kleine-König */ 8339d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 83466f95884SUwe Kleine-König { 83566f95884SUwe Kleine-König unsigned int status, changed; 83666f95884SUwe Kleine-König 8379d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 83866f95884SUwe Kleine-König changed = status ^ sport->old_status; 83966f95884SUwe Kleine-König 84066f95884SUwe Kleine-König if (changed == 0) 84166f95884SUwe Kleine-König return; 84266f95884SUwe Kleine-König 84366f95884SUwe Kleine-König sport->old_status = status; 84466f95884SUwe Kleine-König 84566f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 84666f95884SUwe Kleine-König sport->port.icount.rng++; 84766f95884SUwe Kleine-König if (changed & TIOCM_DSR) 84866f95884SUwe Kleine-König sport->port.icount.dsr++; 84966f95884SUwe Kleine-König if (changed & TIOCM_CAR) 85066f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 85166f95884SUwe Kleine-König if (changed & TIOCM_CTS) 85266f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 85366f95884SUwe Kleine-König 85466f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 85566f95884SUwe Kleine-König } 85666f95884SUwe Kleine-König 8579d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 858ab4382d2SGreg Kroah-Hartman { 859ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 86043776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 8614d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 862ab4382d2SGreg Kroah-Hartman 86327c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 86427c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 86527c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 86627c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 86727c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 86827c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 869ab4382d2SGreg Kroah-Hartman 87043776896SUwe Kleine-König /* 87143776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 87243776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 87343776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 87443776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 87543776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 87643776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 87743776896SUwe Kleine-König */ 87843776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 87943776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 88043776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 88143776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 88243776896SUwe Kleine-König if ((ucr1 & UCR1_TXMPTYEN) == 0) 88343776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 88443776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 88543776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 88643776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 88743776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 88843776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 88943776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 89043776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 89143776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 89243776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 89343776896SUwe Kleine-König usr2 &= ~USR2_ORE; 89443776896SUwe Kleine-König 89543776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 8969d1a50a2SUwe Kleine-König imx_uart_rxint(irq, dev_id); 8974d845a62SUwe Kleine-König ret = IRQ_HANDLED; 898b4cdc8f6SHuang Shijie } 899ab4382d2SGreg Kroah-Hartman 90043776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 9019d1a50a2SUwe Kleine-König imx_uart_txint(irq, dev_id); 9024d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9034d845a62SUwe Kleine-König } 904ab4382d2SGreg Kroah-Hartman 9050399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 90627e16501SUwe Kleine-König unsigned long flags; 90727e16501SUwe Kleine-König 90827c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 90927e16501SUwe Kleine-König 91027e16501SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 9119d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 91227e16501SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 91327e16501SUwe Kleine-König 91427e16501SUwe Kleine-König ret = IRQ_HANDLED; 91527e16501SUwe Kleine-König } 91627e16501SUwe Kleine-König 9170399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 9189d1a50a2SUwe Kleine-König imx_uart_rtsint(irq, dev_id); 9194d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9204d845a62SUwe Kleine-König } 921ab4382d2SGreg Kroah-Hartman 9220399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 92327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 9244d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9254d845a62SUwe Kleine-König } 926db1a9b55SFabio Estevam 9270399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 928f1f836e4SAlexander Stein sport->port.icount.overrun++; 92927c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 9304d845a62SUwe Kleine-König ret = IRQ_HANDLED; 931f1f836e4SAlexander Stein } 932f1f836e4SAlexander Stein 9334d845a62SUwe Kleine-König return ret; 934ab4382d2SGreg Kroah-Hartman } 935ab4382d2SGreg Kroah-Hartman 936ab4382d2SGreg Kroah-Hartman /* 937ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 938ab4382d2SGreg Kroah-Hartman */ 9399d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 940ab4382d2SGreg Kroah-Hartman { 941ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9421ce43e58SHuang Shijie unsigned int ret; 943ab4382d2SGreg Kroah-Hartman 94427c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 9451ce43e58SHuang Shijie 9461ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 947686351f3SUwe Kleine-König if (sport->dma_is_txing) 9481ce43e58SHuang Shijie ret = 0; 9491ce43e58SHuang Shijie 9501ce43e58SHuang Shijie return ret; 951ab4382d2SGreg Kroah-Hartman } 952ab4382d2SGreg Kroah-Hartman 9536aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 9549d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 95558362d5bSUwe Kleine-König { 95658362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 9579d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 95858362d5bSUwe Kleine-König 95958362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 96058362d5bSUwe Kleine-König 96158362d5bSUwe Kleine-König return ret; 96258362d5bSUwe Kleine-König } 96358362d5bSUwe Kleine-König 9646aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 9659d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 966ab4382d2SGreg Kroah-Hartman { 967ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9684444dcf1SUwe Kleine-König u32 ucr3, uts; 969ab4382d2SGreg Kroah-Hartman 97017b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 9714444dcf1SUwe Kleine-König u32 ucr2; 9724444dcf1SUwe Kleine-König 9734444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 9744444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 975ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 9764444dcf1SUwe Kleine-König ucr2 |= UCR2_CTS | UCR2_CTSC; 9774444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 97817b8f2a3SUwe Kleine-König } 9796b471a98SHuang Shijie 9804444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 98190ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 9824444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 9834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 98490ebc483SUwe Kleine-König 9859d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 9866b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 9874444dcf1SUwe Kleine-König uts |= UTS_LOOP; 9889d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 98958362d5bSUwe Kleine-König 99058362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 991ab4382d2SGreg Kroah-Hartman } 992ab4382d2SGreg Kroah-Hartman 993ab4382d2SGreg Kroah-Hartman /* 994ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 995ab4382d2SGreg Kroah-Hartman */ 9969d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 997ab4382d2SGreg Kroah-Hartman { 998ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9994444dcf1SUwe Kleine-König unsigned long flags; 10004444dcf1SUwe Kleine-König u32 ucr1; 1001ab4382d2SGreg Kroah-Hartman 1002ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1003ab4382d2SGreg Kroah-Hartman 10044444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1005ab4382d2SGreg Kroah-Hartman 1006ab4382d2SGreg Kroah-Hartman if (break_state != 0) 10074444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1008ab4382d2SGreg Kroah-Hartman 10094444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1010ab4382d2SGreg Kroah-Hartman 1011ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1012ab4382d2SGreg Kroah-Hartman } 1013ab4382d2SGreg Kroah-Hartman 1014cc568849SUwe Kleine-König /* 1015cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1016cc568849SUwe Kleine-König * modem status signals. 1017cc568849SUwe Kleine-König */ 10189d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1019cc568849SUwe Kleine-König { 1020e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1021cc568849SUwe Kleine-König unsigned long flags; 1022cc568849SUwe Kleine-König 1023cc568849SUwe Kleine-König if (sport->port.state) { 1024cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 10259d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1026cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1027cc568849SUwe Kleine-König 1028cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1029cc568849SUwe Kleine-König } 1030cc568849SUwe Kleine-König } 1031cc568849SUwe Kleine-König 1032351ea50dSGreg Kroah-Hartman #define RX_BUF_SIZE (PAGE_SIZE) 1033351ea50dSGreg Kroah-Hartman 1034b4cdc8f6SHuang Shijie /* 1035905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1036b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1037905c0decSLucas Stach * [2] the aging timer expires 1038b4cdc8f6SHuang Shijie * 1039905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1040905c0decSLucas Stach * for at least 8 byte durations. 1041b4cdc8f6SHuang Shijie */ 10429d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1043b4cdc8f6SHuang Shijie { 1044b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1045b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1046b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 10477cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1048b4cdc8f6SHuang Shijie struct dma_tx_state state; 10499d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1050b4cdc8f6SHuang Shijie enum dma_status status; 10519d297239SNandor Han unsigned int w_bytes = 0; 10529d297239SNandor Han unsigned int r_bytes; 10539d297239SNandor Han unsigned int bd_size; 1054b4cdc8f6SHuang Shijie 1055f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 1056392bceedSPhilipp Zabel 10579d297239SNandor Han if (status == DMA_ERROR) { 10589d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 10599d297239SNandor Han return; 10609d297239SNandor Han } 1061b4cdc8f6SHuang Shijie 10629b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1063976b39cdSLucas Stach 1064976b39cdSLucas Stach /* 10659d297239SNandor Han * The state-residue variable represents the empty space 10669d297239SNandor Han * relative to the entire buffer. Taking this in consideration 10679d297239SNandor Han * the head is always calculated base on the buffer total 10689d297239SNandor Han * length - DMA transaction residue. The UART script from the 10699d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 10709d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 10719d297239SNandor Han * Taking this in consideration the tail is always at the 10729d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1073976b39cdSLucas Stach */ 10749d297239SNandor Han 10759d297239SNandor Han /* Calculate the head */ 10769d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 10779d297239SNandor Han 10789d297239SNandor Han /* Calculate the tail. */ 10799d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 10809d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 10819d297239SNandor Han 10829d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 10839d297239SNandor Han rx_ring->head > rx_ring->tail) { 10849d297239SNandor Han 10859d297239SNandor Han /* Move data from tail to head */ 10869d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 10879d297239SNandor Han 10889d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 10899d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 10909d297239SNandor Han DMA_FROM_DEVICE); 10919d297239SNandor Han 10929d297239SNandor Han w_bytes = tty_insert_flip_string(port, 10939d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 10949d297239SNandor Han 10959d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 10969d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 10979d297239SNandor Han DMA_FROM_DEVICE); 10989d297239SNandor Han 10999d297239SNandor Han if (w_bytes != r_bytes) 11009d297239SNandor Han sport->port.icount.buf_overrun++; 11019d297239SNandor Han 11029d297239SNandor Han sport->port.icount.rx += w_bytes; 11039d297239SNandor Han } else { 11049d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11059d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1106ee5e7c10SRobin Gong } 11079d297239SNandor Han } 11089d297239SNandor Han 11099d297239SNandor Han if (w_bytes) { 11109d297239SNandor Han tty_flip_buffer_push(port); 11119d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 11129d297239SNandor Han } 11139d297239SNandor Han } 11149d297239SNandor Han 1115351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 1116351ea50dSGreg Kroah-Hartman #define RX_DMA_PERIODS 4 1117351ea50dSGreg Kroah-Hartman 11189d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1119b4cdc8f6SHuang Shijie { 1120b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1121b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1122b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1123b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1124b4cdc8f6SHuang Shijie int ret; 1125b4cdc8f6SHuang Shijie 11269d297239SNandor Han sport->rx_ring.head = 0; 11279d297239SNandor Han sport->rx_ring.tail = 0; 1128351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 11299d297239SNandor Han 1130351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1131b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1132b4cdc8f6SHuang Shijie if (ret == 0) { 1133b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1134b4cdc8f6SHuang Shijie return -EINVAL; 1135b4cdc8f6SHuang Shijie } 11369d297239SNandor Han 11379d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 11389d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 11399d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 11409d297239SNandor Han 1141b4cdc8f6SHuang Shijie if (!desc) { 114224649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1143b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1144b4cdc8f6SHuang Shijie return -EINVAL; 1145b4cdc8f6SHuang Shijie } 11469d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1147b4cdc8f6SHuang Shijie desc->callback_param = sport; 1148b4cdc8f6SHuang Shijie 1149b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 11504139fd76SRomain Perier sport->dma_is_rxing = 1; 11519d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1152b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1153b4cdc8f6SHuang Shijie return 0; 1154b4cdc8f6SHuang Shijie } 1155b4cdc8f6SHuang Shijie 11569d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 115741d98b5dSNandor Han { 115845ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 11594444dcf1SUwe Kleine-König u32 usr1, usr2; 116041d98b5dSNandor Han 11614444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 11624444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 116341d98b5dSNandor Han 11644444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 116541d98b5dSNandor Han sport->port.icount.brk++; 116627c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 116745ca673eSTroy Kisky uart_handle_break(&sport->port); 116845ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 116945ca673eSTroy Kisky sport->port.icount.buf_overrun++; 117045ca673eSTroy Kisky tty_flip_buffer_push(port); 117145ca673eSTroy Kisky } else { 117245ca673eSTroy Kisky dev_err(sport->port.dev, "DMA transaction error.\n"); 11734444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 117441d98b5dSNandor Han sport->port.icount.frame++; 117527c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 11764444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 117741d98b5dSNandor Han sport->port.icount.parity++; 117827c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 117941d98b5dSNandor Han } 118045ca673eSTroy Kisky } 118141d98b5dSNandor Han 11824444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 118341d98b5dSNandor Han sport->port.icount.overrun++; 118427c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 118541d98b5dSNandor Han } 118641d98b5dSNandor Han 118741d98b5dSNandor Han } 118841d98b5dSNandor Han 1189cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1190cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1191184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1192184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1193cc32382dSLucas Stach 11949d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1195cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1196cc32382dSLucas Stach { 1197cc32382dSLucas Stach unsigned int val; 1198cc32382dSLucas Stach 1199cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 120027c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1201cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 120227c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1203cc32382dSLucas Stach } 1204cc32382dSLucas Stach 1205b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1206b4cdc8f6SHuang Shijie { 1207b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1208e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1209b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1210b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 12119d297239SNandor Han sport->rx_cookie = -EINVAL; 1212b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1213b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1214b4cdc8f6SHuang Shijie } 1215b4cdc8f6SHuang Shijie 1216b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1217e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1218b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1219b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1220b4cdc8f6SHuang Shijie } 1221b4cdc8f6SHuang Shijie } 1222b4cdc8f6SHuang Shijie 1223b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1224b4cdc8f6SHuang Shijie { 1225b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1226b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1227b4cdc8f6SHuang Shijie int ret; 1228b4cdc8f6SHuang Shijie 1229b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1230b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1231b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1232b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1233b4cdc8f6SHuang Shijie ret = -EINVAL; 1234b4cdc8f6SHuang Shijie goto err; 1235b4cdc8f6SHuang Shijie } 1236b4cdc8f6SHuang Shijie 1237b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1238b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1239b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1240184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1241184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1242b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1243b4cdc8f6SHuang Shijie if (ret) { 1244b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1245b4cdc8f6SHuang Shijie goto err; 1246b4cdc8f6SHuang Shijie } 1247b4cdc8f6SHuang Shijie 1248f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1249b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1250b4cdc8f6SHuang Shijie ret = -ENOMEM; 1251b4cdc8f6SHuang Shijie goto err; 1252b4cdc8f6SHuang Shijie } 12539d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1254b4cdc8f6SHuang Shijie 1255b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1256b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1257b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1258b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1259b4cdc8f6SHuang Shijie ret = -EINVAL; 1260b4cdc8f6SHuang Shijie goto err; 1261b4cdc8f6SHuang Shijie } 1262b4cdc8f6SHuang Shijie 1263b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1264b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1265b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1266184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1267b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1268b4cdc8f6SHuang Shijie if (ret) { 1269b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1270b4cdc8f6SHuang Shijie goto err; 1271b4cdc8f6SHuang Shijie } 1272b4cdc8f6SHuang Shijie 1273b4cdc8f6SHuang Shijie return 0; 1274b4cdc8f6SHuang Shijie err: 1275b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1276b4cdc8f6SHuang Shijie return ret; 1277b4cdc8f6SHuang Shijie } 1278b4cdc8f6SHuang Shijie 12799d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1280b4cdc8f6SHuang Shijie { 12814444dcf1SUwe Kleine-König u32 ucr1; 1282b4cdc8f6SHuang Shijie 12839d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 128402b0abd3SUwe Kleine-König 1285b4cdc8f6SHuang Shijie /* set UCR1 */ 12864444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12874444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 12884444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1289b4cdc8f6SHuang Shijie 1290b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1291b4cdc8f6SHuang Shijie } 1292b4cdc8f6SHuang Shijie 12939d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1294b4cdc8f6SHuang Shijie { 1295676a31d8SSebastian Reichel u32 ucr1; 1296b4cdc8f6SHuang Shijie 1297b4cdc8f6SHuang Shijie /* clear UCR1 */ 12984444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12994444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 13004444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1301b4cdc8f6SHuang Shijie 13029d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1303184bd70bSLucas Stach 1304b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1305b4cdc8f6SHuang Shijie } 1306b4cdc8f6SHuang Shijie 1307ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1308ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1309ab4382d2SGreg Kroah-Hartman 13109d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1311ab4382d2SGreg Kroah-Hartman { 1312ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1313458e2c82SFabio Estevam int retval, i; 13144444dcf1SUwe Kleine-König unsigned long flags; 13154238c00bSUwe Kleine-König int dma_is_inited = 0; 13164444dcf1SUwe Kleine-König u32 ucr1, ucr2, ucr4; 1317ab4382d2SGreg Kroah-Hartman 131828eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 131928eb4274SHuang Shijie if (retval) 1320cb0f0a5fSFabio Estevam return retval; 132128eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 13220c375501SHuang Shijie if (retval) { 13230c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1324cb0f0a5fSFabio Estevam return retval; 13250c375501SHuang Shijie } 132628eb4274SHuang Shijie 13279d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1328ab4382d2SGreg Kroah-Hartman 1329ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1330ab4382d2SGreg Kroah-Hartman * requesting IRQs 1331ab4382d2SGreg Kroah-Hartman */ 13324444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1333ab4382d2SGreg Kroah-Hartman 1334ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 13354444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 13364444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1337ab4382d2SGreg Kroah-Hartman 13384444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1339ab4382d2SGreg Kroah-Hartman 13407e11577eSLucas Stach /* Can we enable the DMA support? */ 13414238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 13424238c00bSUwe Kleine-König dma_is_inited = 1; 13437e11577eSLucas Stach 134453794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1345772f8991SHuang Shijie /* Reset fifo's and state machines */ 1346458e2c82SFabio Estevam i = 100; 1347458e2c82SFabio Estevam 13484444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 13494444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 13504444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1351458e2c82SFabio Estevam 135227c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1353458e2c82SFabio Estevam udelay(1); 1354ab4382d2SGreg Kroah-Hartman 1355ab4382d2SGreg Kroah-Hartman /* 1356ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1357ab4382d2SGreg Kroah-Hartman */ 135827c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 135927c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1360ab4382d2SGreg Kroah-Hartman 13614444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 13624444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 13636376cd39SNandor Han if (sport->have_rtscts) 13644444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1365ab4382d2SGreg Kroah-Hartman 13664444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1367ab4382d2SGreg Kroah-Hartman 13684444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 13691f043572STroy Kisky if (!sport->dma_is_enabled) 13704444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 13714444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 13726f026d6bSJiada Wang 13734444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 13744444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1375bff09b09SLucas Stach if (!sport->have_rtscts) 13764444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 137716804d68SUwe Kleine-König /* 137816804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 137916804d68SUwe Kleine-König * we're using RTSD instead. 138016804d68SUwe Kleine-König */ 13819d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 13824444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 13834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1384ab4382d2SGreg Kroah-Hartman 13859d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) { 13864444dcf1SUwe Kleine-König u32 ucr3; 138716804d68SUwe Kleine-König 13884444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 13894444dcf1SUwe Kleine-König 13904444dcf1SUwe Kleine-König ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 139116804d68SUwe Kleine-König 139216804d68SUwe Kleine-König if (sport->dte_mode) 1393e61c38d8SUwe Kleine-König /* disable broken interrupts */ 13944444dcf1SUwe Kleine-König ucr3 &= ~(UCR3_RI | UCR3_DCD); 139516804d68SUwe Kleine-König 13964444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 1397ab4382d2SGreg Kroah-Hartman } 1398ab4382d2SGreg Kroah-Hartman 1399ab4382d2SGreg Kroah-Hartman /* 1400ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1401ab4382d2SGreg Kroah-Hartman */ 14029d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 140318a42088SPeter Senna Tschudin 140476821e22SUwe Kleine-König if (dma_is_inited) { 14059d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 14069d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 140776821e22SUwe Kleine-König } else { 140876821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 140976821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 141076821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 141181ca8e82SUwe Kleine-König 141281ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 141381ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 141481ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 141576821e22SUwe Kleine-König } 141618a42088SPeter Senna Tschudin 1417ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1418ab4382d2SGreg Kroah-Hartman 1419ab4382d2SGreg Kroah-Hartman return 0; 1420ab4382d2SGreg Kroah-Hartman } 1421ab4382d2SGreg Kroah-Hartman 14229d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1423ab4382d2SGreg Kroah-Hartman { 1424ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 14259ec1882dSXinyu Chen unsigned long flags; 1426339c7a87SSebastian Reichel u32 ucr1, ucr2, ucr4; 1427ab4382d2SGreg Kroah-Hartman 1428b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1429e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 14307722c240SSebastian Reichel if (sport->dma_is_txing) { 14317722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 14327722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 14337722c240SSebastian Reichel sport->dma_is_txing = 0; 14347722c240SSebastian Reichel } 1435e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 14367722c240SSebastian Reichel if (sport->dma_is_rxing) { 14377722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 14387722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 14397722c240SSebastian Reichel sport->dma_is_rxing = 0; 14407722c240SSebastian Reichel } 14419d297239SNandor Han 144273631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 14439d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 14449d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 14459d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 144673631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1447b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1448b4cdc8f6SHuang Shijie } 1449b4cdc8f6SHuang Shijie 145058362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 145158362d5bSUwe Kleine-König 14529ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14534444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14540fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 14554444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1456339c7a87SSebastian Reichel 1457339c7a87SSebastian Reichel ucr4 = imx_uart_readl(sport, UCR4); 1458339c7a87SSebastian Reichel ucr4 &= ~UCR4_OREN; 1459339c7a87SSebastian Reichel imx_uart_writel(sport, ucr4, UCR4); 14609ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1461ab4382d2SGreg Kroah-Hartman 1462ab4382d2SGreg Kroah-Hartman /* 1463ab4382d2SGreg Kroah-Hartman * Stop our timer. 1464ab4382d2SGreg Kroah-Hartman */ 1465ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1466ab4382d2SGreg Kroah-Hartman 1467ab4382d2SGreg Kroah-Hartman /* 1468ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1469ab4382d2SGreg Kroah-Hartman */ 1470ab4382d2SGreg Kroah-Hartman 14719ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14724444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 147376821e22SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1474ab4382d2SGreg Kroah-Hartman 14754444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14769ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 147728eb4274SHuang Shijie 147828eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 147928eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1480ab4382d2SGreg Kroah-Hartman } 1481ab4382d2SGreg Kroah-Hartman 14826aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 14839d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1484eb56b7edSHuang Shijie { 1485eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 148682e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 14874444dcf1SUwe Kleine-König u32 ucr2; 14884f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1489eb56b7edSHuang Shijie 149082e86ae9SDirk Behme if (!sport->dma_chan_tx) 149182e86ae9SDirk Behme return; 149282e86ae9SDirk Behme 1493eb56b7edSHuang Shijie sport->tx_bytes = 0; 1494eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 149582e86ae9SDirk Behme if (sport->dma_is_txing) { 14964444dcf1SUwe Kleine-König u32 ucr1; 14974444dcf1SUwe Kleine-König 149882e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 149982e86ae9SDirk Behme DMA_TO_DEVICE); 15004444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 15014444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 15024444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 15030f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1504eb56b7edSHuang Shijie } 1505934084a9SFabio Estevam 1506934084a9SFabio Estevam /* 1507934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1508263763c1SMartyn Welch * 1509934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1510934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1511263763c1SMartyn Welch * and UTS[6-3]". 1512263763c1SMartyn Welch * 1513263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1514263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1515263763c1SMartyn Welch * registers. 1516934084a9SFabio Estevam */ 151727c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 151827c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 151927c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1520934084a9SFabio Estevam 15214444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15224444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 15234444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1524934084a9SFabio Estevam 152527c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1526934084a9SFabio Estevam udelay(1); 1527934084a9SFabio Estevam 1528934084a9SFabio Estevam /* Restore the registers */ 152927c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 153027c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 153127c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1532eb56b7edSHuang Shijie } 1533eb56b7edSHuang Shijie 1534ab4382d2SGreg Kroah-Hartman static void 15359d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1536ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1537ab4382d2SGreg Kroah-Hartman { 1538ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1539ab4382d2SGreg Kroah-Hartman unsigned long flags; 15404444dcf1SUwe Kleine-König u32 ucr2, old_ucr1, old_ucr2, ufcr; 154158362d5bSUwe Kleine-König unsigned int baud, quot; 1542ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 15434444dcf1SUwe Kleine-König unsigned long div; 1544ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1545ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1546ab4382d2SGreg Kroah-Hartman 1547ab4382d2SGreg Kroah-Hartman /* 1548ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1549ab4382d2SGreg Kroah-Hartman */ 1550ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1551ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1552ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1553ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1554ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1555ab4382d2SGreg Kroah-Hartman } 1556ab4382d2SGreg Kroah-Hartman 1557ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1558ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1559ab4382d2SGreg Kroah-Hartman else 1560ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1561ab4382d2SGreg Kroah-Hartman 1562ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1563ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1564ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 156517b8f2a3SUwe Kleine-König 156612fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 156717b8f2a3SUwe Kleine-König /* 156817b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 156917b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 157017b8f2a3SUwe Kleine-König * disabled. 157117b8f2a3SUwe Kleine-König */ 157258362d5bSUwe Kleine-König if (port->rs485.flags & 157358362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 15749d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 15751a613626SFabio Estevam else 15769d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 157712fe59f9SFabio Estevam } else { 15789d1a50a2SUwe Kleine-König imx_uart_rts_auto(sport, &ucr2); 157912fe59f9SFabio Estevam } 1580ab4382d2SGreg Kroah-Hartman } else { 1581ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1582ab4382d2SGreg Kroah-Hartman } 158358362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 158417b8f2a3SUwe Kleine-König /* disable transmitter */ 158558362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 15869d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 15871a613626SFabio Estevam else 15889d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 158958362d5bSUwe Kleine-König } 159058362d5bSUwe Kleine-König 1591ab4382d2SGreg Kroah-Hartman 1592ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1593ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1594ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1595ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1596ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1597ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1598ab4382d2SGreg Kroah-Hartman } 1599ab4382d2SGreg Kroah-Hartman 1600995234daSEric Miao del_timer_sync(&sport->timer); 1601995234daSEric Miao 1602ab4382d2SGreg Kroah-Hartman /* 1603ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1604ab4382d2SGreg Kroah-Hartman */ 1605ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1606ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1607ab4382d2SGreg Kroah-Hartman 1608ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1609ab4382d2SGreg Kroah-Hartman 1610ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1611ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1612ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1613ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1614ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1615ab4382d2SGreg Kroah-Hartman 1616ab4382d2SGreg Kroah-Hartman /* 1617ab4382d2SGreg Kroah-Hartman * Characters to ignore 1618ab4382d2SGreg Kroah-Hartman */ 1619ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1620ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1621865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1622ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1623ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1624ab4382d2SGreg Kroah-Hartman /* 1625ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1626ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1627ab4382d2SGreg Kroah-Hartman */ 1628ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1629ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1630ab4382d2SGreg Kroah-Hartman } 1631ab4382d2SGreg Kroah-Hartman 163255d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 163355d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 163455d8693aSJiada Wang 1635ab4382d2SGreg Kroah-Hartman /* 1636ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1637ab4382d2SGreg Kroah-Hartman */ 1638ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1639ab4382d2SGreg Kroah-Hartman 1640ab4382d2SGreg Kroah-Hartman /* 1641ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1642ab4382d2SGreg Kroah-Hartman */ 164327c84426SUwe Kleine-König old_ucr1 = imx_uart_readl(sport, UCR1); 164427c84426SUwe Kleine-König imx_uart_writel(sport, 164527c84426SUwe Kleine-König old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 164627c84426SUwe Kleine-König UCR1); 164781ca8e82SUwe Kleine-König old_ucr2 = imx_uart_readl(sport, UCR2); 164881ca8e82SUwe Kleine-König imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2); 1649ab4382d2SGreg Kroah-Hartman 165027c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)) 1651ab4382d2SGreg Kroah-Hartman barrier(); 1652ab4382d2SGreg Kroah-Hartman 1653ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 165481ca8e82SUwe Kleine-König imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2); 165586a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1656ab4382d2SGreg Kroah-Hartman 165709bd00f6SHubert Feurstein /* custom-baudrate handling */ 165809bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 165909bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 166009bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 166109bd00f6SHubert Feurstein 1662ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1663ab4382d2SGreg Kroah-Hartman if (div > 7) 1664ab4382d2SGreg Kroah-Hartman div = 7; 1665ab4382d2SGreg Kroah-Hartman if (!div) 1666ab4382d2SGreg Kroah-Hartman div = 1; 1667ab4382d2SGreg Kroah-Hartman 1668ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1669ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1670ab4382d2SGreg Kroah-Hartman 1671ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1672ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1673ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1674ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1675ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1676ab4382d2SGreg Kroah-Hartman 1677ab4382d2SGreg Kroah-Hartman num -= 1; 1678ab4382d2SGreg Kroah-Hartman denom -= 1; 1679ab4382d2SGreg Kroah-Hartman 168027c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1681ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 168227c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1683ab4382d2SGreg Kroah-Hartman 168427c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 168527c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1686ab4382d2SGreg Kroah-Hartman 16879d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 168827c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 168927c84426SUwe Kleine-König IMX21_ONEMS); 1690ab4382d2SGreg Kroah-Hartman 169127c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr1, UCR1); 1692ab4382d2SGreg Kroah-Hartman 1693ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 169427c84426SUwe Kleine-König imx_uart_writel(sport, ucr2 | old_ucr2, UCR2); 1695ab4382d2SGreg Kroah-Hartman 1696ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 16979d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1698ab4382d2SGreg Kroah-Hartman 1699ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1700ab4382d2SGreg Kroah-Hartman } 1701ab4382d2SGreg Kroah-Hartman 17029d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1703ab4382d2SGreg Kroah-Hartman { 1704ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1705ab4382d2SGreg Kroah-Hartman 1706ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1707ab4382d2SGreg Kroah-Hartman } 1708ab4382d2SGreg Kroah-Hartman 1709ab4382d2SGreg Kroah-Hartman /* 1710ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1711ab4382d2SGreg Kroah-Hartman */ 17129d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1713ab4382d2SGreg Kroah-Hartman { 1714ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1715ab4382d2SGreg Kroah-Hartman 1716da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1717ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1718ab4382d2SGreg Kroah-Hartman } 1719ab4382d2SGreg Kroah-Hartman 1720ab4382d2SGreg Kroah-Hartman /* 1721ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1722ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1723ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1724ab4382d2SGreg Kroah-Hartman */ 1725ab4382d2SGreg Kroah-Hartman static int 17269d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1727ab4382d2SGreg Kroah-Hartman { 1728ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1729ab4382d2SGreg Kroah-Hartman int ret = 0; 1730ab4382d2SGreg Kroah-Hartman 1731ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1732ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1733ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1734ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1735ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1736ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1737ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1738ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1739a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1740ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1741ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1742ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1743ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1744ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1745ab4382d2SGreg Kroah-Hartman return ret; 1746ab4382d2SGreg Kroah-Hartman } 1747ab4382d2SGreg Kroah-Hartman 174801f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17496b8bdad9SDaniel Thompson 17509d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 17516b8bdad9SDaniel Thompson { 17526b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 17536b8bdad9SDaniel Thompson unsigned long flags; 17544444dcf1SUwe Kleine-König u32 ucr1, ucr2; 17556b8bdad9SDaniel Thompson int retval; 17566b8bdad9SDaniel Thompson 17576b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 17586b8bdad9SDaniel Thompson if (retval) 17596b8bdad9SDaniel Thompson return retval; 17606b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 17616b8bdad9SDaniel Thompson if (retval) 17626b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 17636b8bdad9SDaniel Thompson 17649d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 17656b8bdad9SDaniel Thompson 17666b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 17676b8bdad9SDaniel Thompson 176876821e22SUwe Kleine-König /* 176976821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 177076821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 177176821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 177276821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 177376821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 177476821e22SUwe Kleine-König */ 17754444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 177676821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 177776821e22SUwe Kleine-König 17789d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 17794444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 17806b8bdad9SDaniel Thompson 178176821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 178276821e22SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN); 178376821e22SUwe Kleine-König 17844444dcf1SUwe Kleine-König ucr2 |= UCR2_RXEN; 178581ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 178676821e22SUwe Kleine-König 178776821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 17884444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 17896b8bdad9SDaniel Thompson 179076821e22SUwe Kleine-König /* now enable irqs */ 179176821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 179281ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 179376821e22SUwe Kleine-König 17946b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 17956b8bdad9SDaniel Thompson 17966b8bdad9SDaniel Thompson return 0; 17976b8bdad9SDaniel Thompson } 17986b8bdad9SDaniel Thompson 17999d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 180001f56abdSSaleem Abdulrasool { 180127c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 180227c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 180326c47412SDirk Behme return NO_POLL_CHAR; 180401f56abdSSaleem Abdulrasool 180527c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 180601f56abdSSaleem Abdulrasool } 180701f56abdSSaleem Abdulrasool 18089d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 180901f56abdSSaleem Abdulrasool { 181027c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 181101f56abdSSaleem Abdulrasool unsigned int status; 181201f56abdSSaleem Abdulrasool 181301f56abdSSaleem Abdulrasool /* drain */ 181401f56abdSSaleem Abdulrasool do { 181527c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 181601f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 181701f56abdSSaleem Abdulrasool 181801f56abdSSaleem Abdulrasool /* write */ 181927c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 182001f56abdSSaleem Abdulrasool 182101f56abdSSaleem Abdulrasool /* flush */ 182201f56abdSSaleem Abdulrasool do { 182327c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 182401f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 182501f56abdSSaleem Abdulrasool } 182601f56abdSSaleem Abdulrasool #endif 182701f56abdSSaleem Abdulrasool 18286aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 18299d1a50a2SUwe Kleine-König static int imx_uart_rs485_config(struct uart_port *port, 183017b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 183117b8f2a3SUwe Kleine-König { 183217b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 18334444dcf1SUwe Kleine-König u32 ucr2; 183417b8f2a3SUwe Kleine-König 183517b8f2a3SUwe Kleine-König /* unimplemented */ 183617b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 183717b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 183817b8f2a3SUwe Kleine-König 183917b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 18407b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 184117b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 184217b8f2a3SUwe Kleine-König 184317b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 18446d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 18456d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 18466d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 18476d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 18486d215f83SStefan Agner 184917b8f2a3SUwe Kleine-König /* disable transmitter */ 18504444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 185117b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 18529d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 18531a613626SFabio Estevam else 18549d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 18554444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 185617b8f2a3SUwe Kleine-König } 185717b8f2a3SUwe Kleine-König 18587d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 18597d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 186076821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 18619d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 18627d1cadcaSBaruch Siach 186317b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 186417b8f2a3SUwe Kleine-König 186517b8f2a3SUwe Kleine-König return 0; 186617b8f2a3SUwe Kleine-König } 186717b8f2a3SUwe Kleine-König 18689d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 18699d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 18709d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 18719d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 18729d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 18739d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 18749d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 18759d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 18769d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 18779d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 18789d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 18799d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 18809d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 18819d1a50a2SUwe Kleine-König .type = imx_uart_type, 18829d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 18839d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 188401f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18859d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 18869d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 18879d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 188801f56abdSSaleem Abdulrasool #endif 1889ab4382d2SGreg Kroah-Hartman }; 1890ab4382d2SGreg Kroah-Hartman 18919d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1892ab4382d2SGreg Kroah-Hartman 1893ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 18949d1a50a2SUwe Kleine-König static void imx_uart_console_putchar(struct uart_port *port, int ch) 1895ab4382d2SGreg Kroah-Hartman { 1896ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1897ab4382d2SGreg Kroah-Hartman 18989d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1899ab4382d2SGreg Kroah-Hartman barrier(); 1900ab4382d2SGreg Kroah-Hartman 190127c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1902ab4382d2SGreg Kroah-Hartman } 1903ab4382d2SGreg Kroah-Hartman 1904ab4382d2SGreg Kroah-Hartman /* 1905ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1906ab4382d2SGreg Kroah-Hartman */ 1907ab4382d2SGreg Kroah-Hartman static void 19089d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1909ab4382d2SGreg Kroah-Hartman { 19109d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 19110ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 19120ad5a814SDirk Behme unsigned int ucr1; 1913f30e8260SShawn Guo unsigned long flags = 0; 1914677fe555SThomas Gleixner int locked = 1; 19151cf93e0dSHuang Shijie int retval; 19161cf93e0dSHuang Shijie 19170c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 19181cf93e0dSHuang Shijie if (retval) 19191cf93e0dSHuang Shijie return; 19200c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 19211cf93e0dSHuang Shijie if (retval) { 19220c727a42SFabio Estevam clk_disable(sport->clk_per); 19231cf93e0dSHuang Shijie return; 19241cf93e0dSHuang Shijie } 19259ec1882dSXinyu Chen 1926677fe555SThomas Gleixner if (sport->port.sysrq) 1927677fe555SThomas Gleixner locked = 0; 1928677fe555SThomas Gleixner else if (oops_in_progress) 1929677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1930677fe555SThomas Gleixner else 19319ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1932ab4382d2SGreg Kroah-Hartman 1933ab4382d2SGreg Kroah-Hartman /* 19340ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1935ab4382d2SGreg Kroah-Hartman */ 19369d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 19370ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1938ab4382d2SGreg Kroah-Hartman 19399d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 1940fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1941ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1942ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1943ab4382d2SGreg Kroah-Hartman 194427c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1945ab4382d2SGreg Kroah-Hartman 194627c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1947ab4382d2SGreg Kroah-Hartman 19489d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 1949ab4382d2SGreg Kroah-Hartman 1950ab4382d2SGreg Kroah-Hartman /* 1951ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 19520ad5a814SDirk Behme * and restore UCR1/2/3 1953ab4382d2SGreg Kroah-Hartman */ 195427c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1955ab4382d2SGreg Kroah-Hartman 19569d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 19579ec1882dSXinyu Chen 1958677fe555SThomas Gleixner if (locked) 19599ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 19601cf93e0dSHuang Shijie 19610c727a42SFabio Estevam clk_disable(sport->clk_ipg); 19620c727a42SFabio Estevam clk_disable(sport->clk_per); 1963ab4382d2SGreg Kroah-Hartman } 1964ab4382d2SGreg Kroah-Hartman 1965ab4382d2SGreg Kroah-Hartman /* 1966ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1967ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1968ab4382d2SGreg Kroah-Hartman */ 1969ab4382d2SGreg Kroah-Hartman static void __init 19709d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 1971ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1972ab4382d2SGreg Kroah-Hartman { 1973ab4382d2SGreg Kroah-Hartman 197427c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1975ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1976ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1977ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1978ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1979ab4382d2SGreg Kroah-Hartman 198027c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 1981ab4382d2SGreg Kroah-Hartman 1982ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1983ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1984ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1985ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1986ab4382d2SGreg Kroah-Hartman else 1987ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1988ab4382d2SGreg Kroah-Hartman } 1989ab4382d2SGreg Kroah-Hartman 1990ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1991ab4382d2SGreg Kroah-Hartman *bits = 8; 1992ab4382d2SGreg Kroah-Hartman else 1993ab4382d2SGreg Kroah-Hartman *bits = 7; 1994ab4382d2SGreg Kroah-Hartman 199527c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 199627c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 1997ab4382d2SGreg Kroah-Hartman 199827c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 1999ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 2000ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 2001ab4382d2SGreg Kroah-Hartman else 2002ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 2003ab4382d2SGreg Kroah-Hartman 20043a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2005ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2006ab4382d2SGreg Kroah-Hartman 2007ab4382d2SGreg Kroah-Hartman { /* 2008ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2009ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2010ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2011ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2012ab4382d2SGreg Kroah-Hartman */ 2013ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2014ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2015ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2016ab4382d2SGreg Kroah-Hartman 2017ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2018ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2019ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2020ab4382d2SGreg Kroah-Hartman } 2021ab4382d2SGreg Kroah-Hartman 2022ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 202350bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 2024ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2025ab4382d2SGreg Kroah-Hartman } 2026ab4382d2SGreg Kroah-Hartman } 2027ab4382d2SGreg Kroah-Hartman 2028ab4382d2SGreg Kroah-Hartman static int __init 20299d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2030ab4382d2SGreg Kroah-Hartman { 2031ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2032ab4382d2SGreg Kroah-Hartman int baud = 9600; 2033ab4382d2SGreg Kroah-Hartman int bits = 8; 2034ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2035ab4382d2SGreg Kroah-Hartman int flow = 'n'; 20361cf93e0dSHuang Shijie int retval; 2037ab4382d2SGreg Kroah-Hartman 2038ab4382d2SGreg Kroah-Hartman /* 2039ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2040ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2041ab4382d2SGreg Kroah-Hartman * console support. 2042ab4382d2SGreg Kroah-Hartman */ 20439d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2044ab4382d2SGreg Kroah-Hartman co->index = 0; 20459d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2046ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2047ab4382d2SGreg Kroah-Hartman return -ENODEV; 2048ab4382d2SGreg Kroah-Hartman 20491cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 20501cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 20511cf93e0dSHuang Shijie if (retval) 20521cf93e0dSHuang Shijie goto error_console; 20531cf93e0dSHuang Shijie 2054ab4382d2SGreg Kroah-Hartman if (options) 2055ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2056ab4382d2SGreg Kroah-Hartman else 20579d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2058ab4382d2SGreg Kroah-Hartman 20599d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2060ab4382d2SGreg Kroah-Hartman 20611cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 20621cf93e0dSHuang Shijie 20630c727a42SFabio Estevam clk_disable(sport->clk_ipg); 20640c727a42SFabio Estevam if (retval) { 20650c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 20660c727a42SFabio Estevam goto error_console; 20670c727a42SFabio Estevam } 20680c727a42SFabio Estevam 20690c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 20700c727a42SFabio Estevam if (retval) 20711cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 20721cf93e0dSHuang Shijie 20731cf93e0dSHuang Shijie error_console: 20741cf93e0dSHuang Shijie return retval; 2075ab4382d2SGreg Kroah-Hartman } 2076ab4382d2SGreg Kroah-Hartman 20779d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 20789d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2079ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 20809d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2081ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 20829d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 2083ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2084ab4382d2SGreg Kroah-Hartman .index = -1, 20859d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2086ab4382d2SGreg Kroah-Hartman }; 2087ab4382d2SGreg Kroah-Hartman 20889d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2089913c6c0eSLucas Stach 2090913c6c0eSLucas Stach #ifdef CONFIG_OF 20919d1a50a2SUwe Kleine-König static void imx_uart_console_early_putchar(struct uart_port *port, int ch) 2092913c6c0eSLucas Stach { 209327c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 209427c84426SUwe Kleine-König 209527c84426SUwe Kleine-König while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2096913c6c0eSLucas Stach cpu_relax(); 2097913c6c0eSLucas Stach 209827c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 2099913c6c0eSLucas Stach } 2100913c6c0eSLucas Stach 21019d1a50a2SUwe Kleine-König static void imx_uart_console_early_write(struct console *con, const char *s, 2102913c6c0eSLucas Stach unsigned count) 2103913c6c0eSLucas Stach { 2104913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 2105913c6c0eSLucas Stach 21069d1a50a2SUwe Kleine-König uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar); 2107913c6c0eSLucas Stach } 2108913c6c0eSLucas Stach 2109913c6c0eSLucas Stach static int __init 2110913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2111913c6c0eSLucas Stach { 2112913c6c0eSLucas Stach if (!dev->port.membase) 2113913c6c0eSLucas Stach return -ENODEV; 2114913c6c0eSLucas Stach 21159d1a50a2SUwe Kleine-König dev->con->write = imx_uart_console_early_write; 2116913c6c0eSLucas Stach 2117913c6c0eSLucas Stach return 0; 2118913c6c0eSLucas Stach } 2119913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2120913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2121913c6c0eSLucas Stach #endif 2122913c6c0eSLucas Stach 2123ab4382d2SGreg Kroah-Hartman #else 2124ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2125ab4382d2SGreg Kroah-Hartman #endif 2126ab4382d2SGreg Kroah-Hartman 21279d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2128ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2129ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2130ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2131ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2132ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21339d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2134ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2135ab4382d2SGreg Kroah-Hartman }; 2136ab4382d2SGreg Kroah-Hartman 213722698aa2SShawn Guo #ifdef CONFIG_OF 213820bb8095SUwe Kleine-König /* 213920bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 214020bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 214120bb8095SUwe Kleine-König */ 21429d1a50a2SUwe Kleine-König static int imx_uart_probe_dt(struct imx_port *sport, 214322698aa2SShawn Guo struct platform_device *pdev) 214422698aa2SShawn Guo { 214522698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2146ff05967aSShawn Guo int ret; 214722698aa2SShawn Guo 21485f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 21495f8b9043SLABBE Corentin if (!sport->devdata) 215020bb8095SUwe Kleine-König /* no device tree device */ 215120bb8095SUwe Kleine-König return 1; 215222698aa2SShawn Guo 2153ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2154ff05967aSShawn Guo if (ret < 0) { 2155ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2156a197a191SUwe Kleine-König return ret; 2157ff05967aSShawn Guo } 2158ff05967aSShawn Guo sport->port.line = ret; 215922698aa2SShawn Guo 21601006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 21611006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 216222698aa2SShawn Guo sport->have_rtscts = 1; 216322698aa2SShawn Guo 216420ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 216520ff2fe6SHuang Shijie sport->dte_mode = 1; 216620ff2fe6SHuang Shijie 21677b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 21687b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 21697b7e8e8eSFabio Estevam 217022698aa2SShawn Guo return 0; 217122698aa2SShawn Guo } 217222698aa2SShawn Guo #else 21739d1a50a2SUwe Kleine-König static inline int imx_uart_probe_dt(struct imx_port *sport, 217422698aa2SShawn Guo struct platform_device *pdev) 217522698aa2SShawn Guo { 217620bb8095SUwe Kleine-König return 1; 217722698aa2SShawn Guo } 217822698aa2SShawn Guo #endif 217922698aa2SShawn Guo 21809d1a50a2SUwe Kleine-König static void imx_uart_probe_pdata(struct imx_port *sport, 218122698aa2SShawn Guo struct platform_device *pdev) 218222698aa2SShawn Guo { 2183574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 218422698aa2SShawn Guo 218522698aa2SShawn Guo sport->port.line = pdev->id; 218622698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 218722698aa2SShawn Guo 218822698aa2SShawn Guo if (!pdata) 218922698aa2SShawn Guo return; 219022698aa2SShawn Guo 219122698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 219222698aa2SShawn Guo sport->have_rtscts = 1; 219322698aa2SShawn Guo } 219422698aa2SShawn Guo 21959d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2196ab4382d2SGreg Kroah-Hartman { 2197ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2198ab4382d2SGreg Kroah-Hartman void __iomem *base; 21994444dcf1SUwe Kleine-König int ret = 0; 22004444dcf1SUwe Kleine-König u32 ucr1; 2201ab4382d2SGreg Kroah-Hartman struct resource *res; 2202842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2203ab4382d2SGreg Kroah-Hartman 220442d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2205ab4382d2SGreg Kroah-Hartman if (!sport) 2206ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2207ab4382d2SGreg Kroah-Hartman 22089d1a50a2SUwe Kleine-König ret = imx_uart_probe_dt(sport, pdev); 220920bb8095SUwe Kleine-König if (ret > 0) 22109d1a50a2SUwe Kleine-König imx_uart_probe_pdata(sport, pdev); 221120bb8095SUwe Kleine-König else if (ret < 0) 221242d34191SSachin Kamat return ret; 221322698aa2SShawn Guo 22149d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 221556734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 221656734448SGeert Uytterhoeven sport->port.line); 221756734448SGeert Uytterhoeven return -EINVAL; 221856734448SGeert Uytterhoeven } 221956734448SGeert Uytterhoeven 2220ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2221da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2222da82f997SAlexander Shiyan if (IS_ERR(base)) 2223da82f997SAlexander Shiyan return PTR_ERR(base); 2224ab4382d2SGreg Kroah-Hartman 2225842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2226842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2227842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2228842633bdSUwe Kleine-König 2229ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2230ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2231ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2232ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2233ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2234842633bdSUwe Kleine-König sport->port.irq = rxirq; 2235ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 22369d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 22379d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 2238ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 22399d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2240ab4382d2SGreg Kroah-Hartman 224158362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 224258362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 224358362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 224458362d5bSUwe Kleine-König 22453a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 22463a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 22473a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2248833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 224942d34191SSachin Kamat return ret; 2250ab4382d2SGreg Kroah-Hartman } 2251ab4382d2SGreg Kroah-Hartman 22523a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 22533a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 22543a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2255833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 225642d34191SSachin Kamat return ret; 22573a9465faSSascha Hauer } 22583a9465faSSascha Hauer 22593a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2260ab4382d2SGreg Kroah-Hartman 22618a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 22628a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 22631e512d45SUwe Kleine-König if (ret) { 22641e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 22658a61f0c7SFabio Estevam return ret; 22661e512d45SUwe Kleine-König } 22678a61f0c7SFabio Estevam 22683a0ab62fSUwe Kleine-König /* initialize shadow register values */ 22693a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 22703a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 22713a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 22723a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 22733a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 22743a0ab62fSUwe Kleine-König 2275743f93f8SLukas Wunner uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2276743f93f8SLukas Wunner 2277b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 22785d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2279b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2280b8f3bff0SLukas Wunner 22816d215f83SStefan Agner /* 22826d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 22836d215f83SStefan Agner * signal cannot be set low during transmission in case the 22846d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 22856d215f83SStefan Agner */ 22866d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 22876d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 22886d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 22896d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 22906d215f83SStefan Agner dev_err(&pdev->dev, 22916d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 22926d215f83SStefan Agner 22939d1a50a2SUwe Kleine-König imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2294b8f3bff0SLukas Wunner 22958a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 22964444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 22974444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 22988a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 22994444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 23008a61f0c7SFabio Estevam 23019d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2302e61c38d8SUwe Kleine-König /* 2303e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2304e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2305e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2306e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2307e61c38d8SUwe Kleine-König */ 23084444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23094444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 23104444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2311e61c38d8SUwe Kleine-König 2312e61c38d8SUwe Kleine-König /* 2313e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2314e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2315e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2316e61c38d8SUwe Kleine-König */ 231727c84426SUwe Kleine-König imx_uart_writel(sport, 231827c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 231927c84426SUwe Kleine-König UCR3); 2320e61c38d8SUwe Kleine-König 2321e61c38d8SUwe Kleine-König } else { 23224444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 23234444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23244444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 23254444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 23266df765dcSUwe Kleine-König 23279d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 23286df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 232927c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2330e61c38d8SUwe Kleine-König } 2331e61c38d8SUwe Kleine-König 23328a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 23338a61f0c7SFabio Estevam 2334c0d1c6b0SFabio Estevam /* 2335c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2336c0d1c6b0SFabio Estevam * chips only have one interrupt. 2337c0d1c6b0SFabio Estevam */ 2338842633bdSUwe Kleine-König if (txirq > 0) { 23399d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2340c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23411e512d45SUwe Kleine-König if (ret) { 23421e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 23431e512d45SUwe Kleine-König ret); 2344c0d1c6b0SFabio Estevam return ret; 23451e512d45SUwe Kleine-König } 2346c0d1c6b0SFabio Estevam 23479d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2348c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23491e512d45SUwe Kleine-König if (ret) { 23501e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 23511e512d45SUwe Kleine-König ret); 2352c0d1c6b0SFabio Estevam return ret; 23531e512d45SUwe Kleine-König } 2354c0d1c6b0SFabio Estevam } else { 23559d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2356c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23571e512d45SUwe Kleine-König if (ret) { 23581e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2359c0d1c6b0SFabio Estevam return ret; 2360c0d1c6b0SFabio Estevam } 23611e512d45SUwe Kleine-König } 2362c0d1c6b0SFabio Estevam 23639d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2364ab4382d2SGreg Kroah-Hartman 23650a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2366ab4382d2SGreg Kroah-Hartman 23679d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2368ab4382d2SGreg Kroah-Hartman } 2369ab4382d2SGreg Kroah-Hartman 23709d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2371ab4382d2SGreg Kroah-Hartman { 2372ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2373ab4382d2SGreg Kroah-Hartman 23749d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2375ab4382d2SGreg Kroah-Hartman } 2376ab4382d2SGreg Kroah-Hartman 23779d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2378c868cbb7SEduardo Valentin { 2379c868cbb7SEduardo Valentin if (!sport->context_saved) 2380c868cbb7SEduardo Valentin return; 2381c868cbb7SEduardo Valentin 238227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 238327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 238427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 238527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 238627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 238727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 238827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 238927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 239027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 239127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2392c868cbb7SEduardo Valentin sport->context_saved = false; 2393c868cbb7SEduardo Valentin } 2394c868cbb7SEduardo Valentin 23959d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2396c868cbb7SEduardo Valentin { 2397c868cbb7SEduardo Valentin /* Save necessary regs */ 239827c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 239927c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 240027c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 240127c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 240227c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 240327c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 240427c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 240527c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 240627c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 240727c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2408c868cbb7SEduardo Valentin sport->context_saved = true; 2409c868cbb7SEduardo Valentin } 2410c868cbb7SEduardo Valentin 24119d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2412189550b8SEduardo Valentin { 24134444dcf1SUwe Kleine-König u32 ucr3; 2414189550b8SEduardo Valentin 24154444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 241609df0b34SMartin Kaiser if (on) { 241727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 24184444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 24194444dcf1SUwe Kleine-König } else { 24204444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 242109df0b34SMartin Kaiser } 24224444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2423bc85734bSEduardo Valentin 242438b1f0fbSFabio Estevam if (sport->have_rtscts) { 24254444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2426bc85734bSEduardo Valentin if (on) 24274444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2428bc85734bSEduardo Valentin else 24294444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 24304444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2431189550b8SEduardo Valentin } 243238b1f0fbSFabio Estevam } 2433189550b8SEduardo Valentin 24349d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 243590bb6bd3SShenwei Wang { 2436a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 243790bb6bd3SShenwei Wang 24389d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 243990bb6bd3SShenwei Wang 244090bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 244190bb6bd3SShenwei Wang 244290bb6bd3SShenwei Wang return 0; 244390bb6bd3SShenwei Wang } 244490bb6bd3SShenwei Wang 24459d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 244690bb6bd3SShenwei Wang { 2447a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 244890bb6bd3SShenwei Wang int ret; 244990bb6bd3SShenwei Wang 245090bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 245190bb6bd3SShenwei Wang if (ret) 245290bb6bd3SShenwei Wang return ret; 245390bb6bd3SShenwei Wang 24549d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 245590bb6bd3SShenwei Wang 245690bb6bd3SShenwei Wang return 0; 245790bb6bd3SShenwei Wang } 245890bb6bd3SShenwei Wang 24599d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 246090bb6bd3SShenwei Wang { 2461a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 246209df0b34SMartin Kaiser int ret; 246390bb6bd3SShenwei Wang 24649d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 246581b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 246690bb6bd3SShenwei Wang 246709df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 246809df0b34SMartin Kaiser if (ret) 246909df0b34SMartin Kaiser return ret; 247009df0b34SMartin Kaiser 247109df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 24729d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 247309df0b34SMartin Kaiser 247409df0b34SMartin Kaiser return 0; 247590bb6bd3SShenwei Wang } 247690bb6bd3SShenwei Wang 24779d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 247890bb6bd3SShenwei Wang { 2479a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 248090bb6bd3SShenwei Wang 248190bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 24829d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 248390bb6bd3SShenwei Wang 24849d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 248581b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 248690bb6bd3SShenwei Wang 248709df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 248829add68dSMartin Fuzzey 248990bb6bd3SShenwei Wang return 0; 249090bb6bd3SShenwei Wang } 249190bb6bd3SShenwei Wang 24929d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 249394be6d74SPhilipp Zabel { 2494a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 249594be6d74SPhilipp Zabel 24969d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 249794be6d74SPhilipp Zabel 249809df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 249994be6d74SPhilipp Zabel } 250094be6d74SPhilipp Zabel 25019d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 250294be6d74SPhilipp Zabel { 2503a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 250494be6d74SPhilipp Zabel 25059d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 250694be6d74SPhilipp Zabel 250709df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 250894be6d74SPhilipp Zabel 250994be6d74SPhilipp Zabel return 0; 251094be6d74SPhilipp Zabel } 251194be6d74SPhilipp Zabel 25129d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 25139d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 25149d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 25159d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 25169d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 25179d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 25189d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 25199d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 25209d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 25219d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 252290bb6bd3SShenwei Wang }; 252390bb6bd3SShenwei Wang 25249d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 25259d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 25269d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2527ab4382d2SGreg Kroah-Hartman 2528fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2529ab4382d2SGreg Kroah-Hartman .driver = { 2530ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 253122698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 25329d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2533ab4382d2SGreg Kroah-Hartman }, 2534ab4382d2SGreg Kroah-Hartman }; 2535ab4382d2SGreg Kroah-Hartman 25369d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2537ab4382d2SGreg Kroah-Hartman { 25389d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2539ab4382d2SGreg Kroah-Hartman 2540ab4382d2SGreg Kroah-Hartman if (ret) 2541ab4382d2SGreg Kroah-Hartman return ret; 2542ab4382d2SGreg Kroah-Hartman 25439d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2544ab4382d2SGreg Kroah-Hartman if (ret != 0) 25459d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2546ab4382d2SGreg Kroah-Hartman 2547f227824eSUwe Kleine-König return ret; 2548ab4382d2SGreg Kroah-Hartman } 2549ab4382d2SGreg Kroah-Hartman 25509d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2551ab4382d2SGreg Kroah-Hartman { 25529d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 25539d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2554ab4382d2SGreg Kroah-Hartman } 2555ab4382d2SGreg Kroah-Hartman 25569d1a50a2SUwe Kleine-König module_init(imx_uart_init); 25579d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2558ab4382d2SGreg Kroah-Hartman 2559ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2560ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2561ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2562ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2563