1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 13ab4382d2SGreg Kroah-Hartman #endif 14ab4382d2SGreg Kroah-Hartman 15ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 23ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 24ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 27fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 29ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 3022698aa2SShawn Guo #include <linux/of.h> 3122698aa2SShawn Guo #include <linux/of_device.h> 32e32a9f8fSSachin Kamat #include <linux/io.h> 33b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 34ab4382d2SGreg Kroah-Hartman 35ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 3682906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 37b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 38ab4382d2SGreg Kroah-Hartman 3958362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 4058362d5bSUwe Kleine-König 41ab4382d2SGreg Kroah-Hartman /* Register definitions */ 42ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 43ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 44ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 45ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 46ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 47ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 48ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 49ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 50ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 51ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 52ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 53ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 54ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 55ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 56fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 57fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 58fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 59ab4382d2SGreg Kroah-Hartman 60ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6155d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 62ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 63ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 64ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 65ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 66ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 67ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6826c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6925985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 71ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 72ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 73b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 75302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 77ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 80302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 81fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 82b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 84ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9501f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 98ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 101ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 104ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 105b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 106ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10927e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 110fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 112ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 115ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 119b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 125ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1267be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 127ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 128ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 129ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 130ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 131ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 132ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 133ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 134ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 135ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 136ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13786a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13827e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 139ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 142ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 143ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 144ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14690ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14790ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 148ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 15090ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 151ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 152ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 153ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 154ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 155ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 156ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 157ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 158ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 159ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 160ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 161ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 162ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 163ab4382d2SGreg Kroah-Hartman 164ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 165ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 166ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 167ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 168ab4382d2SGreg Kroah-Hartman 169ab4382d2SGreg Kroah-Hartman /* 170ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 171ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 172ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 173ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 174ab4382d2SGreg Kroah-Hartman */ 175ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 176ab4382d2SGreg Kroah-Hartman 177ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 178ab4382d2SGreg Kroah-Hartman 179ab4382d2SGreg Kroah-Hartman #define UART_NR 8 180ab4382d2SGreg Kroah-Hartman 181f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 182fe6b540aSShawn Guo enum imx_uart_type { 183fe6b540aSShawn Guo IMX1_UART, 184fe6b540aSShawn Guo IMX21_UART, 1851c06bde6SMartyn Welch IMX53_UART, 186a496e628SHuang Shijie IMX6Q_UART, 187fe6b540aSShawn Guo }; 188fe6b540aSShawn Guo 189fe6b540aSShawn Guo /* device type dependent stuff */ 190fe6b540aSShawn Guo struct imx_uart_data { 191fe6b540aSShawn Guo unsigned uts_reg; 192fe6b540aSShawn Guo enum imx_uart_type devtype; 193fe6b540aSShawn Guo }; 194fe6b540aSShawn Guo 195ab4382d2SGreg Kroah-Hartman struct imx_port { 196ab4382d2SGreg Kroah-Hartman struct uart_port port; 197ab4382d2SGreg Kroah-Hartman struct timer_list timer; 198ab4382d2SGreg Kroah-Hartman unsigned int old_status; 199ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2007b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20120ff2fe6SHuang Shijie unsigned int dte_mode:1; 2023a9465faSSascha Hauer struct clk *clk_ipg; 2033a9465faSSascha Hauer struct clk *clk_per; 2047d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 205b4cdc8f6SHuang Shijie 20658362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 20758362d5bSUwe Kleine-König 2083a0ab62fSUwe Kleine-König /* shadow registers */ 2093a0ab62fSUwe Kleine-König unsigned int ucr1; 2103a0ab62fSUwe Kleine-König unsigned int ucr2; 2113a0ab62fSUwe Kleine-König unsigned int ucr3; 2123a0ab62fSUwe Kleine-König unsigned int ucr4; 2133a0ab62fSUwe Kleine-König unsigned int ufcr; 2143a0ab62fSUwe Kleine-König 215b4cdc8f6SHuang Shijie /* DMA fields */ 216b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 217b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 218b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 219b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 220b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 221b4cdc8f6SHuang Shijie void *rx_buf; 2229d297239SNandor Han struct circ_buf rx_ring; 2239d297239SNandor Han unsigned int rx_periods; 2249d297239SNandor Han dma_cookie_t rx_cookie; 2257cb92fd2SHuang Shijie unsigned int tx_bytes; 226b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 22790bb6bd3SShenwei Wang unsigned int saved_reg[10]; 228c868cbb7SEduardo Valentin bool context_saved; 229ab4382d2SGreg Kroah-Hartman }; 230ab4382d2SGreg Kroah-Hartman 2310ad5a814SDirk Behme struct imx_port_ucrs { 2320ad5a814SDirk Behme unsigned int ucr1; 2330ad5a814SDirk Behme unsigned int ucr2; 2340ad5a814SDirk Behme unsigned int ucr3; 2350ad5a814SDirk Behme }; 2360ad5a814SDirk Behme 237fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 238fe6b540aSShawn Guo [IMX1_UART] = { 239fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 240fe6b540aSShawn Guo .devtype = IMX1_UART, 241fe6b540aSShawn Guo }, 242fe6b540aSShawn Guo [IMX21_UART] = { 243fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 244fe6b540aSShawn Guo .devtype = IMX21_UART, 245fe6b540aSShawn Guo }, 2461c06bde6SMartyn Welch [IMX53_UART] = { 2471c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2481c06bde6SMartyn Welch .devtype = IMX53_UART, 2491c06bde6SMartyn Welch }, 250a496e628SHuang Shijie [IMX6Q_UART] = { 251a496e628SHuang Shijie .uts_reg = IMX21_UTS, 252a496e628SHuang Shijie .devtype = IMX6Q_UART, 253a496e628SHuang Shijie }, 254fe6b540aSShawn Guo }; 255fe6b540aSShawn Guo 25631ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 257fe6b540aSShawn Guo { 258fe6b540aSShawn Guo .name = "imx1-uart", 259fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 260fe6b540aSShawn Guo }, { 261fe6b540aSShawn Guo .name = "imx21-uart", 262fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 263fe6b540aSShawn Guo }, { 2641c06bde6SMartyn Welch .name = "imx53-uart", 2651c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2661c06bde6SMartyn Welch }, { 267a496e628SHuang Shijie .name = "imx6q-uart", 268a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 269a496e628SHuang Shijie }, { 270fe6b540aSShawn Guo /* sentinel */ 271fe6b540aSShawn Guo } 272fe6b540aSShawn Guo }; 273fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 274fe6b540aSShawn Guo 275ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 276a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2771c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27822698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27922698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 28022698aa2SShawn Guo { /* sentinel */ } 28122698aa2SShawn Guo }; 28222698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28322698aa2SShawn Guo 28427c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 28527c84426SUwe Kleine-König { 2863a0ab62fSUwe Kleine-König switch (offset) { 2873a0ab62fSUwe Kleine-König case UCR1: 2883a0ab62fSUwe Kleine-König sport->ucr1 = val; 2893a0ab62fSUwe Kleine-König break; 2903a0ab62fSUwe Kleine-König case UCR2: 2913a0ab62fSUwe Kleine-König sport->ucr2 = val; 2923a0ab62fSUwe Kleine-König break; 2933a0ab62fSUwe Kleine-König case UCR3: 2943a0ab62fSUwe Kleine-König sport->ucr3 = val; 2953a0ab62fSUwe Kleine-König break; 2963a0ab62fSUwe Kleine-König case UCR4: 2973a0ab62fSUwe Kleine-König sport->ucr4 = val; 2983a0ab62fSUwe Kleine-König break; 2993a0ab62fSUwe Kleine-König case UFCR: 3003a0ab62fSUwe Kleine-König sport->ufcr = val; 3013a0ab62fSUwe Kleine-König break; 3023a0ab62fSUwe Kleine-König default: 3033a0ab62fSUwe Kleine-König break; 3043a0ab62fSUwe Kleine-König } 30527c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 30627c84426SUwe Kleine-König } 30727c84426SUwe Kleine-König 30827c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30927c84426SUwe Kleine-König { 3103a0ab62fSUwe Kleine-König switch (offset) { 3113a0ab62fSUwe Kleine-König case UCR1: 3123a0ab62fSUwe Kleine-König return sport->ucr1; 3133a0ab62fSUwe Kleine-König break; 3143a0ab62fSUwe Kleine-König case UCR2: 3153a0ab62fSUwe Kleine-König /* 3163a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3173a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 318728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 319728e74a4SUwe Kleine-König * conditionally. 3203a0ab62fSUwe Kleine-König */ 3210aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3223a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3233a0ab62fSUwe Kleine-König return sport->ucr2; 3243a0ab62fSUwe Kleine-König break; 3253a0ab62fSUwe Kleine-König case UCR3: 3263a0ab62fSUwe Kleine-König return sport->ucr3; 3273a0ab62fSUwe Kleine-König break; 3283a0ab62fSUwe Kleine-König case UCR4: 3293a0ab62fSUwe Kleine-König return sport->ucr4; 3303a0ab62fSUwe Kleine-König break; 3313a0ab62fSUwe Kleine-König case UFCR: 3323a0ab62fSUwe Kleine-König return sport->ufcr; 3333a0ab62fSUwe Kleine-König break; 3343a0ab62fSUwe Kleine-König default: 33527c84426SUwe Kleine-König return readl(sport->port.membase + offset); 33627c84426SUwe Kleine-König } 3373a0ab62fSUwe Kleine-König } 33827c84426SUwe Kleine-König 3399d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 340fe6b540aSShawn Guo { 341fe6b540aSShawn Guo return sport->devdata->uts_reg; 342fe6b540aSShawn Guo } 343fe6b540aSShawn Guo 3449d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 345fe6b540aSShawn Guo { 346fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 347fe6b540aSShawn Guo } 348fe6b540aSShawn Guo 3499d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 350fe6b540aSShawn Guo { 351fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 352fe6b540aSShawn Guo } 353fe6b540aSShawn Guo 3549d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3551c06bde6SMartyn Welch { 3561c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3571c06bde6SMartyn Welch } 3581c06bde6SMartyn Welch 3599d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 360a496e628SHuang Shijie { 361a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 362a496e628SHuang Shijie } 363ab4382d2SGreg Kroah-Hartman /* 36444a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 36544a75411Sfabio.estevam@freescale.com */ 36693d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 3679d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 36844a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36944a75411Sfabio.estevam@freescale.com { 37044a75411Sfabio.estevam@freescale.com /* save control registers */ 37127c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 37227c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 37327c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 37444a75411Sfabio.estevam@freescale.com } 37544a75411Sfabio.estevam@freescale.com 3769d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 37744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37844a75411Sfabio.estevam@freescale.com { 37944a75411Sfabio.estevam@freescale.com /* restore control registers */ 38027c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 38127c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 38227c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 38344a75411Sfabio.estevam@freescale.com } 384e8bfa760SFabio Estevam #endif 38544a75411Sfabio.estevam@freescale.com 3869d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 38758362d5bSUwe Kleine-König { 388bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38958362d5bSUwe Kleine-König 390a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 391a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39258362d5bSUwe Kleine-König } 39358362d5bSUwe Kleine-König 3949d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 39558362d5bSUwe Kleine-König { 396bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 397bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39858362d5bSUwe Kleine-König 399a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 400a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 40158362d5bSUwe Kleine-König } 40258362d5bSUwe Kleine-König 4039d1a50a2SUwe Kleine-König static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2) 40458362d5bSUwe Kleine-König { 40558362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 40658362d5bSUwe Kleine-König } 40758362d5bSUwe Kleine-König 4086aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4099d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 41076821e22SUwe Kleine-König { 41176821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 41276821e22SUwe Kleine-König unsigned int ucr1, ucr2; 41376821e22SUwe Kleine-König 41476821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 41576821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 41676821e22SUwe Kleine-König 41776821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41876821e22SUwe Kleine-König 41976821e22SUwe Kleine-König if (sport->dma_is_enabled) { 42076821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 42176821e22SUwe Kleine-König } else { 42276821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 42381ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 42476821e22SUwe Kleine-König } 42576821e22SUwe Kleine-König 42676821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 42776821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42876821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42976821e22SUwe Kleine-König } 43076821e22SUwe Kleine-König 43176821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4329d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 433ab4382d2SGreg Kroah-Hartman { 434ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4354444dcf1SUwe Kleine-König u32 ucr1; 436ab4382d2SGreg Kroah-Hartman 4379ce4f8f3SGreg Kroah-Hartman /* 4389ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4399ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4409ce4f8f3SGreg Kroah-Hartman */ 441686351f3SUwe Kleine-König if (sport->dma_is_txing) 4429ce4f8f3SGreg Kroah-Hartman return; 443b4cdc8f6SHuang Shijie 4444444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 4454444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1); 44617b8f2a3SUwe Kleine-König 44717b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 44817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 44927c84426SUwe Kleine-König imx_uart_readl(sport, USR2) & USR2_TXDC) { 4504444dcf1SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 45117b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4529d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4531a613626SFabio Estevam else 4549d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4554444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 45617b8f2a3SUwe Kleine-König 4579d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 45876821e22SUwe Kleine-König 4594444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 4604444dcf1SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 4614444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 46217b8f2a3SUwe Kleine-König } 463ab4382d2SGreg Kroah-Hartman } 464ab4382d2SGreg Kroah-Hartman 4656aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4669d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 467ab4382d2SGreg Kroah-Hartman { 468ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4694444dcf1SUwe Kleine-König u32 ucr1, ucr2; 470ab4382d2SGreg Kroah-Hartman 4714444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 47276821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 47376821e22SUwe Kleine-König 47476821e22SUwe Kleine-König if (sport->dma_is_enabled) { 47576821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 47676821e22SUwe Kleine-König } else { 47776821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 47881ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 47976821e22SUwe Kleine-König } 48076821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 48176821e22SUwe Kleine-König 48276821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 48376821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 484ab4382d2SGreg Kroah-Hartman } 485ab4382d2SGreg Kroah-Hartman 4866aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4879d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 488ab4382d2SGreg Kroah-Hartman { 489ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 490ab4382d2SGreg Kroah-Hartman 491ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 49258362d5bSUwe Kleine-König 49358362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 494ab4382d2SGreg Kroah-Hartman } 495ab4382d2SGreg Kroah-Hartman 4969d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 4976aed2a88SUwe Kleine-König 4986aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4999d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 500ab4382d2SGreg Kroah-Hartman { 501ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 502ab4382d2SGreg Kroah-Hartman 5035e42e9a3SPeter Hurley if (sport->port.x_char) { 5045e42e9a3SPeter Hurley /* Send next char */ 50527c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5067e2fb5aaSJiada Wang sport->port.icount.tx++; 5077e2fb5aaSJiada Wang sport->port.x_char = 0; 5085e42e9a3SPeter Hurley return; 5095e42e9a3SPeter Hurley } 5105e42e9a3SPeter Hurley 5115e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5129d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5135e42e9a3SPeter Hurley return; 5145e42e9a3SPeter Hurley } 5155e42e9a3SPeter Hurley 51691a1a909SJiada Wang if (sport->dma_is_enabled) { 5174444dcf1SUwe Kleine-König u32 ucr1; 51891a1a909SJiada Wang /* 51991a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 52091a1a909SJiada Wang * and the TX IRQ is disabled. 52191a1a909SJiada Wang **/ 5224444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5234444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXMPTYEN; 52491a1a909SJiada Wang if (sport->dma_is_txing) { 5254444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5264444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 52791a1a909SJiada Wang } else { 5284444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5299d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 53091a1a909SJiada Wang } 53191a1a909SJiada Wang 5325aabd3b0SIan Jamison return; 5330c549223SUwe Kleine-König } 5345aabd3b0SIan Jamison 5355aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5369d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 537ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 538ab4382d2SGreg Kroah-Hartman * out the port here */ 53927c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 540ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 541ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 542ab4382d2SGreg Kroah-Hartman } 543ab4382d2SGreg Kroah-Hartman 544ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 545ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 546ab4382d2SGreg Kroah-Hartman 547ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5489d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 549ab4382d2SGreg Kroah-Hartman } 550ab4382d2SGreg Kroah-Hartman 5519d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 552b4cdc8f6SHuang Shijie { 553b4cdc8f6SHuang Shijie struct imx_port *sport = data; 554b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 555b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 556b4cdc8f6SHuang Shijie unsigned long flags; 5574444dcf1SUwe Kleine-König u32 ucr1; 558b4cdc8f6SHuang Shijie 55942f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 56042f752b3SDirk Behme 561b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 562b4cdc8f6SHuang Shijie 5634444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5644444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5654444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 566a2c718ceSDirk Behme 56742f752b3SDirk Behme /* update the stat */ 56842f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 56942f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 57042f752b3SDirk Behme 57142f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 57242f752b3SDirk Behme 573b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 574b4cdc8f6SHuang Shijie 575d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 576b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5779ce4f8f3SGreg Kroah-Hartman 5780bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5799d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 58018665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 58118665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 58218665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 58318665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 58418665414SUwe Kleine-König } 58564432a85SUwe Kleine-König 5860bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 587b4cdc8f6SHuang Shijie } 588b4cdc8f6SHuang Shijie 5896aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5909d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 591b4cdc8f6SHuang Shijie { 592b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 593b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 594b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 595b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 596b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 59718665414SUwe Kleine-König u32 ucr1, ucr4; 598b4cdc8f6SHuang Shijie int ret; 599b4cdc8f6SHuang Shijie 60042f752b3SDirk Behme if (sport->dma_is_txing) 601b4cdc8f6SHuang Shijie return; 602b4cdc8f6SHuang Shijie 60318665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 60418665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 60518665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 60618665414SUwe Kleine-König 607b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 608b4cdc8f6SHuang Shijie 6097942f857SDirk Behme if (xmit->tail < xmit->head) { 6107942f857SDirk Behme sport->dma_tx_nents = 1; 6117942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6127942f857SDirk Behme } else { 613b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 614b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 615b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 616b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 617b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 618b4cdc8f6SHuang Shijie } 619b4cdc8f6SHuang Shijie 620b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 621b4cdc8f6SHuang Shijie if (ret == 0) { 622b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 623b4cdc8f6SHuang Shijie return; 624b4cdc8f6SHuang Shijie } 625b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 626b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 627b4cdc8f6SHuang Shijie if (!desc) { 62824649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 62924649821SDirk Behme DMA_TO_DEVICE); 630b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 631b4cdc8f6SHuang Shijie return; 632b4cdc8f6SHuang Shijie } 6339d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 634b4cdc8f6SHuang Shijie desc->callback_param = sport; 635b4cdc8f6SHuang Shijie 636b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 637b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 638a2c718ceSDirk Behme 6394444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6404444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6414444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 642a2c718ceSDirk Behme 643b4cdc8f6SHuang Shijie /* fire it */ 644b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 645b4cdc8f6SHuang Shijie dmaengine_submit(desc); 646b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 647b4cdc8f6SHuang Shijie return; 648b4cdc8f6SHuang Shijie } 649b4cdc8f6SHuang Shijie 6506aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6519d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 652ab4382d2SGreg Kroah-Hartman { 653ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6544444dcf1SUwe Kleine-König u32 ucr1; 655ab4382d2SGreg Kroah-Hartman 65648669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 65748669b69SUwe Kleine-König return; 65848669b69SUwe Kleine-König 65917b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 66018665414SUwe Kleine-König u32 ucr2; 6614444dcf1SUwe Kleine-König 6624444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 66317b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6649d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 6651a613626SFabio Estevam else 6669d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 6674444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 66817b8f2a3SUwe Kleine-König 66976821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 6709d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 67176821e22SUwe Kleine-König 67218665414SUwe Kleine-König /* 67318665414SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA is off. 67418665414SUwe Kleine-König * In the DMA case this is done in the tx-callback. 67518665414SUwe Kleine-König */ 67618665414SUwe Kleine-König if (!sport->dma_is_enabled) { 67718665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 6784444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 6794444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 68017b8f2a3SUwe Kleine-König } 68118665414SUwe Kleine-König } 68217b8f2a3SUwe Kleine-König 683b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 6844444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6854444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1); 686b4cdc8f6SHuang Shijie } 687ab4382d2SGreg Kroah-Hartman 688b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 68991a1a909SJiada Wang if (sport->port.x_char) { 69091a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 69191a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 6924444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6934444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 6944444dcf1SUwe Kleine-König ucr1 |= UCR1_TXMPTYEN; 6954444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 69691a1a909SJiada Wang return; 69791a1a909SJiada Wang } 69891a1a909SJiada Wang 6995e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 7005e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7019d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 702b4cdc8f6SHuang Shijie return; 703b4cdc8f6SHuang Shijie } 704ab4382d2SGreg Kroah-Hartman } 705ab4382d2SGreg Kroah-Hartman 7069d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 707ab4382d2SGreg Kroah-Hartman { 708ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7094444dcf1SUwe Kleine-König u32 usr1; 710ab4382d2SGreg Kroah-Hartman 711c974991dSjun qian spin_lock(&sport->port.lock); 712ab4382d2SGreg Kroah-Hartman 71327c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7144444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7154444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 716ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 717ab4382d2SGreg Kroah-Hartman 718c974991dSjun qian spin_unlock(&sport->port.lock); 719ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 720ab4382d2SGreg Kroah-Hartman } 721ab4382d2SGreg Kroah-Hartman 7229d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 723ab4382d2SGreg Kroah-Hartman { 724ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 725ab4382d2SGreg Kroah-Hartman 726c974991dSjun qian spin_lock(&sport->port.lock); 7279d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 728c974991dSjun qian spin_unlock(&sport->port.lock); 729ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 730ab4382d2SGreg Kroah-Hartman } 731ab4382d2SGreg Kroah-Hartman 7329d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 733ab4382d2SGreg Kroah-Hartman { 734ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 735ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 73692a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 737ab4382d2SGreg Kroah-Hartman 738c974991dSjun qian spin_lock(&sport->port.lock); 739ab4382d2SGreg Kroah-Hartman 74027c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 7414444dcf1SUwe Kleine-König u32 usr2; 7424444dcf1SUwe Kleine-König 743ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 744ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 745ab4382d2SGreg Kroah-Hartman 74627c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 747ab4382d2SGreg Kroah-Hartman 7484444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 7494444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 75027c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 751ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 752ab4382d2SGreg Kroah-Hartman continue; 753ab4382d2SGreg Kroah-Hartman } 754ab4382d2SGreg Kroah-Hartman 755ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 756ab4382d2SGreg Kroah-Hartman continue; 757ab4382d2SGreg Kroah-Hartman 758019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 759019dc9eaSHui Wang if (rx & URXD_BRK) 760019dc9eaSHui Wang sport->port.icount.brk++; 761019dc9eaSHui Wang else if (rx & URXD_PRERR) 762ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 763ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 764ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 765ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 766ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 767ab4382d2SGreg Kroah-Hartman 768ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 769ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 770ab4382d2SGreg Kroah-Hartman goto out; 771ab4382d2SGreg Kroah-Hartman continue; 772ab4382d2SGreg Kroah-Hartman } 773ab4382d2SGreg Kroah-Hartman 7748d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 775ab4382d2SGreg Kroah-Hartman 776019dc9eaSHui Wang if (rx & URXD_BRK) 777019dc9eaSHui Wang flg = TTY_BREAK; 778019dc9eaSHui Wang else if (rx & URXD_PRERR) 779ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 780ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 781ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 782ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 783ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 784ab4382d2SGreg Kroah-Hartman 785ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 786ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 787ab4382d2SGreg Kroah-Hartman #endif 788ab4382d2SGreg Kroah-Hartman } 789ab4382d2SGreg Kroah-Hartman 79055d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 79155d8693aSJiada Wang goto out; 79255d8693aSJiada Wang 7939b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 7949b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 795ab4382d2SGreg Kroah-Hartman } 796ab4382d2SGreg Kroah-Hartman 797ab4382d2SGreg Kroah-Hartman out: 798c974991dSjun qian spin_unlock(&sport->port.lock); 7992e124b4aSJiri Slaby tty_flip_buffer_push(port); 800ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 801ab4382d2SGreg Kroah-Hartman } 802ab4382d2SGreg Kroah-Hartman 8039d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 804b4cdc8f6SHuang Shijie 80566f95884SUwe Kleine-König /* 80666f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 80766f95884SUwe Kleine-König */ 8089d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 80966f95884SUwe Kleine-König { 81066f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 81127c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 81227c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 81366f95884SUwe Kleine-König 81466f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 81566f95884SUwe Kleine-König tmp |= TIOCM_CTS; 81666f95884SUwe Kleine-König 81766f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 8184b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 81966f95884SUwe Kleine-König tmp |= TIOCM_CAR; 82066f95884SUwe Kleine-König 82166f95884SUwe Kleine-König if (sport->dte_mode) 82227c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 82366f95884SUwe Kleine-König tmp |= TIOCM_RI; 82466f95884SUwe Kleine-König 82566f95884SUwe Kleine-König return tmp; 82666f95884SUwe Kleine-König } 82766f95884SUwe Kleine-König 82866f95884SUwe Kleine-König /* 82966f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 83066f95884SUwe Kleine-König */ 8319d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 83266f95884SUwe Kleine-König { 83366f95884SUwe Kleine-König unsigned int status, changed; 83466f95884SUwe Kleine-König 8359d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 83666f95884SUwe Kleine-König changed = status ^ sport->old_status; 83766f95884SUwe Kleine-König 83866f95884SUwe Kleine-König if (changed == 0) 83966f95884SUwe Kleine-König return; 84066f95884SUwe Kleine-König 84166f95884SUwe Kleine-König sport->old_status = status; 84266f95884SUwe Kleine-König 84366f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 84466f95884SUwe Kleine-König sport->port.icount.rng++; 84566f95884SUwe Kleine-König if (changed & TIOCM_DSR) 84666f95884SUwe Kleine-König sport->port.icount.dsr++; 84766f95884SUwe Kleine-König if (changed & TIOCM_CAR) 84866f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 84966f95884SUwe Kleine-König if (changed & TIOCM_CTS) 85066f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 85166f95884SUwe Kleine-König 85266f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 85366f95884SUwe Kleine-König } 85466f95884SUwe Kleine-König 8559d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 856ab4382d2SGreg Kroah-Hartman { 857ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 85843776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 8594d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 860ab4382d2SGreg Kroah-Hartman 86127c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 86227c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 86327c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 86427c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 86527c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 86627c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 867ab4382d2SGreg Kroah-Hartman 86843776896SUwe Kleine-König /* 86943776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 87043776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 87143776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 87243776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 87343776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 87443776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 87543776896SUwe Kleine-König */ 87643776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 87743776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 87843776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 87943776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 88043776896SUwe Kleine-König if ((ucr1 & UCR1_TXMPTYEN) == 0) 88143776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 88243776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 88343776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 88443776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 88543776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 88643776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 88743776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 88843776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 88943776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 89043776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 89143776896SUwe Kleine-König usr2 &= ~USR2_ORE; 89243776896SUwe Kleine-König 89343776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 8949d1a50a2SUwe Kleine-König imx_uart_rxint(irq, dev_id); 8954d845a62SUwe Kleine-König ret = IRQ_HANDLED; 896b4cdc8f6SHuang Shijie } 897ab4382d2SGreg Kroah-Hartman 89843776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 8999d1a50a2SUwe Kleine-König imx_uart_txint(irq, dev_id); 9004d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9014d845a62SUwe Kleine-König } 902ab4382d2SGreg Kroah-Hartman 9030399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 90427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 90527e16501SUwe Kleine-König 906c974991dSjun qian spin_lock(&sport->port.lock); 9079d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 908c974991dSjun qian spin_unlock(&sport->port.lock); 90927e16501SUwe Kleine-König 91027e16501SUwe Kleine-König ret = IRQ_HANDLED; 91127e16501SUwe Kleine-König } 91227e16501SUwe Kleine-König 9130399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 9149d1a50a2SUwe Kleine-König imx_uart_rtsint(irq, dev_id); 9154d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9164d845a62SUwe Kleine-König } 917ab4382d2SGreg Kroah-Hartman 9180399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 91927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 9204d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9214d845a62SUwe Kleine-König } 922db1a9b55SFabio Estevam 9230399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 924f1f836e4SAlexander Stein sport->port.icount.overrun++; 92527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 9264d845a62SUwe Kleine-König ret = IRQ_HANDLED; 927f1f836e4SAlexander Stein } 928f1f836e4SAlexander Stein 9294d845a62SUwe Kleine-König return ret; 930ab4382d2SGreg Kroah-Hartman } 931ab4382d2SGreg Kroah-Hartman 932ab4382d2SGreg Kroah-Hartman /* 933ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 934ab4382d2SGreg Kroah-Hartman */ 9359d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 936ab4382d2SGreg Kroah-Hartman { 937ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9381ce43e58SHuang Shijie unsigned int ret; 939ab4382d2SGreg Kroah-Hartman 94027c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 9411ce43e58SHuang Shijie 9421ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 943686351f3SUwe Kleine-König if (sport->dma_is_txing) 9441ce43e58SHuang Shijie ret = 0; 9451ce43e58SHuang Shijie 9461ce43e58SHuang Shijie return ret; 947ab4382d2SGreg Kroah-Hartman } 948ab4382d2SGreg Kroah-Hartman 9496aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 9509d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 95158362d5bSUwe Kleine-König { 95258362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 9539d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 95458362d5bSUwe Kleine-König 95558362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 95658362d5bSUwe Kleine-König 95758362d5bSUwe Kleine-König return ret; 95858362d5bSUwe Kleine-König } 95958362d5bSUwe Kleine-König 9606aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 9619d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 962ab4382d2SGreg Kroah-Hartman { 963ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9644444dcf1SUwe Kleine-König u32 ucr3, uts; 965ab4382d2SGreg Kroah-Hartman 96617b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 9674444dcf1SUwe Kleine-König u32 ucr2; 9684444dcf1SUwe Kleine-König 9694444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 9704444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 971ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 9724444dcf1SUwe Kleine-König ucr2 |= UCR2_CTS | UCR2_CTSC; 9734444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 97417b8f2a3SUwe Kleine-König } 9756b471a98SHuang Shijie 9764444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 97790ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 9784444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 9794444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 98090ebc483SUwe Kleine-König 9819d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 9826b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 9834444dcf1SUwe Kleine-König uts |= UTS_LOOP; 9849d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 98558362d5bSUwe Kleine-König 98658362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 987ab4382d2SGreg Kroah-Hartman } 988ab4382d2SGreg Kroah-Hartman 989ab4382d2SGreg Kroah-Hartman /* 990ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 991ab4382d2SGreg Kroah-Hartman */ 9929d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 993ab4382d2SGreg Kroah-Hartman { 994ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9954444dcf1SUwe Kleine-König unsigned long flags; 9964444dcf1SUwe Kleine-König u32 ucr1; 997ab4382d2SGreg Kroah-Hartman 998ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 999ab4382d2SGreg Kroah-Hartman 10004444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1001ab4382d2SGreg Kroah-Hartman 1002ab4382d2SGreg Kroah-Hartman if (break_state != 0) 10034444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1004ab4382d2SGreg Kroah-Hartman 10054444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1006ab4382d2SGreg Kroah-Hartman 1007ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1008ab4382d2SGreg Kroah-Hartman } 1009ab4382d2SGreg Kroah-Hartman 1010cc568849SUwe Kleine-König /* 1011cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1012cc568849SUwe Kleine-König * modem status signals. 1013cc568849SUwe Kleine-König */ 10149d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1015cc568849SUwe Kleine-König { 1016e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1017cc568849SUwe Kleine-König unsigned long flags; 1018cc568849SUwe Kleine-König 1019cc568849SUwe Kleine-König if (sport->port.state) { 1020cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 10219d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1022cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1023cc568849SUwe Kleine-König 1024cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1025cc568849SUwe Kleine-König } 1026cc568849SUwe Kleine-König } 1027cc568849SUwe Kleine-König 1028351ea50dSGreg Kroah-Hartman #define RX_BUF_SIZE (PAGE_SIZE) 1029351ea50dSGreg Kroah-Hartman 1030b4cdc8f6SHuang Shijie /* 1031905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1032b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1033905c0decSLucas Stach * [2] the aging timer expires 1034b4cdc8f6SHuang Shijie * 1035905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1036905c0decSLucas Stach * for at least 8 byte durations. 1037b4cdc8f6SHuang Shijie */ 10389d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1039b4cdc8f6SHuang Shijie { 1040b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1041b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1042b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 10437cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1044b4cdc8f6SHuang Shijie struct dma_tx_state state; 10459d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1046b4cdc8f6SHuang Shijie enum dma_status status; 10479d297239SNandor Han unsigned int w_bytes = 0; 10489d297239SNandor Han unsigned int r_bytes; 10499d297239SNandor Han unsigned int bd_size; 1050b4cdc8f6SHuang Shijie 1051fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1052392bceedSPhilipp Zabel 10539d297239SNandor Han if (status == DMA_ERROR) { 10549d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 10559d297239SNandor Han return; 10569d297239SNandor Han } 1057b4cdc8f6SHuang Shijie 10589b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1059976b39cdSLucas Stach 1060976b39cdSLucas Stach /* 10619d297239SNandor Han * The state-residue variable represents the empty space 10629d297239SNandor Han * relative to the entire buffer. Taking this in consideration 10639d297239SNandor Han * the head is always calculated base on the buffer total 10649d297239SNandor Han * length - DMA transaction residue. The UART script from the 10659d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 10669d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 10679d297239SNandor Han * Taking this in consideration the tail is always at the 10689d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1069976b39cdSLucas Stach */ 10709d297239SNandor Han 10719d297239SNandor Han /* Calculate the head */ 10729d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 10739d297239SNandor Han 10749d297239SNandor Han /* Calculate the tail. */ 10759d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 10769d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 10779d297239SNandor Han 10789d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 10799d297239SNandor Han rx_ring->head > rx_ring->tail) { 10809d297239SNandor Han 10819d297239SNandor Han /* Move data from tail to head */ 10829d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 10839d297239SNandor Han 10849d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 10859d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 10869d297239SNandor Han DMA_FROM_DEVICE); 10879d297239SNandor Han 10889d297239SNandor Han w_bytes = tty_insert_flip_string(port, 10899d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 10909d297239SNandor Han 10919d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 10929d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 10939d297239SNandor Han DMA_FROM_DEVICE); 10949d297239SNandor Han 10959d297239SNandor Han if (w_bytes != r_bytes) 10969d297239SNandor Han sport->port.icount.buf_overrun++; 10979d297239SNandor Han 10989d297239SNandor Han sport->port.icount.rx += w_bytes; 10999d297239SNandor Han } else { 11009d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11019d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1102ee5e7c10SRobin Gong } 11039d297239SNandor Han } 11049d297239SNandor Han 11059d297239SNandor Han if (w_bytes) { 11069d297239SNandor Han tty_flip_buffer_push(port); 11079d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 11089d297239SNandor Han } 11099d297239SNandor Han } 11109d297239SNandor Han 1111351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 1112351ea50dSGreg Kroah-Hartman #define RX_DMA_PERIODS 4 1113351ea50dSGreg Kroah-Hartman 11149d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1115b4cdc8f6SHuang Shijie { 1116b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1117b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1118b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1119b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1120b4cdc8f6SHuang Shijie int ret; 1121b4cdc8f6SHuang Shijie 11229d297239SNandor Han sport->rx_ring.head = 0; 11239d297239SNandor Han sport->rx_ring.tail = 0; 1124351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 11259d297239SNandor Han 1126351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1127b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1128b4cdc8f6SHuang Shijie if (ret == 0) { 1129b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1130b4cdc8f6SHuang Shijie return -EINVAL; 1131b4cdc8f6SHuang Shijie } 11329d297239SNandor Han 11339d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 11349d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 11359d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 11369d297239SNandor Han 1137b4cdc8f6SHuang Shijie if (!desc) { 113824649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1139b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1140b4cdc8f6SHuang Shijie return -EINVAL; 1141b4cdc8f6SHuang Shijie } 11429d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1143b4cdc8f6SHuang Shijie desc->callback_param = sport; 1144b4cdc8f6SHuang Shijie 1145b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 11464139fd76SRomain Perier sport->dma_is_rxing = 1; 11479d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1148b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1149b4cdc8f6SHuang Shijie return 0; 1150b4cdc8f6SHuang Shijie } 1151b4cdc8f6SHuang Shijie 11529d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 115341d98b5dSNandor Han { 115445ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 11554444dcf1SUwe Kleine-König u32 usr1, usr2; 115641d98b5dSNandor Han 11574444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 11584444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 115941d98b5dSNandor Han 11604444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 116141d98b5dSNandor Han sport->port.icount.brk++; 116227c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 116345ca673eSTroy Kisky uart_handle_break(&sport->port); 116445ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 116545ca673eSTroy Kisky sport->port.icount.buf_overrun++; 116645ca673eSTroy Kisky tty_flip_buffer_push(port); 116745ca673eSTroy Kisky } else { 116845ca673eSTroy Kisky dev_err(sport->port.dev, "DMA transaction error.\n"); 11694444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 117041d98b5dSNandor Han sport->port.icount.frame++; 117127c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 11724444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 117341d98b5dSNandor Han sport->port.icount.parity++; 117427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 117541d98b5dSNandor Han } 117645ca673eSTroy Kisky } 117741d98b5dSNandor Han 11784444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 117941d98b5dSNandor Han sport->port.icount.overrun++; 118027c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 118141d98b5dSNandor Han } 118241d98b5dSNandor Han 118341d98b5dSNandor Han } 118441d98b5dSNandor Han 1185cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1186cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1187184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1188184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1189cc32382dSLucas Stach 11909d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1191cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1192cc32382dSLucas Stach { 1193cc32382dSLucas Stach unsigned int val; 1194cc32382dSLucas Stach 1195cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 119627c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1197cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 119827c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1199cc32382dSLucas Stach } 1200cc32382dSLucas Stach 1201b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1202b4cdc8f6SHuang Shijie { 1203b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1204e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1205b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1206b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 12079d297239SNandor Han sport->rx_cookie = -EINVAL; 1208b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1209b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1210b4cdc8f6SHuang Shijie } 1211b4cdc8f6SHuang Shijie 1212b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1213e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1214b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1215b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1216b4cdc8f6SHuang Shijie } 1217b4cdc8f6SHuang Shijie } 1218b4cdc8f6SHuang Shijie 1219b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1220b4cdc8f6SHuang Shijie { 1221b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1222b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1223b4cdc8f6SHuang Shijie int ret; 1224b4cdc8f6SHuang Shijie 1225b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1226b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1227b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1228b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1229b4cdc8f6SHuang Shijie ret = -EINVAL; 1230b4cdc8f6SHuang Shijie goto err; 1231b4cdc8f6SHuang Shijie } 1232b4cdc8f6SHuang Shijie 1233b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1234b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1235b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1236184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1237184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1238b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1239b4cdc8f6SHuang Shijie if (ret) { 1240b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1241b4cdc8f6SHuang Shijie goto err; 1242b4cdc8f6SHuang Shijie } 1243b4cdc8f6SHuang Shijie 1244f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1245b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1246b4cdc8f6SHuang Shijie ret = -ENOMEM; 1247b4cdc8f6SHuang Shijie goto err; 1248b4cdc8f6SHuang Shijie } 12499d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1250b4cdc8f6SHuang Shijie 1251b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1252b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1253b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1254b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1255b4cdc8f6SHuang Shijie ret = -EINVAL; 1256b4cdc8f6SHuang Shijie goto err; 1257b4cdc8f6SHuang Shijie } 1258b4cdc8f6SHuang Shijie 1259b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1260b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1261b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1262184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1263b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1264b4cdc8f6SHuang Shijie if (ret) { 1265b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1266b4cdc8f6SHuang Shijie goto err; 1267b4cdc8f6SHuang Shijie } 1268b4cdc8f6SHuang Shijie 1269b4cdc8f6SHuang Shijie return 0; 1270b4cdc8f6SHuang Shijie err: 1271b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1272b4cdc8f6SHuang Shijie return ret; 1273b4cdc8f6SHuang Shijie } 1274b4cdc8f6SHuang Shijie 12759d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1276b4cdc8f6SHuang Shijie { 12774444dcf1SUwe Kleine-König u32 ucr1; 1278b4cdc8f6SHuang Shijie 12799d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 128002b0abd3SUwe Kleine-König 1281b4cdc8f6SHuang Shijie /* set UCR1 */ 12824444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12834444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 12844444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1285b4cdc8f6SHuang Shijie 1286b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1287b4cdc8f6SHuang Shijie } 1288b4cdc8f6SHuang Shijie 12899d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1290b4cdc8f6SHuang Shijie { 1291676a31d8SSebastian Reichel u32 ucr1; 1292b4cdc8f6SHuang Shijie 1293b4cdc8f6SHuang Shijie /* clear UCR1 */ 12944444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12954444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 12964444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1297b4cdc8f6SHuang Shijie 12989d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1299184bd70bSLucas Stach 1300b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1301b4cdc8f6SHuang Shijie } 1302b4cdc8f6SHuang Shijie 1303ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1304ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1305ab4382d2SGreg Kroah-Hartman 13069d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1307ab4382d2SGreg Kroah-Hartman { 1308ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1309458e2c82SFabio Estevam int retval, i; 13104444dcf1SUwe Kleine-König unsigned long flags; 13114238c00bSUwe Kleine-König int dma_is_inited = 0; 13124444dcf1SUwe Kleine-König u32 ucr1, ucr2, ucr4; 1313ab4382d2SGreg Kroah-Hartman 131428eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 131528eb4274SHuang Shijie if (retval) 1316cb0f0a5fSFabio Estevam return retval; 131728eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 13180c375501SHuang Shijie if (retval) { 13190c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1320cb0f0a5fSFabio Estevam return retval; 13210c375501SHuang Shijie } 132228eb4274SHuang Shijie 13239d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1324ab4382d2SGreg Kroah-Hartman 1325ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1326ab4382d2SGreg Kroah-Hartman * requesting IRQs 1327ab4382d2SGreg Kroah-Hartman */ 13284444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1329ab4382d2SGreg Kroah-Hartman 1330ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 13314444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 13324444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1333ab4382d2SGreg Kroah-Hartman 13344444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1335ab4382d2SGreg Kroah-Hartman 13367e11577eSLucas Stach /* Can we enable the DMA support? */ 13374238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 13384238c00bSUwe Kleine-König dma_is_inited = 1; 13397e11577eSLucas Stach 134053794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1341772f8991SHuang Shijie /* Reset fifo's and state machines */ 1342458e2c82SFabio Estevam i = 100; 1343458e2c82SFabio Estevam 13444444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 13454444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 13464444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1347458e2c82SFabio Estevam 134827c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1349458e2c82SFabio Estevam udelay(1); 1350ab4382d2SGreg Kroah-Hartman 1351ab4382d2SGreg Kroah-Hartman /* 1352ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1353ab4382d2SGreg Kroah-Hartman */ 135427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 135527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1356ab4382d2SGreg Kroah-Hartman 13574444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 13584444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 13596376cd39SNandor Han if (sport->have_rtscts) 13604444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1361ab4382d2SGreg Kroah-Hartman 13624444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1363ab4382d2SGreg Kroah-Hartman 13644444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 13651f043572STroy Kisky if (!sport->dma_is_enabled) 13664444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 13674444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 13686f026d6bSJiada Wang 13694444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 13704444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1371bff09b09SLucas Stach if (!sport->have_rtscts) 13724444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 137316804d68SUwe Kleine-König /* 137416804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 137516804d68SUwe Kleine-König * we're using RTSD instead. 137616804d68SUwe Kleine-König */ 13779d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 13784444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 13794444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1380ab4382d2SGreg Kroah-Hartman 13819d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) { 13824444dcf1SUwe Kleine-König u32 ucr3; 138316804d68SUwe Kleine-König 13844444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 13854444dcf1SUwe Kleine-König 13864444dcf1SUwe Kleine-König ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 138716804d68SUwe Kleine-König 138816804d68SUwe Kleine-König if (sport->dte_mode) 1389e61c38d8SUwe Kleine-König /* disable broken interrupts */ 13904444dcf1SUwe Kleine-König ucr3 &= ~(UCR3_RI | UCR3_DCD); 139116804d68SUwe Kleine-König 13924444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 1393ab4382d2SGreg Kroah-Hartman } 1394ab4382d2SGreg Kroah-Hartman 1395ab4382d2SGreg Kroah-Hartman /* 1396ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1397ab4382d2SGreg Kroah-Hartman */ 13989d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 139918a42088SPeter Senna Tschudin 140076821e22SUwe Kleine-König if (dma_is_inited) { 14019d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 14029d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 140376821e22SUwe Kleine-König } else { 140476821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 140576821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 140676821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 140781ca8e82SUwe Kleine-König 140881ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 140981ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 141081ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 141176821e22SUwe Kleine-König } 141218a42088SPeter Senna Tschudin 1413ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1414ab4382d2SGreg Kroah-Hartman 1415ab4382d2SGreg Kroah-Hartman return 0; 1416ab4382d2SGreg Kroah-Hartman } 1417ab4382d2SGreg Kroah-Hartman 14189d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1419ab4382d2SGreg Kroah-Hartman { 1420ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 14219ec1882dSXinyu Chen unsigned long flags; 1422339c7a87SSebastian Reichel u32 ucr1, ucr2, ucr4; 1423ab4382d2SGreg Kroah-Hartman 1424b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1425e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 14267722c240SSebastian Reichel if (sport->dma_is_txing) { 14277722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 14287722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 14297722c240SSebastian Reichel sport->dma_is_txing = 0; 14307722c240SSebastian Reichel } 1431e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 14327722c240SSebastian Reichel if (sport->dma_is_rxing) { 14337722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 14347722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 14357722c240SSebastian Reichel sport->dma_is_rxing = 0; 14367722c240SSebastian Reichel } 14379d297239SNandor Han 143873631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 14399d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 14409d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 14419d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 144273631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1443b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1444b4cdc8f6SHuang Shijie } 1445b4cdc8f6SHuang Shijie 144658362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 144758362d5bSUwe Kleine-König 14489ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14494444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14500fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 14514444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1452339c7a87SSebastian Reichel 1453339c7a87SSebastian Reichel ucr4 = imx_uart_readl(sport, UCR4); 1454339c7a87SSebastian Reichel ucr4 &= ~UCR4_OREN; 1455339c7a87SSebastian Reichel imx_uart_writel(sport, ucr4, UCR4); 14569ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1457ab4382d2SGreg Kroah-Hartman 1458ab4382d2SGreg Kroah-Hartman /* 1459ab4382d2SGreg Kroah-Hartman * Stop our timer. 1460ab4382d2SGreg Kroah-Hartman */ 1461ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1462ab4382d2SGreg Kroah-Hartman 1463ab4382d2SGreg Kroah-Hartman /* 1464ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1465ab4382d2SGreg Kroah-Hartman */ 1466ab4382d2SGreg Kroah-Hartman 14679ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14684444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 146976821e22SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1470ab4382d2SGreg Kroah-Hartman 14714444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14729ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 147328eb4274SHuang Shijie 147428eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 147528eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1476ab4382d2SGreg Kroah-Hartman } 1477ab4382d2SGreg Kroah-Hartman 14786aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 14799d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1480eb56b7edSHuang Shijie { 1481eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 148282e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 14834444dcf1SUwe Kleine-König u32 ucr2; 14844f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1485eb56b7edSHuang Shijie 148682e86ae9SDirk Behme if (!sport->dma_chan_tx) 148782e86ae9SDirk Behme return; 148882e86ae9SDirk Behme 1489eb56b7edSHuang Shijie sport->tx_bytes = 0; 1490eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 149182e86ae9SDirk Behme if (sport->dma_is_txing) { 14924444dcf1SUwe Kleine-König u32 ucr1; 14934444dcf1SUwe Kleine-König 149482e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 149582e86ae9SDirk Behme DMA_TO_DEVICE); 14964444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 14974444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 14984444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14990f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1500eb56b7edSHuang Shijie } 1501934084a9SFabio Estevam 1502934084a9SFabio Estevam /* 1503934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1504263763c1SMartyn Welch * 1505934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1506934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1507263763c1SMartyn Welch * and UTS[6-3]". 1508263763c1SMartyn Welch * 1509263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1510263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1511263763c1SMartyn Welch * registers. 1512934084a9SFabio Estevam */ 151327c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 151427c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 151527c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1516934084a9SFabio Estevam 15174444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15184444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 15194444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1520934084a9SFabio Estevam 152127c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1522934084a9SFabio Estevam udelay(1); 1523934084a9SFabio Estevam 1524934084a9SFabio Estevam /* Restore the registers */ 152527c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 152627c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 152727c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1528eb56b7edSHuang Shijie } 1529eb56b7edSHuang Shijie 1530ab4382d2SGreg Kroah-Hartman static void 15319d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1532ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1533ab4382d2SGreg Kroah-Hartman { 1534ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1535ab4382d2SGreg Kroah-Hartman unsigned long flags; 15364444dcf1SUwe Kleine-König u32 ucr2, old_ucr1, old_ucr2, ufcr; 153758362d5bSUwe Kleine-König unsigned int baud, quot; 1538ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 15394444dcf1SUwe Kleine-König unsigned long div; 1540ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1541ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1542ab4382d2SGreg Kroah-Hartman 1543ab4382d2SGreg Kroah-Hartman /* 1544ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1545ab4382d2SGreg Kroah-Hartman */ 1546ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1547ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1548ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1549ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1550ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1551ab4382d2SGreg Kroah-Hartman } 1552ab4382d2SGreg Kroah-Hartman 1553ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1554ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1555ab4382d2SGreg Kroah-Hartman else 1556ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1557ab4382d2SGreg Kroah-Hartman 1558ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1559ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1560ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 156117b8f2a3SUwe Kleine-König 156212fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 156317b8f2a3SUwe Kleine-König /* 156417b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 156517b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 156617b8f2a3SUwe Kleine-König * disabled. 156717b8f2a3SUwe Kleine-König */ 156858362d5bSUwe Kleine-König if (port->rs485.flags & 156958362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 15709d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 15711a613626SFabio Estevam else 15729d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 157312fe59f9SFabio Estevam } else { 15749d1a50a2SUwe Kleine-König imx_uart_rts_auto(sport, &ucr2); 157512fe59f9SFabio Estevam } 1576ab4382d2SGreg Kroah-Hartman } else { 1577ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1578ab4382d2SGreg Kroah-Hartman } 157958362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 158017b8f2a3SUwe Kleine-König /* disable transmitter */ 158158362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 15829d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 15831a613626SFabio Estevam else 15849d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 158558362d5bSUwe Kleine-König } 158658362d5bSUwe Kleine-König 1587ab4382d2SGreg Kroah-Hartman 1588ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1589ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1590ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1591ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1592ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1593ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1594ab4382d2SGreg Kroah-Hartman } 1595ab4382d2SGreg Kroah-Hartman 1596995234daSEric Miao del_timer_sync(&sport->timer); 1597995234daSEric Miao 1598ab4382d2SGreg Kroah-Hartman /* 1599ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1600ab4382d2SGreg Kroah-Hartman */ 1601ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1602ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1603ab4382d2SGreg Kroah-Hartman 1604ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1605ab4382d2SGreg Kroah-Hartman 1606ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1607ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1608ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1609ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1610ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1611ab4382d2SGreg Kroah-Hartman 1612ab4382d2SGreg Kroah-Hartman /* 1613ab4382d2SGreg Kroah-Hartman * Characters to ignore 1614ab4382d2SGreg Kroah-Hartman */ 1615ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1616ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1617865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1618ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1619ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1620ab4382d2SGreg Kroah-Hartman /* 1621ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1622ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1623ab4382d2SGreg Kroah-Hartman */ 1624ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1625ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1626ab4382d2SGreg Kroah-Hartman } 1627ab4382d2SGreg Kroah-Hartman 162855d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 162955d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 163055d8693aSJiada Wang 1631ab4382d2SGreg Kroah-Hartman /* 1632ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1633ab4382d2SGreg Kroah-Hartman */ 1634ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1635ab4382d2SGreg Kroah-Hartman 1636ab4382d2SGreg Kroah-Hartman /* 1637ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1638ab4382d2SGreg Kroah-Hartman */ 163927c84426SUwe Kleine-König old_ucr1 = imx_uart_readl(sport, UCR1); 164027c84426SUwe Kleine-König imx_uart_writel(sport, 164127c84426SUwe Kleine-König old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 164227c84426SUwe Kleine-König UCR1); 164381ca8e82SUwe Kleine-König old_ucr2 = imx_uart_readl(sport, UCR2); 164481ca8e82SUwe Kleine-König imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2); 1645ab4382d2SGreg Kroah-Hartman 164627c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)) 1647ab4382d2SGreg Kroah-Hartman barrier(); 1648ab4382d2SGreg Kroah-Hartman 1649ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 165081ca8e82SUwe Kleine-König imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2); 165186a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1652ab4382d2SGreg Kroah-Hartman 165309bd00f6SHubert Feurstein /* custom-baudrate handling */ 165409bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 165509bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 165609bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 165709bd00f6SHubert Feurstein 1658ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1659ab4382d2SGreg Kroah-Hartman if (div > 7) 1660ab4382d2SGreg Kroah-Hartman div = 7; 1661ab4382d2SGreg Kroah-Hartman if (!div) 1662ab4382d2SGreg Kroah-Hartman div = 1; 1663ab4382d2SGreg Kroah-Hartman 1664ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1665ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1666ab4382d2SGreg Kroah-Hartman 1667ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1668ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1669ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1670ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1671ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1672ab4382d2SGreg Kroah-Hartman 1673ab4382d2SGreg Kroah-Hartman num -= 1; 1674ab4382d2SGreg Kroah-Hartman denom -= 1; 1675ab4382d2SGreg Kroah-Hartman 167627c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1677ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 167827c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1679ab4382d2SGreg Kroah-Hartman 168027c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 168127c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1682ab4382d2SGreg Kroah-Hartman 16839d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 168427c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 168527c84426SUwe Kleine-König IMX21_ONEMS); 1686ab4382d2SGreg Kroah-Hartman 168727c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr1, UCR1); 1688ab4382d2SGreg Kroah-Hartman 1689ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 169027c84426SUwe Kleine-König imx_uart_writel(sport, ucr2 | old_ucr2, UCR2); 1691ab4382d2SGreg Kroah-Hartman 1692ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 16939d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1694ab4382d2SGreg Kroah-Hartman 1695ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1696ab4382d2SGreg Kroah-Hartman } 1697ab4382d2SGreg Kroah-Hartman 16989d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1699ab4382d2SGreg Kroah-Hartman { 1700ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1701ab4382d2SGreg Kroah-Hartman 1702ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1703ab4382d2SGreg Kroah-Hartman } 1704ab4382d2SGreg Kroah-Hartman 1705ab4382d2SGreg Kroah-Hartman /* 1706ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1707ab4382d2SGreg Kroah-Hartman */ 17089d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1709ab4382d2SGreg Kroah-Hartman { 1710ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1711ab4382d2SGreg Kroah-Hartman 1712da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1713ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1714ab4382d2SGreg Kroah-Hartman } 1715ab4382d2SGreg Kroah-Hartman 1716ab4382d2SGreg Kroah-Hartman /* 1717ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1718ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1719ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1720ab4382d2SGreg Kroah-Hartman */ 1721ab4382d2SGreg Kroah-Hartman static int 17229d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1723ab4382d2SGreg Kroah-Hartman { 1724ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1725ab4382d2SGreg Kroah-Hartman int ret = 0; 1726ab4382d2SGreg Kroah-Hartman 1727ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1728ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1729ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1730ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1731ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1732ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1733ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1734ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1735a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1736ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1737ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1738ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1739ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1740ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1741ab4382d2SGreg Kroah-Hartman return ret; 1742ab4382d2SGreg Kroah-Hartman } 1743ab4382d2SGreg Kroah-Hartman 174401f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17456b8bdad9SDaniel Thompson 17469d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 17476b8bdad9SDaniel Thompson { 17486b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 17496b8bdad9SDaniel Thompson unsigned long flags; 17504444dcf1SUwe Kleine-König u32 ucr1, ucr2; 17516b8bdad9SDaniel Thompson int retval; 17526b8bdad9SDaniel Thompson 17536b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 17546b8bdad9SDaniel Thompson if (retval) 17556b8bdad9SDaniel Thompson return retval; 17566b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 17576b8bdad9SDaniel Thompson if (retval) 17586b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 17596b8bdad9SDaniel Thompson 17609d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 17616b8bdad9SDaniel Thompson 17626b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 17636b8bdad9SDaniel Thompson 176476821e22SUwe Kleine-König /* 176576821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 176676821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 176776821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 176876821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 176976821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 177076821e22SUwe Kleine-König */ 17714444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 177276821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 177376821e22SUwe Kleine-König 17749d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 17754444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 17766b8bdad9SDaniel Thompson 177776821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 177876821e22SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN); 177976821e22SUwe Kleine-König 17804444dcf1SUwe Kleine-König ucr2 |= UCR2_RXEN; 178181ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 178276821e22SUwe Kleine-König 178376821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 17844444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 17856b8bdad9SDaniel Thompson 178676821e22SUwe Kleine-König /* now enable irqs */ 178776821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 178881ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 178976821e22SUwe Kleine-König 17906b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 17916b8bdad9SDaniel Thompson 17926b8bdad9SDaniel Thompson return 0; 17936b8bdad9SDaniel Thompson } 17946b8bdad9SDaniel Thompson 17959d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 179601f56abdSSaleem Abdulrasool { 179727c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 179827c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 179926c47412SDirk Behme return NO_POLL_CHAR; 180001f56abdSSaleem Abdulrasool 180127c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 180201f56abdSSaleem Abdulrasool } 180301f56abdSSaleem Abdulrasool 18049d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 180501f56abdSSaleem Abdulrasool { 180627c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 180701f56abdSSaleem Abdulrasool unsigned int status; 180801f56abdSSaleem Abdulrasool 180901f56abdSSaleem Abdulrasool /* drain */ 181001f56abdSSaleem Abdulrasool do { 181127c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 181201f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 181301f56abdSSaleem Abdulrasool 181401f56abdSSaleem Abdulrasool /* write */ 181527c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 181601f56abdSSaleem Abdulrasool 181701f56abdSSaleem Abdulrasool /* flush */ 181801f56abdSSaleem Abdulrasool do { 181927c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 182001f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 182101f56abdSSaleem Abdulrasool } 182201f56abdSSaleem Abdulrasool #endif 182301f56abdSSaleem Abdulrasool 18246aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 18259d1a50a2SUwe Kleine-König static int imx_uart_rs485_config(struct uart_port *port, 182617b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 182717b8f2a3SUwe Kleine-König { 182817b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 18294444dcf1SUwe Kleine-König u32 ucr2; 183017b8f2a3SUwe Kleine-König 183117b8f2a3SUwe Kleine-König /* unimplemented */ 183217b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 183317b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 183417b8f2a3SUwe Kleine-König 183517b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 18367b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 183717b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 183817b8f2a3SUwe Kleine-König 183917b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 18406d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 18416d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 18426d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 18436d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 18446d215f83SStefan Agner 184517b8f2a3SUwe Kleine-König /* disable transmitter */ 18464444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 184717b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 18489d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 18491a613626SFabio Estevam else 18509d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 18514444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 185217b8f2a3SUwe Kleine-König } 185317b8f2a3SUwe Kleine-König 18547d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 18557d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 185676821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 18579d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 18587d1cadcaSBaruch Siach 185917b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 186017b8f2a3SUwe Kleine-König 186117b8f2a3SUwe Kleine-König return 0; 186217b8f2a3SUwe Kleine-König } 186317b8f2a3SUwe Kleine-König 18649d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 18659d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 18669d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 18679d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 18689d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 18699d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 18709d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 18719d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 18729d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 18739d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 18749d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 18759d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 18769d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 18779d1a50a2SUwe Kleine-König .type = imx_uart_type, 18789d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 18799d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 188001f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18819d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 18829d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 18839d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 188401f56abdSSaleem Abdulrasool #endif 1885ab4382d2SGreg Kroah-Hartman }; 1886ab4382d2SGreg Kroah-Hartman 18879d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1888ab4382d2SGreg Kroah-Hartman 1889ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 18909d1a50a2SUwe Kleine-König static void imx_uart_console_putchar(struct uart_port *port, int ch) 1891ab4382d2SGreg Kroah-Hartman { 1892ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1893ab4382d2SGreg Kroah-Hartman 18949d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1895ab4382d2SGreg Kroah-Hartman barrier(); 1896ab4382d2SGreg Kroah-Hartman 189727c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1898ab4382d2SGreg Kroah-Hartman } 1899ab4382d2SGreg Kroah-Hartman 1900ab4382d2SGreg Kroah-Hartman /* 1901ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1902ab4382d2SGreg Kroah-Hartman */ 1903ab4382d2SGreg Kroah-Hartman static void 19049d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1905ab4382d2SGreg Kroah-Hartman { 19069d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 19070ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 19080ad5a814SDirk Behme unsigned int ucr1; 1909f30e8260SShawn Guo unsigned long flags = 0; 1910677fe555SThomas Gleixner int locked = 1; 19111cf93e0dSHuang Shijie int retval; 19121cf93e0dSHuang Shijie 19130c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 19141cf93e0dSHuang Shijie if (retval) 19151cf93e0dSHuang Shijie return; 19160c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 19171cf93e0dSHuang Shijie if (retval) { 19180c727a42SFabio Estevam clk_disable(sport->clk_per); 19191cf93e0dSHuang Shijie return; 19201cf93e0dSHuang Shijie } 19219ec1882dSXinyu Chen 1922677fe555SThomas Gleixner if (sport->port.sysrq) 1923677fe555SThomas Gleixner locked = 0; 1924677fe555SThomas Gleixner else if (oops_in_progress) 1925677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1926677fe555SThomas Gleixner else 19279ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1928ab4382d2SGreg Kroah-Hartman 1929ab4382d2SGreg Kroah-Hartman /* 19300ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1931ab4382d2SGreg Kroah-Hartman */ 19329d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 19330ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1934ab4382d2SGreg Kroah-Hartman 19359d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 1936fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1937ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1938ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1939ab4382d2SGreg Kroah-Hartman 194027c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1941ab4382d2SGreg Kroah-Hartman 194227c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1943ab4382d2SGreg Kroah-Hartman 19449d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 1945ab4382d2SGreg Kroah-Hartman 1946ab4382d2SGreg Kroah-Hartman /* 1947ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 19480ad5a814SDirk Behme * and restore UCR1/2/3 1949ab4382d2SGreg Kroah-Hartman */ 195027c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1951ab4382d2SGreg Kroah-Hartman 19529d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 19539ec1882dSXinyu Chen 1954677fe555SThomas Gleixner if (locked) 19559ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 19561cf93e0dSHuang Shijie 19570c727a42SFabio Estevam clk_disable(sport->clk_ipg); 19580c727a42SFabio Estevam clk_disable(sport->clk_per); 1959ab4382d2SGreg Kroah-Hartman } 1960ab4382d2SGreg Kroah-Hartman 1961ab4382d2SGreg Kroah-Hartman /* 1962ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1963ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1964ab4382d2SGreg Kroah-Hartman */ 1965ab4382d2SGreg Kroah-Hartman static void __init 19669d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 1967ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1968ab4382d2SGreg Kroah-Hartman { 1969ab4382d2SGreg Kroah-Hartman 197027c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1971ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1972ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1973ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1974ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1975ab4382d2SGreg Kroah-Hartman 197627c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 1977ab4382d2SGreg Kroah-Hartman 1978ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1979ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1980ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1981ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1982ab4382d2SGreg Kroah-Hartman else 1983ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1984ab4382d2SGreg Kroah-Hartman } 1985ab4382d2SGreg Kroah-Hartman 1986ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1987ab4382d2SGreg Kroah-Hartman *bits = 8; 1988ab4382d2SGreg Kroah-Hartman else 1989ab4382d2SGreg Kroah-Hartman *bits = 7; 1990ab4382d2SGreg Kroah-Hartman 199127c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 199227c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 1993ab4382d2SGreg Kroah-Hartman 199427c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 1995ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1996ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1997ab4382d2SGreg Kroah-Hartman else 1998ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1999ab4382d2SGreg Kroah-Hartman 20003a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2001ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2002ab4382d2SGreg Kroah-Hartman 2003ab4382d2SGreg Kroah-Hartman { /* 2004ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2005ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2006ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2007ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2008ab4382d2SGreg Kroah-Hartman */ 2009ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2010ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2011ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2012ab4382d2SGreg Kroah-Hartman 2013ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2014ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2015ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2016ab4382d2SGreg Kroah-Hartman } 2017ab4382d2SGreg Kroah-Hartman 2018ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 201950bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 2020ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2021ab4382d2SGreg Kroah-Hartman } 2022ab4382d2SGreg Kroah-Hartman } 2023ab4382d2SGreg Kroah-Hartman 2024ab4382d2SGreg Kroah-Hartman static int __init 20259d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2026ab4382d2SGreg Kroah-Hartman { 2027ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2028ab4382d2SGreg Kroah-Hartman int baud = 9600; 2029ab4382d2SGreg Kroah-Hartman int bits = 8; 2030ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2031ab4382d2SGreg Kroah-Hartman int flow = 'n'; 20321cf93e0dSHuang Shijie int retval; 2033ab4382d2SGreg Kroah-Hartman 2034ab4382d2SGreg Kroah-Hartman /* 2035ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2036ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2037ab4382d2SGreg Kroah-Hartman * console support. 2038ab4382d2SGreg Kroah-Hartman */ 20399d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2040ab4382d2SGreg Kroah-Hartman co->index = 0; 20419d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2042ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2043ab4382d2SGreg Kroah-Hartman return -ENODEV; 2044ab4382d2SGreg Kroah-Hartman 20451cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 20461cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 20471cf93e0dSHuang Shijie if (retval) 20481cf93e0dSHuang Shijie goto error_console; 20491cf93e0dSHuang Shijie 2050ab4382d2SGreg Kroah-Hartman if (options) 2051ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2052ab4382d2SGreg Kroah-Hartman else 20539d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2054ab4382d2SGreg Kroah-Hartman 20559d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2056ab4382d2SGreg Kroah-Hartman 20571cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 20581cf93e0dSHuang Shijie 20590c727a42SFabio Estevam clk_disable(sport->clk_ipg); 20600c727a42SFabio Estevam if (retval) { 20610c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 20620c727a42SFabio Estevam goto error_console; 20630c727a42SFabio Estevam } 20640c727a42SFabio Estevam 20650c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 20660c727a42SFabio Estevam if (retval) 206763fd4b94SStefan Agner clk_unprepare(sport->clk_ipg); 20681cf93e0dSHuang Shijie 20691cf93e0dSHuang Shijie error_console: 20701cf93e0dSHuang Shijie return retval; 2071ab4382d2SGreg Kroah-Hartman } 2072ab4382d2SGreg Kroah-Hartman 20739d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 20749d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2075ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 20769d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2077ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 20789d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 2079ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2080ab4382d2SGreg Kroah-Hartman .index = -1, 20819d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2082ab4382d2SGreg Kroah-Hartman }; 2083ab4382d2SGreg Kroah-Hartman 20849d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2085913c6c0eSLucas Stach 2086913c6c0eSLucas Stach #ifdef CONFIG_OF 20879d1a50a2SUwe Kleine-König static void imx_uart_console_early_putchar(struct uart_port *port, int ch) 2088913c6c0eSLucas Stach { 208927c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 209027c84426SUwe Kleine-König 209127c84426SUwe Kleine-König while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2092913c6c0eSLucas Stach cpu_relax(); 2093913c6c0eSLucas Stach 209427c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 2095913c6c0eSLucas Stach } 2096913c6c0eSLucas Stach 20979d1a50a2SUwe Kleine-König static void imx_uart_console_early_write(struct console *con, const char *s, 2098913c6c0eSLucas Stach unsigned count) 2099913c6c0eSLucas Stach { 2100913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 2101913c6c0eSLucas Stach 21029d1a50a2SUwe Kleine-König uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar); 2103913c6c0eSLucas Stach } 2104913c6c0eSLucas Stach 2105913c6c0eSLucas Stach static int __init 2106913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2107913c6c0eSLucas Stach { 2108913c6c0eSLucas Stach if (!dev->port.membase) 2109913c6c0eSLucas Stach return -ENODEV; 2110913c6c0eSLucas Stach 21119d1a50a2SUwe Kleine-König dev->con->write = imx_uart_console_early_write; 2112913c6c0eSLucas Stach 2113913c6c0eSLucas Stach return 0; 2114913c6c0eSLucas Stach } 2115913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2116913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2117913c6c0eSLucas Stach #endif 2118913c6c0eSLucas Stach 2119ab4382d2SGreg Kroah-Hartman #else 2120ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2121ab4382d2SGreg Kroah-Hartman #endif 2122ab4382d2SGreg Kroah-Hartman 21239d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2124ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2125ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2126ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2127ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2128ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21299d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2130ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2131ab4382d2SGreg Kroah-Hartman }; 2132ab4382d2SGreg Kroah-Hartman 213322698aa2SShawn Guo #ifdef CONFIG_OF 213420bb8095SUwe Kleine-König /* 213520bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 213620bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 213720bb8095SUwe Kleine-König */ 21389d1a50a2SUwe Kleine-König static int imx_uart_probe_dt(struct imx_port *sport, 213922698aa2SShawn Guo struct platform_device *pdev) 214022698aa2SShawn Guo { 214122698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2142ff05967aSShawn Guo int ret; 214322698aa2SShawn Guo 21445f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 21455f8b9043SLABBE Corentin if (!sport->devdata) 214620bb8095SUwe Kleine-König /* no device tree device */ 214720bb8095SUwe Kleine-König return 1; 214822698aa2SShawn Guo 2149ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2150ff05967aSShawn Guo if (ret < 0) { 2151ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2152a197a191SUwe Kleine-König return ret; 2153ff05967aSShawn Guo } 2154ff05967aSShawn Guo sport->port.line = ret; 215522698aa2SShawn Guo 21561006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 21571006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 215822698aa2SShawn Guo sport->have_rtscts = 1; 215922698aa2SShawn Guo 216020ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 216120ff2fe6SHuang Shijie sport->dte_mode = 1; 216220ff2fe6SHuang Shijie 21637b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 21647b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 21657b7e8e8eSFabio Estevam 216622698aa2SShawn Guo return 0; 216722698aa2SShawn Guo } 216822698aa2SShawn Guo #else 21699d1a50a2SUwe Kleine-König static inline int imx_uart_probe_dt(struct imx_port *sport, 217022698aa2SShawn Guo struct platform_device *pdev) 217122698aa2SShawn Guo { 217220bb8095SUwe Kleine-König return 1; 217322698aa2SShawn Guo } 217422698aa2SShawn Guo #endif 217522698aa2SShawn Guo 21769d1a50a2SUwe Kleine-König static void imx_uart_probe_pdata(struct imx_port *sport, 217722698aa2SShawn Guo struct platform_device *pdev) 217822698aa2SShawn Guo { 2179574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 218022698aa2SShawn Guo 218122698aa2SShawn Guo sport->port.line = pdev->id; 218222698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 218322698aa2SShawn Guo 218422698aa2SShawn Guo if (!pdata) 218522698aa2SShawn Guo return; 218622698aa2SShawn Guo 218722698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 218822698aa2SShawn Guo sport->have_rtscts = 1; 218922698aa2SShawn Guo } 219022698aa2SShawn Guo 21919d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2192ab4382d2SGreg Kroah-Hartman { 2193ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2194ab4382d2SGreg Kroah-Hartman void __iomem *base; 21954444dcf1SUwe Kleine-König int ret = 0; 21964444dcf1SUwe Kleine-König u32 ucr1; 2197ab4382d2SGreg Kroah-Hartman struct resource *res; 2198842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2199ab4382d2SGreg Kroah-Hartman 220042d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2201ab4382d2SGreg Kroah-Hartman if (!sport) 2202ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2203ab4382d2SGreg Kroah-Hartman 22049d1a50a2SUwe Kleine-König ret = imx_uart_probe_dt(sport, pdev); 220520bb8095SUwe Kleine-König if (ret > 0) 22069d1a50a2SUwe Kleine-König imx_uart_probe_pdata(sport, pdev); 220720bb8095SUwe Kleine-König else if (ret < 0) 220842d34191SSachin Kamat return ret; 220922698aa2SShawn Guo 22109d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 221156734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 221256734448SGeert Uytterhoeven sport->port.line); 221356734448SGeert Uytterhoeven return -EINVAL; 221456734448SGeert Uytterhoeven } 221556734448SGeert Uytterhoeven 2216ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2217da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2218da82f997SAlexander Shiyan if (IS_ERR(base)) 2219da82f997SAlexander Shiyan return PTR_ERR(base); 2220ab4382d2SGreg Kroah-Hartman 2221842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2222842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2223842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2224842633bdSUwe Kleine-König 2225ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2226ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2227ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2228ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2229ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2230842633bdSUwe Kleine-König sport->port.irq = rxirq; 2231ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 22329d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 22339d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 2234ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 22359d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2236ab4382d2SGreg Kroah-Hartman 223758362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 223858362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 223958362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 224058362d5bSUwe Kleine-König 22413a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 22423a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 22433a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2244833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 224542d34191SSachin Kamat return ret; 2246ab4382d2SGreg Kroah-Hartman } 2247ab4382d2SGreg Kroah-Hartman 22483a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 22493a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 22503a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2251833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 225242d34191SSachin Kamat return ret; 22533a9465faSSascha Hauer } 22543a9465faSSascha Hauer 22553a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2256ab4382d2SGreg Kroah-Hartman 22578a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 22588a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 22591e512d45SUwe Kleine-König if (ret) { 22601e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 22618a61f0c7SFabio Estevam return ret; 22621e512d45SUwe Kleine-König } 22638a61f0c7SFabio Estevam 22643a0ab62fSUwe Kleine-König /* initialize shadow register values */ 22653a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 22663a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 22673a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 22683a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 22693a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 22703a0ab62fSUwe Kleine-König 2271743f93f8SLukas Wunner uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2272743f93f8SLukas Wunner 2273b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 22745d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2275b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2276b8f3bff0SLukas Wunner 22776d215f83SStefan Agner /* 22786d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 22796d215f83SStefan Agner * signal cannot be set low during transmission in case the 22806d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 22816d215f83SStefan Agner */ 22826d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 22836d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 22846d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 22856d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 22866d215f83SStefan Agner dev_err(&pdev->dev, 22876d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 22886d215f83SStefan Agner 22899d1a50a2SUwe Kleine-König imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2290b8f3bff0SLukas Wunner 22918a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 22924444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 22934444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 22948a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 22954444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 22968a61f0c7SFabio Estevam 22979d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2298e61c38d8SUwe Kleine-König /* 2299e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2300e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2301e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2302e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2303e61c38d8SUwe Kleine-König */ 23044444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23054444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 23064444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2307e61c38d8SUwe Kleine-König 2308e61c38d8SUwe Kleine-König /* 2309e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2310e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2311e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2312e61c38d8SUwe Kleine-König */ 231327c84426SUwe Kleine-König imx_uart_writel(sport, 231427c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 231527c84426SUwe Kleine-König UCR3); 2316e61c38d8SUwe Kleine-König 2317e61c38d8SUwe Kleine-König } else { 23184444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 23194444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23204444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 23214444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 23226df765dcSUwe Kleine-König 23239d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 23246df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 232527c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2326e61c38d8SUwe Kleine-König } 2327e61c38d8SUwe Kleine-König 23288a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 23298a61f0c7SFabio Estevam 2330c0d1c6b0SFabio Estevam /* 2331c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2332c0d1c6b0SFabio Estevam * chips only have one interrupt. 2333c0d1c6b0SFabio Estevam */ 2334842633bdSUwe Kleine-König if (txirq > 0) { 23359d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2336c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23371e512d45SUwe Kleine-König if (ret) { 23381e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 23391e512d45SUwe Kleine-König ret); 2340c0d1c6b0SFabio Estevam return ret; 23411e512d45SUwe Kleine-König } 2342c0d1c6b0SFabio Estevam 23439d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2344c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23451e512d45SUwe Kleine-König if (ret) { 23461e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 23471e512d45SUwe Kleine-König ret); 2348c0d1c6b0SFabio Estevam return ret; 23491e512d45SUwe Kleine-König } 23507e620984SUwe Kleine-König 23517e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 23527e620984SUwe Kleine-König dev_name(&pdev->dev), sport); 23537e620984SUwe Kleine-König if (ret) { 23547e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n", 23557e620984SUwe Kleine-König ret); 23567e620984SUwe Kleine-König return ret; 23577e620984SUwe Kleine-König } 2358c0d1c6b0SFabio Estevam } else { 23599d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2360c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23611e512d45SUwe Kleine-König if (ret) { 23621e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2363c0d1c6b0SFabio Estevam return ret; 2364c0d1c6b0SFabio Estevam } 23651e512d45SUwe Kleine-König } 2366c0d1c6b0SFabio Estevam 23679d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2368ab4382d2SGreg Kroah-Hartman 23690a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2370ab4382d2SGreg Kroah-Hartman 23719d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2372ab4382d2SGreg Kroah-Hartman } 2373ab4382d2SGreg Kroah-Hartman 23749d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2375ab4382d2SGreg Kroah-Hartman { 2376ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2377ab4382d2SGreg Kroah-Hartman 23789d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2379ab4382d2SGreg Kroah-Hartman } 2380ab4382d2SGreg Kroah-Hartman 23819d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2382c868cbb7SEduardo Valentin { 238307b5e16eSAnson Huang unsigned long flags; 238407b5e16eSAnson Huang 238507b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 238607b5e16eSAnson Huang if (!sport->context_saved) { 238707b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2388c868cbb7SEduardo Valentin return; 238907b5e16eSAnson Huang } 2390c868cbb7SEduardo Valentin 239127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 239227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 239327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 239427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 239527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 239627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 239727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 239827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 239927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 240027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2401c868cbb7SEduardo Valentin sport->context_saved = false; 240207b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2403c868cbb7SEduardo Valentin } 2404c868cbb7SEduardo Valentin 24059d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2406c868cbb7SEduardo Valentin { 240707b5e16eSAnson Huang unsigned long flags; 240807b5e16eSAnson Huang 2409c868cbb7SEduardo Valentin /* Save necessary regs */ 241007b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 241127c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 241227c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 241327c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 241427c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 241527c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 241627c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 241727c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 241827c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 241927c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 242027c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2421c868cbb7SEduardo Valentin sport->context_saved = true; 242207b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2423c868cbb7SEduardo Valentin } 2424c868cbb7SEduardo Valentin 24259d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2426189550b8SEduardo Valentin { 24274444dcf1SUwe Kleine-König u32 ucr3; 2428189550b8SEduardo Valentin 24294444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 243009df0b34SMartin Kaiser if (on) { 243127c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 24324444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 24334444dcf1SUwe Kleine-König } else { 24344444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 243509df0b34SMartin Kaiser } 24364444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2437bc85734bSEduardo Valentin 243838b1f0fbSFabio Estevam if (sport->have_rtscts) { 24394444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2440bc85734bSEduardo Valentin if (on) 24414444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2442bc85734bSEduardo Valentin else 24434444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 24444444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2445189550b8SEduardo Valentin } 244638b1f0fbSFabio Estevam } 2447189550b8SEduardo Valentin 24489d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 244990bb6bd3SShenwei Wang { 2450a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 245190bb6bd3SShenwei Wang 24529d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 245390bb6bd3SShenwei Wang 245490bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 245590bb6bd3SShenwei Wang 2456fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev); 2457fcfed1beSAnson Huang 245890bb6bd3SShenwei Wang return 0; 245990bb6bd3SShenwei Wang } 246090bb6bd3SShenwei Wang 24619d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 246290bb6bd3SShenwei Wang { 2463a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 246490bb6bd3SShenwei Wang int ret; 246590bb6bd3SShenwei Wang 2466fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev); 2467fcfed1beSAnson Huang 246890bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 246990bb6bd3SShenwei Wang if (ret) 247090bb6bd3SShenwei Wang return ret; 247190bb6bd3SShenwei Wang 24729d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 247390bb6bd3SShenwei Wang 247490bb6bd3SShenwei Wang return 0; 247590bb6bd3SShenwei Wang } 247690bb6bd3SShenwei Wang 24779d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 247890bb6bd3SShenwei Wang { 2479a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 248009df0b34SMartin Kaiser int ret; 248190bb6bd3SShenwei Wang 24829d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 248381b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 248490bb6bd3SShenwei Wang 248509df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 248609df0b34SMartin Kaiser if (ret) 248709df0b34SMartin Kaiser return ret; 248809df0b34SMartin Kaiser 248909df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 24909d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 249109df0b34SMartin Kaiser 249209df0b34SMartin Kaiser return 0; 249390bb6bd3SShenwei Wang } 249490bb6bd3SShenwei Wang 24959d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 249690bb6bd3SShenwei Wang { 2497a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 249890bb6bd3SShenwei Wang 249990bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 25009d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 250190bb6bd3SShenwei Wang 25029d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 250381b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 250490bb6bd3SShenwei Wang 250509df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 250629add68dSMartin Fuzzey 250790bb6bd3SShenwei Wang return 0; 250890bb6bd3SShenwei Wang } 250990bb6bd3SShenwei Wang 25109d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 251194be6d74SPhilipp Zabel { 2512a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 251394be6d74SPhilipp Zabel 25149d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 251594be6d74SPhilipp Zabel 251609df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 251794be6d74SPhilipp Zabel } 251894be6d74SPhilipp Zabel 25199d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 252094be6d74SPhilipp Zabel { 2521a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 252294be6d74SPhilipp Zabel 25239d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 252494be6d74SPhilipp Zabel 252509df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 252694be6d74SPhilipp Zabel 252794be6d74SPhilipp Zabel return 0; 252894be6d74SPhilipp Zabel } 252994be6d74SPhilipp Zabel 25309d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 25319d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 25329d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 25339d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 25349d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 25359d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 25369d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 25379d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 25389d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 25399d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 254090bb6bd3SShenwei Wang }; 254190bb6bd3SShenwei Wang 25429d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 25439d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 25449d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2545ab4382d2SGreg Kroah-Hartman 2546fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2547ab4382d2SGreg Kroah-Hartman .driver = { 2548ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 254922698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 25509d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2551ab4382d2SGreg Kroah-Hartman }, 2552ab4382d2SGreg Kroah-Hartman }; 2553ab4382d2SGreg Kroah-Hartman 25549d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2555ab4382d2SGreg Kroah-Hartman { 25569d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2557ab4382d2SGreg Kroah-Hartman 2558ab4382d2SGreg Kroah-Hartman if (ret) 2559ab4382d2SGreg Kroah-Hartman return ret; 2560ab4382d2SGreg Kroah-Hartman 25619d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2562ab4382d2SGreg Kroah-Hartman if (ret != 0) 25639d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2564ab4382d2SGreg Kroah-Hartman 2565f227824eSUwe Kleine-König return ret; 2566ab4382d2SGreg Kroah-Hartman } 2567ab4382d2SGreg Kroah-Hartman 25689d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2569ab4382d2SGreg Kroah-Hartman { 25709d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 25719d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2572ab4382d2SGreg Kroah-Hartman } 2573ab4382d2SGreg Kroah-Hartman 25749d1a50a2SUwe Kleine-König module_init(imx_uart_init); 25759d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2576ab4382d2SGreg Kroah-Hartman 2577ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2578ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2579ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2580ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2581