1ab4382d2SGreg Kroah-Hartman /* 2f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 7ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 8ab4382d2SGreg Kroah-Hartman * 9ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 10ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 11ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2 of the License, or 12ab4382d2SGreg Kroah-Hartman * (at your option) any later version. 13ab4382d2SGreg Kroah-Hartman * 14ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 15ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY; without even the implied warranty of 16ab4382d2SGreg Kroah-Hartman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17ab4382d2SGreg Kroah-Hartman * GNU General Public License for more details. 18ab4382d2SGreg Kroah-Hartman */ 19ab4382d2SGreg Kroah-Hartman 20ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 22ab4382d2SGreg Kroah-Hartman #endif 23ab4382d2SGreg Kroah-Hartman 24ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 29ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 30ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 31ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 32ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 33ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 34ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 35ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 36ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 37ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 3822698aa2SShawn Guo #include <linux/of.h> 3922698aa2SShawn Guo #include <linux/of_device.h> 40e32a9f8fSSachin Kamat #include <linux/io.h> 41b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 42ab4382d2SGreg Kroah-Hartman 43ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 4482906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 45b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 46ab4382d2SGreg Kroah-Hartman 4758362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 4858362d5bSUwe Kleine-König 49ab4382d2SGreg Kroah-Hartman /* Register definitions */ 50ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 51ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 52ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 53ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 54ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 55ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 56ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 57ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 58ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 59ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 60ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 61ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 62ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 63ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 64fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 65fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 66fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 67ab4382d2SGreg Kroah-Hartman 68ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6955d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 70ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 71ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 72ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 73ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 74ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 75ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 7626c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 7725985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 81b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 84ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 88ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 89fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 90b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 91ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 92ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 100ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 101ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 102ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 10301f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 105ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 106ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 112ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 113b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 114ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 115ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 11727e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 118fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 119ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 120ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 124ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 125ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 126ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 127b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 128ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 129ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 130ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 131ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 132ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 133ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1347be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 135ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 136ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 137ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 138ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 140ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 141ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 142ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 143ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 14586a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 14627e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 147ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 150ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 151ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 152ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 153ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 15490ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 15590ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 156ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 157ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 15890ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 159ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 160ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 161ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 162ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 163ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 164ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 165ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 166ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 167ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 168ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 169ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 170ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 171ab4382d2SGreg Kroah-Hartman 172ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 173ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 174ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 175ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 176ab4382d2SGreg Kroah-Hartman 177ab4382d2SGreg Kroah-Hartman /* 178ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 179ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 180ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 181ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 182ab4382d2SGreg Kroah-Hartman */ 183ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 184ab4382d2SGreg Kroah-Hartman 185ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 186ab4382d2SGreg Kroah-Hartman 187ab4382d2SGreg Kroah-Hartman #define UART_NR 8 188ab4382d2SGreg Kroah-Hartman 189f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 190fe6b540aSShawn Guo enum imx_uart_type { 191fe6b540aSShawn Guo IMX1_UART, 192fe6b540aSShawn Guo IMX21_UART, 1931c06bde6SMartyn Welch IMX53_UART, 194a496e628SHuang Shijie IMX6Q_UART, 195fe6b540aSShawn Guo }; 196fe6b540aSShawn Guo 197fe6b540aSShawn Guo /* device type dependent stuff */ 198fe6b540aSShawn Guo struct imx_uart_data { 199fe6b540aSShawn Guo unsigned uts_reg; 200fe6b540aSShawn Guo enum imx_uart_type devtype; 201fe6b540aSShawn Guo }; 202fe6b540aSShawn Guo 203ab4382d2SGreg Kroah-Hartman struct imx_port { 204ab4382d2SGreg Kroah-Hartman struct uart_port port; 205ab4382d2SGreg Kroah-Hartman struct timer_list timer; 206ab4382d2SGreg Kroah-Hartman unsigned int old_status; 207ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2087b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20920ff2fe6SHuang Shijie unsigned int dte_mode:1; 210ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_rx:1; 211ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_tx:1; 212ab4382d2SGreg Kroah-Hartman unsigned short trcv_delay; /* transceiver delay */ 2133a9465faSSascha Hauer struct clk *clk_ipg; 2143a9465faSSascha Hauer struct clk *clk_per; 2157d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 216b4cdc8f6SHuang Shijie 21758362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21858362d5bSUwe Kleine-König 219b4cdc8f6SHuang Shijie /* DMA fields */ 220b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 221b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 224b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 225b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 226b4cdc8f6SHuang Shijie void *rx_buf; 2279d297239SNandor Han struct circ_buf rx_ring; 2289d297239SNandor Han unsigned int rx_periods; 2299d297239SNandor Han dma_cookie_t rx_cookie; 2307cb92fd2SHuang Shijie unsigned int tx_bytes; 231b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 2329ce4f8f3SGreg Kroah-Hartman wait_queue_head_t dma_wait; 23390bb6bd3SShenwei Wang unsigned int saved_reg[10]; 234c868cbb7SEduardo Valentin bool context_saved; 235ab4382d2SGreg Kroah-Hartman }; 236ab4382d2SGreg Kroah-Hartman 2370ad5a814SDirk Behme struct imx_port_ucrs { 2380ad5a814SDirk Behme unsigned int ucr1; 2390ad5a814SDirk Behme unsigned int ucr2; 2400ad5a814SDirk Behme unsigned int ucr3; 2410ad5a814SDirk Behme }; 2420ad5a814SDirk Behme 243fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 244fe6b540aSShawn Guo [IMX1_UART] = { 245fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 246fe6b540aSShawn Guo .devtype = IMX1_UART, 247fe6b540aSShawn Guo }, 248fe6b540aSShawn Guo [IMX21_UART] = { 249fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 250fe6b540aSShawn Guo .devtype = IMX21_UART, 251fe6b540aSShawn Guo }, 2521c06bde6SMartyn Welch [IMX53_UART] = { 2531c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2541c06bde6SMartyn Welch .devtype = IMX53_UART, 2551c06bde6SMartyn Welch }, 256a496e628SHuang Shijie [IMX6Q_UART] = { 257a496e628SHuang Shijie .uts_reg = IMX21_UTS, 258a496e628SHuang Shijie .devtype = IMX6Q_UART, 259a496e628SHuang Shijie }, 260fe6b540aSShawn Guo }; 261fe6b540aSShawn Guo 26231ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 263fe6b540aSShawn Guo { 264fe6b540aSShawn Guo .name = "imx1-uart", 265fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 266fe6b540aSShawn Guo }, { 267fe6b540aSShawn Guo .name = "imx21-uart", 268fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 269fe6b540aSShawn Guo }, { 2701c06bde6SMartyn Welch .name = "imx53-uart", 2711c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2721c06bde6SMartyn Welch }, { 273a496e628SHuang Shijie .name = "imx6q-uart", 274a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 275a496e628SHuang Shijie }, { 276fe6b540aSShawn Guo /* sentinel */ 277fe6b540aSShawn Guo } 278fe6b540aSShawn Guo }; 279fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 280fe6b540aSShawn Guo 281ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 282a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2831c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 28422698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 28522698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 28622698aa2SShawn Guo { /* sentinel */ } 28722698aa2SShawn Guo }; 28822698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28922698aa2SShawn Guo 290fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 291fe6b540aSShawn Guo { 292fe6b540aSShawn Guo return sport->devdata->uts_reg; 293fe6b540aSShawn Guo } 294fe6b540aSShawn Guo 295fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 296fe6b540aSShawn Guo { 297fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 298fe6b540aSShawn Guo } 299fe6b540aSShawn Guo 300fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 301fe6b540aSShawn Guo { 302fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 303fe6b540aSShawn Guo } 304fe6b540aSShawn Guo 3051c06bde6SMartyn Welch static inline int is_imx53_uart(struct imx_port *sport) 3061c06bde6SMartyn Welch { 3071c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3081c06bde6SMartyn Welch } 3091c06bde6SMartyn Welch 310a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 311a496e628SHuang Shijie { 312a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 313a496e628SHuang Shijie } 314ab4382d2SGreg Kroah-Hartman /* 31544a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 31644a75411Sfabio.estevam@freescale.com */ 31793d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 31844a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 31944a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 32044a75411Sfabio.estevam@freescale.com { 32144a75411Sfabio.estevam@freescale.com /* save control registers */ 32244a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 32344a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 32444a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 32544a75411Sfabio.estevam@freescale.com } 32644a75411Sfabio.estevam@freescale.com 32744a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 32844a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 32944a75411Sfabio.estevam@freescale.com { 33044a75411Sfabio.estevam@freescale.com /* restore control registers */ 33144a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 33244a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 33344a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 33444a75411Sfabio.estevam@freescale.com } 335e8bfa760SFabio Estevam #endif 33644a75411Sfabio.estevam@freescale.com 33758362d5bSUwe Kleine-König static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2) 33858362d5bSUwe Kleine-König { 339bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 34058362d5bSUwe Kleine-König 34158362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); 34258362d5bSUwe Kleine-König } 34358362d5bSUwe Kleine-König 34458362d5bSUwe Kleine-König static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2) 34558362d5bSUwe Kleine-König { 346bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 347bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 34858362d5bSUwe Kleine-König 34958362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); 35058362d5bSUwe Kleine-König } 35158362d5bSUwe Kleine-König 35258362d5bSUwe Kleine-König static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2) 35358362d5bSUwe Kleine-König { 35458362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 35558362d5bSUwe Kleine-König } 35658362d5bSUwe Kleine-König 35744a75411Sfabio.estevam@freescale.com /* 358ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 359ab4382d2SGreg Kroah-Hartman */ 360ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 361ab4382d2SGreg Kroah-Hartman { 362ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 363ab4382d2SGreg Kroah-Hartman unsigned long temp; 364ab4382d2SGreg Kroah-Hartman 3659ce4f8f3SGreg Kroah-Hartman /* 3669ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 3679ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 3689ce4f8f3SGreg Kroah-Hartman */ 3699ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 3709ce4f8f3SGreg Kroah-Hartman return; 371b4cdc8f6SHuang Shijie 37217b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR1); 37317b8f2a3SUwe Kleine-König writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); 37417b8f2a3SUwe Kleine-König 37517b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 37617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 37717b8f2a3SUwe Kleine-König readl(port->membase + USR2) & USR2_TXDC) { 37817b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 37917b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 38058362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 3811a613626SFabio Estevam else 3821a613626SFabio Estevam imx_port_rts_inactive(sport, &temp); 3837d1cadcaSBaruch Siach temp |= UCR2_RXEN; 38417b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 38517b8f2a3SUwe Kleine-König 38617b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 38717b8f2a3SUwe Kleine-König temp &= ~UCR4_TCEN; 38817b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 38917b8f2a3SUwe Kleine-König } 390ab4382d2SGreg Kroah-Hartman } 391ab4382d2SGreg Kroah-Hartman 392ab4382d2SGreg Kroah-Hartman /* 393ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 394ab4382d2SGreg Kroah-Hartman */ 395ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 396ab4382d2SGreg Kroah-Hartman { 397ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 398ab4382d2SGreg Kroah-Hartman unsigned long temp; 399ab4382d2SGreg Kroah-Hartman 40045564a66SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) { 40145564a66SHuang Shijie if (sport->port.suspended) { 40245564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 40345564a66SHuang Shijie sport->dma_is_rxing = 0; 40445564a66SHuang Shijie } else { 4059ce4f8f3SGreg Kroah-Hartman return; 40645564a66SHuang Shijie } 40745564a66SHuang Shijie } 408b4cdc8f6SHuang Shijie 409ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 410ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 41185878399SHuang Shijie 41285878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 41385878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 41485878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 415ab4382d2SGreg Kroah-Hartman } 416ab4382d2SGreg Kroah-Hartman 417ab4382d2SGreg Kroah-Hartman /* 418ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 419ab4382d2SGreg Kroah-Hartman */ 420ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 421ab4382d2SGreg Kroah-Hartman { 422ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 423ab4382d2SGreg Kroah-Hartman 424ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 42558362d5bSUwe Kleine-König 42658362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 427ab4382d2SGreg Kroah-Hartman } 428ab4382d2SGreg Kroah-Hartman 42991a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 430ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 431ab4382d2SGreg Kroah-Hartman { 432ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 43391a1a909SJiada Wang unsigned long temp; 434ab4382d2SGreg Kroah-Hartman 4355e42e9a3SPeter Hurley if (sport->port.x_char) { 4365e42e9a3SPeter Hurley /* Send next char */ 4375e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4387e2fb5aaSJiada Wang sport->port.icount.tx++; 4397e2fb5aaSJiada Wang sport->port.x_char = 0; 4405e42e9a3SPeter Hurley return; 4415e42e9a3SPeter Hurley } 4425e42e9a3SPeter Hurley 4435e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4445e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4455e42e9a3SPeter Hurley return; 4465e42e9a3SPeter Hurley } 4475e42e9a3SPeter Hurley 44891a1a909SJiada Wang if (sport->dma_is_enabled) { 44991a1a909SJiada Wang /* 45091a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 45191a1a909SJiada Wang * and the TX IRQ is disabled. 45291a1a909SJiada Wang **/ 45391a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 45491a1a909SJiada Wang temp &= ~UCR1_TXMPTYEN; 45591a1a909SJiada Wang if (sport->dma_is_txing) { 45691a1a909SJiada Wang temp |= UCR1_TDMAEN; 45791a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 45891a1a909SJiada Wang } else { 45991a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 46091a1a909SJiada Wang imx_dma_tx(sport); 46191a1a909SJiada Wang } 46291a1a909SJiada Wang } 46391a1a909SJiada Wang 464ab4382d2SGreg Kroah-Hartman while (!uart_circ_empty(xmit) && 4655e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 466ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 467ab4382d2SGreg Kroah-Hartman * out the port here */ 468ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 469ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 470ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 471ab4382d2SGreg Kroah-Hartman } 472ab4382d2SGreg Kroah-Hartman 473ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 474ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 475ab4382d2SGreg Kroah-Hartman 476ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 477ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 478ab4382d2SGreg Kroah-Hartman } 479ab4382d2SGreg Kroah-Hartman 480b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 481b4cdc8f6SHuang Shijie { 482b4cdc8f6SHuang Shijie struct imx_port *sport = data; 483b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 484b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 485b4cdc8f6SHuang Shijie unsigned long flags; 486a2c718ceSDirk Behme unsigned long temp; 487b4cdc8f6SHuang Shijie 48842f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 48942f752b3SDirk Behme 490b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 491b4cdc8f6SHuang Shijie 492a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 493a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 494a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 495a2c718ceSDirk Behme 49642f752b3SDirk Behme /* update the stat */ 49742f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 49842f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 49942f752b3SDirk Behme 50042f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 50142f752b3SDirk Behme 502b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 503b4cdc8f6SHuang Shijie 504b4cdc8f6SHuang Shijie spin_unlock_irqrestore(&sport->port.lock, flags); 505b4cdc8f6SHuang Shijie 506d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 507b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5089ce4f8f3SGreg Kroah-Hartman 5099ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) { 5109ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 5119ce4f8f3SGreg Kroah-Hartman dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 5129ce4f8f3SGreg Kroah-Hartman return; 5139ce4f8f3SGreg Kroah-Hartman } 5140bbc9b81SJiada Wang 5150bbc9b81SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 5160bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5170bbc9b81SJiada Wang imx_dma_tx(sport); 5180bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 519b4cdc8f6SHuang Shijie } 520b4cdc8f6SHuang Shijie 5217cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 522b4cdc8f6SHuang Shijie { 523b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 524b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 525b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 526b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 527b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 528a2c718ceSDirk Behme unsigned long temp; 529b4cdc8f6SHuang Shijie int ret; 530b4cdc8f6SHuang Shijie 53142f752b3SDirk Behme if (sport->dma_is_txing) 532b4cdc8f6SHuang Shijie return; 533b4cdc8f6SHuang Shijie 534b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 535b4cdc8f6SHuang Shijie 5367942f857SDirk Behme if (xmit->tail < xmit->head) { 5377942f857SDirk Behme sport->dma_tx_nents = 1; 5387942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5397942f857SDirk Behme } else { 540b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 541b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 542b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 543b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 544b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 545b4cdc8f6SHuang Shijie } 546b4cdc8f6SHuang Shijie 547b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 548b4cdc8f6SHuang Shijie if (ret == 0) { 549b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 550b4cdc8f6SHuang Shijie return; 551b4cdc8f6SHuang Shijie } 552b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 553b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 554b4cdc8f6SHuang Shijie if (!desc) { 55524649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 55624649821SDirk Behme DMA_TO_DEVICE); 557b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 558b4cdc8f6SHuang Shijie return; 559b4cdc8f6SHuang Shijie } 560b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 561b4cdc8f6SHuang Shijie desc->callback_param = sport; 562b4cdc8f6SHuang Shijie 563b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 564b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 565a2c718ceSDirk Behme 566a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 567a2c718ceSDirk Behme temp |= UCR1_TDMAEN; 568a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 569a2c718ceSDirk Behme 570b4cdc8f6SHuang Shijie /* fire it */ 571b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 572b4cdc8f6SHuang Shijie dmaengine_submit(desc); 573b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 574b4cdc8f6SHuang Shijie return; 575b4cdc8f6SHuang Shijie } 576b4cdc8f6SHuang Shijie 577ab4382d2SGreg Kroah-Hartman /* 578ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 579ab4382d2SGreg Kroah-Hartman */ 580ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 581ab4382d2SGreg Kroah-Hartman { 582ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 583ab4382d2SGreg Kroah-Hartman unsigned long temp; 584ab4382d2SGreg Kroah-Hartman 58517b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 58617b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 58717b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 58858362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 5891a613626SFabio Estevam else 5901a613626SFabio Estevam imx_port_rts_inactive(sport, &temp); 5917d1cadcaSBaruch Siach if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 5927d1cadcaSBaruch Siach temp &= ~UCR2_RXEN; 59317b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 59417b8f2a3SUwe Kleine-König 59558362d5bSUwe Kleine-König /* enable transmitter and shifter empty irq */ 59617b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 59717b8f2a3SUwe Kleine-König temp |= UCR4_TCEN; 59817b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 59917b8f2a3SUwe Kleine-König } 60017b8f2a3SUwe Kleine-König 601b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 602ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 603ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 604b4cdc8f6SHuang Shijie } 605ab4382d2SGreg Kroah-Hartman 606b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 60791a1a909SJiada Wang if (sport->port.x_char) { 60891a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 60991a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 61091a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 61191a1a909SJiada Wang temp &= ~UCR1_TDMAEN; 61291a1a909SJiada Wang temp |= UCR1_TXMPTYEN; 61391a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 61491a1a909SJiada Wang return; 61591a1a909SJiada Wang } 61691a1a909SJiada Wang 6175e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6185e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6197cb92fd2SHuang Shijie imx_dma_tx(sport); 620b4cdc8f6SHuang Shijie return; 621b4cdc8f6SHuang Shijie } 622ab4382d2SGreg Kroah-Hartman } 623ab4382d2SGreg Kroah-Hartman 624ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 625ab4382d2SGreg Kroah-Hartman { 626ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6275680e941SUwe Kleine-König unsigned int val; 628ab4382d2SGreg Kroah-Hartman unsigned long flags; 629ab4382d2SGreg Kroah-Hartman 630ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 631ab4382d2SGreg Kroah-Hartman 632ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6335680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 634ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 635ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 636ab4382d2SGreg Kroah-Hartman 637ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 638ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 639ab4382d2SGreg Kroah-Hartman } 640ab4382d2SGreg Kroah-Hartman 641ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 642ab4382d2SGreg Kroah-Hartman { 643ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 644ab4382d2SGreg Kroah-Hartman unsigned long flags; 645ab4382d2SGreg Kroah-Hartman 646ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 647ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 648ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 649ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 650ab4382d2SGreg Kroah-Hartman } 651ab4382d2SGreg Kroah-Hartman 652ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 653ab4382d2SGreg Kroah-Hartman { 654ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 655ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 65692a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 657ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 658ab4382d2SGreg Kroah-Hartman 659ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 660ab4382d2SGreg Kroah-Hartman 661ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 662ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 663ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 664ab4382d2SGreg Kroah-Hartman 665ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 666ab4382d2SGreg Kroah-Hartman 667ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 668ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 669ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 670ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 671ab4382d2SGreg Kroah-Hartman continue; 672ab4382d2SGreg Kroah-Hartman } 673ab4382d2SGreg Kroah-Hartman 674ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 675ab4382d2SGreg Kroah-Hartman continue; 676ab4382d2SGreg Kroah-Hartman 677019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 678019dc9eaSHui Wang if (rx & URXD_BRK) 679019dc9eaSHui Wang sport->port.icount.brk++; 680019dc9eaSHui Wang else if (rx & URXD_PRERR) 681ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 682ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 683ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 684ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 685ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 686ab4382d2SGreg Kroah-Hartman 687ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 688ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 689ab4382d2SGreg Kroah-Hartman goto out; 690ab4382d2SGreg Kroah-Hartman continue; 691ab4382d2SGreg Kroah-Hartman } 692ab4382d2SGreg Kroah-Hartman 6938d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 694ab4382d2SGreg Kroah-Hartman 695019dc9eaSHui Wang if (rx & URXD_BRK) 696019dc9eaSHui Wang flg = TTY_BREAK; 697019dc9eaSHui Wang else if (rx & URXD_PRERR) 698ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 699ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 700ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 701ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 702ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 703ab4382d2SGreg Kroah-Hartman 704ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 705ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 706ab4382d2SGreg Kroah-Hartman #endif 707ab4382d2SGreg Kroah-Hartman } 708ab4382d2SGreg Kroah-Hartman 70955d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 71055d8693aSJiada Wang goto out; 71155d8693aSJiada Wang 7129b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 7139b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 714ab4382d2SGreg Kroah-Hartman } 715ab4382d2SGreg Kroah-Hartman 716ab4382d2SGreg Kroah-Hartman out: 717ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7182e124b4aSJiri Slaby tty_flip_buffer_push(port); 719ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 720ab4382d2SGreg Kroah-Hartman } 721ab4382d2SGreg Kroah-Hartman 72218a42088SPeter Senna Tschudin static void imx_disable_rx_int(struct imx_port *sport) 723b4cdc8f6SHuang Shijie { 724b4cdc8f6SHuang Shijie unsigned long temp; 72573631813SJiada Wang 726b4cdc8f6SHuang Shijie sport->dma_is_rxing = 1; 727b4cdc8f6SHuang Shijie 72886a04ba6SLucas Stach /* disable the receiver ready and aging timer interrupts */ 729b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 730b4cdc8f6SHuang Shijie temp &= ~(UCR1_RRDYEN); 731b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 732b4cdc8f6SHuang Shijie 73386a04ba6SLucas Stach temp = readl(sport->port.membase + UCR2); 73486a04ba6SLucas Stach temp &= ~(UCR2_ATEN); 73586a04ba6SLucas Stach writel(temp, sport->port.membase + UCR2); 73686a04ba6SLucas Stach 73741d98b5dSNandor Han /* disable the rx errors interrupts */ 73841d98b5dSNandor Han temp = readl(sport->port.membase + UCR4); 73941d98b5dSNandor Han temp &= ~UCR4_OREN; 74041d98b5dSNandor Han writel(temp, sport->port.membase + UCR4); 74118a42088SPeter Senna Tschudin } 74218a42088SPeter Senna Tschudin 74318a42088SPeter Senna Tschudin static void clear_rx_errors(struct imx_port *sport); 74418a42088SPeter Senna Tschudin static int start_rx_dma(struct imx_port *sport); 74518a42088SPeter Senna Tschudin /* 74618a42088SPeter Senna Tschudin * If the RXFIFO is filled with some data, and then we 74718a42088SPeter Senna Tschudin * arise a DMA operation to receive them. 74818a42088SPeter Senna Tschudin */ 74918a42088SPeter Senna Tschudin static void imx_dma_rxint(struct imx_port *sport) 75018a42088SPeter Senna Tschudin { 75118a42088SPeter Senna Tschudin unsigned long temp; 75218a42088SPeter Senna Tschudin unsigned long flags; 75318a42088SPeter Senna Tschudin 75418a42088SPeter Senna Tschudin spin_lock_irqsave(&sport->port.lock, flags); 75518a42088SPeter Senna Tschudin 75618a42088SPeter Senna Tschudin temp = readl(sport->port.membase + USR2); 75718a42088SPeter Senna Tschudin if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 75818a42088SPeter Senna Tschudin 75918a42088SPeter Senna Tschudin imx_disable_rx_int(sport); 76041d98b5dSNandor Han 761b4cdc8f6SHuang Shijie /* tell the DMA to receive the data. */ 7627cb92fd2SHuang Shijie start_rx_dma(sport); 763b4cdc8f6SHuang Shijie } 76473631813SJiada Wang 76573631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 766b4cdc8f6SHuang Shijie } 767b4cdc8f6SHuang Shijie 76866f95884SUwe Kleine-König /* 76966f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 77066f95884SUwe Kleine-König */ 77166f95884SUwe Kleine-König static unsigned int imx_get_hwmctrl(struct imx_port *sport) 77266f95884SUwe Kleine-König { 77366f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 77466f95884SUwe Kleine-König unsigned usr1 = readl(sport->port.membase + USR1); 7754b75f800SSascha Hauer unsigned usr2 = readl(sport->port.membase + USR2); 77666f95884SUwe Kleine-König 77766f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 77866f95884SUwe Kleine-König tmp |= TIOCM_CTS; 77966f95884SUwe Kleine-König 78066f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 7814b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 78266f95884SUwe Kleine-König tmp |= TIOCM_CAR; 78366f95884SUwe Kleine-König 78466f95884SUwe Kleine-König if (sport->dte_mode) 78566f95884SUwe Kleine-König if (!(readl(sport->port.membase + USR2) & USR2_RIIN)) 78666f95884SUwe Kleine-König tmp |= TIOCM_RI; 78766f95884SUwe Kleine-König 78866f95884SUwe Kleine-König return tmp; 78966f95884SUwe Kleine-König } 79066f95884SUwe Kleine-König 79166f95884SUwe Kleine-König /* 79266f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 79366f95884SUwe Kleine-König */ 79466f95884SUwe Kleine-König static void imx_mctrl_check(struct imx_port *sport) 79566f95884SUwe Kleine-König { 79666f95884SUwe Kleine-König unsigned int status, changed; 79766f95884SUwe Kleine-König 79866f95884SUwe Kleine-König status = imx_get_hwmctrl(sport); 79966f95884SUwe Kleine-König changed = status ^ sport->old_status; 80066f95884SUwe Kleine-König 80166f95884SUwe Kleine-König if (changed == 0) 80266f95884SUwe Kleine-König return; 80366f95884SUwe Kleine-König 80466f95884SUwe Kleine-König sport->old_status = status; 80566f95884SUwe Kleine-König 80666f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 80766f95884SUwe Kleine-König sport->port.icount.rng++; 80866f95884SUwe Kleine-König if (changed & TIOCM_DSR) 80966f95884SUwe Kleine-König sport->port.icount.dsr++; 81066f95884SUwe Kleine-König if (changed & TIOCM_CAR) 81166f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 81266f95884SUwe Kleine-König if (changed & TIOCM_CTS) 81366f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 81466f95884SUwe Kleine-König 81566f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 81666f95884SUwe Kleine-König } 81766f95884SUwe Kleine-König 818ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 819ab4382d2SGreg Kroah-Hartman { 820ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 821ab4382d2SGreg Kroah-Hartman unsigned int sts; 822f1f836e4SAlexander Stein unsigned int sts2; 8234d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 824ab4382d2SGreg Kroah-Hartman 825ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 82617b8f2a3SUwe Kleine-König sts2 = readl(sport->port.membase + USR2); 827ab4382d2SGreg Kroah-Hartman 82886a04ba6SLucas Stach if (sts & (USR1_RRDY | USR1_AGTIM)) { 829b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) 830b4cdc8f6SHuang Shijie imx_dma_rxint(sport); 831b4cdc8f6SHuang Shijie else 832ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 8334d845a62SUwe Kleine-König ret = IRQ_HANDLED; 834b4cdc8f6SHuang Shijie } 835ab4382d2SGreg Kroah-Hartman 83617b8f2a3SUwe Kleine-König if ((sts & USR1_TRDY && 83717b8f2a3SUwe Kleine-König readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || 83817b8f2a3SUwe Kleine-König (sts2 & USR2_TXDC && 8394d845a62SUwe Kleine-König readl(sport->port.membase + UCR4) & UCR4_TCEN)) { 840ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 8414d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8424d845a62SUwe Kleine-König } 843ab4382d2SGreg Kroah-Hartman 84427e16501SUwe Kleine-König if (sts & USR1_DTRD) { 84527e16501SUwe Kleine-König unsigned long flags; 84627e16501SUwe Kleine-König 84727e16501SUwe Kleine-König if (sts & USR1_DTRD) 84827e16501SUwe Kleine-König writel(USR1_DTRD, sport->port.membase + USR1); 84927e16501SUwe Kleine-König 85027e16501SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 85127e16501SUwe Kleine-König imx_mctrl_check(sport); 85227e16501SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 85327e16501SUwe Kleine-König 85427e16501SUwe Kleine-König ret = IRQ_HANDLED; 85527e16501SUwe Kleine-König } 85627e16501SUwe Kleine-König 8574d845a62SUwe Kleine-König if (sts & USR1_RTSD) { 858ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 8594d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8604d845a62SUwe Kleine-König } 861ab4382d2SGreg Kroah-Hartman 8624d845a62SUwe Kleine-König if (sts & USR1_AWAKE) { 863db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 8644d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8654d845a62SUwe Kleine-König } 866db1a9b55SFabio Estevam 867f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 868f1f836e4SAlexander Stein sport->port.icount.overrun++; 86991555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 8704d845a62SUwe Kleine-König ret = IRQ_HANDLED; 871f1f836e4SAlexander Stein } 872f1f836e4SAlexander Stein 8734d845a62SUwe Kleine-König return ret; 874ab4382d2SGreg Kroah-Hartman } 875ab4382d2SGreg Kroah-Hartman 876ab4382d2SGreg Kroah-Hartman /* 877ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 878ab4382d2SGreg Kroah-Hartman */ 879ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 880ab4382d2SGreg Kroah-Hartman { 881ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 8821ce43e58SHuang Shijie unsigned int ret; 883ab4382d2SGreg Kroah-Hartman 8841ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 8851ce43e58SHuang Shijie 8861ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 8871ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 8881ce43e58SHuang Shijie ret = 0; 8891ce43e58SHuang Shijie 8901ce43e58SHuang Shijie return ret; 891ab4382d2SGreg Kroah-Hartman } 892ab4382d2SGreg Kroah-Hartman 89358362d5bSUwe Kleine-König static unsigned int imx_get_mctrl(struct uart_port *port) 89458362d5bSUwe Kleine-König { 89558362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 89658362d5bSUwe Kleine-König unsigned int ret = imx_get_hwmctrl(sport); 89758362d5bSUwe Kleine-König 89858362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 89958362d5bSUwe Kleine-König 90058362d5bSUwe Kleine-König return ret; 90158362d5bSUwe Kleine-König } 90258362d5bSUwe Kleine-König 903ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 904ab4382d2SGreg Kroah-Hartman { 905ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 906ab4382d2SGreg Kroah-Hartman unsigned long temp; 907ab4382d2SGreg Kroah-Hartman 90817b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 90917b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 91017b8f2a3SUwe Kleine-König temp &= ~(UCR2_CTS | UCR2_CTSC); 911ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 912bb2f861aSFugang Duan temp |= UCR2_CTS | UCR2_CTSC; 913ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 91417b8f2a3SUwe Kleine-König } 9156b471a98SHuang Shijie 91690ebc483SUwe Kleine-König temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR; 91790ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 91890ebc483SUwe Kleine-König temp |= UCR3_DSR; 91990ebc483SUwe Kleine-König writel(temp, sport->port.membase + UCR3); 92090ebc483SUwe Kleine-König 9216b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 9226b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 9236b471a98SHuang Shijie temp |= UTS_LOOP; 9246b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 92558362d5bSUwe Kleine-König 92658362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 927ab4382d2SGreg Kroah-Hartman } 928ab4382d2SGreg Kroah-Hartman 929ab4382d2SGreg Kroah-Hartman /* 930ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 931ab4382d2SGreg Kroah-Hartman */ 932ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 933ab4382d2SGreg Kroah-Hartman { 934ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 935ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 936ab4382d2SGreg Kroah-Hartman 937ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 938ab4382d2SGreg Kroah-Hartman 939ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 940ab4382d2SGreg Kroah-Hartman 941ab4382d2SGreg Kroah-Hartman if (break_state != 0) 942ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 943ab4382d2SGreg Kroah-Hartman 944ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 945ab4382d2SGreg Kroah-Hartman 946ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 947ab4382d2SGreg Kroah-Hartman } 948ab4382d2SGreg Kroah-Hartman 949cc568849SUwe Kleine-König /* 950cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 951cc568849SUwe Kleine-König * modem status signals. 952cc568849SUwe Kleine-König */ 953cc568849SUwe Kleine-König static void imx_timeout(unsigned long data) 954cc568849SUwe Kleine-König { 955cc568849SUwe Kleine-König struct imx_port *sport = (struct imx_port *)data; 956cc568849SUwe Kleine-König unsigned long flags; 957cc568849SUwe Kleine-König 958cc568849SUwe Kleine-König if (sport->port.state) { 959cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 960cc568849SUwe Kleine-König imx_mctrl_check(sport); 961cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 962cc568849SUwe Kleine-König 963cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 964cc568849SUwe Kleine-König } 965cc568849SUwe Kleine-König } 966cc568849SUwe Kleine-König 967b4cdc8f6SHuang Shijie #define RX_BUF_SIZE (PAGE_SIZE) 968b4cdc8f6SHuang Shijie 969b4cdc8f6SHuang Shijie /* 970905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 971b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 972905c0decSLucas Stach * [2] the aging timer expires 973b4cdc8f6SHuang Shijie * 974905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 975905c0decSLucas Stach * for at least 8 byte durations. 976b4cdc8f6SHuang Shijie */ 977b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 978b4cdc8f6SHuang Shijie { 979b4cdc8f6SHuang Shijie struct imx_port *sport = data; 980b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 981b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9827cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 983b4cdc8f6SHuang Shijie struct dma_tx_state state; 9849d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 985b4cdc8f6SHuang Shijie enum dma_status status; 9869d297239SNandor Han unsigned int w_bytes = 0; 9879d297239SNandor Han unsigned int r_bytes; 9889d297239SNandor Han unsigned int bd_size; 989b4cdc8f6SHuang Shijie 990f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 991392bceedSPhilipp Zabel 9929d297239SNandor Han if (status == DMA_ERROR) { 9939d297239SNandor Han dev_err(sport->port.dev, "DMA transaction error.\n"); 99441d98b5dSNandor Han clear_rx_errors(sport); 9959d297239SNandor Han return; 9969d297239SNandor Han } 997b4cdc8f6SHuang Shijie 9989b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 999976b39cdSLucas Stach 1000976b39cdSLucas Stach /* 10019d297239SNandor Han * The state-residue variable represents the empty space 10029d297239SNandor Han * relative to the entire buffer. Taking this in consideration 10039d297239SNandor Han * the head is always calculated base on the buffer total 10049d297239SNandor Han * length - DMA transaction residue. The UART script from the 10059d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 10069d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 10079d297239SNandor Han * Taking this in consideration the tail is always at the 10089d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1009976b39cdSLucas Stach */ 10109d297239SNandor Han 10119d297239SNandor Han /* Calculate the head */ 10129d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 10139d297239SNandor Han 10149d297239SNandor Han /* Calculate the tail. */ 10159d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 10169d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 10179d297239SNandor Han 10189d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 10199d297239SNandor Han rx_ring->head > rx_ring->tail) { 10209d297239SNandor Han 10219d297239SNandor Han /* Move data from tail to head */ 10229d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 10239d297239SNandor Han 10249d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 10259d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 10269d297239SNandor Han DMA_FROM_DEVICE); 10279d297239SNandor Han 10289d297239SNandor Han w_bytes = tty_insert_flip_string(port, 10299d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 10309d297239SNandor Han 10319d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 10329d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 10339d297239SNandor Han DMA_FROM_DEVICE); 10349d297239SNandor Han 10359d297239SNandor Han if (w_bytes != r_bytes) 10369d297239SNandor Han sport->port.icount.buf_overrun++; 10379d297239SNandor Han 10389d297239SNandor Han sport->port.icount.rx += w_bytes; 10399d297239SNandor Han } else { 10409d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 10419d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1042ee5e7c10SRobin Gong } 10439d297239SNandor Han } 10449d297239SNandor Han 10459d297239SNandor Han if (w_bytes) { 10469d297239SNandor Han tty_flip_buffer_push(port); 10479d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 10489d297239SNandor Han } 10499d297239SNandor Han } 10509d297239SNandor Han 10519d297239SNandor Han /* RX DMA buffer periods */ 10529d297239SNandor Han #define RX_DMA_PERIODS 4 1053b4cdc8f6SHuang Shijie 1054b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 1055b4cdc8f6SHuang Shijie { 1056b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1057b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1058b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1059b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1060b4cdc8f6SHuang Shijie int ret; 1061b4cdc8f6SHuang Shijie 10629d297239SNandor Han sport->rx_ring.head = 0; 10639d297239SNandor Han sport->rx_ring.tail = 0; 10649d297239SNandor Han sport->rx_periods = RX_DMA_PERIODS; 10659d297239SNandor Han 1066b4cdc8f6SHuang Shijie sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1067b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1068b4cdc8f6SHuang Shijie if (ret == 0) { 1069b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1070b4cdc8f6SHuang Shijie return -EINVAL; 1071b4cdc8f6SHuang Shijie } 10729d297239SNandor Han 10739d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 10749d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 10759d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 10769d297239SNandor Han 1077b4cdc8f6SHuang Shijie if (!desc) { 107824649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1079b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1080b4cdc8f6SHuang Shijie return -EINVAL; 1081b4cdc8f6SHuang Shijie } 1082b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 1083b4cdc8f6SHuang Shijie desc->callback_param = sport; 1084b4cdc8f6SHuang Shijie 1085b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 10869d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1087b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1088b4cdc8f6SHuang Shijie return 0; 1089b4cdc8f6SHuang Shijie } 1090b4cdc8f6SHuang Shijie 109141d98b5dSNandor Han static void clear_rx_errors(struct imx_port *sport) 109241d98b5dSNandor Han { 109341d98b5dSNandor Han unsigned int status_usr1, status_usr2; 109441d98b5dSNandor Han 109541d98b5dSNandor Han status_usr1 = readl(sport->port.membase + USR1); 109641d98b5dSNandor Han status_usr2 = readl(sport->port.membase + USR2); 109741d98b5dSNandor Han 109841d98b5dSNandor Han if (status_usr2 & USR2_BRCD) { 109941d98b5dSNandor Han sport->port.icount.brk++; 110041d98b5dSNandor Han writel(USR2_BRCD, sport->port.membase + USR2); 110141d98b5dSNandor Han } else if (status_usr1 & USR1_FRAMERR) { 110241d98b5dSNandor Han sport->port.icount.frame++; 110341d98b5dSNandor Han writel(USR1_FRAMERR, sport->port.membase + USR1); 110441d98b5dSNandor Han } else if (status_usr1 & USR1_PARITYERR) { 110541d98b5dSNandor Han sport->port.icount.parity++; 110641d98b5dSNandor Han writel(USR1_PARITYERR, sport->port.membase + USR1); 110741d98b5dSNandor Han } 110841d98b5dSNandor Han 110941d98b5dSNandor Han if (status_usr2 & USR2_ORE) { 111041d98b5dSNandor Han sport->port.icount.overrun++; 111141d98b5dSNandor Han writel(USR2_ORE, sport->port.membase + USR2); 111241d98b5dSNandor Han } 111341d98b5dSNandor Han 111441d98b5dSNandor Han } 111541d98b5dSNandor Han 1116cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1117cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1118184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1119184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1120cc32382dSLucas Stach 1121cc32382dSLucas Stach static void imx_setup_ufcr(struct imx_port *sport, 1122cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1123cc32382dSLucas Stach { 1124cc32382dSLucas Stach unsigned int val; 1125cc32382dSLucas Stach 1126cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 1127cc32382dSLucas Stach val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1128cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 1129cc32382dSLucas Stach writel(val, sport->port.membase + UFCR); 1130cc32382dSLucas Stach } 1131cc32382dSLucas Stach 1132b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1133b4cdc8f6SHuang Shijie { 1134b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1135e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1136b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1137b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 11389d297239SNandor Han sport->rx_cookie = -EINVAL; 1139b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1140b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1141b4cdc8f6SHuang Shijie } 1142b4cdc8f6SHuang Shijie 1143b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1144e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1145b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1146b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1147b4cdc8f6SHuang Shijie } 1148b4cdc8f6SHuang Shijie 1149b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 1150b4cdc8f6SHuang Shijie } 1151b4cdc8f6SHuang Shijie 1152b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1153b4cdc8f6SHuang Shijie { 1154b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1155b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1156b4cdc8f6SHuang Shijie int ret; 1157b4cdc8f6SHuang Shijie 1158b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1159b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1160b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1161b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1162b4cdc8f6SHuang Shijie ret = -EINVAL; 1163b4cdc8f6SHuang Shijie goto err; 1164b4cdc8f6SHuang Shijie } 1165b4cdc8f6SHuang Shijie 1166b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1167b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1168b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1169184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1170184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1171b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1172b4cdc8f6SHuang Shijie if (ret) { 1173b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1174b4cdc8f6SHuang Shijie goto err; 1175b4cdc8f6SHuang Shijie } 1176b4cdc8f6SHuang Shijie 1177b4cdc8f6SHuang Shijie sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1178b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1179b4cdc8f6SHuang Shijie ret = -ENOMEM; 1180b4cdc8f6SHuang Shijie goto err; 1181b4cdc8f6SHuang Shijie } 11829d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1183b4cdc8f6SHuang Shijie 1184b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1185b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1186b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1187b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1188b4cdc8f6SHuang Shijie ret = -EINVAL; 1189b4cdc8f6SHuang Shijie goto err; 1190b4cdc8f6SHuang Shijie } 1191b4cdc8f6SHuang Shijie 1192b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1193b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1194b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1195184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1196b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1197b4cdc8f6SHuang Shijie if (ret) { 1198b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1199b4cdc8f6SHuang Shijie goto err; 1200b4cdc8f6SHuang Shijie } 1201b4cdc8f6SHuang Shijie 1202b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1203b4cdc8f6SHuang Shijie 1204b4cdc8f6SHuang Shijie return 0; 1205b4cdc8f6SHuang Shijie err: 1206b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1207b4cdc8f6SHuang Shijie return ret; 1208b4cdc8f6SHuang Shijie } 1209b4cdc8f6SHuang Shijie 1210b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1211b4cdc8f6SHuang Shijie { 1212b4cdc8f6SHuang Shijie unsigned long temp; 1213b4cdc8f6SHuang Shijie 12149ce4f8f3SGreg Kroah-Hartman init_waitqueue_head(&sport->dma_wait); 12159ce4f8f3SGreg Kroah-Hartman 1216b4cdc8f6SHuang Shijie /* set UCR1 */ 1217b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1218905c0decSLucas Stach temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN; 1219b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1220b4cdc8f6SHuang Shijie 122186a04ba6SLucas Stach temp = readl(sport->port.membase + UCR2); 122286a04ba6SLucas Stach temp |= UCR2_ATEN; 122386a04ba6SLucas Stach writel(temp, sport->port.membase + UCR2); 122486a04ba6SLucas Stach 1225184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1226184bd70bSLucas Stach 1227b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1228b4cdc8f6SHuang Shijie } 1229b4cdc8f6SHuang Shijie 1230b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1231b4cdc8f6SHuang Shijie { 1232b4cdc8f6SHuang Shijie unsigned long temp; 1233b4cdc8f6SHuang Shijie 1234b4cdc8f6SHuang Shijie /* clear UCR1 */ 1235b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1236b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1237b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1238b4cdc8f6SHuang Shijie 1239b4cdc8f6SHuang Shijie /* clear UCR2 */ 1240b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 124186a04ba6SLucas Stach temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN); 1242b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1243b4cdc8f6SHuang Shijie 1244184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1245184bd70bSLucas Stach 1246b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1247b4cdc8f6SHuang Shijie } 1248b4cdc8f6SHuang Shijie 1249ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1250ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1251ab4382d2SGreg Kroah-Hartman 1252ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1253ab4382d2SGreg Kroah-Hartman { 1254ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1255458e2c82SFabio Estevam int retval, i; 1256ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1257ab4382d2SGreg Kroah-Hartman 125828eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 125928eb4274SHuang Shijie if (retval) 1260cb0f0a5fSFabio Estevam return retval; 126128eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 12620c375501SHuang Shijie if (retval) { 12630c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1264cb0f0a5fSFabio Estevam return retval; 12650c375501SHuang Shijie } 126628eb4274SHuang Shijie 1267cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1268ab4382d2SGreg Kroah-Hartman 1269ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1270ab4382d2SGreg Kroah-Hartman * requesting IRQs 1271ab4382d2SGreg Kroah-Hartman */ 1272ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1273ab4382d2SGreg Kroah-Hartman 1274ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1275ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1276ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1277ab4382d2SGreg Kroah-Hartman 1278ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1279ab4382d2SGreg Kroah-Hartman 12807e11577eSLucas Stach /* Can we enable the DMA support? */ 12811c06bde6SMartyn Welch if (!uart_console(port) && !sport->dma_is_inited) 12827e11577eSLucas Stach imx_uart_dma_init(sport); 12837e11577eSLucas Stach 128453794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1285772f8991SHuang Shijie /* Reset fifo's and state machines */ 1286458e2c82SFabio Estevam i = 100; 1287458e2c82SFabio Estevam 1288458e2c82SFabio Estevam temp = readl(sport->port.membase + UCR2); 1289458e2c82SFabio Estevam temp &= ~UCR2_SRST; 1290458e2c82SFabio Estevam writel(temp, sport->port.membase + UCR2); 1291458e2c82SFabio Estevam 1292458e2c82SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1293458e2c82SFabio Estevam udelay(1); 1294ab4382d2SGreg Kroah-Hartman 1295ab4382d2SGreg Kroah-Hartman /* 1296ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1297ab4382d2SGreg Kroah-Hartman */ 129827e16501SUwe Kleine-König writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1); 129991555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 1300ab4382d2SGreg Kroah-Hartman 13017e11577eSLucas Stach if (sport->dma_is_inited && !sport->dma_is_enabled) 13027e11577eSLucas Stach imx_enable_dma(sport); 13037e11577eSLucas Stach 1304ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1305ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1306ab4382d2SGreg Kroah-Hartman 1307ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1308ab4382d2SGreg Kroah-Hartman 13096f026d6bSJiada Wang temp = readl(sport->port.membase + UCR4); 13106f026d6bSJiada Wang temp |= UCR4_OREN; 13116f026d6bSJiada Wang writel(temp, sport->port.membase + UCR4); 13126f026d6bSJiada Wang 1313ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1314ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1315bff09b09SLucas Stach if (!sport->have_rtscts) 1316bff09b09SLucas Stach temp |= UCR2_IRTS; 131716804d68SUwe Kleine-König /* 131816804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 131916804d68SUwe Kleine-König * we're using RTSD instead. 132016804d68SUwe Kleine-König */ 132116804d68SUwe Kleine-König if (!is_imx1_uart(sport)) 132216804d68SUwe Kleine-König temp &= ~UCR2_RTSEN; 1323ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1324ab4382d2SGreg Kroah-Hartman 1325a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1326ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 132716804d68SUwe Kleine-König 1328e61c38d8SUwe Kleine-König temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 132916804d68SUwe Kleine-König 133016804d68SUwe Kleine-König if (sport->dte_mode) 1331e61c38d8SUwe Kleine-König /* disable broken interrupts */ 133216804d68SUwe Kleine-König temp &= ~(UCR3_RI | UCR3_DCD); 133316804d68SUwe Kleine-König 1334ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1335ab4382d2SGreg Kroah-Hartman } 1336ab4382d2SGreg Kroah-Hartman 1337ab4382d2SGreg Kroah-Hartman /* 1338ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1339ab4382d2SGreg Kroah-Hartman */ 1340ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 134118a42088SPeter Senna Tschudin 134218a42088SPeter Senna Tschudin /* 13434dec2f11SPeter Senna Tschudin * Start RX DMA immediately instead of waiting for RX FIFO interrupts. 13444dec2f11SPeter Senna Tschudin * In our iMX53 the average delay for the first reception dropped from 13454dec2f11SPeter Senna Tschudin * approximately 35000 microseconds to 1000 microseconds. 134618a42088SPeter Senna Tschudin */ 134718a42088SPeter Senna Tschudin if (sport->dma_is_enabled) { 134818a42088SPeter Senna Tschudin imx_disable_rx_int(sport); 134918a42088SPeter Senna Tschudin start_rx_dma(sport); 135018a42088SPeter Senna Tschudin } 135118a42088SPeter Senna Tschudin 1352ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1353ab4382d2SGreg Kroah-Hartman 1354ab4382d2SGreg Kroah-Hartman return 0; 1355ab4382d2SGreg Kroah-Hartman } 1356ab4382d2SGreg Kroah-Hartman 1357ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1358ab4382d2SGreg Kroah-Hartman { 1359ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1360ab4382d2SGreg Kroah-Hartman unsigned long temp; 13619ec1882dSXinyu Chen unsigned long flags; 1362ab4382d2SGreg Kroah-Hartman 1363b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1364a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1365a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1366e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1367e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 13689d297239SNandor Han 136973631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1370a4688bcdSHuang Shijie imx_stop_tx(port); 1371b4cdc8f6SHuang Shijie imx_stop_rx(port); 1372b4cdc8f6SHuang Shijie imx_disable_dma(sport); 137373631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1374b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1375b4cdc8f6SHuang Shijie } 1376b4cdc8f6SHuang Shijie 137758362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 137858362d5bSUwe Kleine-König 13799ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1380ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1381ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1382ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 13839ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1384ab4382d2SGreg Kroah-Hartman 1385ab4382d2SGreg Kroah-Hartman /* 1386ab4382d2SGreg Kroah-Hartman * Stop our timer. 1387ab4382d2SGreg Kroah-Hartman */ 1388ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1389ab4382d2SGreg Kroah-Hartman 1390ab4382d2SGreg Kroah-Hartman /* 1391ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1392ab4382d2SGreg Kroah-Hartman */ 1393ab4382d2SGreg Kroah-Hartman 13949ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1395ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1396ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1397ab4382d2SGreg Kroah-Hartman 1398ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 13999ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 140028eb4274SHuang Shijie 140128eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 140228eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1403ab4382d2SGreg Kroah-Hartman } 1404ab4382d2SGreg Kroah-Hartman 1405eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1406eb56b7edSHuang Shijie { 1407eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 140882e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1409a2c718ceSDirk Behme unsigned long temp; 14104f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1411eb56b7edSHuang Shijie 141282e86ae9SDirk Behme if (!sport->dma_chan_tx) 141382e86ae9SDirk Behme return; 141482e86ae9SDirk Behme 1415eb56b7edSHuang Shijie sport->tx_bytes = 0; 1416eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 141782e86ae9SDirk Behme if (sport->dma_is_txing) { 141882e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 141982e86ae9SDirk Behme DMA_TO_DEVICE); 1420a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 1421a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 1422a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 142382e86ae9SDirk Behme sport->dma_is_txing = false; 1424eb56b7edSHuang Shijie } 1425934084a9SFabio Estevam 1426934084a9SFabio Estevam /* 1427934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1428934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1429934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1430934084a9SFabio Estevam * and UTS[6-3]". As we don't need to restore the old values from 1431934084a9SFabio Estevam * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1432934084a9SFabio Estevam */ 1433934084a9SFabio Estevam ubir = readl(sport->port.membase + UBIR); 1434934084a9SFabio Estevam ubmr = readl(sport->port.membase + UBMR); 1435934084a9SFabio Estevam uts = readl(sport->port.membase + IMX21_UTS); 1436934084a9SFabio Estevam 1437934084a9SFabio Estevam temp = readl(sport->port.membase + UCR2); 1438934084a9SFabio Estevam temp &= ~UCR2_SRST; 1439934084a9SFabio Estevam writel(temp, sport->port.membase + UCR2); 1440934084a9SFabio Estevam 1441934084a9SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1442934084a9SFabio Estevam udelay(1); 1443934084a9SFabio Estevam 1444934084a9SFabio Estevam /* Restore the registers */ 1445934084a9SFabio Estevam writel(ubir, sport->port.membase + UBIR); 1446934084a9SFabio Estevam writel(ubmr, sport->port.membase + UBMR); 1447934084a9SFabio Estevam writel(uts, sport->port.membase + IMX21_UTS); 1448eb56b7edSHuang Shijie } 1449eb56b7edSHuang Shijie 1450ab4382d2SGreg Kroah-Hartman static void 1451ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1452ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1453ab4382d2SGreg Kroah-Hartman { 1454ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1455ab4382d2SGreg Kroah-Hartman unsigned long flags; 145658362d5bSUwe Kleine-König unsigned long ucr2, old_ucr1, old_ucr2; 145758362d5bSUwe Kleine-König unsigned int baud, quot; 1458ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 145958362d5bSUwe Kleine-König unsigned long div, ufcr; 1460ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1461ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1462ab4382d2SGreg Kroah-Hartman 1463ab4382d2SGreg Kroah-Hartman /* 1464ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1465ab4382d2SGreg Kroah-Hartman */ 1466ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1467ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1468ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1469ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1470ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1471ab4382d2SGreg Kroah-Hartman } 1472ab4382d2SGreg Kroah-Hartman 1473ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1474ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1475ab4382d2SGreg Kroah-Hartman else 1476ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1477ab4382d2SGreg Kroah-Hartman 1478ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1479ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1480ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 148117b8f2a3SUwe Kleine-König 148212fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 148317b8f2a3SUwe Kleine-König /* 148417b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 148517b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 148617b8f2a3SUwe Kleine-König * disabled. 148717b8f2a3SUwe Kleine-König */ 148858362d5bSUwe Kleine-König if (port->rs485.flags & 148958362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 149058362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 14911a613626SFabio Estevam else 14921a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 149312fe59f9SFabio Estevam } else { 149458362d5bSUwe Kleine-König imx_port_rts_auto(sport, &ucr2); 149512fe59f9SFabio Estevam } 1496ab4382d2SGreg Kroah-Hartman } else { 1497ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1498ab4382d2SGreg Kroah-Hartman } 149958362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 150017b8f2a3SUwe Kleine-König /* disable transmitter */ 150158362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 150258362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 15031a613626SFabio Estevam else 15041a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 150558362d5bSUwe Kleine-König } 150658362d5bSUwe Kleine-König 1507ab4382d2SGreg Kroah-Hartman 1508ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1509ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1510ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1511ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1512ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1513ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1514ab4382d2SGreg Kroah-Hartman } 1515ab4382d2SGreg Kroah-Hartman 1516995234daSEric Miao del_timer_sync(&sport->timer); 1517995234daSEric Miao 1518ab4382d2SGreg Kroah-Hartman /* 1519ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1520ab4382d2SGreg Kroah-Hartman */ 1521ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1522ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1523ab4382d2SGreg Kroah-Hartman 1524ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1525ab4382d2SGreg Kroah-Hartman 1526ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1527ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1528ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1529ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1530ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1531ab4382d2SGreg Kroah-Hartman 1532ab4382d2SGreg Kroah-Hartman /* 1533ab4382d2SGreg Kroah-Hartman * Characters to ignore 1534ab4382d2SGreg Kroah-Hartman */ 1535ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1536ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1537865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1538ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1539ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1540ab4382d2SGreg Kroah-Hartman /* 1541ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1542ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1543ab4382d2SGreg Kroah-Hartman */ 1544ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1545ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1546ab4382d2SGreg Kroah-Hartman } 1547ab4382d2SGreg Kroah-Hartman 154855d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 154955d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 155055d8693aSJiada Wang 1551ab4382d2SGreg Kroah-Hartman /* 1552ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1553ab4382d2SGreg Kroah-Hartman */ 1554ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1555ab4382d2SGreg Kroah-Hartman 1556ab4382d2SGreg Kroah-Hartman /* 1557ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1558ab4382d2SGreg Kroah-Hartman */ 1559ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1560ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1561ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1562ab4382d2SGreg Kroah-Hartman 1563ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1564ab4382d2SGreg Kroah-Hartman barrier(); 1565ab4382d2SGreg Kroah-Hartman 1566ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 156786a04ba6SLucas Stach old_ucr2 = readl(sport->port.membase + UCR2); 156886a04ba6SLucas Stach writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN), 1569ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 157086a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1571ab4382d2SGreg Kroah-Hartman 157209bd00f6SHubert Feurstein /* custom-baudrate handling */ 157309bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 157409bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 157509bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 157609bd00f6SHubert Feurstein 1577ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1578ab4382d2SGreg Kroah-Hartman if (div > 7) 1579ab4382d2SGreg Kroah-Hartman div = 7; 1580ab4382d2SGreg Kroah-Hartman if (!div) 1581ab4382d2SGreg Kroah-Hartman div = 1; 1582ab4382d2SGreg Kroah-Hartman 1583ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1584ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1585ab4382d2SGreg Kroah-Hartman 1586ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1587ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1588ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1589ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1590ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1591ab4382d2SGreg Kroah-Hartman 1592ab4382d2SGreg Kroah-Hartman num -= 1; 1593ab4382d2SGreg Kroah-Hartman denom -= 1; 1594ab4382d2SGreg Kroah-Hartman 1595ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1596ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1597ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1598ab4382d2SGreg Kroah-Hartman 1599ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1600ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1601ab4382d2SGreg Kroah-Hartman 1602a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1603ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1604fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1605ab4382d2SGreg Kroah-Hartman 1606ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1607ab4382d2SGreg Kroah-Hartman 1608ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 160986a04ba6SLucas Stach writel(ucr2 | old_ucr2, sport->port.membase + UCR2); 1610ab4382d2SGreg Kroah-Hartman 1611ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1612ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1613ab4382d2SGreg Kroah-Hartman 1614ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1615ab4382d2SGreg Kroah-Hartman } 1616ab4382d2SGreg Kroah-Hartman 1617ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1618ab4382d2SGreg Kroah-Hartman { 1619ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1620ab4382d2SGreg Kroah-Hartman 1621ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1622ab4382d2SGreg Kroah-Hartman } 1623ab4382d2SGreg Kroah-Hartman 1624ab4382d2SGreg Kroah-Hartman /* 1625ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1626ab4382d2SGreg Kroah-Hartman */ 1627ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1628ab4382d2SGreg Kroah-Hartman { 1629ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1630ab4382d2SGreg Kroah-Hartman 1631da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1632ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1633ab4382d2SGreg Kroah-Hartman } 1634ab4382d2SGreg Kroah-Hartman 1635ab4382d2SGreg Kroah-Hartman /* 1636ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1637ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1638ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1639ab4382d2SGreg Kroah-Hartman */ 1640ab4382d2SGreg Kroah-Hartman static int 1641ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1642ab4382d2SGreg Kroah-Hartman { 1643ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1644ab4382d2SGreg Kroah-Hartman int ret = 0; 1645ab4382d2SGreg Kroah-Hartman 1646ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1647ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1648ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1649ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1650ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1651ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1652ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1653ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1654a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1655ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1656ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1657ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1658ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1659ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1660ab4382d2SGreg Kroah-Hartman return ret; 1661ab4382d2SGreg Kroah-Hartman } 1662ab4382d2SGreg Kroah-Hartman 166301f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 16646b8bdad9SDaniel Thompson 16656b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 16666b8bdad9SDaniel Thompson { 16676b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 16686b8bdad9SDaniel Thompson unsigned long flags; 16696b8bdad9SDaniel Thompson unsigned long temp; 16706b8bdad9SDaniel Thompson int retval; 16716b8bdad9SDaniel Thompson 16726b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 16736b8bdad9SDaniel Thompson if (retval) 16746b8bdad9SDaniel Thompson return retval; 16756b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 16766b8bdad9SDaniel Thompson if (retval) 16776b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 16786b8bdad9SDaniel Thompson 1679cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 16806b8bdad9SDaniel Thompson 16816b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 16826b8bdad9SDaniel Thompson 16836b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR1); 16846b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 16856b8bdad9SDaniel Thompson temp |= IMX1_UCR1_UARTCLKEN; 16866b8bdad9SDaniel Thompson temp |= UCR1_UARTEN | UCR1_RRDYEN; 16876b8bdad9SDaniel Thompson temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 16886b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR1); 16896b8bdad9SDaniel Thompson 16906b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR2); 16916b8bdad9SDaniel Thompson temp |= UCR2_RXEN; 16926b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR2); 16936b8bdad9SDaniel Thompson 16946b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 16956b8bdad9SDaniel Thompson 16966b8bdad9SDaniel Thompson return 0; 16976b8bdad9SDaniel Thompson } 16986b8bdad9SDaniel Thompson 169901f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 170001f56abdSSaleem Abdulrasool { 1701f968ef34SDaniel Thompson if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 170226c47412SDirk Behme return NO_POLL_CHAR; 170301f56abdSSaleem Abdulrasool 1704f968ef34SDaniel Thompson return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 170501f56abdSSaleem Abdulrasool } 170601f56abdSSaleem Abdulrasool 170701f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 170801f56abdSSaleem Abdulrasool { 170901f56abdSSaleem Abdulrasool unsigned int status; 171001f56abdSSaleem Abdulrasool 171101f56abdSSaleem Abdulrasool /* drain */ 171201f56abdSSaleem Abdulrasool do { 1713f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR1); 171401f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 171501f56abdSSaleem Abdulrasool 171601f56abdSSaleem Abdulrasool /* write */ 1717f968ef34SDaniel Thompson writel_relaxed(c, port->membase + URTX0); 171801f56abdSSaleem Abdulrasool 171901f56abdSSaleem Abdulrasool /* flush */ 172001f56abdSSaleem Abdulrasool do { 1721f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR2); 172201f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 172301f56abdSSaleem Abdulrasool } 172401f56abdSSaleem Abdulrasool #endif 172501f56abdSSaleem Abdulrasool 172617b8f2a3SUwe Kleine-König static int imx_rs485_config(struct uart_port *port, 172717b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 172817b8f2a3SUwe Kleine-König { 172917b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 17307d1cadcaSBaruch Siach unsigned long temp; 173117b8f2a3SUwe Kleine-König 173217b8f2a3SUwe Kleine-König /* unimplemented */ 173317b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 173417b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 173517b8f2a3SUwe Kleine-König 173617b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 17377b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 173817b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 173917b8f2a3SUwe Kleine-König 174017b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 174117b8f2a3SUwe Kleine-König /* disable transmitter */ 174217b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 174317b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 174458362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 17451a613626SFabio Estevam else 17461a613626SFabio Estevam imx_port_rts_inactive(sport, &temp); 174717b8f2a3SUwe Kleine-König writel(temp, sport->port.membase + UCR2); 174817b8f2a3SUwe Kleine-König } 174917b8f2a3SUwe Kleine-König 17507d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 17517d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 17527d1cadcaSBaruch Siach rs485conf->flags & SER_RS485_RX_DURING_TX) { 17537d1cadcaSBaruch Siach temp = readl(sport->port.membase + UCR2); 17547d1cadcaSBaruch Siach temp |= UCR2_RXEN; 17557d1cadcaSBaruch Siach writel(temp, sport->port.membase + UCR2); 17567d1cadcaSBaruch Siach } 17577d1cadcaSBaruch Siach 175817b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 175917b8f2a3SUwe Kleine-König 176017b8f2a3SUwe Kleine-König return 0; 176117b8f2a3SUwe Kleine-König } 176217b8f2a3SUwe Kleine-König 1763069a47e5SJulia Lawall static const struct uart_ops imx_pops = { 1764ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1765ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1766ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1767ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1768ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1769ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1770ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1771ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1772ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1773ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1774eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1775ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1776ab4382d2SGreg Kroah-Hartman .type = imx_type, 1777ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1778ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 177901f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17806b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 178101f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 178201f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 178301f56abdSSaleem Abdulrasool #endif 1784ab4382d2SGreg Kroah-Hartman }; 1785ab4382d2SGreg Kroah-Hartman 1786ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1787ab4382d2SGreg Kroah-Hartman 1788ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1789ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1790ab4382d2SGreg Kroah-Hartman { 1791ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1792ab4382d2SGreg Kroah-Hartman 1793fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1794ab4382d2SGreg Kroah-Hartman barrier(); 1795ab4382d2SGreg Kroah-Hartman 1796ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1797ab4382d2SGreg Kroah-Hartman } 1798ab4382d2SGreg Kroah-Hartman 1799ab4382d2SGreg Kroah-Hartman /* 1800ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1801ab4382d2SGreg Kroah-Hartman */ 1802ab4382d2SGreg Kroah-Hartman static void 1803ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1804ab4382d2SGreg Kroah-Hartman { 1805ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 18060ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 18070ad5a814SDirk Behme unsigned int ucr1; 1808f30e8260SShawn Guo unsigned long flags = 0; 1809677fe555SThomas Gleixner int locked = 1; 18101cf93e0dSHuang Shijie int retval; 18111cf93e0dSHuang Shijie 18120c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 18131cf93e0dSHuang Shijie if (retval) 18141cf93e0dSHuang Shijie return; 18150c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 18161cf93e0dSHuang Shijie if (retval) { 18170c727a42SFabio Estevam clk_disable(sport->clk_per); 18181cf93e0dSHuang Shijie return; 18191cf93e0dSHuang Shijie } 18209ec1882dSXinyu Chen 1821677fe555SThomas Gleixner if (sport->port.sysrq) 1822677fe555SThomas Gleixner locked = 0; 1823677fe555SThomas Gleixner else if (oops_in_progress) 1824677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1825677fe555SThomas Gleixner else 18269ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1827ab4382d2SGreg Kroah-Hartman 1828ab4382d2SGreg Kroah-Hartman /* 18290ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1830ab4382d2SGreg Kroah-Hartman */ 18310ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 18320ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1833ab4382d2SGreg Kroah-Hartman 1834fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1835fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1836ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1837ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1838ab4382d2SGreg Kroah-Hartman 1839ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1840ab4382d2SGreg Kroah-Hartman 18410ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1842ab4382d2SGreg Kroah-Hartman 1843ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1844ab4382d2SGreg Kroah-Hartman 1845ab4382d2SGreg Kroah-Hartman /* 1846ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 18470ad5a814SDirk Behme * and restore UCR1/2/3 1848ab4382d2SGreg Kroah-Hartman */ 1849ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1850ab4382d2SGreg Kroah-Hartman 18510ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 18529ec1882dSXinyu Chen 1853677fe555SThomas Gleixner if (locked) 18549ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 18551cf93e0dSHuang Shijie 18560c727a42SFabio Estevam clk_disable(sport->clk_ipg); 18570c727a42SFabio Estevam clk_disable(sport->clk_per); 1858ab4382d2SGreg Kroah-Hartman } 1859ab4382d2SGreg Kroah-Hartman 1860ab4382d2SGreg Kroah-Hartman /* 1861ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1862ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1863ab4382d2SGreg Kroah-Hartman */ 1864ab4382d2SGreg Kroah-Hartman static void __init 1865ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1866ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1867ab4382d2SGreg Kroah-Hartman { 1868ab4382d2SGreg Kroah-Hartman 1869ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1870ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1871ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1872ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1873ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1874ab4382d2SGreg Kroah-Hartman 1875ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1876ab4382d2SGreg Kroah-Hartman 1877ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1878ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1879ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1880ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1881ab4382d2SGreg Kroah-Hartman else 1882ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1883ab4382d2SGreg Kroah-Hartman } 1884ab4382d2SGreg Kroah-Hartman 1885ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1886ab4382d2SGreg Kroah-Hartman *bits = 8; 1887ab4382d2SGreg Kroah-Hartman else 1888ab4382d2SGreg Kroah-Hartman *bits = 7; 1889ab4382d2SGreg Kroah-Hartman 1890ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1891ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1892ab4382d2SGreg Kroah-Hartman 1893ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1894ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1895ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1896ab4382d2SGreg Kroah-Hartman else 1897ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1898ab4382d2SGreg Kroah-Hartman 18993a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1900ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1901ab4382d2SGreg Kroah-Hartman 1902ab4382d2SGreg Kroah-Hartman { /* 1903ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1904ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1905ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1906ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1907ab4382d2SGreg Kroah-Hartman */ 1908ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1909ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1910ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1911ab4382d2SGreg Kroah-Hartman 1912ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1913ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1914ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1915ab4382d2SGreg Kroah-Hartman } 1916ab4382d2SGreg Kroah-Hartman 1917ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 191850bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1919ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1920ab4382d2SGreg Kroah-Hartman } 1921ab4382d2SGreg Kroah-Hartman } 1922ab4382d2SGreg Kroah-Hartman 1923ab4382d2SGreg Kroah-Hartman static int __init 1924ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1925ab4382d2SGreg Kroah-Hartman { 1926ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1927ab4382d2SGreg Kroah-Hartman int baud = 9600; 1928ab4382d2SGreg Kroah-Hartman int bits = 8; 1929ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1930ab4382d2SGreg Kroah-Hartman int flow = 'n'; 19311cf93e0dSHuang Shijie int retval; 1932ab4382d2SGreg Kroah-Hartman 1933ab4382d2SGreg Kroah-Hartman /* 1934ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1935ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1936ab4382d2SGreg Kroah-Hartman * console support. 1937ab4382d2SGreg Kroah-Hartman */ 1938ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1939ab4382d2SGreg Kroah-Hartman co->index = 0; 1940ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1941ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1942ab4382d2SGreg Kroah-Hartman return -ENODEV; 1943ab4382d2SGreg Kroah-Hartman 19441cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 19451cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 19461cf93e0dSHuang Shijie if (retval) 19471cf93e0dSHuang Shijie goto error_console; 19481cf93e0dSHuang Shijie 1949ab4382d2SGreg Kroah-Hartman if (options) 1950ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1951ab4382d2SGreg Kroah-Hartman else 1952ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1953ab4382d2SGreg Kroah-Hartman 1954cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1955ab4382d2SGreg Kroah-Hartman 19561cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 19571cf93e0dSHuang Shijie 19580c727a42SFabio Estevam clk_disable(sport->clk_ipg); 19590c727a42SFabio Estevam if (retval) { 19600c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 19610c727a42SFabio Estevam goto error_console; 19620c727a42SFabio Estevam } 19630c727a42SFabio Estevam 19640c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 19650c727a42SFabio Estevam if (retval) 19661cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 19671cf93e0dSHuang Shijie 19681cf93e0dSHuang Shijie error_console: 19691cf93e0dSHuang Shijie return retval; 1970ab4382d2SGreg Kroah-Hartman } 1971ab4382d2SGreg Kroah-Hartman 1972ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1973ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1974ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1975ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1976ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1977ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1978ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1979ab4382d2SGreg Kroah-Hartman .index = -1, 1980ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1981ab4382d2SGreg Kroah-Hartman }; 1982ab4382d2SGreg Kroah-Hartman 1983ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1984913c6c0eSLucas Stach 1985913c6c0eSLucas Stach #ifdef CONFIG_OF 1986913c6c0eSLucas Stach static void imx_console_early_putchar(struct uart_port *port, int ch) 1987913c6c0eSLucas Stach { 1988913c6c0eSLucas Stach while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL) 1989913c6c0eSLucas Stach cpu_relax(); 1990913c6c0eSLucas Stach 1991913c6c0eSLucas Stach writel_relaxed(ch, port->membase + URTX0); 1992913c6c0eSLucas Stach } 1993913c6c0eSLucas Stach 1994913c6c0eSLucas Stach static void imx_console_early_write(struct console *con, const char *s, 1995913c6c0eSLucas Stach unsigned count) 1996913c6c0eSLucas Stach { 1997913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 1998913c6c0eSLucas Stach 1999913c6c0eSLucas Stach uart_console_write(&dev->port, s, count, imx_console_early_putchar); 2000913c6c0eSLucas Stach } 2001913c6c0eSLucas Stach 2002913c6c0eSLucas Stach static int __init 2003913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2004913c6c0eSLucas Stach { 2005913c6c0eSLucas Stach if (!dev->port.membase) 2006913c6c0eSLucas Stach return -ENODEV; 2007913c6c0eSLucas Stach 2008913c6c0eSLucas Stach dev->con->write = imx_console_early_write; 2009913c6c0eSLucas Stach 2010913c6c0eSLucas Stach return 0; 2011913c6c0eSLucas Stach } 2012913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2013913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2014913c6c0eSLucas Stach #endif 2015913c6c0eSLucas Stach 2016ab4382d2SGreg Kroah-Hartman #else 2017ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2018ab4382d2SGreg Kroah-Hartman #endif 2019ab4382d2SGreg Kroah-Hartman 2020ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 2021ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2022ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2023ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2024ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2025ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 2026ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 2027ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2028ab4382d2SGreg Kroah-Hartman }; 2029ab4382d2SGreg Kroah-Hartman 203022698aa2SShawn Guo #ifdef CONFIG_OF 203120bb8095SUwe Kleine-König /* 203220bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 203320bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 203420bb8095SUwe Kleine-König */ 203522698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 203622698aa2SShawn Guo struct platform_device *pdev) 203722698aa2SShawn Guo { 203822698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2039ff05967aSShawn Guo int ret; 204022698aa2SShawn Guo 20415f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 20425f8b9043SLABBE Corentin if (!sport->devdata) 204320bb8095SUwe Kleine-König /* no device tree device */ 204420bb8095SUwe Kleine-König return 1; 204522698aa2SShawn Guo 2046ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2047ff05967aSShawn Guo if (ret < 0) { 2048ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2049a197a191SUwe Kleine-König return ret; 2050ff05967aSShawn Guo } 2051ff05967aSShawn Guo sport->port.line = ret; 205222698aa2SShawn Guo 20531006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 20541006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 205522698aa2SShawn Guo sport->have_rtscts = 1; 205622698aa2SShawn Guo 205720ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 205820ff2fe6SHuang Shijie sport->dte_mode = 1; 205920ff2fe6SHuang Shijie 20607b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 20617b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 20627b7e8e8eSFabio Estevam 206322698aa2SShawn Guo return 0; 206422698aa2SShawn Guo } 206522698aa2SShawn Guo #else 206622698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 206722698aa2SShawn Guo struct platform_device *pdev) 206822698aa2SShawn Guo { 206920bb8095SUwe Kleine-König return 1; 207022698aa2SShawn Guo } 207122698aa2SShawn Guo #endif 207222698aa2SShawn Guo 207322698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 207422698aa2SShawn Guo struct platform_device *pdev) 207522698aa2SShawn Guo { 2076574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 207722698aa2SShawn Guo 207822698aa2SShawn Guo sport->port.line = pdev->id; 207922698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 208022698aa2SShawn Guo 208122698aa2SShawn Guo if (!pdata) 208222698aa2SShawn Guo return; 208322698aa2SShawn Guo 208422698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 208522698aa2SShawn Guo sport->have_rtscts = 1; 208622698aa2SShawn Guo } 208722698aa2SShawn Guo 2088ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 2089ab4382d2SGreg Kroah-Hartman { 2090ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2091ab4382d2SGreg Kroah-Hartman void __iomem *base; 20928a61f0c7SFabio Estevam int ret = 0, reg; 2093ab4382d2SGreg Kroah-Hartman struct resource *res; 2094842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2095ab4382d2SGreg Kroah-Hartman 209642d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2097ab4382d2SGreg Kroah-Hartman if (!sport) 2098ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2099ab4382d2SGreg Kroah-Hartman 210022698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 210120bb8095SUwe Kleine-König if (ret > 0) 210222698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 210320bb8095SUwe Kleine-König else if (ret < 0) 210442d34191SSachin Kamat return ret; 210522698aa2SShawn Guo 2106ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2107da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2108da82f997SAlexander Shiyan if (IS_ERR(base)) 2109da82f997SAlexander Shiyan return PTR_ERR(base); 2110ab4382d2SGreg Kroah-Hartman 2111842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2112842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2113842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2114842633bdSUwe Kleine-König 2115ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2116ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2117ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2118ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2119ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2120842633bdSUwe Kleine-König sport->port.irq = rxirq; 2121ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2122ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 212317b8f2a3SUwe Kleine-König sport->port.rs485_config = imx_rs485_config; 212417b8f2a3SUwe Kleine-König sport->port.rs485.flags = 212517b8f2a3SUwe Kleine-König SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX; 2126ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 2127ab4382d2SGreg Kroah-Hartman init_timer(&sport->timer); 2128ab4382d2SGreg Kroah-Hartman sport->timer.function = imx_timeout; 2129ab4382d2SGreg Kroah-Hartman sport->timer.data = (unsigned long)sport; 2130ab4382d2SGreg Kroah-Hartman 213158362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 213258362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 213358362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 213458362d5bSUwe Kleine-König 21353a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 21363a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 21373a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2138833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 213942d34191SSachin Kamat return ret; 2140ab4382d2SGreg Kroah-Hartman } 2141ab4382d2SGreg Kroah-Hartman 21423a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 21433a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 21443a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2145833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 214642d34191SSachin Kamat return ret; 21473a9465faSSascha Hauer } 21483a9465faSSascha Hauer 21493a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2150ab4382d2SGreg Kroah-Hartman 21518a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 21528a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 21531e512d45SUwe Kleine-König if (ret) { 21541e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 21558a61f0c7SFabio Estevam return ret; 21561e512d45SUwe Kleine-König } 21578a61f0c7SFabio Estevam 21588a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 21598a61f0c7SFabio Estevam reg = readl_relaxed(sport->port.membase + UCR1); 21608a61f0c7SFabio Estevam reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 21618a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 21628a61f0c7SFabio Estevam writel_relaxed(reg, sport->port.membase + UCR1); 21638a61f0c7SFabio Estevam 2164e61c38d8SUwe Kleine-König if (!is_imx1_uart(sport) && sport->dte_mode) { 2165e61c38d8SUwe Kleine-König /* 2166e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2167e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2168e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2169e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2170e61c38d8SUwe Kleine-König */ 2171e61c38d8SUwe Kleine-König writel(UFCR_DCEDTE, sport->port.membase + UFCR); 2172e61c38d8SUwe Kleine-König 2173e61c38d8SUwe Kleine-König /* 2174e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2175e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2176e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2177e61c38d8SUwe Kleine-König */ 2178e61c38d8SUwe Kleine-König writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2179e61c38d8SUwe Kleine-König sport->port.membase + UCR3); 2180e61c38d8SUwe Kleine-König 2181e61c38d8SUwe Kleine-König } else { 2182e61c38d8SUwe Kleine-König writel(0, sport->port.membase + UFCR); 2183e61c38d8SUwe Kleine-König } 2184e61c38d8SUwe Kleine-König 21858a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 21868a61f0c7SFabio Estevam 2187c0d1c6b0SFabio Estevam /* 2188c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2189c0d1c6b0SFabio Estevam * chips only have one interrupt. 2190c0d1c6b0SFabio Estevam */ 2191842633bdSUwe Kleine-König if (txirq > 0) { 2192842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2193c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 21941e512d45SUwe Kleine-König if (ret) { 21951e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 21961e512d45SUwe Kleine-König ret); 2197c0d1c6b0SFabio Estevam return ret; 21981e512d45SUwe Kleine-König } 2199c0d1c6b0SFabio Estevam 2200842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2201c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 22021e512d45SUwe Kleine-König if (ret) { 22031e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 22041e512d45SUwe Kleine-König ret); 2205c0d1c6b0SFabio Estevam return ret; 22061e512d45SUwe Kleine-König } 2207c0d1c6b0SFabio Estevam } else { 2208842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2209c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 22101e512d45SUwe Kleine-König if (ret) { 22111e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2212c0d1c6b0SFabio Estevam return ret; 2213c0d1c6b0SFabio Estevam } 22141e512d45SUwe Kleine-König } 2215c0d1c6b0SFabio Estevam 221622698aa2SShawn Guo imx_ports[sport->port.line] = sport; 2217ab4382d2SGreg Kroah-Hartman 22180a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2219ab4382d2SGreg Kroah-Hartman 222045af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2221ab4382d2SGreg Kroah-Hartman } 2222ab4382d2SGreg Kroah-Hartman 2223ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2224ab4382d2SGreg Kroah-Hartman { 2225ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2226ab4382d2SGreg Kroah-Hartman 222745af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2228ab4382d2SGreg Kroah-Hartman } 2229ab4382d2SGreg Kroah-Hartman 2230c868cbb7SEduardo Valentin static void serial_imx_restore_context(struct imx_port *sport) 2231c868cbb7SEduardo Valentin { 2232c868cbb7SEduardo Valentin if (!sport->context_saved) 2233c868cbb7SEduardo Valentin return; 2234c868cbb7SEduardo Valentin 2235c868cbb7SEduardo Valentin writel(sport->saved_reg[4], sport->port.membase + UFCR); 2236c868cbb7SEduardo Valentin writel(sport->saved_reg[5], sport->port.membase + UESC); 2237c868cbb7SEduardo Valentin writel(sport->saved_reg[6], sport->port.membase + UTIM); 2238c868cbb7SEduardo Valentin writel(sport->saved_reg[7], sport->port.membase + UBIR); 2239c868cbb7SEduardo Valentin writel(sport->saved_reg[8], sport->port.membase + UBMR); 2240c868cbb7SEduardo Valentin writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS); 2241c868cbb7SEduardo Valentin writel(sport->saved_reg[0], sport->port.membase + UCR1); 2242c868cbb7SEduardo Valentin writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2); 2243c868cbb7SEduardo Valentin writel(sport->saved_reg[2], sport->port.membase + UCR3); 2244c868cbb7SEduardo Valentin writel(sport->saved_reg[3], sport->port.membase + UCR4); 2245c868cbb7SEduardo Valentin sport->context_saved = false; 2246c868cbb7SEduardo Valentin } 2247c868cbb7SEduardo Valentin 2248c868cbb7SEduardo Valentin static void serial_imx_save_context(struct imx_port *sport) 2249c868cbb7SEduardo Valentin { 2250c868cbb7SEduardo Valentin /* Save necessary regs */ 2251c868cbb7SEduardo Valentin sport->saved_reg[0] = readl(sport->port.membase + UCR1); 2252c868cbb7SEduardo Valentin sport->saved_reg[1] = readl(sport->port.membase + UCR2); 2253c868cbb7SEduardo Valentin sport->saved_reg[2] = readl(sport->port.membase + UCR3); 2254c868cbb7SEduardo Valentin sport->saved_reg[3] = readl(sport->port.membase + UCR4); 2255c868cbb7SEduardo Valentin sport->saved_reg[4] = readl(sport->port.membase + UFCR); 2256c868cbb7SEduardo Valentin sport->saved_reg[5] = readl(sport->port.membase + UESC); 2257c868cbb7SEduardo Valentin sport->saved_reg[6] = readl(sport->port.membase + UTIM); 2258c868cbb7SEduardo Valentin sport->saved_reg[7] = readl(sport->port.membase + UBIR); 2259c868cbb7SEduardo Valentin sport->saved_reg[8] = readl(sport->port.membase + UBMR); 2260c868cbb7SEduardo Valentin sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS); 2261c868cbb7SEduardo Valentin sport->context_saved = true; 2262c868cbb7SEduardo Valentin } 2263c868cbb7SEduardo Valentin 2264189550b8SEduardo Valentin static void serial_imx_enable_wakeup(struct imx_port *sport, bool on) 2265189550b8SEduardo Valentin { 2266189550b8SEduardo Valentin unsigned int val; 2267189550b8SEduardo Valentin 2268189550b8SEduardo Valentin val = readl(sport->port.membase + UCR3); 2269189550b8SEduardo Valentin if (on) 2270189550b8SEduardo Valentin val |= UCR3_AWAKEN; 2271189550b8SEduardo Valentin else 2272189550b8SEduardo Valentin val &= ~UCR3_AWAKEN; 2273189550b8SEduardo Valentin writel(val, sport->port.membase + UCR3); 2274bc85734bSEduardo Valentin 2275bc85734bSEduardo Valentin val = readl(sport->port.membase + UCR1); 2276bc85734bSEduardo Valentin if (on) 2277bc85734bSEduardo Valentin val |= UCR1_RTSDEN; 2278bc85734bSEduardo Valentin else 2279bc85734bSEduardo Valentin val &= ~UCR1_RTSDEN; 2280bc85734bSEduardo Valentin writel(val, sport->port.membase + UCR1); 2281189550b8SEduardo Valentin } 2282189550b8SEduardo Valentin 228390bb6bd3SShenwei Wang static int imx_serial_port_suspend_noirq(struct device *dev) 228490bb6bd3SShenwei Wang { 228590bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 228690bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 228790bb6bd3SShenwei Wang int ret; 228890bb6bd3SShenwei Wang 228990bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 229090bb6bd3SShenwei Wang if (ret) 229190bb6bd3SShenwei Wang return ret; 229290bb6bd3SShenwei Wang 2293c868cbb7SEduardo Valentin serial_imx_save_context(sport); 229490bb6bd3SShenwei Wang 229590bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 229690bb6bd3SShenwei Wang 229790bb6bd3SShenwei Wang return 0; 229890bb6bd3SShenwei Wang } 229990bb6bd3SShenwei Wang 230090bb6bd3SShenwei Wang static int imx_serial_port_resume_noirq(struct device *dev) 230190bb6bd3SShenwei Wang { 230290bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 230390bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 230490bb6bd3SShenwei Wang int ret; 230590bb6bd3SShenwei Wang 230690bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 230790bb6bd3SShenwei Wang if (ret) 230890bb6bd3SShenwei Wang return ret; 230990bb6bd3SShenwei Wang 2310c868cbb7SEduardo Valentin serial_imx_restore_context(sport); 231190bb6bd3SShenwei Wang 231290bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 231390bb6bd3SShenwei Wang 231490bb6bd3SShenwei Wang return 0; 231590bb6bd3SShenwei Wang } 231690bb6bd3SShenwei Wang 231790bb6bd3SShenwei Wang static int imx_serial_port_suspend(struct device *dev) 231890bb6bd3SShenwei Wang { 231990bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 232090bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 232190bb6bd3SShenwei Wang 232290bb6bd3SShenwei Wang /* enable wakeup from i.MX UART */ 2323189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, true); 232490bb6bd3SShenwei Wang 232590bb6bd3SShenwei Wang uart_suspend_port(&imx_reg, &sport->port); 232690bb6bd3SShenwei Wang 232729add68dSMartin Fuzzey /* Needed to enable clock in suspend_noirq */ 232829add68dSMartin Fuzzey return clk_prepare(sport->clk_ipg); 232990bb6bd3SShenwei Wang } 233090bb6bd3SShenwei Wang 233190bb6bd3SShenwei Wang static int imx_serial_port_resume(struct device *dev) 233290bb6bd3SShenwei Wang { 233390bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 233490bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 233590bb6bd3SShenwei Wang 233690bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 2337189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, false); 233890bb6bd3SShenwei Wang 233990bb6bd3SShenwei Wang uart_resume_port(&imx_reg, &sport->port); 234090bb6bd3SShenwei Wang 234129add68dSMartin Fuzzey clk_unprepare(sport->clk_ipg); 234229add68dSMartin Fuzzey 234390bb6bd3SShenwei Wang return 0; 234490bb6bd3SShenwei Wang } 234590bb6bd3SShenwei Wang 234690bb6bd3SShenwei Wang static const struct dev_pm_ops imx_serial_port_pm_ops = { 234790bb6bd3SShenwei Wang .suspend_noirq = imx_serial_port_suspend_noirq, 234890bb6bd3SShenwei Wang .resume_noirq = imx_serial_port_resume_noirq, 234990bb6bd3SShenwei Wang .suspend = imx_serial_port_suspend, 235090bb6bd3SShenwei Wang .resume = imx_serial_port_resume, 235190bb6bd3SShenwei Wang }; 235290bb6bd3SShenwei Wang 2353ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2354ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2355ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2356ab4382d2SGreg Kroah-Hartman 2357fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2358ab4382d2SGreg Kroah-Hartman .driver = { 2359ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 236022698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 236190bb6bd3SShenwei Wang .pm = &imx_serial_port_pm_ops, 2362ab4382d2SGreg Kroah-Hartman }, 2363ab4382d2SGreg Kroah-Hartman }; 2364ab4382d2SGreg Kroah-Hartman 2365ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2366ab4382d2SGreg Kroah-Hartman { 2367f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2368ab4382d2SGreg Kroah-Hartman 2369ab4382d2SGreg Kroah-Hartman if (ret) 2370ab4382d2SGreg Kroah-Hartman return ret; 2371ab4382d2SGreg Kroah-Hartman 2372ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2373ab4382d2SGreg Kroah-Hartman if (ret != 0) 2374ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2375ab4382d2SGreg Kroah-Hartman 2376f227824eSUwe Kleine-König return ret; 2377ab4382d2SGreg Kroah-Hartman } 2378ab4382d2SGreg Kroah-Hartman 2379ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2380ab4382d2SGreg Kroah-Hartman { 2381ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2382ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2383ab4382d2SGreg Kroah-Hartman } 2384ab4382d2SGreg Kroah-Hartman 2385ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2386ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2387ab4382d2SGreg Kroah-Hartman 2388ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2389ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2390ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2391ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2392