1ab4382d2SGreg Kroah-Hartman /* 2f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 7ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 8ab4382d2SGreg Kroah-Hartman * 9ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 10ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 11ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2 of the License, or 12ab4382d2SGreg Kroah-Hartman * (at your option) any later version. 13ab4382d2SGreg Kroah-Hartman * 14ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 15ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY; without even the implied warranty of 16ab4382d2SGreg Kroah-Hartman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17ab4382d2SGreg Kroah-Hartman * GNU General Public License for more details. 18ab4382d2SGreg Kroah-Hartman */ 19ab4382d2SGreg Kroah-Hartman 20ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 22ab4382d2SGreg Kroah-Hartman #endif 23ab4382d2SGreg Kroah-Hartman 24ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 29ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 30ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 31ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 32ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 33ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 34ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 35ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 36ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 37ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 3822698aa2SShawn Guo #include <linux/of.h> 3922698aa2SShawn Guo #include <linux/of_device.h> 40e32a9f8fSSachin Kamat #include <linux/io.h> 41b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 42ab4382d2SGreg Kroah-Hartman 43ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 4482906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 45b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 46ab4382d2SGreg Kroah-Hartman 47ab4382d2SGreg Kroah-Hartman /* Register definitions */ 48ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 49ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 50ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 51ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 52ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 53ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 54ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 55ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 56ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 57ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 58ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 59ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 60ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 61ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 62fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 63fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 64fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 65ab4382d2SGreg Kroah-Hartman 66ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 68ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 69ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 70ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 71ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 72ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 73ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 7426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 7525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 77ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 79b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 81ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 84ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 86ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 87fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 88b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 89ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 90ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 98ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 99ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 100ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 10101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 102ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 103ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 104ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 105ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 109ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 111b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 112ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 113ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 114ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 115fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 116ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 117ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 124b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 125ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 126ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 127ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 128ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 129ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 130ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1317be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 132ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 133ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 134ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 135ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 136ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 137ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 138ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 139ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 142ab4382d2SGreg Kroah-Hartman #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 143ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 146ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 147ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 148ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 150ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 151ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 152ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 153ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 154ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 155ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 156ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 157ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 158ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 159ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 160ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 161ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 162ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 163ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 164ab4382d2SGreg Kroah-Hartman 165ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 166ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 167ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 168ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 169ab4382d2SGreg Kroah-Hartman 170ab4382d2SGreg Kroah-Hartman /* 171ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 172ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 173ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 174ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 175ab4382d2SGreg Kroah-Hartman */ 176ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 177ab4382d2SGreg Kroah-Hartman 178ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 179ab4382d2SGreg Kroah-Hartman 180ab4382d2SGreg Kroah-Hartman #define UART_NR 8 181ab4382d2SGreg Kroah-Hartman 182f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 183fe6b540aSShawn Guo enum imx_uart_type { 184fe6b540aSShawn Guo IMX1_UART, 185fe6b540aSShawn Guo IMX21_UART, 186a496e628SHuang Shijie IMX6Q_UART, 187fe6b540aSShawn Guo }; 188fe6b540aSShawn Guo 189fe6b540aSShawn Guo /* device type dependent stuff */ 190fe6b540aSShawn Guo struct imx_uart_data { 191fe6b540aSShawn Guo unsigned uts_reg; 192fe6b540aSShawn Guo enum imx_uart_type devtype; 193fe6b540aSShawn Guo }; 194fe6b540aSShawn Guo 195ab4382d2SGreg Kroah-Hartman struct imx_port { 196ab4382d2SGreg Kroah-Hartman struct uart_port port; 197ab4382d2SGreg Kroah-Hartman struct timer_list timer; 198ab4382d2SGreg Kroah-Hartman unsigned int old_status; 199ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 20020ff2fe6SHuang Shijie unsigned int dte_mode:1; 201ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_rx:1; 202ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_tx:1; 203ab4382d2SGreg Kroah-Hartman unsigned short trcv_delay; /* transceiver delay */ 2043a9465faSSascha Hauer struct clk *clk_ipg; 2053a9465faSSascha Hauer struct clk *clk_per; 2067d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 207b4cdc8f6SHuang Shijie 208b4cdc8f6SHuang Shijie /* DMA fields */ 209b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 210b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 211b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 212b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 213b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 214b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 215b4cdc8f6SHuang Shijie void *rx_buf; 2167cb92fd2SHuang Shijie unsigned int tx_bytes; 217b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 2189ce4f8f3SGreg Kroah-Hartman wait_queue_head_t dma_wait; 219ab4382d2SGreg Kroah-Hartman }; 220ab4382d2SGreg Kroah-Hartman 2210ad5a814SDirk Behme struct imx_port_ucrs { 2220ad5a814SDirk Behme unsigned int ucr1; 2230ad5a814SDirk Behme unsigned int ucr2; 2240ad5a814SDirk Behme unsigned int ucr3; 2250ad5a814SDirk Behme }; 2260ad5a814SDirk Behme 227fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 228fe6b540aSShawn Guo [IMX1_UART] = { 229fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 230fe6b540aSShawn Guo .devtype = IMX1_UART, 231fe6b540aSShawn Guo }, 232fe6b540aSShawn Guo [IMX21_UART] = { 233fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 234fe6b540aSShawn Guo .devtype = IMX21_UART, 235fe6b540aSShawn Guo }, 236a496e628SHuang Shijie [IMX6Q_UART] = { 237a496e628SHuang Shijie .uts_reg = IMX21_UTS, 238a496e628SHuang Shijie .devtype = IMX6Q_UART, 239a496e628SHuang Shijie }, 240fe6b540aSShawn Guo }; 241fe6b540aSShawn Guo 24231ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 243fe6b540aSShawn Guo { 244fe6b540aSShawn Guo .name = "imx1-uart", 245fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 246fe6b540aSShawn Guo }, { 247fe6b540aSShawn Guo .name = "imx21-uart", 248fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 249fe6b540aSShawn Guo }, { 250a496e628SHuang Shijie .name = "imx6q-uart", 251a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 252a496e628SHuang Shijie }, { 253fe6b540aSShawn Guo /* sentinel */ 254fe6b540aSShawn Guo } 255fe6b540aSShawn Guo }; 256fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 257fe6b540aSShawn Guo 258ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 259a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 26022698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 26122698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 26222698aa2SShawn Guo { /* sentinel */ } 26322698aa2SShawn Guo }; 26422698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 26522698aa2SShawn Guo 266fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 267fe6b540aSShawn Guo { 268fe6b540aSShawn Guo return sport->devdata->uts_reg; 269fe6b540aSShawn Guo } 270fe6b540aSShawn Guo 271fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 272fe6b540aSShawn Guo { 273fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 274fe6b540aSShawn Guo } 275fe6b540aSShawn Guo 276fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 277fe6b540aSShawn Guo { 278fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 279fe6b540aSShawn Guo } 280fe6b540aSShawn Guo 281a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 282a496e628SHuang Shijie { 283a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 284a496e628SHuang Shijie } 285ab4382d2SGreg Kroah-Hartman /* 28644a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 28744a75411Sfabio.estevam@freescale.com */ 28893d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 28944a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 29044a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 29144a75411Sfabio.estevam@freescale.com { 29244a75411Sfabio.estevam@freescale.com /* save control registers */ 29344a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 29444a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 29544a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 29644a75411Sfabio.estevam@freescale.com } 29744a75411Sfabio.estevam@freescale.com 29844a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 29944a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30044a75411Sfabio.estevam@freescale.com { 30144a75411Sfabio.estevam@freescale.com /* restore control registers */ 30244a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 30344a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 30444a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 30544a75411Sfabio.estevam@freescale.com } 306e8bfa760SFabio Estevam #endif 30744a75411Sfabio.estevam@freescale.com 30844a75411Sfabio.estevam@freescale.com /* 309ab4382d2SGreg Kroah-Hartman * Handle any change of modem status signal since we were last called. 310ab4382d2SGreg Kroah-Hartman */ 311ab4382d2SGreg Kroah-Hartman static void imx_mctrl_check(struct imx_port *sport) 312ab4382d2SGreg Kroah-Hartman { 313ab4382d2SGreg Kroah-Hartman unsigned int status, changed; 314ab4382d2SGreg Kroah-Hartman 315ab4382d2SGreg Kroah-Hartman status = sport->port.ops->get_mctrl(&sport->port); 316ab4382d2SGreg Kroah-Hartman changed = status ^ sport->old_status; 317ab4382d2SGreg Kroah-Hartman 318ab4382d2SGreg Kroah-Hartman if (changed == 0) 319ab4382d2SGreg Kroah-Hartman return; 320ab4382d2SGreg Kroah-Hartman 321ab4382d2SGreg Kroah-Hartman sport->old_status = status; 322ab4382d2SGreg Kroah-Hartman 323ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_RI) 324ab4382d2SGreg Kroah-Hartman sport->port.icount.rng++; 325ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_DSR) 326ab4382d2SGreg Kroah-Hartman sport->port.icount.dsr++; 327ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CAR) 328ab4382d2SGreg Kroah-Hartman uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 329ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CTS) 330ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 331ab4382d2SGreg Kroah-Hartman 332ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 333ab4382d2SGreg Kroah-Hartman } 334ab4382d2SGreg Kroah-Hartman 335ab4382d2SGreg Kroah-Hartman /* 336ab4382d2SGreg Kroah-Hartman * This is our per-port timeout handler, for checking the 337ab4382d2SGreg Kroah-Hartman * modem status signals. 338ab4382d2SGreg Kroah-Hartman */ 339ab4382d2SGreg Kroah-Hartman static void imx_timeout(unsigned long data) 340ab4382d2SGreg Kroah-Hartman { 341ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)data; 342ab4382d2SGreg Kroah-Hartman unsigned long flags; 343ab4382d2SGreg Kroah-Hartman 344ab4382d2SGreg Kroah-Hartman if (sport->port.state) { 345ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 346ab4382d2SGreg Kroah-Hartman imx_mctrl_check(sport); 347ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 348ab4382d2SGreg Kroah-Hartman 349ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 350ab4382d2SGreg Kroah-Hartman } 351ab4382d2SGreg Kroah-Hartman } 352ab4382d2SGreg Kroah-Hartman 353ab4382d2SGreg Kroah-Hartman /* 354ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 355ab4382d2SGreg Kroah-Hartman */ 356ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 357ab4382d2SGreg Kroah-Hartman { 358ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 359ab4382d2SGreg Kroah-Hartman unsigned long temp; 360ab4382d2SGreg Kroah-Hartman 3619ce4f8f3SGreg Kroah-Hartman /* 3629ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 3639ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 3649ce4f8f3SGreg Kroah-Hartman */ 3659ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 3669ce4f8f3SGreg Kroah-Hartman return; 367b4cdc8f6SHuang Shijie 36817b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR1); 36917b8f2a3SUwe Kleine-König writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); 37017b8f2a3SUwe Kleine-König 37117b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 37217b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 37317b8f2a3SUwe Kleine-König readl(port->membase + USR2) & USR2_TXDC) { 37417b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 37517b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 37617b8f2a3SUwe Kleine-König temp &= ~UCR2_CTS; 37717b8f2a3SUwe Kleine-König else 37817b8f2a3SUwe Kleine-König temp |= UCR2_CTS; 37917b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 38017b8f2a3SUwe Kleine-König 38117b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 38217b8f2a3SUwe Kleine-König temp &= ~UCR4_TCEN; 38317b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 38417b8f2a3SUwe Kleine-König } 385ab4382d2SGreg Kroah-Hartman } 386ab4382d2SGreg Kroah-Hartman 387ab4382d2SGreg Kroah-Hartman /* 388ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 389ab4382d2SGreg Kroah-Hartman */ 390ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 391ab4382d2SGreg Kroah-Hartman { 392ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 393ab4382d2SGreg Kroah-Hartman unsigned long temp; 394ab4382d2SGreg Kroah-Hartman 39545564a66SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) { 39645564a66SHuang Shijie if (sport->port.suspended) { 39745564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 39845564a66SHuang Shijie sport->dma_is_rxing = 0; 39945564a66SHuang Shijie } else { 4009ce4f8f3SGreg Kroah-Hartman return; 40145564a66SHuang Shijie } 40245564a66SHuang Shijie } 403b4cdc8f6SHuang Shijie 404ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 405ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 40685878399SHuang Shijie 40785878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 40885878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 40985878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 410ab4382d2SGreg Kroah-Hartman } 411ab4382d2SGreg Kroah-Hartman 412ab4382d2SGreg Kroah-Hartman /* 413ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 414ab4382d2SGreg Kroah-Hartman */ 415ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 416ab4382d2SGreg Kroah-Hartman { 417ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 418ab4382d2SGreg Kroah-Hartman 419ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 420ab4382d2SGreg Kroah-Hartman } 421ab4382d2SGreg Kroah-Hartman 42291a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 423ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 424ab4382d2SGreg Kroah-Hartman { 425ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 42691a1a909SJiada Wang unsigned long temp; 427ab4382d2SGreg Kroah-Hartman 4285e42e9a3SPeter Hurley if (sport->port.x_char) { 4295e42e9a3SPeter Hurley /* Send next char */ 4305e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4317e2fb5aaSJiada Wang sport->port.icount.tx++; 4327e2fb5aaSJiada Wang sport->port.x_char = 0; 4335e42e9a3SPeter Hurley return; 4345e42e9a3SPeter Hurley } 4355e42e9a3SPeter Hurley 4365e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4375e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4385e42e9a3SPeter Hurley return; 4395e42e9a3SPeter Hurley } 4405e42e9a3SPeter Hurley 44191a1a909SJiada Wang if (sport->dma_is_enabled) { 44291a1a909SJiada Wang /* 44391a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 44491a1a909SJiada Wang * and the TX IRQ is disabled. 44591a1a909SJiada Wang **/ 44691a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 44791a1a909SJiada Wang temp &= ~UCR1_TXMPTYEN; 44891a1a909SJiada Wang if (sport->dma_is_txing) { 44991a1a909SJiada Wang temp |= UCR1_TDMAEN; 45091a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 45191a1a909SJiada Wang } else { 45291a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 45391a1a909SJiada Wang imx_dma_tx(sport); 45491a1a909SJiada Wang } 45591a1a909SJiada Wang } 45691a1a909SJiada Wang 457ab4382d2SGreg Kroah-Hartman while (!uart_circ_empty(xmit) && 4585e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 459ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 460ab4382d2SGreg Kroah-Hartman * out the port here */ 461ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 462ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 463ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 464ab4382d2SGreg Kroah-Hartman } 465ab4382d2SGreg Kroah-Hartman 466ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 467ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 468ab4382d2SGreg Kroah-Hartman 469ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 470ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 471ab4382d2SGreg Kroah-Hartman } 472ab4382d2SGreg Kroah-Hartman 473b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 474b4cdc8f6SHuang Shijie { 475b4cdc8f6SHuang Shijie struct imx_port *sport = data; 476b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 477b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 478b4cdc8f6SHuang Shijie unsigned long flags; 479a2c718ceSDirk Behme unsigned long temp; 480b4cdc8f6SHuang Shijie 48142f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 48242f752b3SDirk Behme 483b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 484b4cdc8f6SHuang Shijie 485a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 486a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 487a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 488a2c718ceSDirk Behme 48942f752b3SDirk Behme /* update the stat */ 49042f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 49142f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 49242f752b3SDirk Behme 49342f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 49442f752b3SDirk Behme 495b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 496b4cdc8f6SHuang Shijie 497b4cdc8f6SHuang Shijie spin_unlock_irqrestore(&sport->port.lock, flags); 498b4cdc8f6SHuang Shijie 499d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 500b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5019ce4f8f3SGreg Kroah-Hartman 5029ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) { 5039ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 5049ce4f8f3SGreg Kroah-Hartman dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 5059ce4f8f3SGreg Kroah-Hartman return; 5069ce4f8f3SGreg Kroah-Hartman } 5070bbc9b81SJiada Wang 5080bbc9b81SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 5090bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5100bbc9b81SJiada Wang imx_dma_tx(sport); 5110bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 512b4cdc8f6SHuang Shijie } 513b4cdc8f6SHuang Shijie 5147cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 515b4cdc8f6SHuang Shijie { 516b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 517b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 518b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 519b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 520b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 521a2c718ceSDirk Behme unsigned long temp; 522b4cdc8f6SHuang Shijie int ret; 523b4cdc8f6SHuang Shijie 52442f752b3SDirk Behme if (sport->dma_is_txing) 525b4cdc8f6SHuang Shijie return; 526b4cdc8f6SHuang Shijie 527b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 528b4cdc8f6SHuang Shijie 5297942f857SDirk Behme if (xmit->tail < xmit->head) { 5307942f857SDirk Behme sport->dma_tx_nents = 1; 5317942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5327942f857SDirk Behme } else { 533b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 534b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 535b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 536b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 537b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 538b4cdc8f6SHuang Shijie } 539b4cdc8f6SHuang Shijie 540b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 541b4cdc8f6SHuang Shijie if (ret == 0) { 542b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 543b4cdc8f6SHuang Shijie return; 544b4cdc8f6SHuang Shijie } 545b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 546b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 547b4cdc8f6SHuang Shijie if (!desc) { 54824649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 54924649821SDirk Behme DMA_TO_DEVICE); 550b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 551b4cdc8f6SHuang Shijie return; 552b4cdc8f6SHuang Shijie } 553b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 554b4cdc8f6SHuang Shijie desc->callback_param = sport; 555b4cdc8f6SHuang Shijie 556b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 557b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 558a2c718ceSDirk Behme 559a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 560a2c718ceSDirk Behme temp |= UCR1_TDMAEN; 561a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 562a2c718ceSDirk Behme 563b4cdc8f6SHuang Shijie /* fire it */ 564b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 565b4cdc8f6SHuang Shijie dmaengine_submit(desc); 566b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 567b4cdc8f6SHuang Shijie return; 568b4cdc8f6SHuang Shijie } 569b4cdc8f6SHuang Shijie 570ab4382d2SGreg Kroah-Hartman /* 571ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 572ab4382d2SGreg Kroah-Hartman */ 573ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 574ab4382d2SGreg Kroah-Hartman { 575ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 576ab4382d2SGreg Kroah-Hartman unsigned long temp; 577ab4382d2SGreg Kroah-Hartman 57817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 57917b8f2a3SUwe Kleine-König /* enable transmitter and shifter empty irq */ 58017b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 58117b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 58217b8f2a3SUwe Kleine-König temp &= ~UCR2_CTS; 58317b8f2a3SUwe Kleine-König else 58417b8f2a3SUwe Kleine-König temp |= UCR2_CTS; 58517b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 58617b8f2a3SUwe Kleine-König 58717b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 58817b8f2a3SUwe Kleine-König temp |= UCR4_TCEN; 58917b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 59017b8f2a3SUwe Kleine-König } 59117b8f2a3SUwe Kleine-König 592b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 593ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 594ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 595b4cdc8f6SHuang Shijie } 596ab4382d2SGreg Kroah-Hartman 597b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 59891a1a909SJiada Wang if (sport->port.x_char) { 59991a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 60091a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 60191a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 60291a1a909SJiada Wang temp &= ~UCR1_TDMAEN; 60391a1a909SJiada Wang temp |= UCR1_TXMPTYEN; 60491a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 60591a1a909SJiada Wang return; 60691a1a909SJiada Wang } 60791a1a909SJiada Wang 6085e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6095e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6107cb92fd2SHuang Shijie imx_dma_tx(sport); 611b4cdc8f6SHuang Shijie return; 612b4cdc8f6SHuang Shijie } 613ab4382d2SGreg Kroah-Hartman } 614ab4382d2SGreg Kroah-Hartman 615ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 616ab4382d2SGreg Kroah-Hartman { 617ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6185680e941SUwe Kleine-König unsigned int val; 619ab4382d2SGreg Kroah-Hartman unsigned long flags; 620ab4382d2SGreg Kroah-Hartman 621ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 622ab4382d2SGreg Kroah-Hartman 623ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6245680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 625ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 626ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 627ab4382d2SGreg Kroah-Hartman 628ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 629ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 630ab4382d2SGreg Kroah-Hartman } 631ab4382d2SGreg Kroah-Hartman 632ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 633ab4382d2SGreg Kroah-Hartman { 634ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 635ab4382d2SGreg Kroah-Hartman unsigned long flags; 636ab4382d2SGreg Kroah-Hartman 637ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 638ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 639ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 640ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 641ab4382d2SGreg Kroah-Hartman } 642ab4382d2SGreg Kroah-Hartman 643ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 644ab4382d2SGreg Kroah-Hartman { 645ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 646ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 64792a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 648ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 649ab4382d2SGreg Kroah-Hartman 650ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 651ab4382d2SGreg Kroah-Hartman 652ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 653ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 654ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 655ab4382d2SGreg Kroah-Hartman 656ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 657ab4382d2SGreg Kroah-Hartman 658ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 659ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 660ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 661ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 662ab4382d2SGreg Kroah-Hartman continue; 663ab4382d2SGreg Kroah-Hartman } 664ab4382d2SGreg Kroah-Hartman 665ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 666ab4382d2SGreg Kroah-Hartman continue; 667ab4382d2SGreg Kroah-Hartman 668019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 669019dc9eaSHui Wang if (rx & URXD_BRK) 670019dc9eaSHui Wang sport->port.icount.brk++; 671019dc9eaSHui Wang else if (rx & URXD_PRERR) 672ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 673ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 674ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 675ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 676ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 677ab4382d2SGreg Kroah-Hartman 678ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 679ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 680ab4382d2SGreg Kroah-Hartman goto out; 681ab4382d2SGreg Kroah-Hartman continue; 682ab4382d2SGreg Kroah-Hartman } 683ab4382d2SGreg Kroah-Hartman 6848d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 685ab4382d2SGreg Kroah-Hartman 686019dc9eaSHui Wang if (rx & URXD_BRK) 687019dc9eaSHui Wang flg = TTY_BREAK; 688019dc9eaSHui Wang else if (rx & URXD_PRERR) 689ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 690ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 691ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 692ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 693ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 694ab4382d2SGreg Kroah-Hartman 695ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 696ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 697ab4382d2SGreg Kroah-Hartman #endif 698ab4382d2SGreg Kroah-Hartman } 699ab4382d2SGreg Kroah-Hartman 70055d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 70155d8693aSJiada Wang goto out; 70255d8693aSJiada Wang 7039b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 7049b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 705ab4382d2SGreg Kroah-Hartman } 706ab4382d2SGreg Kroah-Hartman 707ab4382d2SGreg Kroah-Hartman out: 708ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7092e124b4aSJiri Slaby tty_flip_buffer_push(port); 710ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 711ab4382d2SGreg Kroah-Hartman } 712ab4382d2SGreg Kroah-Hartman 7137cb92fd2SHuang Shijie static int start_rx_dma(struct imx_port *sport); 714b4cdc8f6SHuang Shijie /* 715b4cdc8f6SHuang Shijie * If the RXFIFO is filled with some data, and then we 716b4cdc8f6SHuang Shijie * arise a DMA operation to receive them. 717b4cdc8f6SHuang Shijie */ 718b4cdc8f6SHuang Shijie static void imx_dma_rxint(struct imx_port *sport) 719b4cdc8f6SHuang Shijie { 720b4cdc8f6SHuang Shijie unsigned long temp; 72173631813SJiada Wang unsigned long flags; 72273631813SJiada Wang 72373631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 724b4cdc8f6SHuang Shijie 725b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + USR2); 726b4cdc8f6SHuang Shijie if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 727b4cdc8f6SHuang Shijie sport->dma_is_rxing = 1; 728b4cdc8f6SHuang Shijie 729b4cdc8f6SHuang Shijie /* disable the `Recerver Ready Interrrupt` */ 730b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 731b4cdc8f6SHuang Shijie temp &= ~(UCR1_RRDYEN); 732b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 733b4cdc8f6SHuang Shijie 734b4cdc8f6SHuang Shijie /* tell the DMA to receive the data. */ 7357cb92fd2SHuang Shijie start_rx_dma(sport); 736b4cdc8f6SHuang Shijie } 73773631813SJiada Wang 73873631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 739b4cdc8f6SHuang Shijie } 740b4cdc8f6SHuang Shijie 741ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 742ab4382d2SGreg Kroah-Hartman { 743ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 744ab4382d2SGreg Kroah-Hartman unsigned int sts; 745f1f836e4SAlexander Stein unsigned int sts2; 746ab4382d2SGreg Kroah-Hartman 747ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 74817b8f2a3SUwe Kleine-König sts2 = readl(sport->port.membase + USR2); 749ab4382d2SGreg Kroah-Hartman 750b4cdc8f6SHuang Shijie if (sts & USR1_RRDY) { 751b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) 752b4cdc8f6SHuang Shijie imx_dma_rxint(sport); 753b4cdc8f6SHuang Shijie else 754ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 755b4cdc8f6SHuang Shijie } 756ab4382d2SGreg Kroah-Hartman 75717b8f2a3SUwe Kleine-König if ((sts & USR1_TRDY && 75817b8f2a3SUwe Kleine-König readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || 75917b8f2a3SUwe Kleine-König (sts2 & USR2_TXDC && 76017b8f2a3SUwe Kleine-König readl(sport->port.membase + UCR4) & UCR4_TCEN)) 761ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 762ab4382d2SGreg Kroah-Hartman 763ab4382d2SGreg Kroah-Hartman if (sts & USR1_RTSD) 764ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 765ab4382d2SGreg Kroah-Hartman 766db1a9b55SFabio Estevam if (sts & USR1_AWAKE) 767db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 768db1a9b55SFabio Estevam 769f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 770f1f836e4SAlexander Stein sport->port.icount.overrun++; 77191555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 772f1f836e4SAlexander Stein } 773f1f836e4SAlexander Stein 774ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 775ab4382d2SGreg Kroah-Hartman } 776ab4382d2SGreg Kroah-Hartman 777ab4382d2SGreg Kroah-Hartman /* 778ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 779ab4382d2SGreg Kroah-Hartman */ 780ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 781ab4382d2SGreg Kroah-Hartman { 782ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 7831ce43e58SHuang Shijie unsigned int ret; 784ab4382d2SGreg Kroah-Hartman 7851ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 7861ce43e58SHuang Shijie 7871ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 7881ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 7891ce43e58SHuang Shijie ret = 0; 7901ce43e58SHuang Shijie 7911ce43e58SHuang Shijie return ret; 792ab4382d2SGreg Kroah-Hartman } 793ab4382d2SGreg Kroah-Hartman 794ab4382d2SGreg Kroah-Hartman /* 795ab4382d2SGreg Kroah-Hartman * We have a modem side uart, so the meanings of RTS and CTS are inverted. 796ab4382d2SGreg Kroah-Hartman */ 797ab4382d2SGreg Kroah-Hartman static unsigned int imx_get_mctrl(struct uart_port *port) 798ab4382d2SGreg Kroah-Hartman { 799ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 800ab4382d2SGreg Kroah-Hartman unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 801ab4382d2SGreg Kroah-Hartman 802ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR1) & USR1_RTSS) 803ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_CTS; 804ab4382d2SGreg Kroah-Hartman 805ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR2) & UCR2_CTS) 806ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_RTS; 807ab4382d2SGreg Kroah-Hartman 8086b471a98SHuang Shijie if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 8096b471a98SHuang Shijie tmp |= TIOCM_LOOP; 8106b471a98SHuang Shijie 811ab4382d2SGreg Kroah-Hartman return tmp; 812ab4382d2SGreg Kroah-Hartman } 813ab4382d2SGreg Kroah-Hartman 814ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 815ab4382d2SGreg Kroah-Hartman { 816ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 817ab4382d2SGreg Kroah-Hartman unsigned long temp; 818ab4382d2SGreg Kroah-Hartman 81917b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 82017b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 82117b8f2a3SUwe Kleine-König temp &= ~(UCR2_CTS | UCR2_CTSC); 822ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 823bb2f861aSFugang Duan temp |= UCR2_CTS | UCR2_CTSC; 824ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 82517b8f2a3SUwe Kleine-König } 8266b471a98SHuang Shijie 8276b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8286b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8296b471a98SHuang Shijie temp |= UTS_LOOP; 8306b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 831ab4382d2SGreg Kroah-Hartman } 832ab4382d2SGreg Kroah-Hartman 833ab4382d2SGreg Kroah-Hartman /* 834ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 835ab4382d2SGreg Kroah-Hartman */ 836ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 837ab4382d2SGreg Kroah-Hartman { 838ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 839ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 840ab4382d2SGreg Kroah-Hartman 841ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 842ab4382d2SGreg Kroah-Hartman 843ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 844ab4382d2SGreg Kroah-Hartman 845ab4382d2SGreg Kroah-Hartman if (break_state != 0) 846ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 847ab4382d2SGreg Kroah-Hartman 848ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 849ab4382d2SGreg Kroah-Hartman 850ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 851ab4382d2SGreg Kroah-Hartman } 852ab4382d2SGreg Kroah-Hartman 853ab4382d2SGreg Kroah-Hartman #define TXTL 2 /* reset default */ 854ab4382d2SGreg Kroah-Hartman #define RXTL 1 /* reset default */ 855ab4382d2SGreg Kroah-Hartman 856caec172dSFabio Estevam static void imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 857ab4382d2SGreg Kroah-Hartman { 858ab4382d2SGreg Kroah-Hartman unsigned int val; 859ab4382d2SGreg Kroah-Hartman 8607be0670fSDirk Behme /* set receiver / transmitter trigger level */ 8617be0670fSDirk Behme val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 8627be0670fSDirk Behme val |= TXTL << UFCR_TXTL_SHF | RXTL; 863ab4382d2SGreg Kroah-Hartman writel(val, sport->port.membase + UFCR); 864ab4382d2SGreg Kroah-Hartman } 865ab4382d2SGreg Kroah-Hartman 866b4cdc8f6SHuang Shijie #define RX_BUF_SIZE (PAGE_SIZE) 867b4cdc8f6SHuang Shijie static void imx_rx_dma_done(struct imx_port *sport) 868b4cdc8f6SHuang Shijie { 869b4cdc8f6SHuang Shijie unsigned long temp; 87073631813SJiada Wang unsigned long flags; 87173631813SJiada Wang 87273631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 873b4cdc8f6SHuang Shijie 874b4cdc8f6SHuang Shijie /* Enable this interrupt when the RXFIFO is empty. */ 875b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 876b4cdc8f6SHuang Shijie temp |= UCR1_RRDYEN; 877b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 878b4cdc8f6SHuang Shijie 879b4cdc8f6SHuang Shijie sport->dma_is_rxing = 0; 8809ce4f8f3SGreg Kroah-Hartman 8819ce4f8f3SGreg Kroah-Hartman /* Is the shutdown waiting for us? */ 8829ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) 8839ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 88473631813SJiada Wang 88573631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 886b4cdc8f6SHuang Shijie } 887b4cdc8f6SHuang Shijie 888b4cdc8f6SHuang Shijie /* 889b4cdc8f6SHuang Shijie * There are three kinds of RX DMA interrupts(such as in the MX6Q): 890b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 891b4cdc8f6SHuang Shijie * [2] the Aging timer expires(wait for 8 bytes long) 892b4cdc8f6SHuang Shijie * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 893b4cdc8f6SHuang Shijie * 894b4cdc8f6SHuang Shijie * The [2] is trigger when a character was been sitting in the FIFO 895b4cdc8f6SHuang Shijie * meanwhile [3] can wait for 32 bytes long when the RX line is 896b4cdc8f6SHuang Shijie * on IDLE state and RxFIFO is empty. 897b4cdc8f6SHuang Shijie */ 898b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 899b4cdc8f6SHuang Shijie { 900b4cdc8f6SHuang Shijie struct imx_port *sport = data; 901b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 902b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9037cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 904b4cdc8f6SHuang Shijie struct dma_tx_state state; 905b4cdc8f6SHuang Shijie enum dma_status status; 906b4cdc8f6SHuang Shijie unsigned int count; 907b4cdc8f6SHuang Shijie 908b4cdc8f6SHuang Shijie /* unmap it first */ 909b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 910b4cdc8f6SHuang Shijie 911f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 912b4cdc8f6SHuang Shijie count = RX_BUF_SIZE - state.residue; 913392bceedSPhilipp Zabel 914392bceedSPhilipp Zabel if (readl(sport->port.membase + USR2) & USR2_IDLE) { 915392bceedSPhilipp Zabel /* In condition [3] the SDMA counted up too early */ 916392bceedSPhilipp Zabel count--; 917392bceedSPhilipp Zabel 918392bceedSPhilipp Zabel writel(USR2_IDLE, sport->port.membase + USR2); 919392bceedSPhilipp Zabel } 920392bceedSPhilipp Zabel 921b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 922b4cdc8f6SHuang Shijie 923b4cdc8f6SHuang Shijie if (count) { 9249b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 9259b289932SManfred Schlaegl int bytes = tty_insert_flip_string(port, sport->rx_buf, 9269b289932SManfred Schlaegl count); 9279b289932SManfred Schlaegl 9289b289932SManfred Schlaegl if (bytes != count) 9299b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 9309b289932SManfred Schlaegl } 9317cb92fd2SHuang Shijie tty_flip_buffer_push(port); 9327cb92fd2SHuang Shijie 9337cb92fd2SHuang Shijie start_rx_dma(sport); 934ee5e7c10SRobin Gong } else if (readl(sport->port.membase + USR2) & USR2_RDR) { 935ee5e7c10SRobin Gong /* 936ee5e7c10SRobin Gong * start rx_dma directly once data in RXFIFO, more efficient 937ee5e7c10SRobin Gong * than before: 938ee5e7c10SRobin Gong * 1. call imx_rx_dma_done to stop dma if no data received 939ee5e7c10SRobin Gong * 2. wait next RDR interrupt to start dma transfer. 940ee5e7c10SRobin Gong */ 941ee5e7c10SRobin Gong start_rx_dma(sport); 942ee5e7c10SRobin Gong } else { 943ee5e7c10SRobin Gong /* 944ee5e7c10SRobin Gong * stop dma to prevent too many IDLE event trigged if no data 945ee5e7c10SRobin Gong * in RXFIFO 946ee5e7c10SRobin Gong */ 947b4cdc8f6SHuang Shijie imx_rx_dma_done(sport); 948b4cdc8f6SHuang Shijie } 949ee5e7c10SRobin Gong } 950b4cdc8f6SHuang Shijie 951b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 952b4cdc8f6SHuang Shijie { 953b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 954b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 955b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 956b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 957b4cdc8f6SHuang Shijie int ret; 958b4cdc8f6SHuang Shijie 959b4cdc8f6SHuang Shijie sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 960b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 961b4cdc8f6SHuang Shijie if (ret == 0) { 962b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 963b4cdc8f6SHuang Shijie return -EINVAL; 964b4cdc8f6SHuang Shijie } 965b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 966b4cdc8f6SHuang Shijie DMA_PREP_INTERRUPT); 967b4cdc8f6SHuang Shijie if (!desc) { 96824649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 969b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 970b4cdc8f6SHuang Shijie return -EINVAL; 971b4cdc8f6SHuang Shijie } 972b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 973b4cdc8f6SHuang Shijie desc->callback_param = sport; 974b4cdc8f6SHuang Shijie 975b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 976b4cdc8f6SHuang Shijie dmaengine_submit(desc); 977b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 978b4cdc8f6SHuang Shijie return 0; 979b4cdc8f6SHuang Shijie } 980b4cdc8f6SHuang Shijie 981b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 982b4cdc8f6SHuang Shijie { 983b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 984b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 985b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 986b4cdc8f6SHuang Shijie 987b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 988b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 989b4cdc8f6SHuang Shijie } 990b4cdc8f6SHuang Shijie 991b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 992b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 993b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 994b4cdc8f6SHuang Shijie } 995b4cdc8f6SHuang Shijie 996b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 997b4cdc8f6SHuang Shijie } 998b4cdc8f6SHuang Shijie 999b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1000b4cdc8f6SHuang Shijie { 1001b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1002b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1003b4cdc8f6SHuang Shijie int ret; 1004b4cdc8f6SHuang Shijie 1005b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1006b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1007b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1008b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1009b4cdc8f6SHuang Shijie ret = -EINVAL; 1010b4cdc8f6SHuang Shijie goto err; 1011b4cdc8f6SHuang Shijie } 1012b4cdc8f6SHuang Shijie 1013b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1014b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1015b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1016b4cdc8f6SHuang Shijie slave_config.src_maxburst = RXTL; 1017b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1018b4cdc8f6SHuang Shijie if (ret) { 1019b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1020b4cdc8f6SHuang Shijie goto err; 1021b4cdc8f6SHuang Shijie } 1022b4cdc8f6SHuang Shijie 1023b4cdc8f6SHuang Shijie sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1024b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1025b4cdc8f6SHuang Shijie ret = -ENOMEM; 1026b4cdc8f6SHuang Shijie goto err; 1027b4cdc8f6SHuang Shijie } 1028b4cdc8f6SHuang Shijie 1029b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1030b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1031b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1032b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1033b4cdc8f6SHuang Shijie ret = -EINVAL; 1034b4cdc8f6SHuang Shijie goto err; 1035b4cdc8f6SHuang Shijie } 1036b4cdc8f6SHuang Shijie 1037b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1038b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1039b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1040b4cdc8f6SHuang Shijie slave_config.dst_maxburst = TXTL; 1041b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1042b4cdc8f6SHuang Shijie if (ret) { 1043b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1044b4cdc8f6SHuang Shijie goto err; 1045b4cdc8f6SHuang Shijie } 1046b4cdc8f6SHuang Shijie 1047b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1048b4cdc8f6SHuang Shijie 1049b4cdc8f6SHuang Shijie return 0; 1050b4cdc8f6SHuang Shijie err: 1051b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1052b4cdc8f6SHuang Shijie return ret; 1053b4cdc8f6SHuang Shijie } 1054b4cdc8f6SHuang Shijie 1055b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1056b4cdc8f6SHuang Shijie { 1057b4cdc8f6SHuang Shijie unsigned long temp; 1058b4cdc8f6SHuang Shijie 10599ce4f8f3SGreg Kroah-Hartman init_waitqueue_head(&sport->dma_wait); 10609ce4f8f3SGreg Kroah-Hartman 1061b4cdc8f6SHuang Shijie /* set UCR1 */ 1062b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1063b4cdc8f6SHuang Shijie temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1064b4cdc8f6SHuang Shijie /* wait for 32 idle frames for IDDMA interrupt */ 1065b4cdc8f6SHuang Shijie UCR1_ICD_REG(3); 1066b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1067b4cdc8f6SHuang Shijie 1068b4cdc8f6SHuang Shijie /* set UCR4 */ 1069b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1070b4cdc8f6SHuang Shijie temp |= UCR4_IDDMAEN; 1071b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1072b4cdc8f6SHuang Shijie 1073b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1074b4cdc8f6SHuang Shijie } 1075b4cdc8f6SHuang Shijie 1076b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1077b4cdc8f6SHuang Shijie { 1078b4cdc8f6SHuang Shijie unsigned long temp; 1079b4cdc8f6SHuang Shijie 1080b4cdc8f6SHuang Shijie /* clear UCR1 */ 1081b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1082b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1083b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1084b4cdc8f6SHuang Shijie 1085b4cdc8f6SHuang Shijie /* clear UCR2 */ 1086b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 1087b4cdc8f6SHuang Shijie temp &= ~(UCR2_CTSC | UCR2_CTS); 1088b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1089b4cdc8f6SHuang Shijie 1090b4cdc8f6SHuang Shijie /* clear UCR4 */ 1091b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1092b4cdc8f6SHuang Shijie temp &= ~UCR4_IDDMAEN; 1093b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1094b4cdc8f6SHuang Shijie 1095b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1096b4cdc8f6SHuang Shijie } 1097b4cdc8f6SHuang Shijie 1098ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1099ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1100ab4382d2SGreg Kroah-Hartman 1101ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1102ab4382d2SGreg Kroah-Hartman { 1103ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1104458e2c82SFabio Estevam int retval, i; 1105ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1106ab4382d2SGreg Kroah-Hartman 110728eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 110828eb4274SHuang Shijie if (retval) 1109cb0f0a5fSFabio Estevam return retval; 111028eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 11110c375501SHuang Shijie if (retval) { 11120c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1113cb0f0a5fSFabio Estevam return retval; 11140c375501SHuang Shijie } 111528eb4274SHuang Shijie 1116ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1117ab4382d2SGreg Kroah-Hartman 1118ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1119ab4382d2SGreg Kroah-Hartman * requesting IRQs 1120ab4382d2SGreg Kroah-Hartman */ 1121ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1122ab4382d2SGreg Kroah-Hartman 1123ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1124ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1125ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1126ab4382d2SGreg Kroah-Hartman 1127ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1128ab4382d2SGreg Kroah-Hartman 112953794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1130772f8991SHuang Shijie /* Reset fifo's and state machines */ 1131458e2c82SFabio Estevam i = 100; 1132458e2c82SFabio Estevam 1133458e2c82SFabio Estevam temp = readl(sport->port.membase + UCR2); 1134458e2c82SFabio Estevam temp &= ~UCR2_SRST; 1135458e2c82SFabio Estevam writel(temp, sport->port.membase + UCR2); 1136458e2c82SFabio Estevam 1137458e2c82SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1138458e2c82SFabio Estevam udelay(1); 1139ab4382d2SGreg Kroah-Hartman 1140ab4382d2SGreg Kroah-Hartman /* 1141ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1142ab4382d2SGreg Kroah-Hartman */ 1143ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 114491555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 1145ab4382d2SGreg Kroah-Hartman 1146ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1147ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1148ab4382d2SGreg Kroah-Hartman 1149ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1150ab4382d2SGreg Kroah-Hartman 11516f026d6bSJiada Wang temp = readl(sport->port.membase + UCR4); 11526f026d6bSJiada Wang temp |= UCR4_OREN; 11536f026d6bSJiada Wang writel(temp, sport->port.membase + UCR4); 11546f026d6bSJiada Wang 1155ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1156ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1157bff09b09SLucas Stach if (!sport->have_rtscts) 1158bff09b09SLucas Stach temp |= UCR2_IRTS; 1159ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1160ab4382d2SGreg Kroah-Hartman 1161a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1162ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1163b38cb7d2SFabio Estevam temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1164ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1165ab4382d2SGreg Kroah-Hartman } 1166ab4382d2SGreg Kroah-Hartman 1167ab4382d2SGreg Kroah-Hartman /* 1168ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1169ab4382d2SGreg Kroah-Hartman */ 1170ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1171ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1172ab4382d2SGreg Kroah-Hartman 1173ab4382d2SGreg Kroah-Hartman return 0; 1174ab4382d2SGreg Kroah-Hartman } 1175ab4382d2SGreg Kroah-Hartman 1176ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1177ab4382d2SGreg Kroah-Hartman { 1178ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1179ab4382d2SGreg Kroah-Hartman unsigned long temp; 11809ec1882dSXinyu Chen unsigned long flags; 1181ab4382d2SGreg Kroah-Hartman 1182b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1183a4688bcdSHuang Shijie int ret; 1184a4688bcdSHuang Shijie 11859ce4f8f3SGreg Kroah-Hartman /* We have to wait for the DMA to finish. */ 1186a4688bcdSHuang Shijie ret = wait_event_interruptible(sport->dma_wait, 11879ce4f8f3SGreg Kroah-Hartman !sport->dma_is_rxing && !sport->dma_is_txing); 1188a4688bcdSHuang Shijie if (ret != 0) { 1189a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1190a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1191a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 1192a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 1193a4688bcdSHuang Shijie } 119473631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1195a4688bcdSHuang Shijie imx_stop_tx(port); 1196b4cdc8f6SHuang Shijie imx_stop_rx(port); 1197b4cdc8f6SHuang Shijie imx_disable_dma(sport); 119873631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1199b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1200b4cdc8f6SHuang Shijie } 1201b4cdc8f6SHuang Shijie 12029ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1203ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1204ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1205ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 12069ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1207ab4382d2SGreg Kroah-Hartman 1208ab4382d2SGreg Kroah-Hartman /* 1209ab4382d2SGreg Kroah-Hartman * Stop our timer. 1210ab4382d2SGreg Kroah-Hartman */ 1211ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1212ab4382d2SGreg Kroah-Hartman 1213ab4382d2SGreg Kroah-Hartman /* 1214ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1215ab4382d2SGreg Kroah-Hartman */ 1216ab4382d2SGreg Kroah-Hartman 12179ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1218ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1219ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1220ab4382d2SGreg Kroah-Hartman 1221ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 12229ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 122328eb4274SHuang Shijie 122428eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 122528eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1226ab4382d2SGreg Kroah-Hartman } 1227ab4382d2SGreg Kroah-Hartman 1228eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1229eb56b7edSHuang Shijie { 1230eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 123182e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1232a2c718ceSDirk Behme unsigned long temp; 12334f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1234eb56b7edSHuang Shijie 123582e86ae9SDirk Behme if (!sport->dma_chan_tx) 123682e86ae9SDirk Behme return; 123782e86ae9SDirk Behme 1238eb56b7edSHuang Shijie sport->tx_bytes = 0; 1239eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 124082e86ae9SDirk Behme if (sport->dma_is_txing) { 124182e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 124282e86ae9SDirk Behme DMA_TO_DEVICE); 1243a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 1244a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 1245a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 124682e86ae9SDirk Behme sport->dma_is_txing = false; 1247eb56b7edSHuang Shijie } 1248934084a9SFabio Estevam 1249934084a9SFabio Estevam /* 1250934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1251934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1252934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1253934084a9SFabio Estevam * and UTS[6-3]". As we don't need to restore the old values from 1254934084a9SFabio Estevam * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1255934084a9SFabio Estevam */ 1256934084a9SFabio Estevam ubir = readl(sport->port.membase + UBIR); 1257934084a9SFabio Estevam ubmr = readl(sport->port.membase + UBMR); 1258934084a9SFabio Estevam uts = readl(sport->port.membase + IMX21_UTS); 1259934084a9SFabio Estevam 1260934084a9SFabio Estevam temp = readl(sport->port.membase + UCR2); 1261934084a9SFabio Estevam temp &= ~UCR2_SRST; 1262934084a9SFabio Estevam writel(temp, sport->port.membase + UCR2); 1263934084a9SFabio Estevam 1264934084a9SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1265934084a9SFabio Estevam udelay(1); 1266934084a9SFabio Estevam 1267934084a9SFabio Estevam /* Restore the registers */ 1268934084a9SFabio Estevam writel(ubir, sport->port.membase + UBIR); 1269934084a9SFabio Estevam writel(ubmr, sport->port.membase + UBMR); 1270934084a9SFabio Estevam writel(uts, sport->port.membase + IMX21_UTS); 1271eb56b7edSHuang Shijie } 1272eb56b7edSHuang Shijie 1273ab4382d2SGreg Kroah-Hartman static void 1274ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1275ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1276ab4382d2SGreg Kroah-Hartman { 1277ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1278ab4382d2SGreg Kroah-Hartman unsigned long flags; 1279ab4382d2SGreg Kroah-Hartman unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1280ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1281ab4382d2SGreg Kroah-Hartman unsigned int div, ufcr; 1282ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1283ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1284ab4382d2SGreg Kroah-Hartman 1285ab4382d2SGreg Kroah-Hartman /* 1286ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1287ab4382d2SGreg Kroah-Hartman */ 1288ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1289ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1290ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1291ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1292ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1293ab4382d2SGreg Kroah-Hartman } 1294ab4382d2SGreg Kroah-Hartman 1295ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1296ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1297ab4382d2SGreg Kroah-Hartman else 1298ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1299ab4382d2SGreg Kroah-Hartman 1300ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1301ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1302ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 130317b8f2a3SUwe Kleine-König 130412fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 130517b8f2a3SUwe Kleine-König /* 130617b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 130717b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 130817b8f2a3SUwe Kleine-König * disabled. 130917b8f2a3SUwe Kleine-König */ 131017b8f2a3SUwe Kleine-König if (!(port->rs485.flags & 131117b8f2a3SUwe Kleine-König SER_RS485_RTS_AFTER_SEND)) 131217b8f2a3SUwe Kleine-König ucr2 |= UCR2_CTS; 131312fe59f9SFabio Estevam } else { 1314ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_CTSC; 131512fe59f9SFabio Estevam } 1316907eda32SDavid Jander 1317907eda32SDavid Jander /* Can we enable the DMA support? */ 1318907eda32SDavid Jander if (is_imx6q_uart(sport) && !uart_console(port) 1319907eda32SDavid Jander && !sport->dma_is_inited) 1320907eda32SDavid Jander imx_uart_dma_init(sport); 1321ab4382d2SGreg Kroah-Hartman } else { 1322ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1323ab4382d2SGreg Kroah-Hartman } 132417b8f2a3SUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) 132517b8f2a3SUwe Kleine-König /* disable transmitter */ 132617b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND)) 132717b8f2a3SUwe Kleine-König ucr2 |= UCR2_CTS; 1328ab4382d2SGreg Kroah-Hartman 1329ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1330ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1331ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1332ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1333ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1334ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1335ab4382d2SGreg Kroah-Hartman } 1336ab4382d2SGreg Kroah-Hartman 1337995234daSEric Miao del_timer_sync(&sport->timer); 1338995234daSEric Miao 1339ab4382d2SGreg Kroah-Hartman /* 1340ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1341ab4382d2SGreg Kroah-Hartman */ 1342ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1343ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1344ab4382d2SGreg Kroah-Hartman 1345ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1346ab4382d2SGreg Kroah-Hartman 1347ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1348ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1349ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1350ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1351ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1352ab4382d2SGreg Kroah-Hartman 1353ab4382d2SGreg Kroah-Hartman /* 1354ab4382d2SGreg Kroah-Hartman * Characters to ignore 1355ab4382d2SGreg Kroah-Hartman */ 1356ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1357ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1358865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1359ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1360ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1361ab4382d2SGreg Kroah-Hartman /* 1362ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1363ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1364ab4382d2SGreg Kroah-Hartman */ 1365ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1366ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1367ab4382d2SGreg Kroah-Hartman } 1368ab4382d2SGreg Kroah-Hartman 136955d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 137055d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 137155d8693aSJiada Wang 1372ab4382d2SGreg Kroah-Hartman /* 1373ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1374ab4382d2SGreg Kroah-Hartman */ 1375ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1376ab4382d2SGreg Kroah-Hartman 1377ab4382d2SGreg Kroah-Hartman /* 1378ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1379ab4382d2SGreg Kroah-Hartman */ 1380ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1381ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1382ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1383ab4382d2SGreg Kroah-Hartman 1384ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1385ab4382d2SGreg Kroah-Hartman barrier(); 1386ab4382d2SGreg Kroah-Hartman 1387ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 1388ab4382d2SGreg Kroah-Hartman old_txrxen = readl(sport->port.membase + UCR2); 1389ab4382d2SGreg Kroah-Hartman writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1390ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 1391ab4382d2SGreg Kroah-Hartman old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1392ab4382d2SGreg Kroah-Hartman 139309bd00f6SHubert Feurstein /* custom-baudrate handling */ 139409bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 139509bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 139609bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 139709bd00f6SHubert Feurstein 1398ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1399ab4382d2SGreg Kroah-Hartman if (div > 7) 1400ab4382d2SGreg Kroah-Hartman div = 7; 1401ab4382d2SGreg Kroah-Hartman if (!div) 1402ab4382d2SGreg Kroah-Hartman div = 1; 1403ab4382d2SGreg Kroah-Hartman 1404ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1405ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1406ab4382d2SGreg Kroah-Hartman 1407ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1408ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1409ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1410ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1411ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1412ab4382d2SGreg Kroah-Hartman 1413ab4382d2SGreg Kroah-Hartman num -= 1; 1414ab4382d2SGreg Kroah-Hartman denom -= 1; 1415ab4382d2SGreg Kroah-Hartman 1416ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1417ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 141820ff2fe6SHuang Shijie if (sport->dte_mode) 141920ff2fe6SHuang Shijie ufcr |= UFCR_DCEDTE; 1420ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1421ab4382d2SGreg Kroah-Hartman 1422ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1423ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1424ab4382d2SGreg Kroah-Hartman 1425a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1426ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1427fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1428ab4382d2SGreg Kroah-Hartman 1429ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1430ab4382d2SGreg Kroah-Hartman 1431ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 1432ab4382d2SGreg Kroah-Hartman writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1433ab4382d2SGreg Kroah-Hartman 1434ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1435ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1436ab4382d2SGreg Kroah-Hartman 1437907eda32SDavid Jander if (sport->dma_is_inited && !sport->dma_is_enabled) 1438907eda32SDavid Jander imx_enable_dma(sport); 1439ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1440ab4382d2SGreg Kroah-Hartman } 1441ab4382d2SGreg Kroah-Hartman 1442ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1443ab4382d2SGreg Kroah-Hartman { 1444ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1445ab4382d2SGreg Kroah-Hartman 1446ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1447ab4382d2SGreg Kroah-Hartman } 1448ab4382d2SGreg Kroah-Hartman 1449ab4382d2SGreg Kroah-Hartman /* 1450ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1451ab4382d2SGreg Kroah-Hartman */ 1452ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1453ab4382d2SGreg Kroah-Hartman { 1454ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1455ab4382d2SGreg Kroah-Hartman 1456da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1457ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1458ab4382d2SGreg Kroah-Hartman } 1459ab4382d2SGreg Kroah-Hartman 1460ab4382d2SGreg Kroah-Hartman /* 1461ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1462ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1463ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1464ab4382d2SGreg Kroah-Hartman */ 1465ab4382d2SGreg Kroah-Hartman static int 1466ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1467ab4382d2SGreg Kroah-Hartman { 1468ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1469ab4382d2SGreg Kroah-Hartman int ret = 0; 1470ab4382d2SGreg Kroah-Hartman 1471ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1472ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1473ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1474ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1475ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1476ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1477ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1478ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1479a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1480ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1481ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1482ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1483ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1484ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1485ab4382d2SGreg Kroah-Hartman return ret; 1486ab4382d2SGreg Kroah-Hartman } 1487ab4382d2SGreg Kroah-Hartman 148801f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 14896b8bdad9SDaniel Thompson 14906b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 14916b8bdad9SDaniel Thompson { 14926b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 14936b8bdad9SDaniel Thompson unsigned long flags; 14946b8bdad9SDaniel Thompson unsigned long temp; 14956b8bdad9SDaniel Thompson int retval; 14966b8bdad9SDaniel Thompson 14976b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 14986b8bdad9SDaniel Thompson if (retval) 14996b8bdad9SDaniel Thompson return retval; 15006b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 15016b8bdad9SDaniel Thompson if (retval) 15026b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 15036b8bdad9SDaniel Thompson 15046b8bdad9SDaniel Thompson imx_setup_ufcr(sport, 0); 15056b8bdad9SDaniel Thompson 15066b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 15076b8bdad9SDaniel Thompson 15086b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR1); 15096b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 15106b8bdad9SDaniel Thompson temp |= IMX1_UCR1_UARTCLKEN; 15116b8bdad9SDaniel Thompson temp |= UCR1_UARTEN | UCR1_RRDYEN; 15126b8bdad9SDaniel Thompson temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 15136b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR1); 15146b8bdad9SDaniel Thompson 15156b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR2); 15166b8bdad9SDaniel Thompson temp |= UCR2_RXEN; 15176b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR2); 15186b8bdad9SDaniel Thompson 15196b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 15206b8bdad9SDaniel Thompson 15216b8bdad9SDaniel Thompson return 0; 15226b8bdad9SDaniel Thompson } 15236b8bdad9SDaniel Thompson 152401f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 152501f56abdSSaleem Abdulrasool { 1526f968ef34SDaniel Thompson if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 152726c47412SDirk Behme return NO_POLL_CHAR; 152801f56abdSSaleem Abdulrasool 1529f968ef34SDaniel Thompson return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 153001f56abdSSaleem Abdulrasool } 153101f56abdSSaleem Abdulrasool 153201f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 153301f56abdSSaleem Abdulrasool { 153401f56abdSSaleem Abdulrasool unsigned int status; 153501f56abdSSaleem Abdulrasool 153601f56abdSSaleem Abdulrasool /* drain */ 153701f56abdSSaleem Abdulrasool do { 1538f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR1); 153901f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 154001f56abdSSaleem Abdulrasool 154101f56abdSSaleem Abdulrasool /* write */ 1542f968ef34SDaniel Thompson writel_relaxed(c, port->membase + URTX0); 154301f56abdSSaleem Abdulrasool 154401f56abdSSaleem Abdulrasool /* flush */ 154501f56abdSSaleem Abdulrasool do { 1546f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR2); 154701f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 154801f56abdSSaleem Abdulrasool } 154901f56abdSSaleem Abdulrasool #endif 155001f56abdSSaleem Abdulrasool 155117b8f2a3SUwe Kleine-König static int imx_rs485_config(struct uart_port *port, 155217b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 155317b8f2a3SUwe Kleine-König { 155417b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 155517b8f2a3SUwe Kleine-König 155617b8f2a3SUwe Kleine-König /* unimplemented */ 155717b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 155817b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 155917b8f2a3SUwe Kleine-König rs485conf->flags |= SER_RS485_RX_DURING_TX; 156017b8f2a3SUwe Kleine-König 156117b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 156217b8f2a3SUwe Kleine-König if (!sport->have_rtscts) 156317b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 156417b8f2a3SUwe Kleine-König 156517b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 156617b8f2a3SUwe Kleine-König unsigned long temp; 156717b8f2a3SUwe Kleine-König 156817b8f2a3SUwe Kleine-König /* disable transmitter */ 156917b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 157017b8f2a3SUwe Kleine-König temp &= ~UCR2_CTSC; 157117b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 157217b8f2a3SUwe Kleine-König temp &= ~UCR2_CTS; 157317b8f2a3SUwe Kleine-König else 157417b8f2a3SUwe Kleine-König temp |= UCR2_CTS; 157517b8f2a3SUwe Kleine-König writel(temp, sport->port.membase + UCR2); 157617b8f2a3SUwe Kleine-König } 157717b8f2a3SUwe Kleine-König 157817b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 157917b8f2a3SUwe Kleine-König 158017b8f2a3SUwe Kleine-König return 0; 158117b8f2a3SUwe Kleine-König } 158217b8f2a3SUwe Kleine-König 1583ab4382d2SGreg Kroah-Hartman static struct uart_ops imx_pops = { 1584ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1585ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1586ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1587ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1588ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1589ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1590ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1591ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1592ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1593ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1594eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1595ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1596ab4382d2SGreg Kroah-Hartman .type = imx_type, 1597ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1598ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 159901f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 16006b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 160101f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 160201f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 160301f56abdSSaleem Abdulrasool #endif 1604ab4382d2SGreg Kroah-Hartman }; 1605ab4382d2SGreg Kroah-Hartman 1606ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1607ab4382d2SGreg Kroah-Hartman 1608ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1609ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1610ab4382d2SGreg Kroah-Hartman { 1611ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1612ab4382d2SGreg Kroah-Hartman 1613fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1614ab4382d2SGreg Kroah-Hartman barrier(); 1615ab4382d2SGreg Kroah-Hartman 1616ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1617ab4382d2SGreg Kroah-Hartman } 1618ab4382d2SGreg Kroah-Hartman 1619ab4382d2SGreg Kroah-Hartman /* 1620ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1621ab4382d2SGreg Kroah-Hartman */ 1622ab4382d2SGreg Kroah-Hartman static void 1623ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1624ab4382d2SGreg Kroah-Hartman { 1625ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 16260ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 16270ad5a814SDirk Behme unsigned int ucr1; 1628f30e8260SShawn Guo unsigned long flags = 0; 1629677fe555SThomas Gleixner int locked = 1; 16301cf93e0dSHuang Shijie int retval; 16311cf93e0dSHuang Shijie 16321cf93e0dSHuang Shijie retval = clk_enable(sport->clk_per); 16331cf93e0dSHuang Shijie if (retval) 16341cf93e0dSHuang Shijie return; 16351cf93e0dSHuang Shijie retval = clk_enable(sport->clk_ipg); 16361cf93e0dSHuang Shijie if (retval) { 16371cf93e0dSHuang Shijie clk_disable(sport->clk_per); 16381cf93e0dSHuang Shijie return; 16391cf93e0dSHuang Shijie } 16409ec1882dSXinyu Chen 1641677fe555SThomas Gleixner if (sport->port.sysrq) 1642677fe555SThomas Gleixner locked = 0; 1643677fe555SThomas Gleixner else if (oops_in_progress) 1644677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1645677fe555SThomas Gleixner else 16469ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1647ab4382d2SGreg Kroah-Hartman 1648ab4382d2SGreg Kroah-Hartman /* 16490ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1650ab4382d2SGreg Kroah-Hartman */ 16510ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 16520ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1653ab4382d2SGreg Kroah-Hartman 1654fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1655fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1656ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1657ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1658ab4382d2SGreg Kroah-Hartman 1659ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1660ab4382d2SGreg Kroah-Hartman 16610ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1662ab4382d2SGreg Kroah-Hartman 1663ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1664ab4382d2SGreg Kroah-Hartman 1665ab4382d2SGreg Kroah-Hartman /* 1666ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 16670ad5a814SDirk Behme * and restore UCR1/2/3 1668ab4382d2SGreg Kroah-Hartman */ 1669ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1670ab4382d2SGreg Kroah-Hartman 16710ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 16729ec1882dSXinyu Chen 1673677fe555SThomas Gleixner if (locked) 16749ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 16751cf93e0dSHuang Shijie 16761cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 16771cf93e0dSHuang Shijie clk_disable(sport->clk_per); 1678ab4382d2SGreg Kroah-Hartman } 1679ab4382d2SGreg Kroah-Hartman 1680ab4382d2SGreg Kroah-Hartman /* 1681ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1682ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1683ab4382d2SGreg Kroah-Hartman */ 1684ab4382d2SGreg Kroah-Hartman static void __init 1685ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1686ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1687ab4382d2SGreg Kroah-Hartman { 1688ab4382d2SGreg Kroah-Hartman 1689ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1690ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1691ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1692ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1693ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1694ab4382d2SGreg Kroah-Hartman 1695ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1696ab4382d2SGreg Kroah-Hartman 1697ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1698ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1699ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1700ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1701ab4382d2SGreg Kroah-Hartman else 1702ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1703ab4382d2SGreg Kroah-Hartman } 1704ab4382d2SGreg Kroah-Hartman 1705ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1706ab4382d2SGreg Kroah-Hartman *bits = 8; 1707ab4382d2SGreg Kroah-Hartman else 1708ab4382d2SGreg Kroah-Hartman *bits = 7; 1709ab4382d2SGreg Kroah-Hartman 1710ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1711ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1712ab4382d2SGreg Kroah-Hartman 1713ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1714ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1715ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1716ab4382d2SGreg Kroah-Hartman else 1717ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1718ab4382d2SGreg Kroah-Hartman 17193a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1720ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1721ab4382d2SGreg Kroah-Hartman 1722ab4382d2SGreg Kroah-Hartman { /* 1723ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1724ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1725ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1726ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1727ab4382d2SGreg Kroah-Hartman */ 1728ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1729ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1730ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1731ab4382d2SGreg Kroah-Hartman 1732ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1733ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1734ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1735ab4382d2SGreg Kroah-Hartman } 1736ab4382d2SGreg Kroah-Hartman 1737ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 173850bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1739ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1740ab4382d2SGreg Kroah-Hartman } 1741ab4382d2SGreg Kroah-Hartman } 1742ab4382d2SGreg Kroah-Hartman 1743ab4382d2SGreg Kroah-Hartman static int __init 1744ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1745ab4382d2SGreg Kroah-Hartman { 1746ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1747ab4382d2SGreg Kroah-Hartman int baud = 9600; 1748ab4382d2SGreg Kroah-Hartman int bits = 8; 1749ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1750ab4382d2SGreg Kroah-Hartman int flow = 'n'; 17511cf93e0dSHuang Shijie int retval; 1752ab4382d2SGreg Kroah-Hartman 1753ab4382d2SGreg Kroah-Hartman /* 1754ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1755ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1756ab4382d2SGreg Kroah-Hartman * console support. 1757ab4382d2SGreg Kroah-Hartman */ 1758ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1759ab4382d2SGreg Kroah-Hartman co->index = 0; 1760ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1761ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1762ab4382d2SGreg Kroah-Hartman return -ENODEV; 1763ab4382d2SGreg Kroah-Hartman 17641cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 17651cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 17661cf93e0dSHuang Shijie if (retval) 17671cf93e0dSHuang Shijie goto error_console; 17681cf93e0dSHuang Shijie 1769ab4382d2SGreg Kroah-Hartman if (options) 1770ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1771ab4382d2SGreg Kroah-Hartman else 1772ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1773ab4382d2SGreg Kroah-Hartman 1774ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1775ab4382d2SGreg Kroah-Hartman 17761cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 17771cf93e0dSHuang Shijie 17781cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 17791cf93e0dSHuang Shijie if (retval) { 17801cf93e0dSHuang Shijie clk_unprepare(sport->clk_ipg); 17811cf93e0dSHuang Shijie goto error_console; 17821cf93e0dSHuang Shijie } 17831cf93e0dSHuang Shijie 17841cf93e0dSHuang Shijie retval = clk_prepare(sport->clk_per); 17851cf93e0dSHuang Shijie if (retval) 17861cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 17871cf93e0dSHuang Shijie 17881cf93e0dSHuang Shijie error_console: 17891cf93e0dSHuang Shijie return retval; 1790ab4382d2SGreg Kroah-Hartman } 1791ab4382d2SGreg Kroah-Hartman 1792ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1793ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1794ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1795ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1796ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1797ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1798ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1799ab4382d2SGreg Kroah-Hartman .index = -1, 1800ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1801ab4382d2SGreg Kroah-Hartman }; 1802ab4382d2SGreg Kroah-Hartman 1803ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1804ab4382d2SGreg Kroah-Hartman #else 1805ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1806ab4382d2SGreg Kroah-Hartman #endif 1807ab4382d2SGreg Kroah-Hartman 1808ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1809ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1810ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 1811ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 1812ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 1813ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 1814ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 1815ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 1816ab4382d2SGreg Kroah-Hartman }; 1817ab4382d2SGreg Kroah-Hartman 1818ab4382d2SGreg Kroah-Hartman static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1819ab4382d2SGreg Kroah-Hartman { 1820ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1821db1a9b55SFabio Estevam unsigned int val; 1822db1a9b55SFabio Estevam 1823db1a9b55SFabio Estevam /* enable wakeup from i.MX UART */ 1824db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1825db1a9b55SFabio Estevam val |= UCR3_AWAKEN; 1826db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1827ab4382d2SGreg Kroah-Hartman 1828ab4382d2SGreg Kroah-Hartman uart_suspend_port(&imx_reg, &sport->port); 1829ab4382d2SGreg Kroah-Hartman 1830ab4382d2SGreg Kroah-Hartman return 0; 1831ab4382d2SGreg Kroah-Hartman } 1832ab4382d2SGreg Kroah-Hartman 1833ab4382d2SGreg Kroah-Hartman static int serial_imx_resume(struct platform_device *dev) 1834ab4382d2SGreg Kroah-Hartman { 1835ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1836db1a9b55SFabio Estevam unsigned int val; 1837db1a9b55SFabio Estevam 1838db1a9b55SFabio Estevam /* disable wakeup from i.MX UART */ 1839db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1840db1a9b55SFabio Estevam val &= ~UCR3_AWAKEN; 1841db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1842ab4382d2SGreg Kroah-Hartman 1843ab4382d2SGreg Kroah-Hartman uart_resume_port(&imx_reg, &sport->port); 1844ab4382d2SGreg Kroah-Hartman 1845ab4382d2SGreg Kroah-Hartman return 0; 1846ab4382d2SGreg Kroah-Hartman } 1847ab4382d2SGreg Kroah-Hartman 184822698aa2SShawn Guo #ifdef CONFIG_OF 184920bb8095SUwe Kleine-König /* 185020bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 185120bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 185220bb8095SUwe Kleine-König */ 185322698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 185422698aa2SShawn Guo struct platform_device *pdev) 185522698aa2SShawn Guo { 185622698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 185722698aa2SShawn Guo const struct of_device_id *of_id = 185822698aa2SShawn Guo of_match_device(imx_uart_dt_ids, &pdev->dev); 1859ff05967aSShawn Guo int ret; 186022698aa2SShawn Guo 186122698aa2SShawn Guo if (!np) 186220bb8095SUwe Kleine-König /* no device tree device */ 186320bb8095SUwe Kleine-König return 1; 186422698aa2SShawn Guo 1865ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 1866ff05967aSShawn Guo if (ret < 0) { 1867ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1868a197a191SUwe Kleine-König return ret; 1869ff05967aSShawn Guo } 1870ff05967aSShawn Guo sport->port.line = ret; 187122698aa2SShawn Guo 187222698aa2SShawn Guo if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 187322698aa2SShawn Guo sport->have_rtscts = 1; 187422698aa2SShawn Guo 187520ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 187620ff2fe6SHuang Shijie sport->dte_mode = 1; 187720ff2fe6SHuang Shijie 187822698aa2SShawn Guo sport->devdata = of_id->data; 187922698aa2SShawn Guo 188022698aa2SShawn Guo return 0; 188122698aa2SShawn Guo } 188222698aa2SShawn Guo #else 188322698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 188422698aa2SShawn Guo struct platform_device *pdev) 188522698aa2SShawn Guo { 188620bb8095SUwe Kleine-König return 1; 188722698aa2SShawn Guo } 188822698aa2SShawn Guo #endif 188922698aa2SShawn Guo 189022698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 189122698aa2SShawn Guo struct platform_device *pdev) 189222698aa2SShawn Guo { 1893574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 189422698aa2SShawn Guo 189522698aa2SShawn Guo sport->port.line = pdev->id; 189622698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 189722698aa2SShawn Guo 189822698aa2SShawn Guo if (!pdata) 189922698aa2SShawn Guo return; 190022698aa2SShawn Guo 190122698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 190222698aa2SShawn Guo sport->have_rtscts = 1; 190322698aa2SShawn Guo } 190422698aa2SShawn Guo 1905ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 1906ab4382d2SGreg Kroah-Hartman { 1907ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1908ab4382d2SGreg Kroah-Hartman void __iomem *base; 19098a61f0c7SFabio Estevam int ret = 0, reg; 1910ab4382d2SGreg Kroah-Hartman struct resource *res; 1911842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 1912ab4382d2SGreg Kroah-Hartman 191342d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1914ab4382d2SGreg Kroah-Hartman if (!sport) 1915ab4382d2SGreg Kroah-Hartman return -ENOMEM; 1916ab4382d2SGreg Kroah-Hartman 191722698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 191820bb8095SUwe Kleine-König if (ret > 0) 191922698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 192020bb8095SUwe Kleine-König else if (ret < 0) 192142d34191SSachin Kamat return ret; 192222698aa2SShawn Guo 1923ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1924da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 1925da82f997SAlexander Shiyan if (IS_ERR(base)) 1926da82f997SAlexander Shiyan return PTR_ERR(base); 1927ab4382d2SGreg Kroah-Hartman 1928842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 1929842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 1930842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 1931842633bdSUwe Kleine-König 1932ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 1933ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 1934ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 1935ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 1936ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 1937842633bdSUwe Kleine-König sport->port.irq = rxirq; 1938ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 1939ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 194017b8f2a3SUwe Kleine-König sport->port.rs485_config = imx_rs485_config; 194117b8f2a3SUwe Kleine-König sport->port.rs485.flags = 194217b8f2a3SUwe Kleine-König SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX; 1943ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 1944ab4382d2SGreg Kroah-Hartman init_timer(&sport->timer); 1945ab4382d2SGreg Kroah-Hartman sport->timer.function = imx_timeout; 1946ab4382d2SGreg Kroah-Hartman sport->timer.data = (unsigned long)sport; 1947ab4382d2SGreg Kroah-Hartman 19483a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 19493a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 19503a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 1951833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 195242d34191SSachin Kamat return ret; 1953ab4382d2SGreg Kroah-Hartman } 1954ab4382d2SGreg Kroah-Hartman 19553a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 19563a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 19573a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 1958833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 195942d34191SSachin Kamat return ret; 19603a9465faSSascha Hauer } 19613a9465faSSascha Hauer 19623a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 1963ab4382d2SGreg Kroah-Hartman 19648a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 19658a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 19668a61f0c7SFabio Estevam if (ret) 19678a61f0c7SFabio Estevam return ret; 19688a61f0c7SFabio Estevam 19698a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 19708a61f0c7SFabio Estevam reg = readl_relaxed(sport->port.membase + UCR1); 19718a61f0c7SFabio Estevam reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 19728a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 19738a61f0c7SFabio Estevam writel_relaxed(reg, sport->port.membase + UCR1); 19748a61f0c7SFabio Estevam 19758a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 19768a61f0c7SFabio Estevam 1977c0d1c6b0SFabio Estevam /* 1978c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 1979c0d1c6b0SFabio Estevam * chips only have one interrupt. 1980c0d1c6b0SFabio Estevam */ 1981842633bdSUwe Kleine-König if (txirq > 0) { 1982842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 1983c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 1984c0d1c6b0SFabio Estevam if (ret) 1985c0d1c6b0SFabio Estevam return ret; 1986c0d1c6b0SFabio Estevam 1987842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 1988c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 1989c0d1c6b0SFabio Estevam if (ret) 1990c0d1c6b0SFabio Estevam return ret; 1991c0d1c6b0SFabio Estevam } else { 1992842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 1993c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 1994c0d1c6b0SFabio Estevam if (ret) 1995c0d1c6b0SFabio Estevam return ret; 1996c0d1c6b0SFabio Estevam } 1997c0d1c6b0SFabio Estevam 199822698aa2SShawn Guo imx_ports[sport->port.line] = sport; 1999ab4382d2SGreg Kroah-Hartman 20000a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2001ab4382d2SGreg Kroah-Hartman 200245af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2003ab4382d2SGreg Kroah-Hartman } 2004ab4382d2SGreg Kroah-Hartman 2005ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2006ab4382d2SGreg Kroah-Hartman { 2007ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2008ab4382d2SGreg Kroah-Hartman 200945af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2010ab4382d2SGreg Kroah-Hartman } 2011ab4382d2SGreg Kroah-Hartman 2012ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2013ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2014ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2015ab4382d2SGreg Kroah-Hartman 2016ab4382d2SGreg Kroah-Hartman .suspend = serial_imx_suspend, 2017ab4382d2SGreg Kroah-Hartman .resume = serial_imx_resume, 2018fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2019ab4382d2SGreg Kroah-Hartman .driver = { 2020ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 202122698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 2022ab4382d2SGreg Kroah-Hartman }, 2023ab4382d2SGreg Kroah-Hartman }; 2024ab4382d2SGreg Kroah-Hartman 2025ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2026ab4382d2SGreg Kroah-Hartman { 2027f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2028ab4382d2SGreg Kroah-Hartman 2029ab4382d2SGreg Kroah-Hartman if (ret) 2030ab4382d2SGreg Kroah-Hartman return ret; 2031ab4382d2SGreg Kroah-Hartman 2032ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2033ab4382d2SGreg Kroah-Hartman if (ret != 0) 2034ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2035ab4382d2SGreg Kroah-Hartman 2036f227824eSUwe Kleine-König return ret; 2037ab4382d2SGreg Kroah-Hartman } 2038ab4382d2SGreg Kroah-Hartman 2039ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2040ab4382d2SGreg Kroah-Hartman { 2041ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2042ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2043ab4382d2SGreg Kroah-Hartman } 2044ab4382d2SGreg Kroah-Hartman 2045ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2046ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2047ab4382d2SGreg Kroah-Hartman 2048ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2049ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2050ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2051ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2052