1ab4382d2SGreg Kroah-Hartman /* 2ab4382d2SGreg Kroah-Hartman * Driver for Motorola IMX serial ports 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 7ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 8ab4382d2SGreg Kroah-Hartman * 9ab4382d2SGreg Kroah-Hartman * Copyright (C) 2009 emlix GmbH 10ab4382d2SGreg Kroah-Hartman * Author: Fabian Godehardt (added IrDA support for iMX) 11ab4382d2SGreg Kroah-Hartman * 12ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 13ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 14ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2 of the License, or 15ab4382d2SGreg Kroah-Hartman * (at your option) any later version. 16ab4382d2SGreg Kroah-Hartman * 17ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 18ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY; without even the implied warranty of 19ab4382d2SGreg Kroah-Hartman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20ab4382d2SGreg Kroah-Hartman * GNU General Public License for more details. 21ab4382d2SGreg Kroah-Hartman * 22ab4382d2SGreg Kroah-Hartman * You should have received a copy of the GNU General Public License 23ab4382d2SGreg Kroah-Hartman * along with this program; if not, write to the Free Software 24ab4382d2SGreg Kroah-Hartman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25ab4382d2SGreg Kroah-Hartman * 26ab4382d2SGreg Kroah-Hartman * [29-Mar-2005] Mike Lee 27ab4382d2SGreg Kroah-Hartman * Added hardware handshake 28ab4382d2SGreg Kroah-Hartman */ 29ab4382d2SGreg Kroah-Hartman 30ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 32ab4382d2SGreg Kroah-Hartman #endif 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 35ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 36ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 37ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 38ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 39ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 40ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 41ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 42ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 43ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 44ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 45ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 46ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 47ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 4822698aa2SShawn Guo #include <linux/of.h> 4922698aa2SShawn Guo #include <linux/of_device.h> 50e32a9f8fSSachin Kamat #include <linux/io.h> 51b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 52ab4382d2SGreg Kroah-Hartman 53ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 5482906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 55b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 56ab4382d2SGreg Kroah-Hartman 57ab4382d2SGreg Kroah-Hartman /* Register definitions */ 58ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 59ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 60ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 61ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 62ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 63ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 64ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 65ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 66ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 67ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 68ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 69ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 70ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 71ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 72fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 73fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 74fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 75ab4382d2SGreg Kroah-Hartman 76ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 77ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 78ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 79ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 80ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 81ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 82ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 8325985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 84ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 85ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 87b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 88ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 89ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 91ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 93ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 94ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 95fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 96b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 97ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 98ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 99ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 101ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 102ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 103ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 105ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 106ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 107ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 108ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 10901f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 110ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 111ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 112ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 113ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 114ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 115ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 117ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 118ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 119ab4382d2SGreg Kroah-Hartman #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 120ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 123fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 124ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 125ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 126ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 127ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 128ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 129ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 130ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 131ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 132b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 133ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 134ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 135ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 136ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 137ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 138ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1397be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 140ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 141ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 142ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 143ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 145ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 146ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 147ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 150ab4382d2SGreg Kroah-Hartman #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 151ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 152ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 153ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 154ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 155ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 156ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 157ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 158ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 159ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 160ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 161ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 162ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 163ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 164ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 165ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 166ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 167ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 168ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 169ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 170ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 171ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 172ab4382d2SGreg Kroah-Hartman 173ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 174ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 175ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 176ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 177ab4382d2SGreg Kroah-Hartman 178ab4382d2SGreg Kroah-Hartman /* 179ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 180ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 181ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 182ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 183ab4382d2SGreg Kroah-Hartman */ 184ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 185ab4382d2SGreg Kroah-Hartman 186ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 187ab4382d2SGreg Kroah-Hartman 188ab4382d2SGreg Kroah-Hartman #define UART_NR 8 189ab4382d2SGreg Kroah-Hartman 190fe6b540aSShawn Guo /* i.mx21 type uart runs on all i.mx except i.mx1 */ 191fe6b540aSShawn Guo enum imx_uart_type { 192fe6b540aSShawn Guo IMX1_UART, 193fe6b540aSShawn Guo IMX21_UART, 194a496e628SHuang Shijie IMX6Q_UART, 195fe6b540aSShawn Guo }; 196fe6b540aSShawn Guo 197fe6b540aSShawn Guo /* device type dependent stuff */ 198fe6b540aSShawn Guo struct imx_uart_data { 199fe6b540aSShawn Guo unsigned uts_reg; 200fe6b540aSShawn Guo enum imx_uart_type devtype; 201fe6b540aSShawn Guo }; 202fe6b540aSShawn Guo 203ab4382d2SGreg Kroah-Hartman struct imx_port { 204ab4382d2SGreg Kroah-Hartman struct uart_port port; 205ab4382d2SGreg Kroah-Hartman struct timer_list timer; 206ab4382d2SGreg Kroah-Hartman unsigned int old_status; 207ab4382d2SGreg Kroah-Hartman int txirq, rxirq, rtsirq; 208ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 20920ff2fe6SHuang Shijie unsigned int dte_mode:1; 210ab4382d2SGreg Kroah-Hartman unsigned int use_irda:1; 211ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_rx:1; 212ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_tx:1; 213ab4382d2SGreg Kroah-Hartman unsigned short trcv_delay; /* transceiver delay */ 2143a9465faSSascha Hauer struct clk *clk_ipg; 2153a9465faSSascha Hauer struct clk *clk_per; 2167d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 217b4cdc8f6SHuang Shijie 218b4cdc8f6SHuang Shijie /* DMA fields */ 219b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 220b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 221b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 223b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 224b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 225b4cdc8f6SHuang Shijie void *rx_buf; 2267cb92fd2SHuang Shijie unsigned int tx_bytes; 227b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 228b4cdc8f6SHuang Shijie wait_queue_head_t dma_wait; 229ab4382d2SGreg Kroah-Hartman }; 230ab4382d2SGreg Kroah-Hartman 2310ad5a814SDirk Behme struct imx_port_ucrs { 2320ad5a814SDirk Behme unsigned int ucr1; 2330ad5a814SDirk Behme unsigned int ucr2; 2340ad5a814SDirk Behme unsigned int ucr3; 2350ad5a814SDirk Behme }; 2360ad5a814SDirk Behme 237ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_IRDA 238ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) ((sport)->use_irda) 239ab4382d2SGreg Kroah-Hartman #else 240ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) (0) 241ab4382d2SGreg Kroah-Hartman #endif 242ab4382d2SGreg Kroah-Hartman 243fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 244fe6b540aSShawn Guo [IMX1_UART] = { 245fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 246fe6b540aSShawn Guo .devtype = IMX1_UART, 247fe6b540aSShawn Guo }, 248fe6b540aSShawn Guo [IMX21_UART] = { 249fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 250fe6b540aSShawn Guo .devtype = IMX21_UART, 251fe6b540aSShawn Guo }, 252a496e628SHuang Shijie [IMX6Q_UART] = { 253a496e628SHuang Shijie .uts_reg = IMX21_UTS, 254a496e628SHuang Shijie .devtype = IMX6Q_UART, 255a496e628SHuang Shijie }, 256fe6b540aSShawn Guo }; 257fe6b540aSShawn Guo 258fe6b540aSShawn Guo static struct platform_device_id imx_uart_devtype[] = { 259fe6b540aSShawn Guo { 260fe6b540aSShawn Guo .name = "imx1-uart", 261fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 262fe6b540aSShawn Guo }, { 263fe6b540aSShawn Guo .name = "imx21-uart", 264fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 265fe6b540aSShawn Guo }, { 266a496e628SHuang Shijie .name = "imx6q-uart", 267a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 268a496e628SHuang Shijie }, { 269fe6b540aSShawn Guo /* sentinel */ 270fe6b540aSShawn Guo } 271fe6b540aSShawn Guo }; 272fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 273fe6b540aSShawn Guo 27422698aa2SShawn Guo static struct of_device_id imx_uart_dt_ids[] = { 275a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 27622698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27722698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27822698aa2SShawn Guo { /* sentinel */ } 27922698aa2SShawn Guo }; 28022698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28122698aa2SShawn Guo 282fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 283fe6b540aSShawn Guo { 284fe6b540aSShawn Guo return sport->devdata->uts_reg; 285fe6b540aSShawn Guo } 286fe6b540aSShawn Guo 287fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 288fe6b540aSShawn Guo { 289fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 290fe6b540aSShawn Guo } 291fe6b540aSShawn Guo 292fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 293fe6b540aSShawn Guo { 294fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 295fe6b540aSShawn Guo } 296fe6b540aSShawn Guo 297a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 298a496e628SHuang Shijie { 299a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 300a496e628SHuang Shijie } 301ab4382d2SGreg Kroah-Hartman /* 30244a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 30344a75411Sfabio.estevam@freescale.com */ 304e8bfa760SFabio Estevam #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE) 30544a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 30644a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30744a75411Sfabio.estevam@freescale.com { 30844a75411Sfabio.estevam@freescale.com /* save control registers */ 30944a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 31044a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 31144a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 31244a75411Sfabio.estevam@freescale.com } 31344a75411Sfabio.estevam@freescale.com 31444a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 31544a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 31644a75411Sfabio.estevam@freescale.com { 31744a75411Sfabio.estevam@freescale.com /* restore control registers */ 31844a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 31944a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 32044a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 32144a75411Sfabio.estevam@freescale.com } 322e8bfa760SFabio Estevam #endif 32344a75411Sfabio.estevam@freescale.com 32444a75411Sfabio.estevam@freescale.com /* 325ab4382d2SGreg Kroah-Hartman * Handle any change of modem status signal since we were last called. 326ab4382d2SGreg Kroah-Hartman */ 327ab4382d2SGreg Kroah-Hartman static void imx_mctrl_check(struct imx_port *sport) 328ab4382d2SGreg Kroah-Hartman { 329ab4382d2SGreg Kroah-Hartman unsigned int status, changed; 330ab4382d2SGreg Kroah-Hartman 331ab4382d2SGreg Kroah-Hartman status = sport->port.ops->get_mctrl(&sport->port); 332ab4382d2SGreg Kroah-Hartman changed = status ^ sport->old_status; 333ab4382d2SGreg Kroah-Hartman 334ab4382d2SGreg Kroah-Hartman if (changed == 0) 335ab4382d2SGreg Kroah-Hartman return; 336ab4382d2SGreg Kroah-Hartman 337ab4382d2SGreg Kroah-Hartman sport->old_status = status; 338ab4382d2SGreg Kroah-Hartman 339ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_RI) 340ab4382d2SGreg Kroah-Hartman sport->port.icount.rng++; 341ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_DSR) 342ab4382d2SGreg Kroah-Hartman sport->port.icount.dsr++; 343ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CAR) 344ab4382d2SGreg Kroah-Hartman uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 345ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CTS) 346ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 347ab4382d2SGreg Kroah-Hartman 348ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 349ab4382d2SGreg Kroah-Hartman } 350ab4382d2SGreg Kroah-Hartman 351ab4382d2SGreg Kroah-Hartman /* 352ab4382d2SGreg Kroah-Hartman * This is our per-port timeout handler, for checking the 353ab4382d2SGreg Kroah-Hartman * modem status signals. 354ab4382d2SGreg Kroah-Hartman */ 355ab4382d2SGreg Kroah-Hartman static void imx_timeout(unsigned long data) 356ab4382d2SGreg Kroah-Hartman { 357ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)data; 358ab4382d2SGreg Kroah-Hartman unsigned long flags; 359ab4382d2SGreg Kroah-Hartman 360ab4382d2SGreg Kroah-Hartman if (sport->port.state) { 361ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 362ab4382d2SGreg Kroah-Hartman imx_mctrl_check(sport); 363ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 364ab4382d2SGreg Kroah-Hartman 365ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 366ab4382d2SGreg Kroah-Hartman } 367ab4382d2SGreg Kroah-Hartman } 368ab4382d2SGreg Kroah-Hartman 369ab4382d2SGreg Kroah-Hartman /* 370ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 371ab4382d2SGreg Kroah-Hartman */ 372ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 373ab4382d2SGreg Kroah-Hartman { 374ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 375ab4382d2SGreg Kroah-Hartman unsigned long temp; 376ab4382d2SGreg Kroah-Hartman 377ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 378ab4382d2SGreg Kroah-Hartman /* half duplex - wait for end of transmission */ 379ab4382d2SGreg Kroah-Hartman int n = 256; 380ab4382d2SGreg Kroah-Hartman while ((--n > 0) && 381ab4382d2SGreg Kroah-Hartman !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 382ab4382d2SGreg Kroah-Hartman udelay(5); 383ab4382d2SGreg Kroah-Hartman barrier(); 384ab4382d2SGreg Kroah-Hartman } 385ab4382d2SGreg Kroah-Hartman /* 386ab4382d2SGreg Kroah-Hartman * irda transceiver - wait a bit more to avoid 387ab4382d2SGreg Kroah-Hartman * cutoff, hardware dependent 388ab4382d2SGreg Kroah-Hartman */ 389ab4382d2SGreg Kroah-Hartman udelay(sport->trcv_delay); 390ab4382d2SGreg Kroah-Hartman 391ab4382d2SGreg Kroah-Hartman /* 392ab4382d2SGreg Kroah-Hartman * half duplex - reactivate receive mode, 393ab4382d2SGreg Kroah-Hartman * flush receive pipe echo crap 394ab4382d2SGreg Kroah-Hartman */ 395ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR2) & USR2_TXDC) { 396ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 397ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 398ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 399ab4382d2SGreg Kroah-Hartman 400ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 401ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_TCEN); 402ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 403ab4382d2SGreg Kroah-Hartman 404ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + URXD0) & 405ab4382d2SGreg Kroah-Hartman URXD_CHARRDY) 406ab4382d2SGreg Kroah-Hartman barrier(); 407ab4382d2SGreg Kroah-Hartman 408ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 409ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN; 410ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 411ab4382d2SGreg Kroah-Hartman 412ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 413ab4382d2SGreg Kroah-Hartman temp |= UCR4_DREN; 414ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 415ab4382d2SGreg Kroah-Hartman } 416ab4382d2SGreg Kroah-Hartman return; 417ab4382d2SGreg Kroah-Hartman } 418ab4382d2SGreg Kroah-Hartman 419b4cdc8f6SHuang Shijie /* 420b4cdc8f6SHuang Shijie * We are maybe in the SMP context, so if the DMA TX thread is running 421b4cdc8f6SHuang Shijie * on other cpu, we have to wait for it to finish. 422b4cdc8f6SHuang Shijie */ 423b4cdc8f6SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 424b4cdc8f6SHuang Shijie return; 425b4cdc8f6SHuang Shijie 426ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 427ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 428ab4382d2SGreg Kroah-Hartman } 429ab4382d2SGreg Kroah-Hartman 430ab4382d2SGreg Kroah-Hartman /* 431ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 432ab4382d2SGreg Kroah-Hartman */ 433ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 434ab4382d2SGreg Kroah-Hartman { 435ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 436ab4382d2SGreg Kroah-Hartman unsigned long temp; 437ab4382d2SGreg Kroah-Hartman 438b4cdc8f6SHuang Shijie /* 439b4cdc8f6SHuang Shijie * We are maybe in the SMP context, so if the DMA TX thread is running 440b4cdc8f6SHuang Shijie * on other cpu, we have to wait for it to finish. 441b4cdc8f6SHuang Shijie */ 442b4cdc8f6SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) 443b4cdc8f6SHuang Shijie return; 444b4cdc8f6SHuang Shijie 445ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 446ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 447ab4382d2SGreg Kroah-Hartman } 448ab4382d2SGreg Kroah-Hartman 449ab4382d2SGreg Kroah-Hartman /* 450ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 451ab4382d2SGreg Kroah-Hartman */ 452ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 453ab4382d2SGreg Kroah-Hartman { 454ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 455ab4382d2SGreg Kroah-Hartman 456ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 457ab4382d2SGreg Kroah-Hartman } 458ab4382d2SGreg Kroah-Hartman 459ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 460ab4382d2SGreg Kroah-Hartman { 461ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 462ab4382d2SGreg Kroah-Hartman 463ab4382d2SGreg Kroah-Hartman while (!uart_circ_empty(xmit) && 464fe6b540aSShawn Guo !(readl(sport->port.membase + uts_reg(sport)) 465fe6b540aSShawn Guo & UTS_TXFULL)) { 466ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 467ab4382d2SGreg Kroah-Hartman * out the port here */ 468ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 469ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 470ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 471ab4382d2SGreg Kroah-Hartman } 472ab4382d2SGreg Kroah-Hartman 473ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 474ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 475ab4382d2SGreg Kroah-Hartman 476ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 477ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 478ab4382d2SGreg Kroah-Hartman } 479ab4382d2SGreg Kroah-Hartman 480b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 481b4cdc8f6SHuang Shijie { 482b4cdc8f6SHuang Shijie struct imx_port *sport = data; 483b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 484b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 485b4cdc8f6SHuang Shijie unsigned long flags; 486b4cdc8f6SHuang Shijie 487b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 488b4cdc8f6SHuang Shijie 489b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 490b4cdc8f6SHuang Shijie 491b4cdc8f6SHuang Shijie /* update the stat */ 492b4cdc8f6SHuang Shijie spin_lock_irqsave(&sport->port.lock, flags); 493b4cdc8f6SHuang Shijie xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 494b4cdc8f6SHuang Shijie sport->port.icount.tx += sport->tx_bytes; 495b4cdc8f6SHuang Shijie spin_unlock_irqrestore(&sport->port.lock, flags); 496b4cdc8f6SHuang Shijie 497b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 498b4cdc8f6SHuang Shijie 499b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 500b4cdc8f6SHuang Shijie 501b4cdc8f6SHuang Shijie if (waitqueue_active(&sport->dma_wait)) { 502b4cdc8f6SHuang Shijie wake_up(&sport->dma_wait); 503b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 504b4cdc8f6SHuang Shijie return; 505b4cdc8f6SHuang Shijie } 506b4cdc8f6SHuang Shijie } 507b4cdc8f6SHuang Shijie 5087cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 509b4cdc8f6SHuang Shijie { 510b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 511b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 512b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 513b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 514b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 515b4cdc8f6SHuang Shijie enum dma_status status; 516b4cdc8f6SHuang Shijie int ret; 517b4cdc8f6SHuang Shijie 518f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL); 519b4cdc8f6SHuang Shijie if (DMA_IN_PROGRESS == status) 520b4cdc8f6SHuang Shijie return; 521b4cdc8f6SHuang Shijie 522b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 523b4cdc8f6SHuang Shijie 524947c74ebSHuang Shijie if (xmit->tail > xmit->head && xmit->head > 0) { 525b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 526b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 527b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 528b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 529b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 530b4cdc8f6SHuang Shijie } else { 531b4cdc8f6SHuang Shijie sport->dma_tx_nents = 1; 532b4cdc8f6SHuang Shijie sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 533b4cdc8f6SHuang Shijie } 534b4cdc8f6SHuang Shijie 535b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 536b4cdc8f6SHuang Shijie if (ret == 0) { 537b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 538b4cdc8f6SHuang Shijie return; 539b4cdc8f6SHuang Shijie } 540b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 541b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 542b4cdc8f6SHuang Shijie if (!desc) { 543b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 544b4cdc8f6SHuang Shijie return; 545b4cdc8f6SHuang Shijie } 546b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 547b4cdc8f6SHuang Shijie desc->callback_param = sport; 548b4cdc8f6SHuang Shijie 549b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 550b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 551b4cdc8f6SHuang Shijie /* fire it */ 552b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 553b4cdc8f6SHuang Shijie dmaengine_submit(desc); 554b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 555b4cdc8f6SHuang Shijie return; 556b4cdc8f6SHuang Shijie } 557b4cdc8f6SHuang Shijie 558ab4382d2SGreg Kroah-Hartman /* 559ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 560ab4382d2SGreg Kroah-Hartman */ 561ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 562ab4382d2SGreg Kroah-Hartman { 563ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 564ab4382d2SGreg Kroah-Hartman unsigned long temp; 565ab4382d2SGreg Kroah-Hartman 566ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 567ab4382d2SGreg Kroah-Hartman /* half duplex in IrDA mode; have to disable receive mode */ 568ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 569ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_DREN); 570ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 571ab4382d2SGreg Kroah-Hartman 572ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 573ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RRDYEN); 574ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 575ab4382d2SGreg Kroah-Hartman } 576f1f836e4SAlexander Stein /* Clear any pending ORE flag before enabling interrupt */ 577f1f836e4SAlexander Stein temp = readl(sport->port.membase + USR2); 578f1f836e4SAlexander Stein writel(temp | USR2_ORE, sport->port.membase + USR2); 579f1f836e4SAlexander Stein 580f1f836e4SAlexander Stein temp = readl(sport->port.membase + UCR4); 581f1f836e4SAlexander Stein temp |= UCR4_OREN; 582f1f836e4SAlexander Stein writel(temp, sport->port.membase + UCR4); 583ab4382d2SGreg Kroah-Hartman 584b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 585ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 586ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 587b4cdc8f6SHuang Shijie } 588ab4382d2SGreg Kroah-Hartman 589ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 590ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 591ab4382d2SGreg Kroah-Hartman temp |= UCR1_TRDYEN; 592ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 593ab4382d2SGreg Kroah-Hartman 594ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 595ab4382d2SGreg Kroah-Hartman temp |= UCR4_TCEN; 596ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 597ab4382d2SGreg Kroah-Hartman } 598ab4382d2SGreg Kroah-Hartman 599b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 6007cb92fd2SHuang Shijie imx_dma_tx(sport); 601b4cdc8f6SHuang Shijie return; 602b4cdc8f6SHuang Shijie } 603b4cdc8f6SHuang Shijie 604fe6b540aSShawn Guo if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) 605ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 606ab4382d2SGreg Kroah-Hartman } 607ab4382d2SGreg Kroah-Hartman 608ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 609ab4382d2SGreg Kroah-Hartman { 610ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6115680e941SUwe Kleine-König unsigned int val; 612ab4382d2SGreg Kroah-Hartman unsigned long flags; 613ab4382d2SGreg Kroah-Hartman 614ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 615ab4382d2SGreg Kroah-Hartman 616ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6175680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 618ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 619ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 620ab4382d2SGreg Kroah-Hartman 621ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 622ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 623ab4382d2SGreg Kroah-Hartman } 624ab4382d2SGreg Kroah-Hartman 625ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 626ab4382d2SGreg Kroah-Hartman { 627ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 628ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 629ab4382d2SGreg Kroah-Hartman unsigned long flags; 630ab4382d2SGreg Kroah-Hartman 631ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 632699cbd67SSachin Kamat if (sport->port.x_char) { 633ab4382d2SGreg Kroah-Hartman /* Send next char */ 634ab4382d2SGreg Kroah-Hartman writel(sport->port.x_char, sport->port.membase + URTX0); 635ab4382d2SGreg Kroah-Hartman goto out; 636ab4382d2SGreg Kroah-Hartman } 637ab4382d2SGreg Kroah-Hartman 638ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 639ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 640ab4382d2SGreg Kroah-Hartman goto out; 641ab4382d2SGreg Kroah-Hartman } 642ab4382d2SGreg Kroah-Hartman 643ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 644ab4382d2SGreg Kroah-Hartman 645ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 646ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 647ab4382d2SGreg Kroah-Hartman 648ab4382d2SGreg Kroah-Hartman out: 649ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 650ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 651ab4382d2SGreg Kroah-Hartman } 652ab4382d2SGreg Kroah-Hartman 653ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 654ab4382d2SGreg Kroah-Hartman { 655ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 656ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 65792a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 658ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 659ab4382d2SGreg Kroah-Hartman 660ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 661ab4382d2SGreg Kroah-Hartman 662ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 663ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 664ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 665ab4382d2SGreg Kroah-Hartman 666ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 667ab4382d2SGreg Kroah-Hartman 668ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 669ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 670ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 671ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 672ab4382d2SGreg Kroah-Hartman continue; 673ab4382d2SGreg Kroah-Hartman } 674ab4382d2SGreg Kroah-Hartman 675ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 676ab4382d2SGreg Kroah-Hartman continue; 677ab4382d2SGreg Kroah-Hartman 678019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 679019dc9eaSHui Wang if (rx & URXD_BRK) 680019dc9eaSHui Wang sport->port.icount.brk++; 681019dc9eaSHui Wang else if (rx & URXD_PRERR) 682ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 683ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 684ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 685ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 686ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 687ab4382d2SGreg Kroah-Hartman 688ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 689ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 690ab4382d2SGreg Kroah-Hartman goto out; 691ab4382d2SGreg Kroah-Hartman continue; 692ab4382d2SGreg Kroah-Hartman } 693ab4382d2SGreg Kroah-Hartman 694ab4382d2SGreg Kroah-Hartman rx &= sport->port.read_status_mask; 695ab4382d2SGreg Kroah-Hartman 696019dc9eaSHui Wang if (rx & URXD_BRK) 697019dc9eaSHui Wang flg = TTY_BREAK; 698019dc9eaSHui Wang else if (rx & URXD_PRERR) 699ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 700ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 701ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 702ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 703ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 704ab4382d2SGreg Kroah-Hartman 705ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 706ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 707ab4382d2SGreg Kroah-Hartman #endif 708ab4382d2SGreg Kroah-Hartman } 709ab4382d2SGreg Kroah-Hartman 71092a19f9cSJiri Slaby tty_insert_flip_char(port, rx, flg); 711ab4382d2SGreg Kroah-Hartman } 712ab4382d2SGreg Kroah-Hartman 713ab4382d2SGreg Kroah-Hartman out: 714ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7152e124b4aSJiri Slaby tty_flip_buffer_push(port); 716ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 717ab4382d2SGreg Kroah-Hartman } 718ab4382d2SGreg Kroah-Hartman 7197cb92fd2SHuang Shijie static int start_rx_dma(struct imx_port *sport); 720b4cdc8f6SHuang Shijie /* 721b4cdc8f6SHuang Shijie * If the RXFIFO is filled with some data, and then we 722b4cdc8f6SHuang Shijie * arise a DMA operation to receive them. 723b4cdc8f6SHuang Shijie */ 724b4cdc8f6SHuang Shijie static void imx_dma_rxint(struct imx_port *sport) 725b4cdc8f6SHuang Shijie { 726b4cdc8f6SHuang Shijie unsigned long temp; 727b4cdc8f6SHuang Shijie 728b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + USR2); 729b4cdc8f6SHuang Shijie if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 730b4cdc8f6SHuang Shijie sport->dma_is_rxing = 1; 731b4cdc8f6SHuang Shijie 732b4cdc8f6SHuang Shijie /* disable the `Recerver Ready Interrrupt` */ 733b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 734b4cdc8f6SHuang Shijie temp &= ~(UCR1_RRDYEN); 735b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 736b4cdc8f6SHuang Shijie 737b4cdc8f6SHuang Shijie /* tell the DMA to receive the data. */ 7387cb92fd2SHuang Shijie start_rx_dma(sport); 739b4cdc8f6SHuang Shijie } 740b4cdc8f6SHuang Shijie } 741b4cdc8f6SHuang Shijie 742ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 743ab4382d2SGreg Kroah-Hartman { 744ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 745ab4382d2SGreg Kroah-Hartman unsigned int sts; 746f1f836e4SAlexander Stein unsigned int sts2; 747ab4382d2SGreg Kroah-Hartman 748ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 749ab4382d2SGreg Kroah-Hartman 750b4cdc8f6SHuang Shijie if (sts & USR1_RRDY) { 751b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) 752b4cdc8f6SHuang Shijie imx_dma_rxint(sport); 753b4cdc8f6SHuang Shijie else 754ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 755b4cdc8f6SHuang Shijie } 756ab4382d2SGreg Kroah-Hartman 757ab4382d2SGreg Kroah-Hartman if (sts & USR1_TRDY && 758ab4382d2SGreg Kroah-Hartman readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 759ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 760ab4382d2SGreg Kroah-Hartman 761ab4382d2SGreg Kroah-Hartman if (sts & USR1_RTSD) 762ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 763ab4382d2SGreg Kroah-Hartman 764db1a9b55SFabio Estevam if (sts & USR1_AWAKE) 765db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 766db1a9b55SFabio Estevam 767f1f836e4SAlexander Stein sts2 = readl(sport->port.membase + USR2); 768f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 769f1f836e4SAlexander Stein dev_err(sport->port.dev, "Rx FIFO overrun\n"); 770f1f836e4SAlexander Stein sport->port.icount.overrun++; 771f1f836e4SAlexander Stein writel(sts2 | USR2_ORE, sport->port.membase + USR2); 772f1f836e4SAlexander Stein } 773f1f836e4SAlexander Stein 774ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 775ab4382d2SGreg Kroah-Hartman } 776ab4382d2SGreg Kroah-Hartman 777ab4382d2SGreg Kroah-Hartman /* 778ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 779ab4382d2SGreg Kroah-Hartman */ 780ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 781ab4382d2SGreg Kroah-Hartman { 782ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 7831ce43e58SHuang Shijie unsigned int ret; 784ab4382d2SGreg Kroah-Hartman 7851ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 7861ce43e58SHuang Shijie 7871ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 7881ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 7891ce43e58SHuang Shijie ret = 0; 7901ce43e58SHuang Shijie 7911ce43e58SHuang Shijie return ret; 792ab4382d2SGreg Kroah-Hartman } 793ab4382d2SGreg Kroah-Hartman 794ab4382d2SGreg Kroah-Hartman /* 795ab4382d2SGreg Kroah-Hartman * We have a modem side uart, so the meanings of RTS and CTS are inverted. 796ab4382d2SGreg Kroah-Hartman */ 797ab4382d2SGreg Kroah-Hartman static unsigned int imx_get_mctrl(struct uart_port *port) 798ab4382d2SGreg Kroah-Hartman { 799ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 800ab4382d2SGreg Kroah-Hartman unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 801ab4382d2SGreg Kroah-Hartman 802ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR1) & USR1_RTSS) 803ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_CTS; 804ab4382d2SGreg Kroah-Hartman 805ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR2) & UCR2_CTS) 806ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_RTS; 807ab4382d2SGreg Kroah-Hartman 8086b471a98SHuang Shijie if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 8096b471a98SHuang Shijie tmp |= TIOCM_LOOP; 8106b471a98SHuang Shijie 811ab4382d2SGreg Kroah-Hartman return tmp; 812ab4382d2SGreg Kroah-Hartman } 813ab4382d2SGreg Kroah-Hartman 814ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 815ab4382d2SGreg Kroah-Hartman { 816ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 817ab4382d2SGreg Kroah-Hartman unsigned long temp; 818ab4382d2SGreg Kroah-Hartman 819ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; 820ab4382d2SGreg Kroah-Hartman 821ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 822b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) 823ab4382d2SGreg Kroah-Hartman temp |= UCR2_CTS; 824ab4382d2SGreg Kroah-Hartman 825ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 8266b471a98SHuang Shijie 8276b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8286b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8296b471a98SHuang Shijie temp |= UTS_LOOP; 8306b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 831ab4382d2SGreg Kroah-Hartman } 832ab4382d2SGreg Kroah-Hartman 833ab4382d2SGreg Kroah-Hartman /* 834ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 835ab4382d2SGreg Kroah-Hartman */ 836ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 837ab4382d2SGreg Kroah-Hartman { 838ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 839ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 840ab4382d2SGreg Kroah-Hartman 841ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 842ab4382d2SGreg Kroah-Hartman 843ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 844ab4382d2SGreg Kroah-Hartman 845ab4382d2SGreg Kroah-Hartman if (break_state != 0) 846ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 847ab4382d2SGreg Kroah-Hartman 848ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 849ab4382d2SGreg Kroah-Hartman 850ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 851ab4382d2SGreg Kroah-Hartman } 852ab4382d2SGreg Kroah-Hartman 853ab4382d2SGreg Kroah-Hartman #define TXTL 2 /* reset default */ 854ab4382d2SGreg Kroah-Hartman #define RXTL 1 /* reset default */ 855ab4382d2SGreg Kroah-Hartman 856ab4382d2SGreg Kroah-Hartman static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 857ab4382d2SGreg Kroah-Hartman { 858ab4382d2SGreg Kroah-Hartman unsigned int val; 859ab4382d2SGreg Kroah-Hartman 8607be0670fSDirk Behme /* set receiver / transmitter trigger level */ 8617be0670fSDirk Behme val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 8627be0670fSDirk Behme val |= TXTL << UFCR_TXTL_SHF | RXTL; 863ab4382d2SGreg Kroah-Hartman writel(val, sport->port.membase + UFCR); 864ab4382d2SGreg Kroah-Hartman return 0; 865ab4382d2SGreg Kroah-Hartman } 866ab4382d2SGreg Kroah-Hartman 867b4cdc8f6SHuang Shijie #define RX_BUF_SIZE (PAGE_SIZE) 868b4cdc8f6SHuang Shijie static void imx_rx_dma_done(struct imx_port *sport) 869b4cdc8f6SHuang Shijie { 870b4cdc8f6SHuang Shijie unsigned long temp; 871b4cdc8f6SHuang Shijie 872b4cdc8f6SHuang Shijie /* Enable this interrupt when the RXFIFO is empty. */ 873b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 874b4cdc8f6SHuang Shijie temp |= UCR1_RRDYEN; 875b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 876b4cdc8f6SHuang Shijie 877b4cdc8f6SHuang Shijie sport->dma_is_rxing = 0; 878b4cdc8f6SHuang Shijie 879b4cdc8f6SHuang Shijie /* Is the shutdown waiting for us? */ 880b4cdc8f6SHuang Shijie if (waitqueue_active(&sport->dma_wait)) 881b4cdc8f6SHuang Shijie wake_up(&sport->dma_wait); 882b4cdc8f6SHuang Shijie } 883b4cdc8f6SHuang Shijie 884b4cdc8f6SHuang Shijie /* 885b4cdc8f6SHuang Shijie * There are three kinds of RX DMA interrupts(such as in the MX6Q): 886b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 887b4cdc8f6SHuang Shijie * [2] the Aging timer expires(wait for 8 bytes long) 888b4cdc8f6SHuang Shijie * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 889b4cdc8f6SHuang Shijie * 890b4cdc8f6SHuang Shijie * The [2] is trigger when a character was been sitting in the FIFO 891b4cdc8f6SHuang Shijie * meanwhile [3] can wait for 32 bytes long when the RX line is 892b4cdc8f6SHuang Shijie * on IDLE state and RxFIFO is empty. 893b4cdc8f6SHuang Shijie */ 894b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 895b4cdc8f6SHuang Shijie { 896b4cdc8f6SHuang Shijie struct imx_port *sport = data; 897b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 898b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 8997cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 900b4cdc8f6SHuang Shijie struct dma_tx_state state; 901b4cdc8f6SHuang Shijie enum dma_status status; 902b4cdc8f6SHuang Shijie unsigned int count; 903b4cdc8f6SHuang Shijie 904b4cdc8f6SHuang Shijie /* unmap it first */ 905b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 906b4cdc8f6SHuang Shijie 907f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 908b4cdc8f6SHuang Shijie count = RX_BUF_SIZE - state.residue; 909b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 910b4cdc8f6SHuang Shijie 911b4cdc8f6SHuang Shijie if (count) { 9127cb92fd2SHuang Shijie tty_insert_flip_string(port, sport->rx_buf, count); 9137cb92fd2SHuang Shijie tty_flip_buffer_push(port); 9147cb92fd2SHuang Shijie 9157cb92fd2SHuang Shijie start_rx_dma(sport); 916b4cdc8f6SHuang Shijie } else 917b4cdc8f6SHuang Shijie imx_rx_dma_done(sport); 918b4cdc8f6SHuang Shijie } 919b4cdc8f6SHuang Shijie 920b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 921b4cdc8f6SHuang Shijie { 922b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 923b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 924b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 925b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 926b4cdc8f6SHuang Shijie int ret; 927b4cdc8f6SHuang Shijie 928b4cdc8f6SHuang Shijie sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 929b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 930b4cdc8f6SHuang Shijie if (ret == 0) { 931b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 932b4cdc8f6SHuang Shijie return -EINVAL; 933b4cdc8f6SHuang Shijie } 934b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 935b4cdc8f6SHuang Shijie DMA_PREP_INTERRUPT); 936b4cdc8f6SHuang Shijie if (!desc) { 937b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 938b4cdc8f6SHuang Shijie return -EINVAL; 939b4cdc8f6SHuang Shijie } 940b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 941b4cdc8f6SHuang Shijie desc->callback_param = sport; 942b4cdc8f6SHuang Shijie 943b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 944b4cdc8f6SHuang Shijie dmaengine_submit(desc); 945b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 946b4cdc8f6SHuang Shijie return 0; 947b4cdc8f6SHuang Shijie } 948b4cdc8f6SHuang Shijie 949b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 950b4cdc8f6SHuang Shijie { 951b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 952b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 953b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 954b4cdc8f6SHuang Shijie 955b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 956b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 957b4cdc8f6SHuang Shijie } 958b4cdc8f6SHuang Shijie 959b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 960b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 961b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 962b4cdc8f6SHuang Shijie } 963b4cdc8f6SHuang Shijie 964b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 965b4cdc8f6SHuang Shijie } 966b4cdc8f6SHuang Shijie 967b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 968b4cdc8f6SHuang Shijie { 969b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 970b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 971b4cdc8f6SHuang Shijie int ret; 972b4cdc8f6SHuang Shijie 973b4cdc8f6SHuang Shijie /* Prepare for RX : */ 974b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 975b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 976b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 977b4cdc8f6SHuang Shijie ret = -EINVAL; 978b4cdc8f6SHuang Shijie goto err; 979b4cdc8f6SHuang Shijie } 980b4cdc8f6SHuang Shijie 981b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 982b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 983b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 984b4cdc8f6SHuang Shijie slave_config.src_maxburst = RXTL; 985b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 986b4cdc8f6SHuang Shijie if (ret) { 987b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 988b4cdc8f6SHuang Shijie goto err; 989b4cdc8f6SHuang Shijie } 990b4cdc8f6SHuang Shijie 991b4cdc8f6SHuang Shijie sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 992b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 993b4cdc8f6SHuang Shijie dev_err(dev, "cannot alloc DMA buffer.\n"); 994b4cdc8f6SHuang Shijie ret = -ENOMEM; 995b4cdc8f6SHuang Shijie goto err; 996b4cdc8f6SHuang Shijie } 997b4cdc8f6SHuang Shijie 998b4cdc8f6SHuang Shijie /* Prepare for TX : */ 999b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1000b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1001b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1002b4cdc8f6SHuang Shijie ret = -EINVAL; 1003b4cdc8f6SHuang Shijie goto err; 1004b4cdc8f6SHuang Shijie } 1005b4cdc8f6SHuang Shijie 1006b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1007b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1008b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1009b4cdc8f6SHuang Shijie slave_config.dst_maxburst = TXTL; 1010b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1011b4cdc8f6SHuang Shijie if (ret) { 1012b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1013b4cdc8f6SHuang Shijie goto err; 1014b4cdc8f6SHuang Shijie } 1015b4cdc8f6SHuang Shijie 1016b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1017b4cdc8f6SHuang Shijie 1018b4cdc8f6SHuang Shijie return 0; 1019b4cdc8f6SHuang Shijie err: 1020b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1021b4cdc8f6SHuang Shijie return ret; 1022b4cdc8f6SHuang Shijie } 1023b4cdc8f6SHuang Shijie 1024b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1025b4cdc8f6SHuang Shijie { 1026b4cdc8f6SHuang Shijie unsigned long temp; 1027b4cdc8f6SHuang Shijie 1028b4cdc8f6SHuang Shijie init_waitqueue_head(&sport->dma_wait); 1029b4cdc8f6SHuang Shijie 1030b4cdc8f6SHuang Shijie /* set UCR1 */ 1031b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1032b4cdc8f6SHuang Shijie temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1033b4cdc8f6SHuang Shijie /* wait for 32 idle frames for IDDMA interrupt */ 1034b4cdc8f6SHuang Shijie UCR1_ICD_REG(3); 1035b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1036b4cdc8f6SHuang Shijie 1037b4cdc8f6SHuang Shijie /* set UCR4 */ 1038b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1039b4cdc8f6SHuang Shijie temp |= UCR4_IDDMAEN; 1040b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1041b4cdc8f6SHuang Shijie 1042b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1043b4cdc8f6SHuang Shijie } 1044b4cdc8f6SHuang Shijie 1045b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1046b4cdc8f6SHuang Shijie { 1047b4cdc8f6SHuang Shijie unsigned long temp; 1048b4cdc8f6SHuang Shijie 1049b4cdc8f6SHuang Shijie /* clear UCR1 */ 1050b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1051b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1052b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1053b4cdc8f6SHuang Shijie 1054b4cdc8f6SHuang Shijie /* clear UCR2 */ 1055b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 1056b4cdc8f6SHuang Shijie temp &= ~(UCR2_CTSC | UCR2_CTS); 1057b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1058b4cdc8f6SHuang Shijie 1059b4cdc8f6SHuang Shijie /* clear UCR4 */ 1060b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1061b4cdc8f6SHuang Shijie temp &= ~UCR4_IDDMAEN; 1062b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1063b4cdc8f6SHuang Shijie 1064b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1065b4cdc8f6SHuang Shijie } 1066b4cdc8f6SHuang Shijie 1067ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1068ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1069ab4382d2SGreg Kroah-Hartman 1070ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1071ab4382d2SGreg Kroah-Hartman { 1072ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1073ab4382d2SGreg Kroah-Hartman int retval; 1074ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1075ab4382d2SGreg Kroah-Hartman 107628eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 107728eb4274SHuang Shijie if (retval) 107828eb4274SHuang Shijie goto error_out1; 107928eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 10800c375501SHuang Shijie if (retval) { 10810c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 108228eb4274SHuang Shijie goto error_out1; 10830c375501SHuang Shijie } 108428eb4274SHuang Shijie 1085ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1086ab4382d2SGreg Kroah-Hartman 1087ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1088ab4382d2SGreg Kroah-Hartman * requesting IRQs 1089ab4382d2SGreg Kroah-Hartman */ 1090ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1091ab4382d2SGreg Kroah-Hartman 1092ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1093ab4382d2SGreg Kroah-Hartman temp |= UCR4_IRSC; 1094ab4382d2SGreg Kroah-Hartman 1095ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1096ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1097ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1098ab4382d2SGreg Kroah-Hartman 1099ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1100ab4382d2SGreg Kroah-Hartman 1101ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1102ab4382d2SGreg Kroah-Hartman /* reset fifo's and state machines */ 1103ab4382d2SGreg Kroah-Hartman int i = 100; 1104ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1105ab4382d2SGreg Kroah-Hartman temp &= ~UCR2_SRST; 1106ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1107ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && 1108ab4382d2SGreg Kroah-Hartman (--i > 0)) { 1109ab4382d2SGreg Kroah-Hartman udelay(1); 1110ab4382d2SGreg Kroah-Hartman } 1111ab4382d2SGreg Kroah-Hartman } 1112ab4382d2SGreg Kroah-Hartman 1113ab4382d2SGreg Kroah-Hartman /* 1114ab4382d2SGreg Kroah-Hartman * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 1115ab4382d2SGreg Kroah-Hartman * chips only have one interrupt. 1116ab4382d2SGreg Kroah-Hartman */ 1117ab4382d2SGreg Kroah-Hartman if (sport->txirq > 0) { 1118ab4382d2SGreg Kroah-Hartman retval = request_irq(sport->rxirq, imx_rxint, 0, 1119*436e4ab5SAlexander Shiyan dev_name(port->dev), sport); 1120ab4382d2SGreg Kroah-Hartman if (retval) 1121ab4382d2SGreg Kroah-Hartman goto error_out1; 1122ab4382d2SGreg Kroah-Hartman 1123ab4382d2SGreg Kroah-Hartman retval = request_irq(sport->txirq, imx_txint, 0, 1124*436e4ab5SAlexander Shiyan dev_name(port->dev), sport); 1125ab4382d2SGreg Kroah-Hartman if (retval) 1126ab4382d2SGreg Kroah-Hartman goto error_out2; 1127ab4382d2SGreg Kroah-Hartman 1128ab4382d2SGreg Kroah-Hartman /* do not use RTS IRQ on IrDA */ 1129ab4382d2SGreg Kroah-Hartman if (!USE_IRDA(sport)) { 11301ee8f65bSShawn Guo retval = request_irq(sport->rtsirq, imx_rtsint, 0, 1131*436e4ab5SAlexander Shiyan dev_name(port->dev), sport); 1132ab4382d2SGreg Kroah-Hartman if (retval) 1133ab4382d2SGreg Kroah-Hartman goto error_out3; 1134ab4382d2SGreg Kroah-Hartman } 1135ab4382d2SGreg Kroah-Hartman } else { 1136ab4382d2SGreg Kroah-Hartman retval = request_irq(sport->port.irq, imx_int, 0, 1137*436e4ab5SAlexander Shiyan dev_name(port->dev), sport); 1138ab4382d2SGreg Kroah-Hartman if (retval) { 1139ab4382d2SGreg Kroah-Hartman free_irq(sport->port.irq, sport); 1140ab4382d2SGreg Kroah-Hartman goto error_out1; 1141ab4382d2SGreg Kroah-Hartman } 1142ab4382d2SGreg Kroah-Hartman } 1143ab4382d2SGreg Kroah-Hartman 11449ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1145ab4382d2SGreg Kroah-Hartman /* 1146ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1147ab4382d2SGreg Kroah-Hartman */ 1148ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 1149ab4382d2SGreg Kroah-Hartman 1150ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1151ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1152ab4382d2SGreg Kroah-Hartman 1153ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1154ab4382d2SGreg Kroah-Hartman temp |= UCR1_IREN; 1155ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RTSDEN); 1156ab4382d2SGreg Kroah-Hartman } 1157ab4382d2SGreg Kroah-Hartman 1158ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1159ab4382d2SGreg Kroah-Hartman 1160ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1161ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1162bff09b09SLucas Stach if (!sport->have_rtscts) 1163bff09b09SLucas Stach temp |= UCR2_IRTS; 1164ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1165ab4382d2SGreg Kroah-Hartman 1166ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1167ab4382d2SGreg Kroah-Hartman /* clear RX-FIFO */ 1168ab4382d2SGreg Kroah-Hartman int i = 64; 1169ab4382d2SGreg Kroah-Hartman while ((--i > 0) && 1170ab4382d2SGreg Kroah-Hartman (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { 1171ab4382d2SGreg Kroah-Hartman barrier(); 1172ab4382d2SGreg Kroah-Hartman } 1173ab4382d2SGreg Kroah-Hartman } 1174ab4382d2SGreg Kroah-Hartman 1175a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1176ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1177fe6b540aSShawn Guo temp |= IMX21_UCR3_RXDMUXSEL; 1178ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1179ab4382d2SGreg Kroah-Hartman } 1180ab4382d2SGreg Kroah-Hartman 1181ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1182ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1183ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_rx) 1184ab4382d2SGreg Kroah-Hartman temp |= UCR4_INVR; 1185ab4382d2SGreg Kroah-Hartman else 1186ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_INVR); 1187ab4382d2SGreg Kroah-Hartman writel(temp | UCR4_DREN, sport->port.membase + UCR4); 1188ab4382d2SGreg Kroah-Hartman 1189ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1190ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_tx) 1191ab4382d2SGreg Kroah-Hartman temp |= UCR3_INVT; 1192ab4382d2SGreg Kroah-Hartman else 1193ab4382d2SGreg Kroah-Hartman temp &= ~(UCR3_INVT); 1194ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1195ab4382d2SGreg Kroah-Hartman } 1196ab4382d2SGreg Kroah-Hartman 1197ab4382d2SGreg Kroah-Hartman /* 1198ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1199ab4382d2SGreg Kroah-Hartman */ 1200ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1201ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1202ab4382d2SGreg Kroah-Hartman 1203ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1204ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1205574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1206ab4382d2SGreg Kroah-Hartman sport->irda_inv_rx = pdata->irda_inv_rx; 1207ab4382d2SGreg Kroah-Hartman sport->irda_inv_tx = pdata->irda_inv_tx; 1208ab4382d2SGreg Kroah-Hartman sport->trcv_delay = pdata->transceiver_delay; 1209ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1210ab4382d2SGreg Kroah-Hartman pdata->irda_enable(1); 1211ab4382d2SGreg Kroah-Hartman } 1212ab4382d2SGreg Kroah-Hartman 1213ab4382d2SGreg Kroah-Hartman return 0; 1214ab4382d2SGreg Kroah-Hartman 1215ab4382d2SGreg Kroah-Hartman error_out3: 1216ab4382d2SGreg Kroah-Hartman if (sport->txirq) 1217ab4382d2SGreg Kroah-Hartman free_irq(sport->txirq, sport); 1218ab4382d2SGreg Kroah-Hartman error_out2: 1219ab4382d2SGreg Kroah-Hartman if (sport->rxirq) 1220ab4382d2SGreg Kroah-Hartman free_irq(sport->rxirq, sport); 1221ab4382d2SGreg Kroah-Hartman error_out1: 1222ab4382d2SGreg Kroah-Hartman return retval; 1223ab4382d2SGreg Kroah-Hartman } 1224ab4382d2SGreg Kroah-Hartman 1225ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1226ab4382d2SGreg Kroah-Hartman { 1227ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1228ab4382d2SGreg Kroah-Hartman unsigned long temp; 12299ec1882dSXinyu Chen unsigned long flags; 1230ab4382d2SGreg Kroah-Hartman 1231b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1232b4cdc8f6SHuang Shijie /* We have to wait for the DMA to finish. */ 1233b4cdc8f6SHuang Shijie wait_event(sport->dma_wait, 1234b4cdc8f6SHuang Shijie !sport->dma_is_rxing && !sport->dma_is_txing); 1235b4cdc8f6SHuang Shijie imx_stop_rx(port); 1236b4cdc8f6SHuang Shijie imx_disable_dma(sport); 1237b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1238b4cdc8f6SHuang Shijie } 1239b4cdc8f6SHuang Shijie 12409ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1241ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1242ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1243ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 12449ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1245ab4382d2SGreg Kroah-Hartman 1246ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1247ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1248574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1249ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1250ab4382d2SGreg Kroah-Hartman pdata->irda_enable(0); 1251ab4382d2SGreg Kroah-Hartman } 1252ab4382d2SGreg Kroah-Hartman 1253ab4382d2SGreg Kroah-Hartman /* 1254ab4382d2SGreg Kroah-Hartman * Stop our timer. 1255ab4382d2SGreg Kroah-Hartman */ 1256ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1257ab4382d2SGreg Kroah-Hartman 1258ab4382d2SGreg Kroah-Hartman /* 1259ab4382d2SGreg Kroah-Hartman * Free the interrupts 1260ab4382d2SGreg Kroah-Hartman */ 1261ab4382d2SGreg Kroah-Hartman if (sport->txirq > 0) { 1262ab4382d2SGreg Kroah-Hartman if (!USE_IRDA(sport)) 1263ab4382d2SGreg Kroah-Hartman free_irq(sport->rtsirq, sport); 1264ab4382d2SGreg Kroah-Hartman free_irq(sport->txirq, sport); 1265ab4382d2SGreg Kroah-Hartman free_irq(sport->rxirq, sport); 1266ab4382d2SGreg Kroah-Hartman } else 1267ab4382d2SGreg Kroah-Hartman free_irq(sport->port.irq, sport); 1268ab4382d2SGreg Kroah-Hartman 1269ab4382d2SGreg Kroah-Hartman /* 1270ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1271ab4382d2SGreg Kroah-Hartman */ 1272ab4382d2SGreg Kroah-Hartman 12739ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1274ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1275ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1276ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1277ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_IREN); 1278ab4382d2SGreg Kroah-Hartman 1279ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 12809ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 128128eb4274SHuang Shijie 128228eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 128328eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1284ab4382d2SGreg Kroah-Hartman } 1285ab4382d2SGreg Kroah-Hartman 1286eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1287eb56b7edSHuang Shijie { 1288eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 1289eb56b7edSHuang Shijie 1290eb56b7edSHuang Shijie if (sport->dma_is_enabled) { 1291eb56b7edSHuang Shijie sport->tx_bytes = 0; 1292eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 1293eb56b7edSHuang Shijie } 1294eb56b7edSHuang Shijie } 1295eb56b7edSHuang Shijie 1296ab4382d2SGreg Kroah-Hartman static void 1297ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1298ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1299ab4382d2SGreg Kroah-Hartman { 1300ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1301ab4382d2SGreg Kroah-Hartman unsigned long flags; 1302ab4382d2SGreg Kroah-Hartman unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1303ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1304ab4382d2SGreg Kroah-Hartman unsigned int div, ufcr; 1305ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1306ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1307ab4382d2SGreg Kroah-Hartman 1308ab4382d2SGreg Kroah-Hartman /* 1309ab4382d2SGreg Kroah-Hartman * If we don't support modem control lines, don't allow 1310ab4382d2SGreg Kroah-Hartman * these to be set. 1311ab4382d2SGreg Kroah-Hartman */ 1312ab4382d2SGreg Kroah-Hartman if (0) { 1313ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 1314ab4382d2SGreg Kroah-Hartman termios->c_cflag |= CLOCAL; 1315ab4382d2SGreg Kroah-Hartman } 1316ab4382d2SGreg Kroah-Hartman 1317ab4382d2SGreg Kroah-Hartman /* 1318ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1319ab4382d2SGreg Kroah-Hartman */ 1320ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1321ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1322ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1323ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1324ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1325ab4382d2SGreg Kroah-Hartman } 1326ab4382d2SGreg Kroah-Hartman 1327ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1328ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1329ab4382d2SGreg Kroah-Hartman else 1330ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1331ab4382d2SGreg Kroah-Hartman 1332ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1333ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1334ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 1335ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_CTSC; 1336b4cdc8f6SHuang Shijie 1337b4cdc8f6SHuang Shijie /* Can we enable the DMA support? */ 1338b4cdc8f6SHuang Shijie if (is_imx6q_uart(sport) && !uart_console(port) 1339b4cdc8f6SHuang Shijie && !sport->dma_is_inited) 1340b4cdc8f6SHuang Shijie imx_uart_dma_init(sport); 1341ab4382d2SGreg Kroah-Hartman } else { 1342ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1343ab4382d2SGreg Kroah-Hartman } 1344ab4382d2SGreg Kroah-Hartman } 1345ab4382d2SGreg Kroah-Hartman 1346ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1347ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1348ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1349ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1350ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1351ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1352ab4382d2SGreg Kroah-Hartman } 1353ab4382d2SGreg Kroah-Hartman 1354995234daSEric Miao del_timer_sync(&sport->timer); 1355995234daSEric Miao 1356ab4382d2SGreg Kroah-Hartman /* 1357ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1358ab4382d2SGreg Kroah-Hartman */ 1359ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1360ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1361ab4382d2SGreg Kroah-Hartman 1362ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1363ab4382d2SGreg Kroah-Hartman 1364ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1365ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1366ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1367ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1368ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1369ab4382d2SGreg Kroah-Hartman 1370ab4382d2SGreg Kroah-Hartman /* 1371ab4382d2SGreg Kroah-Hartman * Characters to ignore 1372ab4382d2SGreg Kroah-Hartman */ 1373ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1374ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1375ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_PRERR; 1376ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1377ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1378ab4382d2SGreg Kroah-Hartman /* 1379ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1380ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1381ab4382d2SGreg Kroah-Hartman */ 1382ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1383ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1384ab4382d2SGreg Kroah-Hartman } 1385ab4382d2SGreg Kroah-Hartman 1386ab4382d2SGreg Kroah-Hartman /* 1387ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1388ab4382d2SGreg Kroah-Hartman */ 1389ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1390ab4382d2SGreg Kroah-Hartman 1391ab4382d2SGreg Kroah-Hartman /* 1392ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1393ab4382d2SGreg Kroah-Hartman */ 1394ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1395ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1396ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1397ab4382d2SGreg Kroah-Hartman 1398ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1399ab4382d2SGreg Kroah-Hartman barrier(); 1400ab4382d2SGreg Kroah-Hartman 1401ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 1402ab4382d2SGreg Kroah-Hartman old_txrxen = readl(sport->port.membase + UCR2); 1403ab4382d2SGreg Kroah-Hartman writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1404ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 1405ab4382d2SGreg Kroah-Hartman old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1406ab4382d2SGreg Kroah-Hartman 1407ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1408ab4382d2SGreg Kroah-Hartman /* 1409ab4382d2SGreg Kroah-Hartman * use maximum available submodule frequency to 1410ab4382d2SGreg Kroah-Hartman * avoid missing short pulses due to low sampling rate 1411ab4382d2SGreg Kroah-Hartman */ 1412ab4382d2SGreg Kroah-Hartman div = 1; 1413ab4382d2SGreg Kroah-Hartman } else { 141409bd00f6SHubert Feurstein /* custom-baudrate handling */ 141509bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 141609bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 141709bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 141809bd00f6SHubert Feurstein 1419ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1420ab4382d2SGreg Kroah-Hartman if (div > 7) 1421ab4382d2SGreg Kroah-Hartman div = 7; 1422ab4382d2SGreg Kroah-Hartman if (!div) 1423ab4382d2SGreg Kroah-Hartman div = 1; 1424ab4382d2SGreg Kroah-Hartman } 1425ab4382d2SGreg Kroah-Hartman 1426ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1427ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1428ab4382d2SGreg Kroah-Hartman 1429ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1430ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1431ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1432ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1433ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1434ab4382d2SGreg Kroah-Hartman 1435ab4382d2SGreg Kroah-Hartman num -= 1; 1436ab4382d2SGreg Kroah-Hartman denom -= 1; 1437ab4382d2SGreg Kroah-Hartman 1438ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1439ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 144020ff2fe6SHuang Shijie if (sport->dte_mode) 144120ff2fe6SHuang Shijie ufcr |= UFCR_DCEDTE; 1442ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1443ab4382d2SGreg Kroah-Hartman 1444ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1445ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1446ab4382d2SGreg Kroah-Hartman 1447a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1448ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1449fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1450ab4382d2SGreg Kroah-Hartman 1451ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1452ab4382d2SGreg Kroah-Hartman 1453ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 1454ab4382d2SGreg Kroah-Hartman writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1455ab4382d2SGreg Kroah-Hartman 1456ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1457ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1458ab4382d2SGreg Kroah-Hartman 1459b4cdc8f6SHuang Shijie if (sport->dma_is_inited && !sport->dma_is_enabled) 1460b4cdc8f6SHuang Shijie imx_enable_dma(sport); 1461ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1462ab4382d2SGreg Kroah-Hartman } 1463ab4382d2SGreg Kroah-Hartman 1464ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1465ab4382d2SGreg Kroah-Hartman { 1466ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1467ab4382d2SGreg Kroah-Hartman 1468ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1469ab4382d2SGreg Kroah-Hartman } 1470ab4382d2SGreg Kroah-Hartman 1471ab4382d2SGreg Kroah-Hartman /* 1472ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1473ab4382d2SGreg Kroah-Hartman */ 1474ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1475ab4382d2SGreg Kroah-Hartman { 1476ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1477ab4382d2SGreg Kroah-Hartman 1478da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1479ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1480ab4382d2SGreg Kroah-Hartman } 1481ab4382d2SGreg Kroah-Hartman 1482ab4382d2SGreg Kroah-Hartman /* 1483ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1484ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1485ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1486ab4382d2SGreg Kroah-Hartman */ 1487ab4382d2SGreg Kroah-Hartman static int 1488ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1489ab4382d2SGreg Kroah-Hartman { 1490ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1491ab4382d2SGreg Kroah-Hartman int ret = 0; 1492ab4382d2SGreg Kroah-Hartman 1493ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1494ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1495ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1496ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1497ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1498ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1499ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1500ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1501a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1502ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1503ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1504ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1505ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1506ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1507ab4382d2SGreg Kroah-Hartman return ret; 1508ab4382d2SGreg Kroah-Hartman } 1509ab4382d2SGreg Kroah-Hartman 151001f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 151101f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 151201f56abdSSaleem Abdulrasool { 151301f56abdSSaleem Abdulrasool struct imx_port_ucrs old_ucr; 151401f56abdSSaleem Abdulrasool unsigned int status; 151501f56abdSSaleem Abdulrasool unsigned char c; 151601f56abdSSaleem Abdulrasool 151701f56abdSSaleem Abdulrasool /* save control registers */ 151801f56abdSSaleem Abdulrasool imx_port_ucrs_save(port, &old_ucr); 151901f56abdSSaleem Abdulrasool 152001f56abdSSaleem Abdulrasool /* disable interrupts */ 152101f56abdSSaleem Abdulrasool writel(UCR1_UARTEN, port->membase + UCR1); 152201f56abdSSaleem Abdulrasool writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 152301f56abdSSaleem Abdulrasool port->membase + UCR2); 152401f56abdSSaleem Abdulrasool writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 152501f56abdSSaleem Abdulrasool port->membase + UCR3); 152601f56abdSSaleem Abdulrasool 152701f56abdSSaleem Abdulrasool /* poll */ 152801f56abdSSaleem Abdulrasool do { 152901f56abdSSaleem Abdulrasool status = readl(port->membase + USR2); 153001f56abdSSaleem Abdulrasool } while (~status & USR2_RDR); 153101f56abdSSaleem Abdulrasool 153201f56abdSSaleem Abdulrasool /* read */ 153301f56abdSSaleem Abdulrasool c = readl(port->membase + URXD0); 153401f56abdSSaleem Abdulrasool 153501f56abdSSaleem Abdulrasool /* restore control registers */ 153601f56abdSSaleem Abdulrasool imx_port_ucrs_restore(port, &old_ucr); 153701f56abdSSaleem Abdulrasool 153801f56abdSSaleem Abdulrasool return c; 153901f56abdSSaleem Abdulrasool } 154001f56abdSSaleem Abdulrasool 154101f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 154201f56abdSSaleem Abdulrasool { 154301f56abdSSaleem Abdulrasool struct imx_port_ucrs old_ucr; 154401f56abdSSaleem Abdulrasool unsigned int status; 154501f56abdSSaleem Abdulrasool 154601f56abdSSaleem Abdulrasool /* save control registers */ 154701f56abdSSaleem Abdulrasool imx_port_ucrs_save(port, &old_ucr); 154801f56abdSSaleem Abdulrasool 154901f56abdSSaleem Abdulrasool /* disable interrupts */ 155001f56abdSSaleem Abdulrasool writel(UCR1_UARTEN, port->membase + UCR1); 155101f56abdSSaleem Abdulrasool writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 155201f56abdSSaleem Abdulrasool port->membase + UCR2); 155301f56abdSSaleem Abdulrasool writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 155401f56abdSSaleem Abdulrasool port->membase + UCR3); 155501f56abdSSaleem Abdulrasool 155601f56abdSSaleem Abdulrasool /* drain */ 155701f56abdSSaleem Abdulrasool do { 155801f56abdSSaleem Abdulrasool status = readl(port->membase + USR1); 155901f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 156001f56abdSSaleem Abdulrasool 156101f56abdSSaleem Abdulrasool /* write */ 156201f56abdSSaleem Abdulrasool writel(c, port->membase + URTX0); 156301f56abdSSaleem Abdulrasool 156401f56abdSSaleem Abdulrasool /* flush */ 156501f56abdSSaleem Abdulrasool do { 156601f56abdSSaleem Abdulrasool status = readl(port->membase + USR2); 156701f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 156801f56abdSSaleem Abdulrasool 156901f56abdSSaleem Abdulrasool /* restore control registers */ 157001f56abdSSaleem Abdulrasool imx_port_ucrs_restore(port, &old_ucr); 157101f56abdSSaleem Abdulrasool } 157201f56abdSSaleem Abdulrasool #endif 157301f56abdSSaleem Abdulrasool 1574ab4382d2SGreg Kroah-Hartman static struct uart_ops imx_pops = { 1575ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1576ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1577ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1578ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1579ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1580ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1581ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1582ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1583ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1584ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1585eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1586ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1587ab4382d2SGreg Kroah-Hartman .type = imx_type, 1588ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1589ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 159001f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 159101f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 159201f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 159301f56abdSSaleem Abdulrasool #endif 1594ab4382d2SGreg Kroah-Hartman }; 1595ab4382d2SGreg Kroah-Hartman 1596ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1597ab4382d2SGreg Kroah-Hartman 1598ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1599ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1600ab4382d2SGreg Kroah-Hartman { 1601ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1602ab4382d2SGreg Kroah-Hartman 1603fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1604ab4382d2SGreg Kroah-Hartman barrier(); 1605ab4382d2SGreg Kroah-Hartman 1606ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1607ab4382d2SGreg Kroah-Hartman } 1608ab4382d2SGreg Kroah-Hartman 1609ab4382d2SGreg Kroah-Hartman /* 1610ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1611ab4382d2SGreg Kroah-Hartman */ 1612ab4382d2SGreg Kroah-Hartman static void 1613ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1614ab4382d2SGreg Kroah-Hartman { 1615ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 16160ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 16170ad5a814SDirk Behme unsigned int ucr1; 1618f30e8260SShawn Guo unsigned long flags = 0; 1619677fe555SThomas Gleixner int locked = 1; 16201cf93e0dSHuang Shijie int retval; 16211cf93e0dSHuang Shijie 16221cf93e0dSHuang Shijie retval = clk_enable(sport->clk_per); 16231cf93e0dSHuang Shijie if (retval) 16241cf93e0dSHuang Shijie return; 16251cf93e0dSHuang Shijie retval = clk_enable(sport->clk_ipg); 16261cf93e0dSHuang Shijie if (retval) { 16271cf93e0dSHuang Shijie clk_disable(sport->clk_per); 16281cf93e0dSHuang Shijie return; 16291cf93e0dSHuang Shijie } 16309ec1882dSXinyu Chen 1631677fe555SThomas Gleixner if (sport->port.sysrq) 1632677fe555SThomas Gleixner locked = 0; 1633677fe555SThomas Gleixner else if (oops_in_progress) 1634677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1635677fe555SThomas Gleixner else 16369ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1637ab4382d2SGreg Kroah-Hartman 1638ab4382d2SGreg Kroah-Hartman /* 16390ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1640ab4382d2SGreg Kroah-Hartman */ 16410ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 16420ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1643ab4382d2SGreg Kroah-Hartman 1644fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1645fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1646ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1647ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1648ab4382d2SGreg Kroah-Hartman 1649ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1650ab4382d2SGreg Kroah-Hartman 16510ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1652ab4382d2SGreg Kroah-Hartman 1653ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1654ab4382d2SGreg Kroah-Hartman 1655ab4382d2SGreg Kroah-Hartman /* 1656ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 16570ad5a814SDirk Behme * and restore UCR1/2/3 1658ab4382d2SGreg Kroah-Hartman */ 1659ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1660ab4382d2SGreg Kroah-Hartman 16610ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 16629ec1882dSXinyu Chen 1663677fe555SThomas Gleixner if (locked) 16649ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 16651cf93e0dSHuang Shijie 16661cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 16671cf93e0dSHuang Shijie clk_disable(sport->clk_per); 1668ab4382d2SGreg Kroah-Hartman } 1669ab4382d2SGreg Kroah-Hartman 1670ab4382d2SGreg Kroah-Hartman /* 1671ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1672ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1673ab4382d2SGreg Kroah-Hartman */ 1674ab4382d2SGreg Kroah-Hartman static void __init 1675ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1676ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1677ab4382d2SGreg Kroah-Hartman { 1678ab4382d2SGreg Kroah-Hartman 1679ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1680ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1681ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1682ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1683ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1684ab4382d2SGreg Kroah-Hartman 1685ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1686ab4382d2SGreg Kroah-Hartman 1687ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1688ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1689ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1690ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1691ab4382d2SGreg Kroah-Hartman else 1692ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1693ab4382d2SGreg Kroah-Hartman } 1694ab4382d2SGreg Kroah-Hartman 1695ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1696ab4382d2SGreg Kroah-Hartman *bits = 8; 1697ab4382d2SGreg Kroah-Hartman else 1698ab4382d2SGreg Kroah-Hartman *bits = 7; 1699ab4382d2SGreg Kroah-Hartman 1700ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1701ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1702ab4382d2SGreg Kroah-Hartman 1703ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1704ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1705ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1706ab4382d2SGreg Kroah-Hartman else 1707ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1708ab4382d2SGreg Kroah-Hartman 17093a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1710ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1711ab4382d2SGreg Kroah-Hartman 1712ab4382d2SGreg Kroah-Hartman { /* 1713ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1714ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1715ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1716ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1717ab4382d2SGreg Kroah-Hartman */ 1718ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1719ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1720ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1721ab4382d2SGreg Kroah-Hartman 1722ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1723ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1724ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1725ab4382d2SGreg Kroah-Hartman } 1726ab4382d2SGreg Kroah-Hartman 1727ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 172850bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1729ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1730ab4382d2SGreg Kroah-Hartman } 1731ab4382d2SGreg Kroah-Hartman } 1732ab4382d2SGreg Kroah-Hartman 1733ab4382d2SGreg Kroah-Hartman static int __init 1734ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1735ab4382d2SGreg Kroah-Hartman { 1736ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1737ab4382d2SGreg Kroah-Hartman int baud = 9600; 1738ab4382d2SGreg Kroah-Hartman int bits = 8; 1739ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1740ab4382d2SGreg Kroah-Hartman int flow = 'n'; 17411cf93e0dSHuang Shijie int retval; 1742ab4382d2SGreg Kroah-Hartman 1743ab4382d2SGreg Kroah-Hartman /* 1744ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1745ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1746ab4382d2SGreg Kroah-Hartman * console support. 1747ab4382d2SGreg Kroah-Hartman */ 1748ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1749ab4382d2SGreg Kroah-Hartman co->index = 0; 1750ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1751ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1752ab4382d2SGreg Kroah-Hartman return -ENODEV; 1753ab4382d2SGreg Kroah-Hartman 17541cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 17551cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 17561cf93e0dSHuang Shijie if (retval) 17571cf93e0dSHuang Shijie goto error_console; 17581cf93e0dSHuang Shijie 1759ab4382d2SGreg Kroah-Hartman if (options) 1760ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1761ab4382d2SGreg Kroah-Hartman else 1762ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1763ab4382d2SGreg Kroah-Hartman 1764ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1765ab4382d2SGreg Kroah-Hartman 17661cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 17671cf93e0dSHuang Shijie 17681cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 17691cf93e0dSHuang Shijie if (retval) { 17701cf93e0dSHuang Shijie clk_unprepare(sport->clk_ipg); 17711cf93e0dSHuang Shijie goto error_console; 17721cf93e0dSHuang Shijie } 17731cf93e0dSHuang Shijie 17741cf93e0dSHuang Shijie retval = clk_prepare(sport->clk_per); 17751cf93e0dSHuang Shijie if (retval) 17761cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 17771cf93e0dSHuang Shijie 17781cf93e0dSHuang Shijie error_console: 17791cf93e0dSHuang Shijie return retval; 1780ab4382d2SGreg Kroah-Hartman } 1781ab4382d2SGreg Kroah-Hartman 1782ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1783ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1784ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1785ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1786ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1787ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1788ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1789ab4382d2SGreg Kroah-Hartman .index = -1, 1790ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1791ab4382d2SGreg Kroah-Hartman }; 1792ab4382d2SGreg Kroah-Hartman 1793ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1794ab4382d2SGreg Kroah-Hartman #else 1795ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1796ab4382d2SGreg Kroah-Hartman #endif 1797ab4382d2SGreg Kroah-Hartman 1798ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1799ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1800ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 1801ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 1802ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 1803ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 1804ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 1805ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 1806ab4382d2SGreg Kroah-Hartman }; 1807ab4382d2SGreg Kroah-Hartman 1808ab4382d2SGreg Kroah-Hartman static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1809ab4382d2SGreg Kroah-Hartman { 1810ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1811db1a9b55SFabio Estevam unsigned int val; 1812db1a9b55SFabio Estevam 1813db1a9b55SFabio Estevam /* enable wakeup from i.MX UART */ 1814db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1815db1a9b55SFabio Estevam val |= UCR3_AWAKEN; 1816db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1817ab4382d2SGreg Kroah-Hartman 1818ab4382d2SGreg Kroah-Hartman uart_suspend_port(&imx_reg, &sport->port); 1819ab4382d2SGreg Kroah-Hartman 1820ab4382d2SGreg Kroah-Hartman return 0; 1821ab4382d2SGreg Kroah-Hartman } 1822ab4382d2SGreg Kroah-Hartman 1823ab4382d2SGreg Kroah-Hartman static int serial_imx_resume(struct platform_device *dev) 1824ab4382d2SGreg Kroah-Hartman { 1825ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1826db1a9b55SFabio Estevam unsigned int val; 1827db1a9b55SFabio Estevam 1828db1a9b55SFabio Estevam /* disable wakeup from i.MX UART */ 1829db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1830db1a9b55SFabio Estevam val &= ~UCR3_AWAKEN; 1831db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1832ab4382d2SGreg Kroah-Hartman 1833ab4382d2SGreg Kroah-Hartman uart_resume_port(&imx_reg, &sport->port); 1834ab4382d2SGreg Kroah-Hartman 1835ab4382d2SGreg Kroah-Hartman return 0; 1836ab4382d2SGreg Kroah-Hartman } 1837ab4382d2SGreg Kroah-Hartman 183822698aa2SShawn Guo #ifdef CONFIG_OF 183920bb8095SUwe Kleine-König /* 184020bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 184120bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 184220bb8095SUwe Kleine-König */ 184322698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 184422698aa2SShawn Guo struct platform_device *pdev) 184522698aa2SShawn Guo { 184622698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 184722698aa2SShawn Guo const struct of_device_id *of_id = 184822698aa2SShawn Guo of_match_device(imx_uart_dt_ids, &pdev->dev); 1849ff05967aSShawn Guo int ret; 185022698aa2SShawn Guo 185122698aa2SShawn Guo if (!np) 185220bb8095SUwe Kleine-König /* no device tree device */ 185320bb8095SUwe Kleine-König return 1; 185422698aa2SShawn Guo 1855ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 1856ff05967aSShawn Guo if (ret < 0) { 1857ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1858a197a191SUwe Kleine-König return ret; 1859ff05967aSShawn Guo } 1860ff05967aSShawn Guo sport->port.line = ret; 186122698aa2SShawn Guo 186222698aa2SShawn Guo if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 186322698aa2SShawn Guo sport->have_rtscts = 1; 186422698aa2SShawn Guo 186522698aa2SShawn Guo if (of_get_property(np, "fsl,irda-mode", NULL)) 186622698aa2SShawn Guo sport->use_irda = 1; 186722698aa2SShawn Guo 186820ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 186920ff2fe6SHuang Shijie sport->dte_mode = 1; 187020ff2fe6SHuang Shijie 187122698aa2SShawn Guo sport->devdata = of_id->data; 187222698aa2SShawn Guo 187322698aa2SShawn Guo return 0; 187422698aa2SShawn Guo } 187522698aa2SShawn Guo #else 187622698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 187722698aa2SShawn Guo struct platform_device *pdev) 187822698aa2SShawn Guo { 187920bb8095SUwe Kleine-König return 1; 188022698aa2SShawn Guo } 188122698aa2SShawn Guo #endif 188222698aa2SShawn Guo 188322698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 188422698aa2SShawn Guo struct platform_device *pdev) 188522698aa2SShawn Guo { 1886574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 188722698aa2SShawn Guo 188822698aa2SShawn Guo sport->port.line = pdev->id; 188922698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 189022698aa2SShawn Guo 189122698aa2SShawn Guo if (!pdata) 189222698aa2SShawn Guo return; 189322698aa2SShawn Guo 189422698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 189522698aa2SShawn Guo sport->have_rtscts = 1; 189622698aa2SShawn Guo 189722698aa2SShawn Guo if (pdata->flags & IMXUART_IRDA) 189822698aa2SShawn Guo sport->use_irda = 1; 189922698aa2SShawn Guo } 190022698aa2SShawn Guo 1901ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 1902ab4382d2SGreg Kroah-Hartman { 1903ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1904ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1905ab4382d2SGreg Kroah-Hartman void __iomem *base; 1906ab4382d2SGreg Kroah-Hartman int ret = 0; 1907ab4382d2SGreg Kroah-Hartman struct resource *res; 1908ab4382d2SGreg Kroah-Hartman 190942d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1910ab4382d2SGreg Kroah-Hartman if (!sport) 1911ab4382d2SGreg Kroah-Hartman return -ENOMEM; 1912ab4382d2SGreg Kroah-Hartman 191322698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 191420bb8095SUwe Kleine-König if (ret > 0) 191522698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 191620bb8095SUwe Kleine-König else if (ret < 0) 191742d34191SSachin Kamat return ret; 191822698aa2SShawn Guo 1919ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1920da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 1921da82f997SAlexander Shiyan if (IS_ERR(base)) 1922da82f997SAlexander Shiyan return PTR_ERR(base); 1923ab4382d2SGreg Kroah-Hartman 1924ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 1925ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 1926ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 1927ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 1928ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 1929ab4382d2SGreg Kroah-Hartman sport->port.irq = platform_get_irq(pdev, 0); 1930ab4382d2SGreg Kroah-Hartman sport->rxirq = platform_get_irq(pdev, 0); 1931ab4382d2SGreg Kroah-Hartman sport->txirq = platform_get_irq(pdev, 1); 1932ab4382d2SGreg Kroah-Hartman sport->rtsirq = platform_get_irq(pdev, 2); 1933ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 1934ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 1935ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 1936ab4382d2SGreg Kroah-Hartman init_timer(&sport->timer); 1937ab4382d2SGreg Kroah-Hartman sport->timer.function = imx_timeout; 1938ab4382d2SGreg Kroah-Hartman sport->timer.data = (unsigned long)sport; 1939ab4382d2SGreg Kroah-Hartman 19403a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 19413a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 19423a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 1943833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 194442d34191SSachin Kamat return ret; 1945ab4382d2SGreg Kroah-Hartman } 1946ab4382d2SGreg Kroah-Hartman 19473a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 19483a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 19493a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 1950833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 195142d34191SSachin Kamat return ret; 19523a9465faSSascha Hauer } 19533a9465faSSascha Hauer 19543a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 1955ab4382d2SGreg Kroah-Hartman 195622698aa2SShawn Guo imx_ports[sport->port.line] = sport; 1957ab4382d2SGreg Kroah-Hartman 1958574de559SJingoo Han pdata = dev_get_platdata(&pdev->dev); 1959ab4382d2SGreg Kroah-Hartman if (pdata && pdata->init) { 1960ab4382d2SGreg Kroah-Hartman ret = pdata->init(pdev); 1961ab4382d2SGreg Kroah-Hartman if (ret) 19621cf93e0dSHuang Shijie return ret; 1963ab4382d2SGreg Kroah-Hartman } 1964ab4382d2SGreg Kroah-Hartman 1965ab4382d2SGreg Kroah-Hartman ret = uart_add_one_port(&imx_reg, &sport->port); 1966ab4382d2SGreg Kroah-Hartman if (ret) 1967ab4382d2SGreg Kroah-Hartman goto deinit; 19680a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 1969ab4382d2SGreg Kroah-Hartman 1970ab4382d2SGreg Kroah-Hartman return 0; 1971ab4382d2SGreg Kroah-Hartman deinit: 1972ab4382d2SGreg Kroah-Hartman if (pdata && pdata->exit) 1973ab4382d2SGreg Kroah-Hartman pdata->exit(pdev); 1974ab4382d2SGreg Kroah-Hartman return ret; 1975ab4382d2SGreg Kroah-Hartman } 1976ab4382d2SGreg Kroah-Hartman 1977ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 1978ab4382d2SGreg Kroah-Hartman { 1979ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1980ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 1981ab4382d2SGreg Kroah-Hartman 1982574de559SJingoo Han pdata = dev_get_platdata(&pdev->dev); 1983ab4382d2SGreg Kroah-Hartman 1984ab4382d2SGreg Kroah-Hartman uart_remove_one_port(&imx_reg, &sport->port); 19853a9465faSSascha Hauer 1986ab4382d2SGreg Kroah-Hartman if (pdata && pdata->exit) 1987ab4382d2SGreg Kroah-Hartman pdata->exit(pdev); 1988ab4382d2SGreg Kroah-Hartman 1989ab4382d2SGreg Kroah-Hartman return 0; 1990ab4382d2SGreg Kroah-Hartman } 1991ab4382d2SGreg Kroah-Hartman 1992ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 1993ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 1994ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 1995ab4382d2SGreg Kroah-Hartman 1996ab4382d2SGreg Kroah-Hartman .suspend = serial_imx_suspend, 1997ab4382d2SGreg Kroah-Hartman .resume = serial_imx_resume, 1998fe6b540aSShawn Guo .id_table = imx_uart_devtype, 1999ab4382d2SGreg Kroah-Hartman .driver = { 2000ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 2001ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 200222698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 2003ab4382d2SGreg Kroah-Hartman }, 2004ab4382d2SGreg Kroah-Hartman }; 2005ab4382d2SGreg Kroah-Hartman 2006ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2007ab4382d2SGreg Kroah-Hartman { 2008ab4382d2SGreg Kroah-Hartman int ret; 2009ab4382d2SGreg Kroah-Hartman 201050bbdba3SSachin Kamat pr_info("Serial: IMX driver\n"); 2011ab4382d2SGreg Kroah-Hartman 2012ab4382d2SGreg Kroah-Hartman ret = uart_register_driver(&imx_reg); 2013ab4382d2SGreg Kroah-Hartman if (ret) 2014ab4382d2SGreg Kroah-Hartman return ret; 2015ab4382d2SGreg Kroah-Hartman 2016ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2017ab4382d2SGreg Kroah-Hartman if (ret != 0) 2018ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2019ab4382d2SGreg Kroah-Hartman 2020f227824eSUwe Kleine-König return ret; 2021ab4382d2SGreg Kroah-Hartman } 2022ab4382d2SGreg Kroah-Hartman 2023ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2024ab4382d2SGreg Kroah-Hartman { 2025ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2026ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2027ab4382d2SGreg Kroah-Hartman } 2028ab4382d2SGreg Kroah-Hartman 2029ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2030ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2031ab4382d2SGreg Kroah-Hartman 2032ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2033ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2034ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2035ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2036