1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 13ab4382d2SGreg Kroah-Hartman #endif 14ab4382d2SGreg Kroah-Hartman 15ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 23ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 24ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2922698aa2SShawn Guo #include <linux/of.h> 3022698aa2SShawn Guo #include <linux/of_device.h> 31e32a9f8fSSachin Kamat #include <linux/io.h> 32b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 3582906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 36b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 37ab4382d2SGreg Kroah-Hartman 3858362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3958362d5bSUwe Kleine-König 40ab4382d2SGreg Kroah-Hartman /* Register definitions */ 41ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 42ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 43ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 44ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 45ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 46ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 47ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 48ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 49ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 50ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 51ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 52ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 53ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 54ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 55fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 56fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 57fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 58ab4382d2SGreg Kroah-Hartman 59ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6055d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 61ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 62ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 63ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 64ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 65ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 66ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6726c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6825985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 69ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 71ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 72b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 77ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 80fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 81b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9401f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 101ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 104b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 105ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10827e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 109fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 115ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 118b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1257be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 126ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 127ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 128ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 129ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 130ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 131ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 133ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 134ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13686a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13727e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 138ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 142ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 143ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14590ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14690ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14990ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 150ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 151ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 152ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 153ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 154ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 155ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 156ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 157ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 158ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 159ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 160ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 161ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 162ab4382d2SGreg Kroah-Hartman 163ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 164ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 165ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 166ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 167ab4382d2SGreg Kroah-Hartman 168ab4382d2SGreg Kroah-Hartman /* 169ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 170ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 171ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 172ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 173ab4382d2SGreg Kroah-Hartman */ 174ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 175ab4382d2SGreg Kroah-Hartman 176ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 177ab4382d2SGreg Kroah-Hartman 178ab4382d2SGreg Kroah-Hartman #define UART_NR 8 179ab4382d2SGreg Kroah-Hartman 180f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 181fe6b540aSShawn Guo enum imx_uart_type { 182fe6b540aSShawn Guo IMX1_UART, 183fe6b540aSShawn Guo IMX21_UART, 1841c06bde6SMartyn Welch IMX53_UART, 185a496e628SHuang Shijie IMX6Q_UART, 186fe6b540aSShawn Guo }; 187fe6b540aSShawn Guo 188fe6b540aSShawn Guo /* device type dependent stuff */ 189fe6b540aSShawn Guo struct imx_uart_data { 190fe6b540aSShawn Guo unsigned uts_reg; 191fe6b540aSShawn Guo enum imx_uart_type devtype; 192fe6b540aSShawn Guo }; 193fe6b540aSShawn Guo 194ab4382d2SGreg Kroah-Hartman struct imx_port { 195ab4382d2SGreg Kroah-Hartman struct uart_port port; 196ab4382d2SGreg Kroah-Hartman struct timer_list timer; 197ab4382d2SGreg Kroah-Hartman unsigned int old_status; 198ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 1997b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20020ff2fe6SHuang Shijie unsigned int dte_mode:1; 2013a9465faSSascha Hauer struct clk *clk_ipg; 2023a9465faSSascha Hauer struct clk *clk_per; 2037d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 204b4cdc8f6SHuang Shijie 20558362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 20658362d5bSUwe Kleine-König 207b4cdc8f6SHuang Shijie /* DMA fields */ 208b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 209b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 210b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 211b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 212b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 213b4cdc8f6SHuang Shijie void *rx_buf; 2149d297239SNandor Han struct circ_buf rx_ring; 2159d297239SNandor Han unsigned int rx_periods; 2169d297239SNandor Han dma_cookie_t rx_cookie; 2177cb92fd2SHuang Shijie unsigned int tx_bytes; 218b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 21990bb6bd3SShenwei Wang unsigned int saved_reg[10]; 220c868cbb7SEduardo Valentin bool context_saved; 221ab4382d2SGreg Kroah-Hartman }; 222ab4382d2SGreg Kroah-Hartman 2230ad5a814SDirk Behme struct imx_port_ucrs { 2240ad5a814SDirk Behme unsigned int ucr1; 2250ad5a814SDirk Behme unsigned int ucr2; 2260ad5a814SDirk Behme unsigned int ucr3; 2270ad5a814SDirk Behme }; 2280ad5a814SDirk Behme 229fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 230fe6b540aSShawn Guo [IMX1_UART] = { 231fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 232fe6b540aSShawn Guo .devtype = IMX1_UART, 233fe6b540aSShawn Guo }, 234fe6b540aSShawn Guo [IMX21_UART] = { 235fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 236fe6b540aSShawn Guo .devtype = IMX21_UART, 237fe6b540aSShawn Guo }, 2381c06bde6SMartyn Welch [IMX53_UART] = { 2391c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2401c06bde6SMartyn Welch .devtype = IMX53_UART, 2411c06bde6SMartyn Welch }, 242a496e628SHuang Shijie [IMX6Q_UART] = { 243a496e628SHuang Shijie .uts_reg = IMX21_UTS, 244a496e628SHuang Shijie .devtype = IMX6Q_UART, 245a496e628SHuang Shijie }, 246fe6b540aSShawn Guo }; 247fe6b540aSShawn Guo 24831ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 249fe6b540aSShawn Guo { 250fe6b540aSShawn Guo .name = "imx1-uart", 251fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 252fe6b540aSShawn Guo }, { 253fe6b540aSShawn Guo .name = "imx21-uart", 254fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 255fe6b540aSShawn Guo }, { 2561c06bde6SMartyn Welch .name = "imx53-uart", 2571c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2581c06bde6SMartyn Welch }, { 259a496e628SHuang Shijie .name = "imx6q-uart", 260a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 261a496e628SHuang Shijie }, { 262fe6b540aSShawn Guo /* sentinel */ 263fe6b540aSShawn Guo } 264fe6b540aSShawn Guo }; 265fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 266fe6b540aSShawn Guo 267ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 268a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2691c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27022698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27122698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27222698aa2SShawn Guo { /* sentinel */ } 27322698aa2SShawn Guo }; 27422698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27522698aa2SShawn Guo 276fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 277fe6b540aSShawn Guo { 278fe6b540aSShawn Guo return sport->devdata->uts_reg; 279fe6b540aSShawn Guo } 280fe6b540aSShawn Guo 281fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 282fe6b540aSShawn Guo { 283fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 284fe6b540aSShawn Guo } 285fe6b540aSShawn Guo 286fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 287fe6b540aSShawn Guo { 288fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 289fe6b540aSShawn Guo } 290fe6b540aSShawn Guo 2911c06bde6SMartyn Welch static inline int is_imx53_uart(struct imx_port *sport) 2921c06bde6SMartyn Welch { 2931c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 2941c06bde6SMartyn Welch } 2951c06bde6SMartyn Welch 296a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 297a496e628SHuang Shijie { 298a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 299a496e628SHuang Shijie } 300ab4382d2SGreg Kroah-Hartman /* 30144a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 30244a75411Sfabio.estevam@freescale.com */ 30393d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 30444a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 30544a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30644a75411Sfabio.estevam@freescale.com { 30744a75411Sfabio.estevam@freescale.com /* save control registers */ 30844a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 30944a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 31044a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 31144a75411Sfabio.estevam@freescale.com } 31244a75411Sfabio.estevam@freescale.com 31344a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 31444a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 31544a75411Sfabio.estevam@freescale.com { 31644a75411Sfabio.estevam@freescale.com /* restore control registers */ 31744a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 31844a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 31944a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 32044a75411Sfabio.estevam@freescale.com } 321e8bfa760SFabio Estevam #endif 32244a75411Sfabio.estevam@freescale.com 32358362d5bSUwe Kleine-König static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2) 32458362d5bSUwe Kleine-König { 325bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 32658362d5bSUwe Kleine-König 327a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 328a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 32958362d5bSUwe Kleine-König } 33058362d5bSUwe Kleine-König 33158362d5bSUwe Kleine-König static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2) 33258362d5bSUwe Kleine-König { 333bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 334bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 33558362d5bSUwe Kleine-König 336a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 337a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 33858362d5bSUwe Kleine-König } 33958362d5bSUwe Kleine-König 34058362d5bSUwe Kleine-König static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2) 34158362d5bSUwe Kleine-König { 34258362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 34358362d5bSUwe Kleine-König } 34458362d5bSUwe Kleine-König 34544a75411Sfabio.estevam@freescale.com /* 346ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 347ab4382d2SGreg Kroah-Hartman */ 348ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 349ab4382d2SGreg Kroah-Hartman { 350ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 351ab4382d2SGreg Kroah-Hartman unsigned long temp; 352ab4382d2SGreg Kroah-Hartman 3539ce4f8f3SGreg Kroah-Hartman /* 3549ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 3559ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 3569ce4f8f3SGreg Kroah-Hartman */ 3579ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 3589ce4f8f3SGreg Kroah-Hartman return; 359b4cdc8f6SHuang Shijie 36017b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR1); 36117b8f2a3SUwe Kleine-König writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); 36217b8f2a3SUwe Kleine-König 36317b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 36417b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 36517b8f2a3SUwe Kleine-König readl(port->membase + USR2) & USR2_TXDC) { 36617b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 36717b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 36858362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 3691a613626SFabio Estevam else 3701a613626SFabio Estevam imx_port_rts_inactive(sport, &temp); 3717d1cadcaSBaruch Siach temp |= UCR2_RXEN; 37217b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 37317b8f2a3SUwe Kleine-König 37417b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 37517b8f2a3SUwe Kleine-König temp &= ~UCR4_TCEN; 37617b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 37717b8f2a3SUwe Kleine-König } 378ab4382d2SGreg Kroah-Hartman } 379ab4382d2SGreg Kroah-Hartman 380ab4382d2SGreg Kroah-Hartman /* 381ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 382ab4382d2SGreg Kroah-Hartman */ 383ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 384ab4382d2SGreg Kroah-Hartman { 385ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 386ab4382d2SGreg Kroah-Hartman unsigned long temp; 387ab4382d2SGreg Kroah-Hartman 38845564a66SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) { 38945564a66SHuang Shijie if (sport->port.suspended) { 39045564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 39145564a66SHuang Shijie sport->dma_is_rxing = 0; 39245564a66SHuang Shijie } else { 3939ce4f8f3SGreg Kroah-Hartman return; 39445564a66SHuang Shijie } 39545564a66SHuang Shijie } 396b4cdc8f6SHuang Shijie 397ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 398ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 39985878399SHuang Shijie 40085878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 40185878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 40285878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 403ab4382d2SGreg Kroah-Hartman } 404ab4382d2SGreg Kroah-Hartman 405ab4382d2SGreg Kroah-Hartman /* 406ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 407ab4382d2SGreg Kroah-Hartman */ 408ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 409ab4382d2SGreg Kroah-Hartman { 410ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 411ab4382d2SGreg Kroah-Hartman 412ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 41358362d5bSUwe Kleine-König 41458362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 415ab4382d2SGreg Kroah-Hartman } 416ab4382d2SGreg Kroah-Hartman 41791a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 418ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 419ab4382d2SGreg Kroah-Hartman { 420ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 42191a1a909SJiada Wang unsigned long temp; 422ab4382d2SGreg Kroah-Hartman 4235e42e9a3SPeter Hurley if (sport->port.x_char) { 4245e42e9a3SPeter Hurley /* Send next char */ 4255e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4267e2fb5aaSJiada Wang sport->port.icount.tx++; 4277e2fb5aaSJiada Wang sport->port.x_char = 0; 4285e42e9a3SPeter Hurley return; 4295e42e9a3SPeter Hurley } 4305e42e9a3SPeter Hurley 4315e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4325e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4335e42e9a3SPeter Hurley return; 4345e42e9a3SPeter Hurley } 4355e42e9a3SPeter Hurley 43691a1a909SJiada Wang if (sport->dma_is_enabled) { 43791a1a909SJiada Wang /* 43891a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 43991a1a909SJiada Wang * and the TX IRQ is disabled. 44091a1a909SJiada Wang **/ 44191a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 44291a1a909SJiada Wang temp &= ~UCR1_TXMPTYEN; 44391a1a909SJiada Wang if (sport->dma_is_txing) { 44491a1a909SJiada Wang temp |= UCR1_TDMAEN; 44591a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 44691a1a909SJiada Wang } else { 44791a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 44891a1a909SJiada Wang imx_dma_tx(sport); 44991a1a909SJiada Wang } 45091a1a909SJiada Wang } 45191a1a909SJiada Wang 4525aabd3b0SIan Jamison if (sport->dma_is_txing) 4535aabd3b0SIan Jamison return; 4545aabd3b0SIan Jamison 4555aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 4565e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 457ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 458ab4382d2SGreg Kroah-Hartman * out the port here */ 459ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 460ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 461ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 462ab4382d2SGreg Kroah-Hartman } 463ab4382d2SGreg Kroah-Hartman 464ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 465ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 466ab4382d2SGreg Kroah-Hartman 467ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 468ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 469ab4382d2SGreg Kroah-Hartman } 470ab4382d2SGreg Kroah-Hartman 471b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 472b4cdc8f6SHuang Shijie { 473b4cdc8f6SHuang Shijie struct imx_port *sport = data; 474b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 475b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 476b4cdc8f6SHuang Shijie unsigned long flags; 477a2c718ceSDirk Behme unsigned long temp; 478b4cdc8f6SHuang Shijie 47942f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 48042f752b3SDirk Behme 481b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 482b4cdc8f6SHuang Shijie 483a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 484a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 485a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 486a2c718ceSDirk Behme 48742f752b3SDirk Behme /* update the stat */ 48842f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 48942f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 49042f752b3SDirk Behme 49142f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 49242f752b3SDirk Behme 493b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 494b4cdc8f6SHuang Shijie 495d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 496b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 4979ce4f8f3SGreg Kroah-Hartman 4980bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 4990bbc9b81SJiada Wang imx_dma_tx(sport); 50064432a85SUwe Kleine-König 5010bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 502b4cdc8f6SHuang Shijie } 503b4cdc8f6SHuang Shijie 5047cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 505b4cdc8f6SHuang Shijie { 506b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 507b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 508b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 509b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 510b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 511a2c718ceSDirk Behme unsigned long temp; 512b4cdc8f6SHuang Shijie int ret; 513b4cdc8f6SHuang Shijie 51442f752b3SDirk Behme if (sport->dma_is_txing) 515b4cdc8f6SHuang Shijie return; 516b4cdc8f6SHuang Shijie 517b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 518b4cdc8f6SHuang Shijie 5197942f857SDirk Behme if (xmit->tail < xmit->head) { 5207942f857SDirk Behme sport->dma_tx_nents = 1; 5217942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5227942f857SDirk Behme } else { 523b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 524b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 525b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 526b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 527b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 528b4cdc8f6SHuang Shijie } 529b4cdc8f6SHuang Shijie 530b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 531b4cdc8f6SHuang Shijie if (ret == 0) { 532b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 533b4cdc8f6SHuang Shijie return; 534b4cdc8f6SHuang Shijie } 535b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 536b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 537b4cdc8f6SHuang Shijie if (!desc) { 53824649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 53924649821SDirk Behme DMA_TO_DEVICE); 540b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 541b4cdc8f6SHuang Shijie return; 542b4cdc8f6SHuang Shijie } 543b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 544b4cdc8f6SHuang Shijie desc->callback_param = sport; 545b4cdc8f6SHuang Shijie 546b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 547b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 548a2c718ceSDirk Behme 549a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 550a2c718ceSDirk Behme temp |= UCR1_TDMAEN; 551a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 552a2c718ceSDirk Behme 553b4cdc8f6SHuang Shijie /* fire it */ 554b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 555b4cdc8f6SHuang Shijie dmaengine_submit(desc); 556b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 557b4cdc8f6SHuang Shijie return; 558b4cdc8f6SHuang Shijie } 559b4cdc8f6SHuang Shijie 560ab4382d2SGreg Kroah-Hartman /* 561ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 562ab4382d2SGreg Kroah-Hartman */ 563ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 564ab4382d2SGreg Kroah-Hartman { 565ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 566ab4382d2SGreg Kroah-Hartman unsigned long temp; 567ab4382d2SGreg Kroah-Hartman 56817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 56917b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 57017b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 57158362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 5721a613626SFabio Estevam else 5731a613626SFabio Estevam imx_port_rts_inactive(sport, &temp); 5747d1cadcaSBaruch Siach if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 5757d1cadcaSBaruch Siach temp &= ~UCR2_RXEN; 57617b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 57717b8f2a3SUwe Kleine-König 57858362d5bSUwe Kleine-König /* enable transmitter and shifter empty irq */ 57917b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 58017b8f2a3SUwe Kleine-König temp |= UCR4_TCEN; 58117b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 58217b8f2a3SUwe Kleine-König } 58317b8f2a3SUwe Kleine-König 584b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 585ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 586ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 587b4cdc8f6SHuang Shijie } 588ab4382d2SGreg Kroah-Hartman 589b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 59091a1a909SJiada Wang if (sport->port.x_char) { 59191a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 59291a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 59391a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 59491a1a909SJiada Wang temp &= ~UCR1_TDMAEN; 59591a1a909SJiada Wang temp |= UCR1_TXMPTYEN; 59691a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 59791a1a909SJiada Wang return; 59891a1a909SJiada Wang } 59991a1a909SJiada Wang 6005e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6015e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6027cb92fd2SHuang Shijie imx_dma_tx(sport); 603b4cdc8f6SHuang Shijie return; 604b4cdc8f6SHuang Shijie } 605ab4382d2SGreg Kroah-Hartman } 606ab4382d2SGreg Kroah-Hartman 607ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 608ab4382d2SGreg Kroah-Hartman { 609ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6105680e941SUwe Kleine-König unsigned int val; 611ab4382d2SGreg Kroah-Hartman unsigned long flags; 612ab4382d2SGreg Kroah-Hartman 613ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 614ab4382d2SGreg Kroah-Hartman 615ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6165680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 617ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 618ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 619ab4382d2SGreg Kroah-Hartman 620ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 621ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 622ab4382d2SGreg Kroah-Hartman } 623ab4382d2SGreg Kroah-Hartman 624ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 625ab4382d2SGreg Kroah-Hartman { 626ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 627ab4382d2SGreg Kroah-Hartman unsigned long flags; 628ab4382d2SGreg Kroah-Hartman 629ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 630ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 631ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 632ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 633ab4382d2SGreg Kroah-Hartman } 634ab4382d2SGreg Kroah-Hartman 635ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 636ab4382d2SGreg Kroah-Hartman { 637ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 638ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 63992a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 640ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 641ab4382d2SGreg Kroah-Hartman 642ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 643ab4382d2SGreg Kroah-Hartman 644ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 645ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 646ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 647ab4382d2SGreg Kroah-Hartman 648ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 649ab4382d2SGreg Kroah-Hartman 650ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 651ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 652ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 653ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 654ab4382d2SGreg Kroah-Hartman continue; 655ab4382d2SGreg Kroah-Hartman } 656ab4382d2SGreg Kroah-Hartman 657ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 658ab4382d2SGreg Kroah-Hartman continue; 659ab4382d2SGreg Kroah-Hartman 660019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 661019dc9eaSHui Wang if (rx & URXD_BRK) 662019dc9eaSHui Wang sport->port.icount.brk++; 663019dc9eaSHui Wang else if (rx & URXD_PRERR) 664ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 665ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 666ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 667ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 668ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 669ab4382d2SGreg Kroah-Hartman 670ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 671ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 672ab4382d2SGreg Kroah-Hartman goto out; 673ab4382d2SGreg Kroah-Hartman continue; 674ab4382d2SGreg Kroah-Hartman } 675ab4382d2SGreg Kroah-Hartman 6768d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 677ab4382d2SGreg Kroah-Hartman 678019dc9eaSHui Wang if (rx & URXD_BRK) 679019dc9eaSHui Wang flg = TTY_BREAK; 680019dc9eaSHui Wang else if (rx & URXD_PRERR) 681ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 682ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 683ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 684ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 685ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 686ab4382d2SGreg Kroah-Hartman 687ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 688ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 689ab4382d2SGreg Kroah-Hartman #endif 690ab4382d2SGreg Kroah-Hartman } 691ab4382d2SGreg Kroah-Hartman 69255d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 69355d8693aSJiada Wang goto out; 69455d8693aSJiada Wang 6959b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 6969b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 697ab4382d2SGreg Kroah-Hartman } 698ab4382d2SGreg Kroah-Hartman 699ab4382d2SGreg Kroah-Hartman out: 700ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7012e124b4aSJiri Slaby tty_flip_buffer_push(port); 702ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 703ab4382d2SGreg Kroah-Hartman } 704ab4382d2SGreg Kroah-Hartman 70518a42088SPeter Senna Tschudin static void clear_rx_errors(struct imx_port *sport); 706b4cdc8f6SHuang Shijie 70766f95884SUwe Kleine-König /* 70866f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 70966f95884SUwe Kleine-König */ 71066f95884SUwe Kleine-König static unsigned int imx_get_hwmctrl(struct imx_port *sport) 71166f95884SUwe Kleine-König { 71266f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 71366f95884SUwe Kleine-König unsigned usr1 = readl(sport->port.membase + USR1); 7144b75f800SSascha Hauer unsigned usr2 = readl(sport->port.membase + USR2); 71566f95884SUwe Kleine-König 71666f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 71766f95884SUwe Kleine-König tmp |= TIOCM_CTS; 71866f95884SUwe Kleine-König 71966f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 7204b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 72166f95884SUwe Kleine-König tmp |= TIOCM_CAR; 72266f95884SUwe Kleine-König 72366f95884SUwe Kleine-König if (sport->dte_mode) 72466f95884SUwe Kleine-König if (!(readl(sport->port.membase + USR2) & USR2_RIIN)) 72566f95884SUwe Kleine-König tmp |= TIOCM_RI; 72666f95884SUwe Kleine-König 72766f95884SUwe Kleine-König return tmp; 72866f95884SUwe Kleine-König } 72966f95884SUwe Kleine-König 73066f95884SUwe Kleine-König /* 73166f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 73266f95884SUwe Kleine-König */ 73366f95884SUwe Kleine-König static void imx_mctrl_check(struct imx_port *sport) 73466f95884SUwe Kleine-König { 73566f95884SUwe Kleine-König unsigned int status, changed; 73666f95884SUwe Kleine-König 73766f95884SUwe Kleine-König status = imx_get_hwmctrl(sport); 73866f95884SUwe Kleine-König changed = status ^ sport->old_status; 73966f95884SUwe Kleine-König 74066f95884SUwe Kleine-König if (changed == 0) 74166f95884SUwe Kleine-König return; 74266f95884SUwe Kleine-König 74366f95884SUwe Kleine-König sport->old_status = status; 74466f95884SUwe Kleine-König 74566f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 74666f95884SUwe Kleine-König sport->port.icount.rng++; 74766f95884SUwe Kleine-König if (changed & TIOCM_DSR) 74866f95884SUwe Kleine-König sport->port.icount.dsr++; 74966f95884SUwe Kleine-König if (changed & TIOCM_CAR) 75066f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 75166f95884SUwe Kleine-König if (changed & TIOCM_CTS) 75266f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 75366f95884SUwe Kleine-König 75466f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 75566f95884SUwe Kleine-König } 75666f95884SUwe Kleine-König 757ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 758ab4382d2SGreg Kroah-Hartman { 759ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 76043776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 7614d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 762ab4382d2SGreg Kroah-Hartman 7630399fd61SUwe Kleine-König usr1 = readl(sport->port.membase + USR1); 7640399fd61SUwe Kleine-König usr2 = readl(sport->port.membase + USR2); 76543776896SUwe Kleine-König ucr1 = readl(sport->port.membase + UCR1); 76643776896SUwe Kleine-König ucr2 = readl(sport->port.membase + UCR2); 76743776896SUwe Kleine-König ucr3 = readl(sport->port.membase + UCR3); 76843776896SUwe Kleine-König ucr4 = readl(sport->port.membase + UCR4); 769ab4382d2SGreg Kroah-Hartman 77043776896SUwe Kleine-König /* 77143776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 77243776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 77343776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 77443776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 77543776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 77643776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 77743776896SUwe Kleine-König */ 77843776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 77943776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 78043776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 78143776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 78243776896SUwe Kleine-König if ((ucr1 & UCR1_TXMPTYEN) == 0) 78343776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 78443776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 78543776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 78643776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 78743776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 78843776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 78943776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 79043776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 79143776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 79243776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 79343776896SUwe Kleine-König usr2 &= ~USR2_ORE; 79443776896SUwe Kleine-König 79543776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 796ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 7974d845a62SUwe Kleine-König ret = IRQ_HANDLED; 798b4cdc8f6SHuang Shijie } 799ab4382d2SGreg Kroah-Hartman 80043776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 801ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 8024d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8034d845a62SUwe Kleine-König } 804ab4382d2SGreg Kroah-Hartman 8050399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 80627e16501SUwe Kleine-König unsigned long flags; 80727e16501SUwe Kleine-König 80827e16501SUwe Kleine-König writel(USR1_DTRD, sport->port.membase + USR1); 80927e16501SUwe Kleine-König 81027e16501SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 81127e16501SUwe Kleine-König imx_mctrl_check(sport); 81227e16501SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 81327e16501SUwe Kleine-König 81427e16501SUwe Kleine-König ret = IRQ_HANDLED; 81527e16501SUwe Kleine-König } 81627e16501SUwe Kleine-König 8170399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 818ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 8194d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8204d845a62SUwe Kleine-König } 821ab4382d2SGreg Kroah-Hartman 8220399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 823db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 8244d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8254d845a62SUwe Kleine-König } 826db1a9b55SFabio Estevam 8270399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 828f1f836e4SAlexander Stein sport->port.icount.overrun++; 82991555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 8304d845a62SUwe Kleine-König ret = IRQ_HANDLED; 831f1f836e4SAlexander Stein } 832f1f836e4SAlexander Stein 8334d845a62SUwe Kleine-König return ret; 834ab4382d2SGreg Kroah-Hartman } 835ab4382d2SGreg Kroah-Hartman 836ab4382d2SGreg Kroah-Hartman /* 837ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 838ab4382d2SGreg Kroah-Hartman */ 839ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 840ab4382d2SGreg Kroah-Hartman { 841ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 8421ce43e58SHuang Shijie unsigned int ret; 843ab4382d2SGreg Kroah-Hartman 8441ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 8451ce43e58SHuang Shijie 8461ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 8471ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 8481ce43e58SHuang Shijie ret = 0; 8491ce43e58SHuang Shijie 8501ce43e58SHuang Shijie return ret; 851ab4382d2SGreg Kroah-Hartman } 852ab4382d2SGreg Kroah-Hartman 85358362d5bSUwe Kleine-König static unsigned int imx_get_mctrl(struct uart_port *port) 85458362d5bSUwe Kleine-König { 85558362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 85658362d5bSUwe Kleine-König unsigned int ret = imx_get_hwmctrl(sport); 85758362d5bSUwe Kleine-König 85858362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 85958362d5bSUwe Kleine-König 86058362d5bSUwe Kleine-König return ret; 86158362d5bSUwe Kleine-König } 86258362d5bSUwe Kleine-König 863ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 864ab4382d2SGreg Kroah-Hartman { 865ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 866ab4382d2SGreg Kroah-Hartman unsigned long temp; 867ab4382d2SGreg Kroah-Hartman 86817b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 86917b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 87017b8f2a3SUwe Kleine-König temp &= ~(UCR2_CTS | UCR2_CTSC); 871ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 872bb2f861aSFugang Duan temp |= UCR2_CTS | UCR2_CTSC; 873ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 87417b8f2a3SUwe Kleine-König } 8756b471a98SHuang Shijie 87690ebc483SUwe Kleine-König temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR; 87790ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 87890ebc483SUwe Kleine-König temp |= UCR3_DSR; 87990ebc483SUwe Kleine-König writel(temp, sport->port.membase + UCR3); 88090ebc483SUwe Kleine-König 8816b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8826b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8836b471a98SHuang Shijie temp |= UTS_LOOP; 8846b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 88558362d5bSUwe Kleine-König 88658362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 887ab4382d2SGreg Kroah-Hartman } 888ab4382d2SGreg Kroah-Hartman 889ab4382d2SGreg Kroah-Hartman /* 890ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 891ab4382d2SGreg Kroah-Hartman */ 892ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 893ab4382d2SGreg Kroah-Hartman { 894ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 895ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 896ab4382d2SGreg Kroah-Hartman 897ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 898ab4382d2SGreg Kroah-Hartman 899ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 900ab4382d2SGreg Kroah-Hartman 901ab4382d2SGreg Kroah-Hartman if (break_state != 0) 902ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 903ab4382d2SGreg Kroah-Hartman 904ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 905ab4382d2SGreg Kroah-Hartman 906ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 907ab4382d2SGreg Kroah-Hartman } 908ab4382d2SGreg Kroah-Hartman 909cc568849SUwe Kleine-König /* 910cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 911cc568849SUwe Kleine-König * modem status signals. 912cc568849SUwe Kleine-König */ 913e99e88a9SKees Cook static void imx_timeout(struct timer_list *t) 914cc568849SUwe Kleine-König { 915e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 916cc568849SUwe Kleine-König unsigned long flags; 917cc568849SUwe Kleine-König 918cc568849SUwe Kleine-König if (sport->port.state) { 919cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 920cc568849SUwe Kleine-König imx_mctrl_check(sport); 921cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 922cc568849SUwe Kleine-König 923cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 924cc568849SUwe Kleine-König } 925cc568849SUwe Kleine-König } 926cc568849SUwe Kleine-König 927351ea50dSGreg Kroah-Hartman #define RX_BUF_SIZE (PAGE_SIZE) 928351ea50dSGreg Kroah-Hartman 929b4cdc8f6SHuang Shijie /* 930905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 931b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 932905c0decSLucas Stach * [2] the aging timer expires 933b4cdc8f6SHuang Shijie * 934905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 935905c0decSLucas Stach * for at least 8 byte durations. 936b4cdc8f6SHuang Shijie */ 937b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 938b4cdc8f6SHuang Shijie { 939b4cdc8f6SHuang Shijie struct imx_port *sport = data; 940b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 941b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9427cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 943b4cdc8f6SHuang Shijie struct dma_tx_state state; 9449d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 945b4cdc8f6SHuang Shijie enum dma_status status; 9469d297239SNandor Han unsigned int w_bytes = 0; 9479d297239SNandor Han unsigned int r_bytes; 9489d297239SNandor Han unsigned int bd_size; 949b4cdc8f6SHuang Shijie 950f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 951392bceedSPhilipp Zabel 9529d297239SNandor Han if (status == DMA_ERROR) { 95341d98b5dSNandor Han clear_rx_errors(sport); 9549d297239SNandor Han return; 9559d297239SNandor Han } 956b4cdc8f6SHuang Shijie 9579b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 958976b39cdSLucas Stach 959976b39cdSLucas Stach /* 9609d297239SNandor Han * The state-residue variable represents the empty space 9619d297239SNandor Han * relative to the entire buffer. Taking this in consideration 9629d297239SNandor Han * the head is always calculated base on the buffer total 9639d297239SNandor Han * length - DMA transaction residue. The UART script from the 9649d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 9659d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 9669d297239SNandor Han * Taking this in consideration the tail is always at the 9679d297239SNandor Han * beginning of the buffer descriptor that contains the head. 968976b39cdSLucas Stach */ 9699d297239SNandor Han 9709d297239SNandor Han /* Calculate the head */ 9719d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 9729d297239SNandor Han 9739d297239SNandor Han /* Calculate the tail. */ 9749d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 9759d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 9769d297239SNandor Han 9779d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 9789d297239SNandor Han rx_ring->head > rx_ring->tail) { 9799d297239SNandor Han 9809d297239SNandor Han /* Move data from tail to head */ 9819d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 9829d297239SNandor Han 9839d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 9849d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 9859d297239SNandor Han DMA_FROM_DEVICE); 9869d297239SNandor Han 9879d297239SNandor Han w_bytes = tty_insert_flip_string(port, 9889d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 9899d297239SNandor Han 9909d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 9919d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 9929d297239SNandor Han DMA_FROM_DEVICE); 9939d297239SNandor Han 9949d297239SNandor Han if (w_bytes != r_bytes) 9959d297239SNandor Han sport->port.icount.buf_overrun++; 9969d297239SNandor Han 9979d297239SNandor Han sport->port.icount.rx += w_bytes; 9989d297239SNandor Han } else { 9999d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 10009d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1001ee5e7c10SRobin Gong } 10029d297239SNandor Han } 10039d297239SNandor Han 10049d297239SNandor Han if (w_bytes) { 10059d297239SNandor Han tty_flip_buffer_push(port); 10069d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 10079d297239SNandor Han } 10089d297239SNandor Han } 10099d297239SNandor Han 1010351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 1011351ea50dSGreg Kroah-Hartman #define RX_DMA_PERIODS 4 1012351ea50dSGreg Kroah-Hartman 1013b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 1014b4cdc8f6SHuang Shijie { 1015b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1016b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1017b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1018b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1019b4cdc8f6SHuang Shijie int ret; 1020b4cdc8f6SHuang Shijie 10219d297239SNandor Han sport->rx_ring.head = 0; 10229d297239SNandor Han sport->rx_ring.tail = 0; 1023351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 10249d297239SNandor Han 1025351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1026b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1027b4cdc8f6SHuang Shijie if (ret == 0) { 1028b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1029b4cdc8f6SHuang Shijie return -EINVAL; 1030b4cdc8f6SHuang Shijie } 10319d297239SNandor Han 10329d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 10339d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 10349d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 10359d297239SNandor Han 1036b4cdc8f6SHuang Shijie if (!desc) { 103724649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1038b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1039b4cdc8f6SHuang Shijie return -EINVAL; 1040b4cdc8f6SHuang Shijie } 1041b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 1042b4cdc8f6SHuang Shijie desc->callback_param = sport; 1043b4cdc8f6SHuang Shijie 1044b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 10454139fd76SRomain Perier sport->dma_is_rxing = 1; 10469d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1047b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1048b4cdc8f6SHuang Shijie return 0; 1049b4cdc8f6SHuang Shijie } 1050b4cdc8f6SHuang Shijie 105141d98b5dSNandor Han static void clear_rx_errors(struct imx_port *sport) 105241d98b5dSNandor Han { 105345ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 105441d98b5dSNandor Han unsigned int status_usr1, status_usr2; 105541d98b5dSNandor Han 105641d98b5dSNandor Han status_usr1 = readl(sport->port.membase + USR1); 105741d98b5dSNandor Han status_usr2 = readl(sport->port.membase + USR2); 105841d98b5dSNandor Han 105941d98b5dSNandor Han if (status_usr2 & USR2_BRCD) { 106041d98b5dSNandor Han sport->port.icount.brk++; 106141d98b5dSNandor Han writel(USR2_BRCD, sport->port.membase + USR2); 106245ca673eSTroy Kisky uart_handle_break(&sport->port); 106345ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 106445ca673eSTroy Kisky sport->port.icount.buf_overrun++; 106545ca673eSTroy Kisky tty_flip_buffer_push(port); 106645ca673eSTroy Kisky } else { 106745ca673eSTroy Kisky dev_err(sport->port.dev, "DMA transaction error.\n"); 106845ca673eSTroy Kisky if (status_usr1 & USR1_FRAMERR) { 106941d98b5dSNandor Han sport->port.icount.frame++; 107041d98b5dSNandor Han writel(USR1_FRAMERR, sport->port.membase + USR1); 107141d98b5dSNandor Han } else if (status_usr1 & USR1_PARITYERR) { 107241d98b5dSNandor Han sport->port.icount.parity++; 107341d98b5dSNandor Han writel(USR1_PARITYERR, sport->port.membase + USR1); 107441d98b5dSNandor Han } 107545ca673eSTroy Kisky } 107641d98b5dSNandor Han 107741d98b5dSNandor Han if (status_usr2 & USR2_ORE) { 107841d98b5dSNandor Han sport->port.icount.overrun++; 107941d98b5dSNandor Han writel(USR2_ORE, sport->port.membase + USR2); 108041d98b5dSNandor Han } 108141d98b5dSNandor Han 108241d98b5dSNandor Han } 108341d98b5dSNandor Han 1084cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1085cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1086184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1087184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1088cc32382dSLucas Stach 1089cc32382dSLucas Stach static void imx_setup_ufcr(struct imx_port *sport, 1090cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1091cc32382dSLucas Stach { 1092cc32382dSLucas Stach unsigned int val; 1093cc32382dSLucas Stach 1094cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 1095cc32382dSLucas Stach val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1096cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 1097cc32382dSLucas Stach writel(val, sport->port.membase + UFCR); 1098cc32382dSLucas Stach } 1099cc32382dSLucas Stach 1100b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1101b4cdc8f6SHuang Shijie { 1102b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1103e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1104b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1105b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 11069d297239SNandor Han sport->rx_cookie = -EINVAL; 1107b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1108b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1109b4cdc8f6SHuang Shijie } 1110b4cdc8f6SHuang Shijie 1111b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1112e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1113b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1114b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1115b4cdc8f6SHuang Shijie } 1116b4cdc8f6SHuang Shijie } 1117b4cdc8f6SHuang Shijie 1118b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1119b4cdc8f6SHuang Shijie { 1120b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1121b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1122b4cdc8f6SHuang Shijie int ret; 1123b4cdc8f6SHuang Shijie 1124b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1125b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1126b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1127b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1128b4cdc8f6SHuang Shijie ret = -EINVAL; 1129b4cdc8f6SHuang Shijie goto err; 1130b4cdc8f6SHuang Shijie } 1131b4cdc8f6SHuang Shijie 1132b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1133b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1134b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1135184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1136184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1137b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1138b4cdc8f6SHuang Shijie if (ret) { 1139b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1140b4cdc8f6SHuang Shijie goto err; 1141b4cdc8f6SHuang Shijie } 1142b4cdc8f6SHuang Shijie 1143f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1144b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1145b4cdc8f6SHuang Shijie ret = -ENOMEM; 1146b4cdc8f6SHuang Shijie goto err; 1147b4cdc8f6SHuang Shijie } 11489d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1149b4cdc8f6SHuang Shijie 1150b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1151b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1152b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1153b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1154b4cdc8f6SHuang Shijie ret = -EINVAL; 1155b4cdc8f6SHuang Shijie goto err; 1156b4cdc8f6SHuang Shijie } 1157b4cdc8f6SHuang Shijie 1158b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1159b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1160b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1161184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1162b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1163b4cdc8f6SHuang Shijie if (ret) { 1164b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1165b4cdc8f6SHuang Shijie goto err; 1166b4cdc8f6SHuang Shijie } 1167b4cdc8f6SHuang Shijie 1168b4cdc8f6SHuang Shijie return 0; 1169b4cdc8f6SHuang Shijie err: 1170b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1171b4cdc8f6SHuang Shijie return ret; 1172b4cdc8f6SHuang Shijie } 1173b4cdc8f6SHuang Shijie 1174b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1175b4cdc8f6SHuang Shijie { 1176b4cdc8f6SHuang Shijie unsigned long temp; 1177b4cdc8f6SHuang Shijie 1178b4cdc8f6SHuang Shijie /* set UCR1 */ 1179b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1180905c0decSLucas Stach temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN; 1181b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1182b4cdc8f6SHuang Shijie 1183184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1184184bd70bSLucas Stach 1185b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1186b4cdc8f6SHuang Shijie } 1187b4cdc8f6SHuang Shijie 1188b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1189b4cdc8f6SHuang Shijie { 1190b4cdc8f6SHuang Shijie unsigned long temp; 1191b4cdc8f6SHuang Shijie 1192b4cdc8f6SHuang Shijie /* clear UCR1 */ 1193b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1194b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1195b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1196b4cdc8f6SHuang Shijie 1197b4cdc8f6SHuang Shijie /* clear UCR2 */ 1198b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 119986a04ba6SLucas Stach temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN); 1200b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1201b4cdc8f6SHuang Shijie 1202184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1203184bd70bSLucas Stach 1204b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1205b4cdc8f6SHuang Shijie } 1206b4cdc8f6SHuang Shijie 1207ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1208ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1209ab4382d2SGreg Kroah-Hartman 1210ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1211ab4382d2SGreg Kroah-Hartman { 1212ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1213458e2c82SFabio Estevam int retval, i; 1214ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 12154238c00bSUwe Kleine-König int dma_is_inited = 0; 1216ab4382d2SGreg Kroah-Hartman 121728eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 121828eb4274SHuang Shijie if (retval) 1219cb0f0a5fSFabio Estevam return retval; 122028eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 12210c375501SHuang Shijie if (retval) { 12220c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1223cb0f0a5fSFabio Estevam return retval; 12240c375501SHuang Shijie } 122528eb4274SHuang Shijie 1226cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1227ab4382d2SGreg Kroah-Hartman 1228ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1229ab4382d2SGreg Kroah-Hartman * requesting IRQs 1230ab4382d2SGreg Kroah-Hartman */ 1231ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1232ab4382d2SGreg Kroah-Hartman 1233ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1234ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1235ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1236ab4382d2SGreg Kroah-Hartman 1237ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1238ab4382d2SGreg Kroah-Hartman 12397e11577eSLucas Stach /* Can we enable the DMA support? */ 12404238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 12414238c00bSUwe Kleine-König dma_is_inited = 1; 12427e11577eSLucas Stach 124353794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1244772f8991SHuang Shijie /* Reset fifo's and state machines */ 1245458e2c82SFabio Estevam i = 100; 1246458e2c82SFabio Estevam 1247458e2c82SFabio Estevam temp = readl(sport->port.membase + UCR2); 1248458e2c82SFabio Estevam temp &= ~UCR2_SRST; 1249458e2c82SFabio Estevam writel(temp, sport->port.membase + UCR2); 1250458e2c82SFabio Estevam 1251458e2c82SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1252458e2c82SFabio Estevam udelay(1); 1253ab4382d2SGreg Kroah-Hartman 1254ab4382d2SGreg Kroah-Hartman /* 1255ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1256ab4382d2SGreg Kroah-Hartman */ 125727e16501SUwe Kleine-König writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1); 125891555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 1259ab4382d2SGreg Kroah-Hartman 126042afa627SUwe Kleine-König if (dma_is_inited) 12617e11577eSLucas Stach imx_enable_dma(sport); 12627e11577eSLucas Stach 12631f043572STroy Kisky temp = readl(sport->port.membase + UCR1) & ~UCR1_RRDYEN; 12641f043572STroy Kisky if (!sport->dma_is_enabled) 12651f043572STroy Kisky temp |= UCR1_RRDYEN; 12661f043572STroy Kisky temp |= UCR1_UARTEN; 12676376cd39SNandor Han if (sport->have_rtscts) 12686376cd39SNandor Han temp |= UCR1_RTSDEN; 1269ab4382d2SGreg Kroah-Hartman 1270ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1271ab4382d2SGreg Kroah-Hartman 12721f043572STroy Kisky temp = readl(sport->port.membase + UCR4) & ~UCR4_OREN; 12731f043572STroy Kisky if (!sport->dma_is_enabled) 12746f026d6bSJiada Wang temp |= UCR4_OREN; 12756f026d6bSJiada Wang writel(temp, sport->port.membase + UCR4); 12766f026d6bSJiada Wang 12771f043572STroy Kisky temp = readl(sport->port.membase + UCR2) & ~UCR2_ATEN; 1278ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1279bff09b09SLucas Stach if (!sport->have_rtscts) 1280bff09b09SLucas Stach temp |= UCR2_IRTS; 128116804d68SUwe Kleine-König /* 128216804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 128316804d68SUwe Kleine-König * we're using RTSD instead. 128416804d68SUwe Kleine-König */ 128516804d68SUwe Kleine-König if (!is_imx1_uart(sport)) 128616804d68SUwe Kleine-König temp &= ~UCR2_RTSEN; 1287ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1288ab4382d2SGreg Kroah-Hartman 1289a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1290ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 129116804d68SUwe Kleine-König 1292e61c38d8SUwe Kleine-König temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 129316804d68SUwe Kleine-König 129416804d68SUwe Kleine-König if (sport->dte_mode) 1295e61c38d8SUwe Kleine-König /* disable broken interrupts */ 129616804d68SUwe Kleine-König temp &= ~(UCR3_RI | UCR3_DCD); 129716804d68SUwe Kleine-König 1298ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1299ab4382d2SGreg Kroah-Hartman } 1300ab4382d2SGreg Kroah-Hartman 1301ab4382d2SGreg Kroah-Hartman /* 1302ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1303ab4382d2SGreg Kroah-Hartman */ 1304ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 130518a42088SPeter Senna Tschudin 130618a42088SPeter Senna Tschudin /* 13074dec2f11SPeter Senna Tschudin * Start RX DMA immediately instead of waiting for RX FIFO interrupts. 13084dec2f11SPeter Senna Tschudin * In our iMX53 the average delay for the first reception dropped from 13094dec2f11SPeter Senna Tschudin * approximately 35000 microseconds to 1000 microseconds. 131018a42088SPeter Senna Tschudin */ 13111f043572STroy Kisky if (sport->dma_is_enabled) 131218a42088SPeter Senna Tschudin start_rx_dma(sport); 131318a42088SPeter Senna Tschudin 1314ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1315ab4382d2SGreg Kroah-Hartman 1316ab4382d2SGreg Kroah-Hartman return 0; 1317ab4382d2SGreg Kroah-Hartman } 1318ab4382d2SGreg Kroah-Hartman 1319ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1320ab4382d2SGreg Kroah-Hartman { 1321ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1322ab4382d2SGreg Kroah-Hartman unsigned long temp; 13239ec1882dSXinyu Chen unsigned long flags; 1324ab4382d2SGreg Kroah-Hartman 1325b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1326a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1327a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1328e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1329e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 13309d297239SNandor Han 133173631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1332a4688bcdSHuang Shijie imx_stop_tx(port); 1333b4cdc8f6SHuang Shijie imx_stop_rx(port); 1334b4cdc8f6SHuang Shijie imx_disable_dma(sport); 133573631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1336b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1337b4cdc8f6SHuang Shijie } 1338b4cdc8f6SHuang Shijie 133958362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 134058362d5bSUwe Kleine-König 13419ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1342ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1343ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1344ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 13459ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1346ab4382d2SGreg Kroah-Hartman 1347ab4382d2SGreg Kroah-Hartman /* 1348ab4382d2SGreg Kroah-Hartman * Stop our timer. 1349ab4382d2SGreg Kroah-Hartman */ 1350ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1351ab4382d2SGreg Kroah-Hartman 1352ab4382d2SGreg Kroah-Hartman /* 1353ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1354ab4382d2SGreg Kroah-Hartman */ 1355ab4382d2SGreg Kroah-Hartman 13569ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1357ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1358ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1359ab4382d2SGreg Kroah-Hartman 1360ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 13619ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 136228eb4274SHuang Shijie 136328eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 136428eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1365ab4382d2SGreg Kroah-Hartman } 1366ab4382d2SGreg Kroah-Hartman 1367eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1368eb56b7edSHuang Shijie { 1369eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 137082e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1371a2c718ceSDirk Behme unsigned long temp; 13724f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1373eb56b7edSHuang Shijie 137482e86ae9SDirk Behme if (!sport->dma_chan_tx) 137582e86ae9SDirk Behme return; 137682e86ae9SDirk Behme 1377eb56b7edSHuang Shijie sport->tx_bytes = 0; 1378eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 137982e86ae9SDirk Behme if (sport->dma_is_txing) { 138082e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 138182e86ae9SDirk Behme DMA_TO_DEVICE); 1382a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 1383a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 1384a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 13850f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1386eb56b7edSHuang Shijie } 1387934084a9SFabio Estevam 1388934084a9SFabio Estevam /* 1389934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1390263763c1SMartyn Welch * 1391934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1392934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1393263763c1SMartyn Welch * and UTS[6-3]". 1394263763c1SMartyn Welch * 1395263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1396263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1397263763c1SMartyn Welch * registers. 1398934084a9SFabio Estevam */ 1399934084a9SFabio Estevam ubir = readl(sport->port.membase + UBIR); 1400934084a9SFabio Estevam ubmr = readl(sport->port.membase + UBMR); 1401934084a9SFabio Estevam uts = readl(sport->port.membase + IMX21_UTS); 1402934084a9SFabio Estevam 1403934084a9SFabio Estevam temp = readl(sport->port.membase + UCR2); 1404934084a9SFabio Estevam temp &= ~UCR2_SRST; 1405934084a9SFabio Estevam writel(temp, sport->port.membase + UCR2); 1406934084a9SFabio Estevam 1407934084a9SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1408934084a9SFabio Estevam udelay(1); 1409934084a9SFabio Estevam 1410934084a9SFabio Estevam /* Restore the registers */ 1411934084a9SFabio Estevam writel(ubir, sport->port.membase + UBIR); 1412934084a9SFabio Estevam writel(ubmr, sport->port.membase + UBMR); 1413934084a9SFabio Estevam writel(uts, sport->port.membase + IMX21_UTS); 1414eb56b7edSHuang Shijie } 1415eb56b7edSHuang Shijie 1416ab4382d2SGreg Kroah-Hartman static void 1417ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1418ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1419ab4382d2SGreg Kroah-Hartman { 1420ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1421ab4382d2SGreg Kroah-Hartman unsigned long flags; 142258362d5bSUwe Kleine-König unsigned long ucr2, old_ucr1, old_ucr2; 142358362d5bSUwe Kleine-König unsigned int baud, quot; 1424ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 142558362d5bSUwe Kleine-König unsigned long div, ufcr; 1426ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1427ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1428ab4382d2SGreg Kroah-Hartman 1429ab4382d2SGreg Kroah-Hartman /* 1430ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1431ab4382d2SGreg Kroah-Hartman */ 1432ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1433ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1434ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1435ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1436ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1437ab4382d2SGreg Kroah-Hartman } 1438ab4382d2SGreg Kroah-Hartman 1439ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1440ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1441ab4382d2SGreg Kroah-Hartman else 1442ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1443ab4382d2SGreg Kroah-Hartman 1444ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1445ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1446ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 144717b8f2a3SUwe Kleine-König 144812fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 144917b8f2a3SUwe Kleine-König /* 145017b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 145117b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 145217b8f2a3SUwe Kleine-König * disabled. 145317b8f2a3SUwe Kleine-König */ 145458362d5bSUwe Kleine-König if (port->rs485.flags & 145558362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 145658362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 14571a613626SFabio Estevam else 14581a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 145912fe59f9SFabio Estevam } else { 146058362d5bSUwe Kleine-König imx_port_rts_auto(sport, &ucr2); 146112fe59f9SFabio Estevam } 1462ab4382d2SGreg Kroah-Hartman } else { 1463ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1464ab4382d2SGreg Kroah-Hartman } 146558362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 146617b8f2a3SUwe Kleine-König /* disable transmitter */ 146758362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 146858362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 14691a613626SFabio Estevam else 14701a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 147158362d5bSUwe Kleine-König } 147258362d5bSUwe Kleine-König 1473ab4382d2SGreg Kroah-Hartman 1474ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1475ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1476ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1477ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1478ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1479ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1480ab4382d2SGreg Kroah-Hartman } 1481ab4382d2SGreg Kroah-Hartman 1482995234daSEric Miao del_timer_sync(&sport->timer); 1483995234daSEric Miao 1484ab4382d2SGreg Kroah-Hartman /* 1485ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1486ab4382d2SGreg Kroah-Hartman */ 1487ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1488ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1489ab4382d2SGreg Kroah-Hartman 1490ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1491ab4382d2SGreg Kroah-Hartman 1492ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1493ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1494ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1495ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1496ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1497ab4382d2SGreg Kroah-Hartman 1498ab4382d2SGreg Kroah-Hartman /* 1499ab4382d2SGreg Kroah-Hartman * Characters to ignore 1500ab4382d2SGreg Kroah-Hartman */ 1501ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1502ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1503865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1504ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1505ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1506ab4382d2SGreg Kroah-Hartman /* 1507ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1508ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1509ab4382d2SGreg Kroah-Hartman */ 1510ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1511ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1512ab4382d2SGreg Kroah-Hartman } 1513ab4382d2SGreg Kroah-Hartman 151455d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 151555d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 151655d8693aSJiada Wang 1517ab4382d2SGreg Kroah-Hartman /* 1518ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1519ab4382d2SGreg Kroah-Hartman */ 1520ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1521ab4382d2SGreg Kroah-Hartman 1522ab4382d2SGreg Kroah-Hartman /* 1523ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1524ab4382d2SGreg Kroah-Hartman */ 1525ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1526ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1527ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1528ab4382d2SGreg Kroah-Hartman 1529ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1530ab4382d2SGreg Kroah-Hartman barrier(); 1531ab4382d2SGreg Kroah-Hartman 1532ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 153386a04ba6SLucas Stach old_ucr2 = readl(sport->port.membase + UCR2); 153486a04ba6SLucas Stach writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN), 1535ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 153686a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1537ab4382d2SGreg Kroah-Hartman 153809bd00f6SHubert Feurstein /* custom-baudrate handling */ 153909bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 154009bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 154109bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 154209bd00f6SHubert Feurstein 1543ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1544ab4382d2SGreg Kroah-Hartman if (div > 7) 1545ab4382d2SGreg Kroah-Hartman div = 7; 1546ab4382d2SGreg Kroah-Hartman if (!div) 1547ab4382d2SGreg Kroah-Hartman div = 1; 1548ab4382d2SGreg Kroah-Hartman 1549ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1550ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1551ab4382d2SGreg Kroah-Hartman 1552ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1553ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1554ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1555ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1556ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1557ab4382d2SGreg Kroah-Hartman 1558ab4382d2SGreg Kroah-Hartman num -= 1; 1559ab4382d2SGreg Kroah-Hartman denom -= 1; 1560ab4382d2SGreg Kroah-Hartman 1561ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1562ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1563ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1564ab4382d2SGreg Kroah-Hartman 1565ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1566ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1567ab4382d2SGreg Kroah-Hartman 1568a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1569ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1570fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1571ab4382d2SGreg Kroah-Hartman 1572ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1573ab4382d2SGreg Kroah-Hartman 1574ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 157586a04ba6SLucas Stach writel(ucr2 | old_ucr2, sport->port.membase + UCR2); 1576ab4382d2SGreg Kroah-Hartman 1577ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1578ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1579ab4382d2SGreg Kroah-Hartman 1580ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1581ab4382d2SGreg Kroah-Hartman } 1582ab4382d2SGreg Kroah-Hartman 1583ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1584ab4382d2SGreg Kroah-Hartman { 1585ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1586ab4382d2SGreg Kroah-Hartman 1587ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1588ab4382d2SGreg Kroah-Hartman } 1589ab4382d2SGreg Kroah-Hartman 1590ab4382d2SGreg Kroah-Hartman /* 1591ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1592ab4382d2SGreg Kroah-Hartman */ 1593ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1594ab4382d2SGreg Kroah-Hartman { 1595ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1596ab4382d2SGreg Kroah-Hartman 1597da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1598ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1599ab4382d2SGreg Kroah-Hartman } 1600ab4382d2SGreg Kroah-Hartman 1601ab4382d2SGreg Kroah-Hartman /* 1602ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1603ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1604ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1605ab4382d2SGreg Kroah-Hartman */ 1606ab4382d2SGreg Kroah-Hartman static int 1607ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1608ab4382d2SGreg Kroah-Hartman { 1609ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1610ab4382d2SGreg Kroah-Hartman int ret = 0; 1611ab4382d2SGreg Kroah-Hartman 1612ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1613ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1614ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1615ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1616ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1617ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1618ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1619ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1620a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1621ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1622ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1623ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1624ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1625ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1626ab4382d2SGreg Kroah-Hartman return ret; 1627ab4382d2SGreg Kroah-Hartman } 1628ab4382d2SGreg Kroah-Hartman 162901f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 16306b8bdad9SDaniel Thompson 16316b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 16326b8bdad9SDaniel Thompson { 16336b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 16346b8bdad9SDaniel Thompson unsigned long flags; 16356b8bdad9SDaniel Thompson unsigned long temp; 16366b8bdad9SDaniel Thompson int retval; 16376b8bdad9SDaniel Thompson 16386b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 16396b8bdad9SDaniel Thompson if (retval) 16406b8bdad9SDaniel Thompson return retval; 16416b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 16426b8bdad9SDaniel Thompson if (retval) 16436b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 16446b8bdad9SDaniel Thompson 1645cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 16466b8bdad9SDaniel Thompson 16476b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 16486b8bdad9SDaniel Thompson 16496b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR1); 16506b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 16516b8bdad9SDaniel Thompson temp |= IMX1_UCR1_UARTCLKEN; 16526b8bdad9SDaniel Thompson temp |= UCR1_UARTEN | UCR1_RRDYEN; 16536b8bdad9SDaniel Thompson temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 16546b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR1); 16556b8bdad9SDaniel Thompson 16566b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR2); 16576b8bdad9SDaniel Thompson temp |= UCR2_RXEN; 16586b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR2); 16596b8bdad9SDaniel Thompson 16606b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 16616b8bdad9SDaniel Thompson 16626b8bdad9SDaniel Thompson return 0; 16636b8bdad9SDaniel Thompson } 16646b8bdad9SDaniel Thompson 166501f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 166601f56abdSSaleem Abdulrasool { 1667f968ef34SDaniel Thompson if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 166826c47412SDirk Behme return NO_POLL_CHAR; 166901f56abdSSaleem Abdulrasool 1670f968ef34SDaniel Thompson return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 167101f56abdSSaleem Abdulrasool } 167201f56abdSSaleem Abdulrasool 167301f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 167401f56abdSSaleem Abdulrasool { 167501f56abdSSaleem Abdulrasool unsigned int status; 167601f56abdSSaleem Abdulrasool 167701f56abdSSaleem Abdulrasool /* drain */ 167801f56abdSSaleem Abdulrasool do { 1679f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR1); 168001f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 168101f56abdSSaleem Abdulrasool 168201f56abdSSaleem Abdulrasool /* write */ 1683f968ef34SDaniel Thompson writel_relaxed(c, port->membase + URTX0); 168401f56abdSSaleem Abdulrasool 168501f56abdSSaleem Abdulrasool /* flush */ 168601f56abdSSaleem Abdulrasool do { 1687f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR2); 168801f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 168901f56abdSSaleem Abdulrasool } 169001f56abdSSaleem Abdulrasool #endif 169101f56abdSSaleem Abdulrasool 169217b8f2a3SUwe Kleine-König static int imx_rs485_config(struct uart_port *port, 169317b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 169417b8f2a3SUwe Kleine-König { 169517b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 16967d1cadcaSBaruch Siach unsigned long temp; 169717b8f2a3SUwe Kleine-König 169817b8f2a3SUwe Kleine-König /* unimplemented */ 169917b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 170017b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 170117b8f2a3SUwe Kleine-König 170217b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 17037b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 170417b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 170517b8f2a3SUwe Kleine-König 170617b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 170717b8f2a3SUwe Kleine-König /* disable transmitter */ 170817b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 170917b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 171058362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 17111a613626SFabio Estevam else 17121a613626SFabio Estevam imx_port_rts_inactive(sport, &temp); 171317b8f2a3SUwe Kleine-König writel(temp, sport->port.membase + UCR2); 171417b8f2a3SUwe Kleine-König } 171517b8f2a3SUwe Kleine-König 17167d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 17177d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 17187d1cadcaSBaruch Siach rs485conf->flags & SER_RS485_RX_DURING_TX) { 17197d1cadcaSBaruch Siach temp = readl(sport->port.membase + UCR2); 17207d1cadcaSBaruch Siach temp |= UCR2_RXEN; 17217d1cadcaSBaruch Siach writel(temp, sport->port.membase + UCR2); 17227d1cadcaSBaruch Siach } 17237d1cadcaSBaruch Siach 172417b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 172517b8f2a3SUwe Kleine-König 172617b8f2a3SUwe Kleine-König return 0; 172717b8f2a3SUwe Kleine-König } 172817b8f2a3SUwe Kleine-König 1729069a47e5SJulia Lawall static const struct uart_ops imx_pops = { 1730ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1731ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1732ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1733ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1734ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1735ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1736ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1737ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1738ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1739ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1740eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1741ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1742ab4382d2SGreg Kroah-Hartman .type = imx_type, 1743ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1744ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 174501f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17466b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 174701f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 174801f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 174901f56abdSSaleem Abdulrasool #endif 1750ab4382d2SGreg Kroah-Hartman }; 1751ab4382d2SGreg Kroah-Hartman 1752ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1753ab4382d2SGreg Kroah-Hartman 1754ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1755ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1756ab4382d2SGreg Kroah-Hartman { 1757ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1758ab4382d2SGreg Kroah-Hartman 1759fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1760ab4382d2SGreg Kroah-Hartman barrier(); 1761ab4382d2SGreg Kroah-Hartman 1762ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1763ab4382d2SGreg Kroah-Hartman } 1764ab4382d2SGreg Kroah-Hartman 1765ab4382d2SGreg Kroah-Hartman /* 1766ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1767ab4382d2SGreg Kroah-Hartman */ 1768ab4382d2SGreg Kroah-Hartman static void 1769ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1770ab4382d2SGreg Kroah-Hartman { 1771ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 17720ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 17730ad5a814SDirk Behme unsigned int ucr1; 1774f30e8260SShawn Guo unsigned long flags = 0; 1775677fe555SThomas Gleixner int locked = 1; 17761cf93e0dSHuang Shijie int retval; 17771cf93e0dSHuang Shijie 17780c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 17791cf93e0dSHuang Shijie if (retval) 17801cf93e0dSHuang Shijie return; 17810c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 17821cf93e0dSHuang Shijie if (retval) { 17830c727a42SFabio Estevam clk_disable(sport->clk_per); 17841cf93e0dSHuang Shijie return; 17851cf93e0dSHuang Shijie } 17869ec1882dSXinyu Chen 1787677fe555SThomas Gleixner if (sport->port.sysrq) 1788677fe555SThomas Gleixner locked = 0; 1789677fe555SThomas Gleixner else if (oops_in_progress) 1790677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1791677fe555SThomas Gleixner else 17929ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1793ab4382d2SGreg Kroah-Hartman 1794ab4382d2SGreg Kroah-Hartman /* 17950ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1796ab4382d2SGreg Kroah-Hartman */ 17970ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 17980ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1799ab4382d2SGreg Kroah-Hartman 1800fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1801fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1802ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1803ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1804ab4382d2SGreg Kroah-Hartman 1805ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1806ab4382d2SGreg Kroah-Hartman 18070ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1808ab4382d2SGreg Kroah-Hartman 1809ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1810ab4382d2SGreg Kroah-Hartman 1811ab4382d2SGreg Kroah-Hartman /* 1812ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 18130ad5a814SDirk Behme * and restore UCR1/2/3 1814ab4382d2SGreg Kroah-Hartman */ 1815ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1816ab4382d2SGreg Kroah-Hartman 18170ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 18189ec1882dSXinyu Chen 1819677fe555SThomas Gleixner if (locked) 18209ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 18211cf93e0dSHuang Shijie 18220c727a42SFabio Estevam clk_disable(sport->clk_ipg); 18230c727a42SFabio Estevam clk_disable(sport->clk_per); 1824ab4382d2SGreg Kroah-Hartman } 1825ab4382d2SGreg Kroah-Hartman 1826ab4382d2SGreg Kroah-Hartman /* 1827ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1828ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1829ab4382d2SGreg Kroah-Hartman */ 1830ab4382d2SGreg Kroah-Hartman static void __init 1831ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1832ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1833ab4382d2SGreg Kroah-Hartman { 1834ab4382d2SGreg Kroah-Hartman 1835ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1836ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1837ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1838ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1839ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1840ab4382d2SGreg Kroah-Hartman 1841ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1842ab4382d2SGreg Kroah-Hartman 1843ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1844ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1845ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1846ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1847ab4382d2SGreg Kroah-Hartman else 1848ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1849ab4382d2SGreg Kroah-Hartman } 1850ab4382d2SGreg Kroah-Hartman 1851ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1852ab4382d2SGreg Kroah-Hartman *bits = 8; 1853ab4382d2SGreg Kroah-Hartman else 1854ab4382d2SGreg Kroah-Hartman *bits = 7; 1855ab4382d2SGreg Kroah-Hartman 1856ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1857ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1858ab4382d2SGreg Kroah-Hartman 1859ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1860ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1861ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1862ab4382d2SGreg Kroah-Hartman else 1863ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1864ab4382d2SGreg Kroah-Hartman 18653a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1866ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1867ab4382d2SGreg Kroah-Hartman 1868ab4382d2SGreg Kroah-Hartman { /* 1869ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1870ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1871ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1872ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1873ab4382d2SGreg Kroah-Hartman */ 1874ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1875ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1876ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1877ab4382d2SGreg Kroah-Hartman 1878ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1879ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1880ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1881ab4382d2SGreg Kroah-Hartman } 1882ab4382d2SGreg Kroah-Hartman 1883ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 188450bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1885ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1886ab4382d2SGreg Kroah-Hartman } 1887ab4382d2SGreg Kroah-Hartman } 1888ab4382d2SGreg Kroah-Hartman 1889ab4382d2SGreg Kroah-Hartman static int __init 1890ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1891ab4382d2SGreg Kroah-Hartman { 1892ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1893ab4382d2SGreg Kroah-Hartman int baud = 9600; 1894ab4382d2SGreg Kroah-Hartman int bits = 8; 1895ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1896ab4382d2SGreg Kroah-Hartman int flow = 'n'; 18971cf93e0dSHuang Shijie int retval; 1898ab4382d2SGreg Kroah-Hartman 1899ab4382d2SGreg Kroah-Hartman /* 1900ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1901ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1902ab4382d2SGreg Kroah-Hartman * console support. 1903ab4382d2SGreg Kroah-Hartman */ 1904ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1905ab4382d2SGreg Kroah-Hartman co->index = 0; 1906ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1907ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1908ab4382d2SGreg Kroah-Hartman return -ENODEV; 1909ab4382d2SGreg Kroah-Hartman 19101cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 19111cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 19121cf93e0dSHuang Shijie if (retval) 19131cf93e0dSHuang Shijie goto error_console; 19141cf93e0dSHuang Shijie 1915ab4382d2SGreg Kroah-Hartman if (options) 1916ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1917ab4382d2SGreg Kroah-Hartman else 1918ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1919ab4382d2SGreg Kroah-Hartman 1920cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1921ab4382d2SGreg Kroah-Hartman 19221cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 19231cf93e0dSHuang Shijie 19240c727a42SFabio Estevam clk_disable(sport->clk_ipg); 19250c727a42SFabio Estevam if (retval) { 19260c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 19270c727a42SFabio Estevam goto error_console; 19280c727a42SFabio Estevam } 19290c727a42SFabio Estevam 19300c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 19310c727a42SFabio Estevam if (retval) 19321cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 19331cf93e0dSHuang Shijie 19341cf93e0dSHuang Shijie error_console: 19351cf93e0dSHuang Shijie return retval; 1936ab4382d2SGreg Kroah-Hartman } 1937ab4382d2SGreg Kroah-Hartman 1938ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1939ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1940ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1941ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1942ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1943ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1944ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1945ab4382d2SGreg Kroah-Hartman .index = -1, 1946ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1947ab4382d2SGreg Kroah-Hartman }; 1948ab4382d2SGreg Kroah-Hartman 1949ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1950913c6c0eSLucas Stach 1951913c6c0eSLucas Stach #ifdef CONFIG_OF 1952913c6c0eSLucas Stach static void imx_console_early_putchar(struct uart_port *port, int ch) 1953913c6c0eSLucas Stach { 1954913c6c0eSLucas Stach while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL) 1955913c6c0eSLucas Stach cpu_relax(); 1956913c6c0eSLucas Stach 1957913c6c0eSLucas Stach writel_relaxed(ch, port->membase + URTX0); 1958913c6c0eSLucas Stach } 1959913c6c0eSLucas Stach 1960913c6c0eSLucas Stach static void imx_console_early_write(struct console *con, const char *s, 1961913c6c0eSLucas Stach unsigned count) 1962913c6c0eSLucas Stach { 1963913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 1964913c6c0eSLucas Stach 1965913c6c0eSLucas Stach uart_console_write(&dev->port, s, count, imx_console_early_putchar); 1966913c6c0eSLucas Stach } 1967913c6c0eSLucas Stach 1968913c6c0eSLucas Stach static int __init 1969913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 1970913c6c0eSLucas Stach { 1971913c6c0eSLucas Stach if (!dev->port.membase) 1972913c6c0eSLucas Stach return -ENODEV; 1973913c6c0eSLucas Stach 1974913c6c0eSLucas Stach dev->con->write = imx_console_early_write; 1975913c6c0eSLucas Stach 1976913c6c0eSLucas Stach return 0; 1977913c6c0eSLucas Stach } 1978913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 1979913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 1980913c6c0eSLucas Stach #endif 1981913c6c0eSLucas Stach 1982ab4382d2SGreg Kroah-Hartman #else 1983ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1984ab4382d2SGreg Kroah-Hartman #endif 1985ab4382d2SGreg Kroah-Hartman 1986ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1987ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1988ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 1989ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 1990ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 1991ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 1992ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 1993ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 1994ab4382d2SGreg Kroah-Hartman }; 1995ab4382d2SGreg Kroah-Hartman 199622698aa2SShawn Guo #ifdef CONFIG_OF 199720bb8095SUwe Kleine-König /* 199820bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 199920bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 200020bb8095SUwe Kleine-König */ 200122698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 200222698aa2SShawn Guo struct platform_device *pdev) 200322698aa2SShawn Guo { 200422698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2005ff05967aSShawn Guo int ret; 200622698aa2SShawn Guo 20075f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 20085f8b9043SLABBE Corentin if (!sport->devdata) 200920bb8095SUwe Kleine-König /* no device tree device */ 201020bb8095SUwe Kleine-König return 1; 201122698aa2SShawn Guo 2012ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2013ff05967aSShawn Guo if (ret < 0) { 2014ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2015a197a191SUwe Kleine-König return ret; 2016ff05967aSShawn Guo } 2017ff05967aSShawn Guo sport->port.line = ret; 201822698aa2SShawn Guo 20191006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 20201006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 202122698aa2SShawn Guo sport->have_rtscts = 1; 202222698aa2SShawn Guo 202320ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 202420ff2fe6SHuang Shijie sport->dte_mode = 1; 202520ff2fe6SHuang Shijie 20267b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 20277b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 20287b7e8e8eSFabio Estevam 202922698aa2SShawn Guo return 0; 203022698aa2SShawn Guo } 203122698aa2SShawn Guo #else 203222698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 203322698aa2SShawn Guo struct platform_device *pdev) 203422698aa2SShawn Guo { 203520bb8095SUwe Kleine-König return 1; 203622698aa2SShawn Guo } 203722698aa2SShawn Guo #endif 203822698aa2SShawn Guo 203922698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 204022698aa2SShawn Guo struct platform_device *pdev) 204122698aa2SShawn Guo { 2042574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 204322698aa2SShawn Guo 204422698aa2SShawn Guo sport->port.line = pdev->id; 204522698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 204622698aa2SShawn Guo 204722698aa2SShawn Guo if (!pdata) 204822698aa2SShawn Guo return; 204922698aa2SShawn Guo 205022698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 205122698aa2SShawn Guo sport->have_rtscts = 1; 205222698aa2SShawn Guo } 205322698aa2SShawn Guo 2054ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 2055ab4382d2SGreg Kroah-Hartman { 2056ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2057ab4382d2SGreg Kroah-Hartman void __iomem *base; 20588a61f0c7SFabio Estevam int ret = 0, reg; 2059ab4382d2SGreg Kroah-Hartman struct resource *res; 2060842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2061ab4382d2SGreg Kroah-Hartman 206242d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2063ab4382d2SGreg Kroah-Hartman if (!sport) 2064ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2065ab4382d2SGreg Kroah-Hartman 206622698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 206720bb8095SUwe Kleine-König if (ret > 0) 206822698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 206920bb8095SUwe Kleine-König else if (ret < 0) 207042d34191SSachin Kamat return ret; 207122698aa2SShawn Guo 2072ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2073da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2074da82f997SAlexander Shiyan if (IS_ERR(base)) 2075da82f997SAlexander Shiyan return PTR_ERR(base); 2076ab4382d2SGreg Kroah-Hartman 2077842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2078842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2079842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2080842633bdSUwe Kleine-König 2081ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2082ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2083ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2084ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2085ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2086842633bdSUwe Kleine-König sport->port.irq = rxirq; 2087ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2088ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 208917b8f2a3SUwe Kleine-König sport->port.rs485_config = imx_rs485_config; 2090ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 2091e99e88a9SKees Cook timer_setup(&sport->timer, imx_timeout, 0); 2092ab4382d2SGreg Kroah-Hartman 209358362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 209458362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 209558362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 209658362d5bSUwe Kleine-König 20973a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 20983a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 20993a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2100833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 210142d34191SSachin Kamat return ret; 2102ab4382d2SGreg Kroah-Hartman } 2103ab4382d2SGreg Kroah-Hartman 21043a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 21053a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 21063a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2107833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 210842d34191SSachin Kamat return ret; 21093a9465faSSascha Hauer } 21103a9465faSSascha Hauer 21113a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2112ab4382d2SGreg Kroah-Hartman 21138a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 21148a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 21151e512d45SUwe Kleine-König if (ret) { 21161e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 21178a61f0c7SFabio Estevam return ret; 21181e512d45SUwe Kleine-König } 21198a61f0c7SFabio Estevam 2120743f93f8SLukas Wunner uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2121743f93f8SLukas Wunner 2122b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 2123b8f3bff0SLukas Wunner (!sport->have_rtscts || !sport->have_rtsgpio)) 2124b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2125b8f3bff0SLukas Wunner 2126b8f3bff0SLukas Wunner imx_rs485_config(&sport->port, &sport->port.rs485); 2127b8f3bff0SLukas Wunner 21288a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 21298a61f0c7SFabio Estevam reg = readl_relaxed(sport->port.membase + UCR1); 21308a61f0c7SFabio Estevam reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 21318a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 21328a61f0c7SFabio Estevam writel_relaxed(reg, sport->port.membase + UCR1); 21338a61f0c7SFabio Estevam 2134e61c38d8SUwe Kleine-König if (!is_imx1_uart(sport) && sport->dte_mode) { 2135e61c38d8SUwe Kleine-König /* 2136e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2137e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2138e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2139e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2140e61c38d8SUwe Kleine-König */ 21416df765dcSUwe Kleine-König reg = readl(sport->port.membase + UFCR); 21426df765dcSUwe Kleine-König if (!(reg & UFCR_DCEDTE)) 21436df765dcSUwe Kleine-König writel(reg | UFCR_DCEDTE, sport->port.membase + UFCR); 2144e61c38d8SUwe Kleine-König 2145e61c38d8SUwe Kleine-König /* 2146e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2147e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2148e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2149e61c38d8SUwe Kleine-König */ 2150e61c38d8SUwe Kleine-König writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2151e61c38d8SUwe Kleine-König sport->port.membase + UCR3); 2152e61c38d8SUwe Kleine-König 2153e61c38d8SUwe Kleine-König } else { 21546df765dcSUwe Kleine-König unsigned long ucr3 = UCR3_DSR; 21556df765dcSUwe Kleine-König 21566df765dcSUwe Kleine-König reg = readl(sport->port.membase + UFCR); 21576df765dcSUwe Kleine-König if (reg & UFCR_DCEDTE) 21586df765dcSUwe Kleine-König writel(reg & ~UFCR_DCEDTE, sport->port.membase + UFCR); 21596df765dcSUwe Kleine-König 21606df765dcSUwe Kleine-König if (!is_imx1_uart(sport)) 21616df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 21626df765dcSUwe Kleine-König writel(ucr3, sport->port.membase + UCR3); 2163e61c38d8SUwe Kleine-König } 2164e61c38d8SUwe Kleine-König 21658a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 21668a61f0c7SFabio Estevam 2167c0d1c6b0SFabio Estevam /* 2168c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2169c0d1c6b0SFabio Estevam * chips only have one interrupt. 2170c0d1c6b0SFabio Estevam */ 2171842633bdSUwe Kleine-König if (txirq > 0) { 2172842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2173c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 21741e512d45SUwe Kleine-König if (ret) { 21751e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 21761e512d45SUwe Kleine-König ret); 2177c0d1c6b0SFabio Estevam return ret; 21781e512d45SUwe Kleine-König } 2179c0d1c6b0SFabio Estevam 2180842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2181c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 21821e512d45SUwe Kleine-König if (ret) { 21831e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 21841e512d45SUwe Kleine-König ret); 2185c0d1c6b0SFabio Estevam return ret; 21861e512d45SUwe Kleine-König } 2187c0d1c6b0SFabio Estevam } else { 2188842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2189c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 21901e512d45SUwe Kleine-König if (ret) { 21911e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2192c0d1c6b0SFabio Estevam return ret; 2193c0d1c6b0SFabio Estevam } 21941e512d45SUwe Kleine-König } 2195c0d1c6b0SFabio Estevam 219622698aa2SShawn Guo imx_ports[sport->port.line] = sport; 2197ab4382d2SGreg Kroah-Hartman 21980a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2199ab4382d2SGreg Kroah-Hartman 220045af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2201ab4382d2SGreg Kroah-Hartman } 2202ab4382d2SGreg Kroah-Hartman 2203ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2204ab4382d2SGreg Kroah-Hartman { 2205ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2206ab4382d2SGreg Kroah-Hartman 220745af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2208ab4382d2SGreg Kroah-Hartman } 2209ab4382d2SGreg Kroah-Hartman 2210c868cbb7SEduardo Valentin static void serial_imx_restore_context(struct imx_port *sport) 2211c868cbb7SEduardo Valentin { 2212c868cbb7SEduardo Valentin if (!sport->context_saved) 2213c868cbb7SEduardo Valentin return; 2214c868cbb7SEduardo Valentin 2215c868cbb7SEduardo Valentin writel(sport->saved_reg[4], sport->port.membase + UFCR); 2216c868cbb7SEduardo Valentin writel(sport->saved_reg[5], sport->port.membase + UESC); 2217c868cbb7SEduardo Valentin writel(sport->saved_reg[6], sport->port.membase + UTIM); 2218c868cbb7SEduardo Valentin writel(sport->saved_reg[7], sport->port.membase + UBIR); 2219c868cbb7SEduardo Valentin writel(sport->saved_reg[8], sport->port.membase + UBMR); 2220c868cbb7SEduardo Valentin writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS); 2221c868cbb7SEduardo Valentin writel(sport->saved_reg[0], sport->port.membase + UCR1); 2222c868cbb7SEduardo Valentin writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2); 2223c868cbb7SEduardo Valentin writel(sport->saved_reg[2], sport->port.membase + UCR3); 2224c868cbb7SEduardo Valentin writel(sport->saved_reg[3], sport->port.membase + UCR4); 2225c868cbb7SEduardo Valentin sport->context_saved = false; 2226c868cbb7SEduardo Valentin } 2227c868cbb7SEduardo Valentin 2228c868cbb7SEduardo Valentin static void serial_imx_save_context(struct imx_port *sport) 2229c868cbb7SEduardo Valentin { 2230c868cbb7SEduardo Valentin /* Save necessary regs */ 2231c868cbb7SEduardo Valentin sport->saved_reg[0] = readl(sport->port.membase + UCR1); 2232c868cbb7SEduardo Valentin sport->saved_reg[1] = readl(sport->port.membase + UCR2); 2233c868cbb7SEduardo Valentin sport->saved_reg[2] = readl(sport->port.membase + UCR3); 2234c868cbb7SEduardo Valentin sport->saved_reg[3] = readl(sport->port.membase + UCR4); 2235c868cbb7SEduardo Valentin sport->saved_reg[4] = readl(sport->port.membase + UFCR); 2236c868cbb7SEduardo Valentin sport->saved_reg[5] = readl(sport->port.membase + UESC); 2237c868cbb7SEduardo Valentin sport->saved_reg[6] = readl(sport->port.membase + UTIM); 2238c868cbb7SEduardo Valentin sport->saved_reg[7] = readl(sport->port.membase + UBIR); 2239c868cbb7SEduardo Valentin sport->saved_reg[8] = readl(sport->port.membase + UBMR); 2240c868cbb7SEduardo Valentin sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS); 2241c868cbb7SEduardo Valentin sport->context_saved = true; 2242c868cbb7SEduardo Valentin } 2243c868cbb7SEduardo Valentin 2244189550b8SEduardo Valentin static void serial_imx_enable_wakeup(struct imx_port *sport, bool on) 2245189550b8SEduardo Valentin { 2246189550b8SEduardo Valentin unsigned int val; 2247189550b8SEduardo Valentin 2248189550b8SEduardo Valentin val = readl(sport->port.membase + UCR3); 224909df0b34SMartin Kaiser if (on) { 225009df0b34SMartin Kaiser writel(USR1_AWAKE, sport->port.membase + USR1); 2251189550b8SEduardo Valentin val |= UCR3_AWAKEN; 225209df0b34SMartin Kaiser } 2253189550b8SEduardo Valentin else 2254189550b8SEduardo Valentin val &= ~UCR3_AWAKEN; 2255189550b8SEduardo Valentin writel(val, sport->port.membase + UCR3); 2256bc85734bSEduardo Valentin 225738b1f0fbSFabio Estevam if (sport->have_rtscts) { 2258bc85734bSEduardo Valentin val = readl(sport->port.membase + UCR1); 2259bc85734bSEduardo Valentin if (on) 2260bc85734bSEduardo Valentin val |= UCR1_RTSDEN; 2261bc85734bSEduardo Valentin else 2262bc85734bSEduardo Valentin val &= ~UCR1_RTSDEN; 2263bc85734bSEduardo Valentin writel(val, sport->port.membase + UCR1); 2264189550b8SEduardo Valentin } 226538b1f0fbSFabio Estevam } 2266189550b8SEduardo Valentin 226790bb6bd3SShenwei Wang static int imx_serial_port_suspend_noirq(struct device *dev) 226890bb6bd3SShenwei Wang { 226990bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 227090bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 227190bb6bd3SShenwei Wang 2272c868cbb7SEduardo Valentin serial_imx_save_context(sport); 227390bb6bd3SShenwei Wang 227490bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 227590bb6bd3SShenwei Wang 227690bb6bd3SShenwei Wang return 0; 227790bb6bd3SShenwei Wang } 227890bb6bd3SShenwei Wang 227990bb6bd3SShenwei Wang static int imx_serial_port_resume_noirq(struct device *dev) 228090bb6bd3SShenwei Wang { 228190bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 228290bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 228390bb6bd3SShenwei Wang int ret; 228490bb6bd3SShenwei Wang 228590bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 228690bb6bd3SShenwei Wang if (ret) 228790bb6bd3SShenwei Wang return ret; 228890bb6bd3SShenwei Wang 2289c868cbb7SEduardo Valentin serial_imx_restore_context(sport); 229090bb6bd3SShenwei Wang 229190bb6bd3SShenwei Wang return 0; 229290bb6bd3SShenwei Wang } 229390bb6bd3SShenwei Wang 229490bb6bd3SShenwei Wang static int imx_serial_port_suspend(struct device *dev) 229590bb6bd3SShenwei Wang { 229690bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 229790bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 229809df0b34SMartin Kaiser int ret; 229990bb6bd3SShenwei Wang 230090bb6bd3SShenwei Wang uart_suspend_port(&imx_reg, &sport->port); 230181b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 230290bb6bd3SShenwei Wang 230309df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 230409df0b34SMartin Kaiser if (ret) 230509df0b34SMartin Kaiser return ret; 230609df0b34SMartin Kaiser 230709df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 230809df0b34SMartin Kaiser serial_imx_enable_wakeup(sport, true); 230909df0b34SMartin Kaiser 231009df0b34SMartin Kaiser return 0; 231190bb6bd3SShenwei Wang } 231290bb6bd3SShenwei Wang 231390bb6bd3SShenwei Wang static int imx_serial_port_resume(struct device *dev) 231490bb6bd3SShenwei Wang { 231590bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 231690bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 231790bb6bd3SShenwei Wang 231890bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 2319189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, false); 232090bb6bd3SShenwei Wang 232190bb6bd3SShenwei Wang uart_resume_port(&imx_reg, &sport->port); 232281b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 232390bb6bd3SShenwei Wang 232409df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 232529add68dSMartin Fuzzey 232690bb6bd3SShenwei Wang return 0; 232790bb6bd3SShenwei Wang } 232890bb6bd3SShenwei Wang 232994be6d74SPhilipp Zabel static int imx_serial_port_freeze(struct device *dev) 233094be6d74SPhilipp Zabel { 233194be6d74SPhilipp Zabel struct platform_device *pdev = to_platform_device(dev); 233294be6d74SPhilipp Zabel struct imx_port *sport = platform_get_drvdata(pdev); 233394be6d74SPhilipp Zabel 233494be6d74SPhilipp Zabel uart_suspend_port(&imx_reg, &sport->port); 233594be6d74SPhilipp Zabel 233609df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 233794be6d74SPhilipp Zabel } 233894be6d74SPhilipp Zabel 233994be6d74SPhilipp Zabel static int imx_serial_port_thaw(struct device *dev) 234094be6d74SPhilipp Zabel { 234194be6d74SPhilipp Zabel struct platform_device *pdev = to_platform_device(dev); 234294be6d74SPhilipp Zabel struct imx_port *sport = platform_get_drvdata(pdev); 234394be6d74SPhilipp Zabel 234494be6d74SPhilipp Zabel uart_resume_port(&imx_reg, &sport->port); 234594be6d74SPhilipp Zabel 234609df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 234794be6d74SPhilipp Zabel 234894be6d74SPhilipp Zabel return 0; 234994be6d74SPhilipp Zabel } 235094be6d74SPhilipp Zabel 235190bb6bd3SShenwei Wang static const struct dev_pm_ops imx_serial_port_pm_ops = { 235290bb6bd3SShenwei Wang .suspend_noirq = imx_serial_port_suspend_noirq, 235390bb6bd3SShenwei Wang .resume_noirq = imx_serial_port_resume_noirq, 235494be6d74SPhilipp Zabel .freeze_noirq = imx_serial_port_suspend_noirq, 235594be6d74SPhilipp Zabel .restore_noirq = imx_serial_port_resume_noirq, 235690bb6bd3SShenwei Wang .suspend = imx_serial_port_suspend, 235790bb6bd3SShenwei Wang .resume = imx_serial_port_resume, 235894be6d74SPhilipp Zabel .freeze = imx_serial_port_freeze, 235994be6d74SPhilipp Zabel .thaw = imx_serial_port_thaw, 236094be6d74SPhilipp Zabel .restore = imx_serial_port_thaw, 236190bb6bd3SShenwei Wang }; 236290bb6bd3SShenwei Wang 2363ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2364ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2365ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2366ab4382d2SGreg Kroah-Hartman 2367fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2368ab4382d2SGreg Kroah-Hartman .driver = { 2369ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 237022698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 237190bb6bd3SShenwei Wang .pm = &imx_serial_port_pm_ops, 2372ab4382d2SGreg Kroah-Hartman }, 2373ab4382d2SGreg Kroah-Hartman }; 2374ab4382d2SGreg Kroah-Hartman 2375ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2376ab4382d2SGreg Kroah-Hartman { 2377f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2378ab4382d2SGreg Kroah-Hartman 2379ab4382d2SGreg Kroah-Hartman if (ret) 2380ab4382d2SGreg Kroah-Hartman return ret; 2381ab4382d2SGreg Kroah-Hartman 2382ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2383ab4382d2SGreg Kroah-Hartman if (ret != 0) 2384ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2385ab4382d2SGreg Kroah-Hartman 2386f227824eSUwe Kleine-König return ret; 2387ab4382d2SGreg Kroah-Hartman } 2388ab4382d2SGreg Kroah-Hartman 2389ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2390ab4382d2SGreg Kroah-Hartman { 2391ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2392ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2393ab4382d2SGreg Kroah-Hartman } 2394ab4382d2SGreg Kroah-Hartman 2395ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2396ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2397ab4382d2SGreg Kroah-Hartman 2398ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2399ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2400ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2401ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2402