1ab4382d2SGreg Kroah-Hartman /* 2ab4382d2SGreg Kroah-Hartman * Driver for Motorola IMX serial ports 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 7ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 8ab4382d2SGreg Kroah-Hartman * 9ab4382d2SGreg Kroah-Hartman * Copyright (C) 2009 emlix GmbH 10ab4382d2SGreg Kroah-Hartman * Author: Fabian Godehardt (added IrDA support for iMX) 11ab4382d2SGreg Kroah-Hartman * 12ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 13ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 14ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2 of the License, or 15ab4382d2SGreg Kroah-Hartman * (at your option) any later version. 16ab4382d2SGreg Kroah-Hartman * 17ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 18ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY; without even the implied warranty of 19ab4382d2SGreg Kroah-Hartman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20ab4382d2SGreg Kroah-Hartman * GNU General Public License for more details. 21ab4382d2SGreg Kroah-Hartman * 22ab4382d2SGreg Kroah-Hartman * You should have received a copy of the GNU General Public License 23ab4382d2SGreg Kroah-Hartman * along with this program; if not, write to the Free Software 24ab4382d2SGreg Kroah-Hartman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25ab4382d2SGreg Kroah-Hartman * 26ab4382d2SGreg Kroah-Hartman * [29-Mar-2005] Mike Lee 27ab4382d2SGreg Kroah-Hartman * Added hardware handshake 28ab4382d2SGreg Kroah-Hartman */ 29ab4382d2SGreg Kroah-Hartman 30ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 31ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 32ab4382d2SGreg Kroah-Hartman #endif 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 35ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 36ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 37ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 38ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 39ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 40ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 41ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 42ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 43ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 44ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 45ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 46ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 47ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 4822698aa2SShawn Guo #include <linux/of.h> 4922698aa2SShawn Guo #include <linux/of_device.h> 50e32a9f8fSSachin Kamat #include <linux/io.h> 51b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 52ab4382d2SGreg Kroah-Hartman 53ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 5482906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 55b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 56ab4382d2SGreg Kroah-Hartman 57ab4382d2SGreg Kroah-Hartman /* Register definitions */ 58ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 59ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 60ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 61ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 62ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 63ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 64ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 65ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 66ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 67ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 68ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 69ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 70ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 71ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 72fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 73fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 74fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 75ab4382d2SGreg Kroah-Hartman 76ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 77ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 78ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 79ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 80ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 81ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 82ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 8326c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 8425985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 85ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 86ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 88b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 89ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 91ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 93ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 94ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 95ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 96fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 97b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 99ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 100ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 101ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 102ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 103ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 104ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 105ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 107ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 108ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 109ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 11001f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 111ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 112ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 113ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 114ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 115ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 118ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 119ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 120b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 121ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 124fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 125ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 126ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 127ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 128ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 129ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 130ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 131ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 132ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 133b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 134ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 135ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 136ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 137ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 138ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 139ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1407be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 141ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 142ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 143ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 144ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 146ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 147ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 148ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 150ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 151ab4382d2SGreg Kroah-Hartman #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 152ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 153ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 154ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 155ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 156ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 157ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 158ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 159ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 160ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 161ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 162ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 163ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 164ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 165ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 166ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 167ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 168ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 169ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 170ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 171ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 172ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 173ab4382d2SGreg Kroah-Hartman 174ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 175ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 176ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 177ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 178ab4382d2SGreg Kroah-Hartman 179ab4382d2SGreg Kroah-Hartman /* 180ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 181ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 182ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 183ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 184ab4382d2SGreg Kroah-Hartman */ 185ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 186ab4382d2SGreg Kroah-Hartman 187ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 188ab4382d2SGreg Kroah-Hartman 189ab4382d2SGreg Kroah-Hartman #define UART_NR 8 190ab4382d2SGreg Kroah-Hartman 191fe6b540aSShawn Guo /* i.mx21 type uart runs on all i.mx except i.mx1 */ 192fe6b540aSShawn Guo enum imx_uart_type { 193fe6b540aSShawn Guo IMX1_UART, 194fe6b540aSShawn Guo IMX21_UART, 195a496e628SHuang Shijie IMX6Q_UART, 196fe6b540aSShawn Guo }; 197fe6b540aSShawn Guo 198fe6b540aSShawn Guo /* device type dependent stuff */ 199fe6b540aSShawn Guo struct imx_uart_data { 200fe6b540aSShawn Guo unsigned uts_reg; 201fe6b540aSShawn Guo enum imx_uart_type devtype; 202fe6b540aSShawn Guo }; 203fe6b540aSShawn Guo 204ab4382d2SGreg Kroah-Hartman struct imx_port { 205ab4382d2SGreg Kroah-Hartman struct uart_port port; 206ab4382d2SGreg Kroah-Hartman struct timer_list timer; 207ab4382d2SGreg Kroah-Hartman unsigned int old_status; 208ab4382d2SGreg Kroah-Hartman int txirq, rxirq, rtsirq; 209ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 21020ff2fe6SHuang Shijie unsigned int dte_mode:1; 211ab4382d2SGreg Kroah-Hartman unsigned int use_irda:1; 212ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_rx:1; 213ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_tx:1; 214ab4382d2SGreg Kroah-Hartman unsigned short trcv_delay; /* transceiver delay */ 2153a9465faSSascha Hauer struct clk *clk_ipg; 2163a9465faSSascha Hauer struct clk *clk_per; 2177d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 218b4cdc8f6SHuang Shijie 219b4cdc8f6SHuang Shijie /* DMA fields */ 220b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 221b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 224b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 225b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 226b4cdc8f6SHuang Shijie void *rx_buf; 2277cb92fd2SHuang Shijie unsigned int tx_bytes; 228b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 2299ce4f8f3SGreg Kroah-Hartman wait_queue_head_t dma_wait; 230ab4382d2SGreg Kroah-Hartman }; 231ab4382d2SGreg Kroah-Hartman 2320ad5a814SDirk Behme struct imx_port_ucrs { 2330ad5a814SDirk Behme unsigned int ucr1; 2340ad5a814SDirk Behme unsigned int ucr2; 2350ad5a814SDirk Behme unsigned int ucr3; 2360ad5a814SDirk Behme }; 2370ad5a814SDirk Behme 238ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_IRDA 239ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) ((sport)->use_irda) 240ab4382d2SGreg Kroah-Hartman #else 241ab4382d2SGreg Kroah-Hartman #define USE_IRDA(sport) (0) 242ab4382d2SGreg Kroah-Hartman #endif 243ab4382d2SGreg Kroah-Hartman 244fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 245fe6b540aSShawn Guo [IMX1_UART] = { 246fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 247fe6b540aSShawn Guo .devtype = IMX1_UART, 248fe6b540aSShawn Guo }, 249fe6b540aSShawn Guo [IMX21_UART] = { 250fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 251fe6b540aSShawn Guo .devtype = IMX21_UART, 252fe6b540aSShawn Guo }, 253a496e628SHuang Shijie [IMX6Q_UART] = { 254a496e628SHuang Shijie .uts_reg = IMX21_UTS, 255a496e628SHuang Shijie .devtype = IMX6Q_UART, 256a496e628SHuang Shijie }, 257fe6b540aSShawn Guo }; 258fe6b540aSShawn Guo 259fe6b540aSShawn Guo static struct platform_device_id imx_uart_devtype[] = { 260fe6b540aSShawn Guo { 261fe6b540aSShawn Guo .name = "imx1-uart", 262fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 263fe6b540aSShawn Guo }, { 264fe6b540aSShawn Guo .name = "imx21-uart", 265fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 266fe6b540aSShawn Guo }, { 267a496e628SHuang Shijie .name = "imx6q-uart", 268a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 269a496e628SHuang Shijie }, { 270fe6b540aSShawn Guo /* sentinel */ 271fe6b540aSShawn Guo } 272fe6b540aSShawn Guo }; 273fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 274fe6b540aSShawn Guo 27522698aa2SShawn Guo static struct of_device_id imx_uart_dt_ids[] = { 276a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 27722698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27822698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27922698aa2SShawn Guo { /* sentinel */ } 28022698aa2SShawn Guo }; 28122698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28222698aa2SShawn Guo 283fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 284fe6b540aSShawn Guo { 285fe6b540aSShawn Guo return sport->devdata->uts_reg; 286fe6b540aSShawn Guo } 287fe6b540aSShawn Guo 288fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 289fe6b540aSShawn Guo { 290fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 291fe6b540aSShawn Guo } 292fe6b540aSShawn Guo 293fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 294fe6b540aSShawn Guo { 295fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 296fe6b540aSShawn Guo } 297fe6b540aSShawn Guo 298a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 299a496e628SHuang Shijie { 300a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 301a496e628SHuang Shijie } 302ab4382d2SGreg Kroah-Hartman /* 30344a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 30444a75411Sfabio.estevam@freescale.com */ 305e8bfa760SFabio Estevam #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE) 30644a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 30744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30844a75411Sfabio.estevam@freescale.com { 30944a75411Sfabio.estevam@freescale.com /* save control registers */ 31044a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 31144a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 31244a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 31344a75411Sfabio.estevam@freescale.com } 31444a75411Sfabio.estevam@freescale.com 31544a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 31644a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 31744a75411Sfabio.estevam@freescale.com { 31844a75411Sfabio.estevam@freescale.com /* restore control registers */ 31944a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 32044a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 32144a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 32244a75411Sfabio.estevam@freescale.com } 323e8bfa760SFabio Estevam #endif 32444a75411Sfabio.estevam@freescale.com 32544a75411Sfabio.estevam@freescale.com /* 326ab4382d2SGreg Kroah-Hartman * Handle any change of modem status signal since we were last called. 327ab4382d2SGreg Kroah-Hartman */ 328ab4382d2SGreg Kroah-Hartman static void imx_mctrl_check(struct imx_port *sport) 329ab4382d2SGreg Kroah-Hartman { 330ab4382d2SGreg Kroah-Hartman unsigned int status, changed; 331ab4382d2SGreg Kroah-Hartman 332ab4382d2SGreg Kroah-Hartman status = sport->port.ops->get_mctrl(&sport->port); 333ab4382d2SGreg Kroah-Hartman changed = status ^ sport->old_status; 334ab4382d2SGreg Kroah-Hartman 335ab4382d2SGreg Kroah-Hartman if (changed == 0) 336ab4382d2SGreg Kroah-Hartman return; 337ab4382d2SGreg Kroah-Hartman 338ab4382d2SGreg Kroah-Hartman sport->old_status = status; 339ab4382d2SGreg Kroah-Hartman 340ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_RI) 341ab4382d2SGreg Kroah-Hartman sport->port.icount.rng++; 342ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_DSR) 343ab4382d2SGreg Kroah-Hartman sport->port.icount.dsr++; 344ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CAR) 345ab4382d2SGreg Kroah-Hartman uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 346ab4382d2SGreg Kroah-Hartman if (changed & TIOCM_CTS) 347ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 348ab4382d2SGreg Kroah-Hartman 349ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 350ab4382d2SGreg Kroah-Hartman } 351ab4382d2SGreg Kroah-Hartman 352ab4382d2SGreg Kroah-Hartman /* 353ab4382d2SGreg Kroah-Hartman * This is our per-port timeout handler, for checking the 354ab4382d2SGreg Kroah-Hartman * modem status signals. 355ab4382d2SGreg Kroah-Hartman */ 356ab4382d2SGreg Kroah-Hartman static void imx_timeout(unsigned long data) 357ab4382d2SGreg Kroah-Hartman { 358ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)data; 359ab4382d2SGreg Kroah-Hartman unsigned long flags; 360ab4382d2SGreg Kroah-Hartman 361ab4382d2SGreg Kroah-Hartman if (sport->port.state) { 362ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 363ab4382d2SGreg Kroah-Hartman imx_mctrl_check(sport); 364ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 365ab4382d2SGreg Kroah-Hartman 366ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 367ab4382d2SGreg Kroah-Hartman } 368ab4382d2SGreg Kroah-Hartman } 369ab4382d2SGreg Kroah-Hartman 370ab4382d2SGreg Kroah-Hartman /* 371ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 372ab4382d2SGreg Kroah-Hartman */ 373ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 374ab4382d2SGreg Kroah-Hartman { 375ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 376ab4382d2SGreg Kroah-Hartman unsigned long temp; 377ab4382d2SGreg Kroah-Hartman 378ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 379ab4382d2SGreg Kroah-Hartman /* half duplex - wait for end of transmission */ 380ab4382d2SGreg Kroah-Hartman int n = 256; 381ab4382d2SGreg Kroah-Hartman while ((--n > 0) && 382ab4382d2SGreg Kroah-Hartman !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 383ab4382d2SGreg Kroah-Hartman udelay(5); 384ab4382d2SGreg Kroah-Hartman barrier(); 385ab4382d2SGreg Kroah-Hartman } 386ab4382d2SGreg Kroah-Hartman /* 387ab4382d2SGreg Kroah-Hartman * irda transceiver - wait a bit more to avoid 388ab4382d2SGreg Kroah-Hartman * cutoff, hardware dependent 389ab4382d2SGreg Kroah-Hartman */ 390ab4382d2SGreg Kroah-Hartman udelay(sport->trcv_delay); 391ab4382d2SGreg Kroah-Hartman 392ab4382d2SGreg Kroah-Hartman /* 393ab4382d2SGreg Kroah-Hartman * half duplex - reactivate receive mode, 394ab4382d2SGreg Kroah-Hartman * flush receive pipe echo crap 395ab4382d2SGreg Kroah-Hartman */ 396ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR2) & USR2_TXDC) { 397ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 398ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); 399ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 400ab4382d2SGreg Kroah-Hartman 401ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 402ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_TCEN); 403ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 404ab4382d2SGreg Kroah-Hartman 405ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + URXD0) & 406ab4382d2SGreg Kroah-Hartman URXD_CHARRDY) 407ab4382d2SGreg Kroah-Hartman barrier(); 408ab4382d2SGreg Kroah-Hartman 409ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 410ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN; 411ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 412ab4382d2SGreg Kroah-Hartman 413ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 414ab4382d2SGreg Kroah-Hartman temp |= UCR4_DREN; 415ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 416ab4382d2SGreg Kroah-Hartman } 417ab4382d2SGreg Kroah-Hartman return; 418ab4382d2SGreg Kroah-Hartman } 419ab4382d2SGreg Kroah-Hartman 4209ce4f8f3SGreg Kroah-Hartman /* 4219ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4229ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4239ce4f8f3SGreg Kroah-Hartman */ 4249ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 4259ce4f8f3SGreg Kroah-Hartman return; 426b4cdc8f6SHuang Shijie 427ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 428ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); 429ab4382d2SGreg Kroah-Hartman } 430ab4382d2SGreg Kroah-Hartman 431ab4382d2SGreg Kroah-Hartman /* 432ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 433ab4382d2SGreg Kroah-Hartman */ 434ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 435ab4382d2SGreg Kroah-Hartman { 436ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 437ab4382d2SGreg Kroah-Hartman unsigned long temp; 438ab4382d2SGreg Kroah-Hartman 4399ce4f8f3SGreg Kroah-Hartman /* 4409ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4419ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4429ce4f8f3SGreg Kroah-Hartman */ 4439ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_rxing) 4449ce4f8f3SGreg Kroah-Hartman return; 445b4cdc8f6SHuang Shijie 446ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 447ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 44885878399SHuang Shijie 44985878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 45085878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 45185878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 452ab4382d2SGreg Kroah-Hartman } 453ab4382d2SGreg Kroah-Hartman 454ab4382d2SGreg Kroah-Hartman /* 455ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 456ab4382d2SGreg Kroah-Hartman */ 457ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 458ab4382d2SGreg Kroah-Hartman { 459ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 460ab4382d2SGreg Kroah-Hartman 461ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 462ab4382d2SGreg Kroah-Hartman } 463ab4382d2SGreg Kroah-Hartman 464ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 465ab4382d2SGreg Kroah-Hartman { 466ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 467ab4382d2SGreg Kroah-Hartman 4685e42e9a3SPeter Hurley if (sport->port.x_char) { 4695e42e9a3SPeter Hurley /* Send next char */ 4705e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4715e42e9a3SPeter Hurley return; 4725e42e9a3SPeter Hurley } 4735e42e9a3SPeter Hurley 4745e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4755e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4765e42e9a3SPeter Hurley return; 4775e42e9a3SPeter Hurley } 4785e42e9a3SPeter Hurley 479ab4382d2SGreg Kroah-Hartman while (!uart_circ_empty(xmit) && 4805e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 481ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 482ab4382d2SGreg Kroah-Hartman * out the port here */ 483ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 484ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 485ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 486ab4382d2SGreg Kroah-Hartman } 487ab4382d2SGreg Kroah-Hartman 488ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 489ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 490ab4382d2SGreg Kroah-Hartman 491ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 492ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 493ab4382d2SGreg Kroah-Hartman } 494ab4382d2SGreg Kroah-Hartman 495b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 496b4cdc8f6SHuang Shijie { 497b4cdc8f6SHuang Shijie struct imx_port *sport = data; 498b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 499b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 500b4cdc8f6SHuang Shijie unsigned long flags; 501b4cdc8f6SHuang Shijie 502b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 503b4cdc8f6SHuang Shijie 504b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 505b4cdc8f6SHuang Shijie 506b4cdc8f6SHuang Shijie /* update the stat */ 507b4cdc8f6SHuang Shijie spin_lock_irqsave(&sport->port.lock, flags); 508b4cdc8f6SHuang Shijie xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 509b4cdc8f6SHuang Shijie sport->port.icount.tx += sport->tx_bytes; 510b4cdc8f6SHuang Shijie spin_unlock_irqrestore(&sport->port.lock, flags); 511b4cdc8f6SHuang Shijie 512b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 513b4cdc8f6SHuang Shijie 514b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5159ce4f8f3SGreg Kroah-Hartman 5169ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) { 5179ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 5189ce4f8f3SGreg Kroah-Hartman dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 5199ce4f8f3SGreg Kroah-Hartman return; 5209ce4f8f3SGreg Kroah-Hartman } 521b4cdc8f6SHuang Shijie } 522b4cdc8f6SHuang Shijie 5237cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 524b4cdc8f6SHuang Shijie { 525b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 526b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 527b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 528b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 529b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 530b4cdc8f6SHuang Shijie enum dma_status status; 531b4cdc8f6SHuang Shijie int ret; 532b4cdc8f6SHuang Shijie 533f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL); 534b4cdc8f6SHuang Shijie if (DMA_IN_PROGRESS == status) 535b4cdc8f6SHuang Shijie return; 536b4cdc8f6SHuang Shijie 537b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 538b4cdc8f6SHuang Shijie 539947c74ebSHuang Shijie if (xmit->tail > xmit->head && xmit->head > 0) { 540b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 541b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 542b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 543b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 544b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 545b4cdc8f6SHuang Shijie } else { 546b4cdc8f6SHuang Shijie sport->dma_tx_nents = 1; 547b4cdc8f6SHuang Shijie sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 548b4cdc8f6SHuang Shijie } 549b4cdc8f6SHuang Shijie 550b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 551b4cdc8f6SHuang Shijie if (ret == 0) { 552b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 553b4cdc8f6SHuang Shijie return; 554b4cdc8f6SHuang Shijie } 555b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 556b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 557b4cdc8f6SHuang Shijie if (!desc) { 558b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 559b4cdc8f6SHuang Shijie return; 560b4cdc8f6SHuang Shijie } 561b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 562b4cdc8f6SHuang Shijie desc->callback_param = sport; 563b4cdc8f6SHuang Shijie 564b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 565b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 566b4cdc8f6SHuang Shijie /* fire it */ 567b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 568b4cdc8f6SHuang Shijie dmaengine_submit(desc); 569b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 570b4cdc8f6SHuang Shijie return; 571b4cdc8f6SHuang Shijie } 572b4cdc8f6SHuang Shijie 573ab4382d2SGreg Kroah-Hartman /* 574ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 575ab4382d2SGreg Kroah-Hartman */ 576ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 577ab4382d2SGreg Kroah-Hartman { 578ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 579ab4382d2SGreg Kroah-Hartman unsigned long temp; 580ab4382d2SGreg Kroah-Hartman 581ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 582ab4382d2SGreg Kroah-Hartman /* half duplex in IrDA mode; have to disable receive mode */ 583ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 584ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_DREN); 585ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 586ab4382d2SGreg Kroah-Hartman 587ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 588ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RRDYEN); 589ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 590ab4382d2SGreg Kroah-Hartman } 591f1f836e4SAlexander Stein /* Clear any pending ORE flag before enabling interrupt */ 592f1f836e4SAlexander Stein temp = readl(sport->port.membase + USR2); 593f1f836e4SAlexander Stein writel(temp | USR2_ORE, sport->port.membase + USR2); 594f1f836e4SAlexander Stein 595f1f836e4SAlexander Stein temp = readl(sport->port.membase + UCR4); 596f1f836e4SAlexander Stein temp |= UCR4_OREN; 597f1f836e4SAlexander Stein writel(temp, sport->port.membase + UCR4); 598ab4382d2SGreg Kroah-Hartman 599b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 600ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 601ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 602b4cdc8f6SHuang Shijie } 603ab4382d2SGreg Kroah-Hartman 604ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 605ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 606ab4382d2SGreg Kroah-Hartman temp |= UCR1_TRDYEN; 607ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 608ab4382d2SGreg Kroah-Hartman 609ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 610ab4382d2SGreg Kroah-Hartman temp |= UCR4_TCEN; 611ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR4); 612ab4382d2SGreg Kroah-Hartman } 613ab4382d2SGreg Kroah-Hartman 614b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 6155e42e9a3SPeter Hurley /* FIXME: port->x_char must be transmitted if != 0 */ 6165e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6175e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6187cb92fd2SHuang Shijie imx_dma_tx(sport); 619b4cdc8f6SHuang Shijie return; 620b4cdc8f6SHuang Shijie } 621b4cdc8f6SHuang Shijie 622fe6b540aSShawn Guo if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) 623ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 624ab4382d2SGreg Kroah-Hartman } 625ab4382d2SGreg Kroah-Hartman 626ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 627ab4382d2SGreg Kroah-Hartman { 628ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6295680e941SUwe Kleine-König unsigned int val; 630ab4382d2SGreg Kroah-Hartman unsigned long flags; 631ab4382d2SGreg Kroah-Hartman 632ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 633ab4382d2SGreg Kroah-Hartman 634ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6355680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 636ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 637ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 638ab4382d2SGreg Kroah-Hartman 639ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 640ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 641ab4382d2SGreg Kroah-Hartman } 642ab4382d2SGreg Kroah-Hartman 643ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 644ab4382d2SGreg Kroah-Hartman { 645ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 646ab4382d2SGreg Kroah-Hartman unsigned long flags; 647ab4382d2SGreg Kroah-Hartman 648ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 649ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 650ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 651ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 652ab4382d2SGreg Kroah-Hartman } 653ab4382d2SGreg Kroah-Hartman 654ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 655ab4382d2SGreg Kroah-Hartman { 656ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 657ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 65892a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 659ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 660ab4382d2SGreg Kroah-Hartman 661ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 662ab4382d2SGreg Kroah-Hartman 663ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 664ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 665ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 666ab4382d2SGreg Kroah-Hartman 667ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 668ab4382d2SGreg Kroah-Hartman 669ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 670ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 671ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 672ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 673ab4382d2SGreg Kroah-Hartman continue; 674ab4382d2SGreg Kroah-Hartman } 675ab4382d2SGreg Kroah-Hartman 676ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 677ab4382d2SGreg Kroah-Hartman continue; 678ab4382d2SGreg Kroah-Hartman 679019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 680019dc9eaSHui Wang if (rx & URXD_BRK) 681019dc9eaSHui Wang sport->port.icount.brk++; 682019dc9eaSHui Wang else if (rx & URXD_PRERR) 683ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 684ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 685ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 686ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 687ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 688ab4382d2SGreg Kroah-Hartman 689ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 690ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 691ab4382d2SGreg Kroah-Hartman goto out; 692ab4382d2SGreg Kroah-Hartman continue; 693ab4382d2SGreg Kroah-Hartman } 694ab4382d2SGreg Kroah-Hartman 695ab4382d2SGreg Kroah-Hartman rx &= sport->port.read_status_mask; 696ab4382d2SGreg Kroah-Hartman 697019dc9eaSHui Wang if (rx & URXD_BRK) 698019dc9eaSHui Wang flg = TTY_BREAK; 699019dc9eaSHui Wang else if (rx & URXD_PRERR) 700ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 701ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 702ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 703ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 704ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 705ab4382d2SGreg Kroah-Hartman 706ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 707ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 708ab4382d2SGreg Kroah-Hartman #endif 709ab4382d2SGreg Kroah-Hartman } 710ab4382d2SGreg Kroah-Hartman 71192a19f9cSJiri Slaby tty_insert_flip_char(port, rx, flg); 712ab4382d2SGreg Kroah-Hartman } 713ab4382d2SGreg Kroah-Hartman 714ab4382d2SGreg Kroah-Hartman out: 715ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7162e124b4aSJiri Slaby tty_flip_buffer_push(port); 717ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 718ab4382d2SGreg Kroah-Hartman } 719ab4382d2SGreg Kroah-Hartman 7207cb92fd2SHuang Shijie static int start_rx_dma(struct imx_port *sport); 721b4cdc8f6SHuang Shijie /* 722b4cdc8f6SHuang Shijie * If the RXFIFO is filled with some data, and then we 723b4cdc8f6SHuang Shijie * arise a DMA operation to receive them. 724b4cdc8f6SHuang Shijie */ 725b4cdc8f6SHuang Shijie static void imx_dma_rxint(struct imx_port *sport) 726b4cdc8f6SHuang Shijie { 727b4cdc8f6SHuang Shijie unsigned long temp; 728b4cdc8f6SHuang Shijie 729b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + USR2); 730b4cdc8f6SHuang Shijie if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 731b4cdc8f6SHuang Shijie sport->dma_is_rxing = 1; 732b4cdc8f6SHuang Shijie 733b4cdc8f6SHuang Shijie /* disable the `Recerver Ready Interrrupt` */ 734b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 735b4cdc8f6SHuang Shijie temp &= ~(UCR1_RRDYEN); 736b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 737b4cdc8f6SHuang Shijie 738b4cdc8f6SHuang Shijie /* tell the DMA to receive the data. */ 7397cb92fd2SHuang Shijie start_rx_dma(sport); 740b4cdc8f6SHuang Shijie } 741b4cdc8f6SHuang Shijie } 742b4cdc8f6SHuang Shijie 743ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 744ab4382d2SGreg Kroah-Hartman { 745ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 746ab4382d2SGreg Kroah-Hartman unsigned int sts; 747f1f836e4SAlexander Stein unsigned int sts2; 748ab4382d2SGreg Kroah-Hartman 749ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 750ab4382d2SGreg Kroah-Hartman 751b4cdc8f6SHuang Shijie if (sts & USR1_RRDY) { 752b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) 753b4cdc8f6SHuang Shijie imx_dma_rxint(sport); 754b4cdc8f6SHuang Shijie else 755ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 756b4cdc8f6SHuang Shijie } 757ab4382d2SGreg Kroah-Hartman 758ab4382d2SGreg Kroah-Hartman if (sts & USR1_TRDY && 759ab4382d2SGreg Kroah-Hartman readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) 760ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 761ab4382d2SGreg Kroah-Hartman 762ab4382d2SGreg Kroah-Hartman if (sts & USR1_RTSD) 763ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 764ab4382d2SGreg Kroah-Hartman 765db1a9b55SFabio Estevam if (sts & USR1_AWAKE) 766db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 767db1a9b55SFabio Estevam 768f1f836e4SAlexander Stein sts2 = readl(sport->port.membase + USR2); 769f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 770f1f836e4SAlexander Stein dev_err(sport->port.dev, "Rx FIFO overrun\n"); 771f1f836e4SAlexander Stein sport->port.icount.overrun++; 772f1f836e4SAlexander Stein writel(sts2 | USR2_ORE, sport->port.membase + USR2); 773f1f836e4SAlexander Stein } 774f1f836e4SAlexander Stein 775ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 776ab4382d2SGreg Kroah-Hartman } 777ab4382d2SGreg Kroah-Hartman 778ab4382d2SGreg Kroah-Hartman /* 779ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 780ab4382d2SGreg Kroah-Hartman */ 781ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 782ab4382d2SGreg Kroah-Hartman { 783ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 7841ce43e58SHuang Shijie unsigned int ret; 785ab4382d2SGreg Kroah-Hartman 7861ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 7871ce43e58SHuang Shijie 7881ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 7891ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 7901ce43e58SHuang Shijie ret = 0; 7911ce43e58SHuang Shijie 7921ce43e58SHuang Shijie return ret; 793ab4382d2SGreg Kroah-Hartman } 794ab4382d2SGreg Kroah-Hartman 795ab4382d2SGreg Kroah-Hartman /* 796ab4382d2SGreg Kroah-Hartman * We have a modem side uart, so the meanings of RTS and CTS are inverted. 797ab4382d2SGreg Kroah-Hartman */ 798ab4382d2SGreg Kroah-Hartman static unsigned int imx_get_mctrl(struct uart_port *port) 799ab4382d2SGreg Kroah-Hartman { 800ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 801ab4382d2SGreg Kroah-Hartman unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 802ab4382d2SGreg Kroah-Hartman 803ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + USR1) & USR1_RTSS) 804ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_CTS; 805ab4382d2SGreg Kroah-Hartman 806ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR2) & UCR2_CTS) 807ab4382d2SGreg Kroah-Hartman tmp |= TIOCM_RTS; 808ab4382d2SGreg Kroah-Hartman 8096b471a98SHuang Shijie if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 8106b471a98SHuang Shijie tmp |= TIOCM_LOOP; 8116b471a98SHuang Shijie 812ab4382d2SGreg Kroah-Hartman return tmp; 813ab4382d2SGreg Kroah-Hartman } 814ab4382d2SGreg Kroah-Hartman 815ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 816ab4382d2SGreg Kroah-Hartman { 817ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 818ab4382d2SGreg Kroah-Hartman unsigned long temp; 819ab4382d2SGreg Kroah-Hartman 820ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; 821ab4382d2SGreg Kroah-Hartman 822ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 823b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) 824ab4382d2SGreg Kroah-Hartman temp |= UCR2_CTS; 825ab4382d2SGreg Kroah-Hartman 826ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 8276b471a98SHuang Shijie 8286b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8296b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8306b471a98SHuang Shijie temp |= UTS_LOOP; 8316b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 832ab4382d2SGreg Kroah-Hartman } 833ab4382d2SGreg Kroah-Hartman 834ab4382d2SGreg Kroah-Hartman /* 835ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 836ab4382d2SGreg Kroah-Hartman */ 837ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 838ab4382d2SGreg Kroah-Hartman { 839ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 840ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 841ab4382d2SGreg Kroah-Hartman 842ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 843ab4382d2SGreg Kroah-Hartman 844ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 845ab4382d2SGreg Kroah-Hartman 846ab4382d2SGreg Kroah-Hartman if (break_state != 0) 847ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 848ab4382d2SGreg Kroah-Hartman 849ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 850ab4382d2SGreg Kroah-Hartman 851ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 852ab4382d2SGreg Kroah-Hartman } 853ab4382d2SGreg Kroah-Hartman 854ab4382d2SGreg Kroah-Hartman #define TXTL 2 /* reset default */ 855ab4382d2SGreg Kroah-Hartman #define RXTL 1 /* reset default */ 856ab4382d2SGreg Kroah-Hartman 857ab4382d2SGreg Kroah-Hartman static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 858ab4382d2SGreg Kroah-Hartman { 859ab4382d2SGreg Kroah-Hartman unsigned int val; 860ab4382d2SGreg Kroah-Hartman 8617be0670fSDirk Behme /* set receiver / transmitter trigger level */ 8627be0670fSDirk Behme val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 8637be0670fSDirk Behme val |= TXTL << UFCR_TXTL_SHF | RXTL; 864ab4382d2SGreg Kroah-Hartman writel(val, sport->port.membase + UFCR); 865ab4382d2SGreg Kroah-Hartman return 0; 866ab4382d2SGreg Kroah-Hartman } 867ab4382d2SGreg Kroah-Hartman 868b4cdc8f6SHuang Shijie #define RX_BUF_SIZE (PAGE_SIZE) 869b4cdc8f6SHuang Shijie static void imx_rx_dma_done(struct imx_port *sport) 870b4cdc8f6SHuang Shijie { 871b4cdc8f6SHuang Shijie unsigned long temp; 872b4cdc8f6SHuang Shijie 873b4cdc8f6SHuang Shijie /* Enable this interrupt when the RXFIFO is empty. */ 874b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 875b4cdc8f6SHuang Shijie temp |= UCR1_RRDYEN; 876b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 877b4cdc8f6SHuang Shijie 878b4cdc8f6SHuang Shijie sport->dma_is_rxing = 0; 8799ce4f8f3SGreg Kroah-Hartman 8809ce4f8f3SGreg Kroah-Hartman /* Is the shutdown waiting for us? */ 8819ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) 8829ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 883b4cdc8f6SHuang Shijie } 884b4cdc8f6SHuang Shijie 885b4cdc8f6SHuang Shijie /* 886b4cdc8f6SHuang Shijie * There are three kinds of RX DMA interrupts(such as in the MX6Q): 887b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 888b4cdc8f6SHuang Shijie * [2] the Aging timer expires(wait for 8 bytes long) 889b4cdc8f6SHuang Shijie * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 890b4cdc8f6SHuang Shijie * 891b4cdc8f6SHuang Shijie * The [2] is trigger when a character was been sitting in the FIFO 892b4cdc8f6SHuang Shijie * meanwhile [3] can wait for 32 bytes long when the RX line is 893b4cdc8f6SHuang Shijie * on IDLE state and RxFIFO is empty. 894b4cdc8f6SHuang Shijie */ 895b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 896b4cdc8f6SHuang Shijie { 897b4cdc8f6SHuang Shijie struct imx_port *sport = data; 898b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 899b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9007cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 901b4cdc8f6SHuang Shijie struct dma_tx_state state; 902b4cdc8f6SHuang Shijie enum dma_status status; 903b4cdc8f6SHuang Shijie unsigned int count; 904b4cdc8f6SHuang Shijie 905b4cdc8f6SHuang Shijie /* unmap it first */ 906b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 907b4cdc8f6SHuang Shijie 908f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 909b4cdc8f6SHuang Shijie count = RX_BUF_SIZE - state.residue; 910b4cdc8f6SHuang Shijie dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 911b4cdc8f6SHuang Shijie 912b4cdc8f6SHuang Shijie if (count) { 9137cb92fd2SHuang Shijie tty_insert_flip_string(port, sport->rx_buf, count); 9147cb92fd2SHuang Shijie tty_flip_buffer_push(port); 9157cb92fd2SHuang Shijie 9167cb92fd2SHuang Shijie start_rx_dma(sport); 917b4cdc8f6SHuang Shijie } else 918b4cdc8f6SHuang Shijie imx_rx_dma_done(sport); 919b4cdc8f6SHuang Shijie } 920b4cdc8f6SHuang Shijie 921b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 922b4cdc8f6SHuang Shijie { 923b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 924b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 925b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 926b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 927b4cdc8f6SHuang Shijie int ret; 928b4cdc8f6SHuang Shijie 929b4cdc8f6SHuang Shijie sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 930b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 931b4cdc8f6SHuang Shijie if (ret == 0) { 932b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 933b4cdc8f6SHuang Shijie return -EINVAL; 934b4cdc8f6SHuang Shijie } 935b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 936b4cdc8f6SHuang Shijie DMA_PREP_INTERRUPT); 937b4cdc8f6SHuang Shijie if (!desc) { 938b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 939b4cdc8f6SHuang Shijie return -EINVAL; 940b4cdc8f6SHuang Shijie } 941b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 942b4cdc8f6SHuang Shijie desc->callback_param = sport; 943b4cdc8f6SHuang Shijie 944b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 945b4cdc8f6SHuang Shijie dmaengine_submit(desc); 946b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 947b4cdc8f6SHuang Shijie return 0; 948b4cdc8f6SHuang Shijie } 949b4cdc8f6SHuang Shijie 950b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 951b4cdc8f6SHuang Shijie { 952b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 953b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 954b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 955b4cdc8f6SHuang Shijie 956b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 957b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 958b4cdc8f6SHuang Shijie } 959b4cdc8f6SHuang Shijie 960b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 961b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 962b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 963b4cdc8f6SHuang Shijie } 964b4cdc8f6SHuang Shijie 965b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 966b4cdc8f6SHuang Shijie } 967b4cdc8f6SHuang Shijie 968b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 969b4cdc8f6SHuang Shijie { 970b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 971b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 972b4cdc8f6SHuang Shijie int ret; 973b4cdc8f6SHuang Shijie 974b4cdc8f6SHuang Shijie /* Prepare for RX : */ 975b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 976b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 977b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 978b4cdc8f6SHuang Shijie ret = -EINVAL; 979b4cdc8f6SHuang Shijie goto err; 980b4cdc8f6SHuang Shijie } 981b4cdc8f6SHuang Shijie 982b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 983b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 984b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 985b4cdc8f6SHuang Shijie slave_config.src_maxburst = RXTL; 986b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 987b4cdc8f6SHuang Shijie if (ret) { 988b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 989b4cdc8f6SHuang Shijie goto err; 990b4cdc8f6SHuang Shijie } 991b4cdc8f6SHuang Shijie 992b4cdc8f6SHuang Shijie sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 993b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 994b4cdc8f6SHuang Shijie dev_err(dev, "cannot alloc DMA buffer.\n"); 995b4cdc8f6SHuang Shijie ret = -ENOMEM; 996b4cdc8f6SHuang Shijie goto err; 997b4cdc8f6SHuang Shijie } 998b4cdc8f6SHuang Shijie 999b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1000b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1001b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1002b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1003b4cdc8f6SHuang Shijie ret = -EINVAL; 1004b4cdc8f6SHuang Shijie goto err; 1005b4cdc8f6SHuang Shijie } 1006b4cdc8f6SHuang Shijie 1007b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1008b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1009b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1010b4cdc8f6SHuang Shijie slave_config.dst_maxburst = TXTL; 1011b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1012b4cdc8f6SHuang Shijie if (ret) { 1013b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1014b4cdc8f6SHuang Shijie goto err; 1015b4cdc8f6SHuang Shijie } 1016b4cdc8f6SHuang Shijie 1017b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1018b4cdc8f6SHuang Shijie 1019b4cdc8f6SHuang Shijie return 0; 1020b4cdc8f6SHuang Shijie err: 1021b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1022b4cdc8f6SHuang Shijie return ret; 1023b4cdc8f6SHuang Shijie } 1024b4cdc8f6SHuang Shijie 1025b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1026b4cdc8f6SHuang Shijie { 1027b4cdc8f6SHuang Shijie unsigned long temp; 1028b4cdc8f6SHuang Shijie 10299ce4f8f3SGreg Kroah-Hartman init_waitqueue_head(&sport->dma_wait); 10309ce4f8f3SGreg Kroah-Hartman 1031b4cdc8f6SHuang Shijie /* set UCR1 */ 1032b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1033b4cdc8f6SHuang Shijie temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1034b4cdc8f6SHuang Shijie /* wait for 32 idle frames for IDDMA interrupt */ 1035b4cdc8f6SHuang Shijie UCR1_ICD_REG(3); 1036b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1037b4cdc8f6SHuang Shijie 1038b4cdc8f6SHuang Shijie /* set UCR4 */ 1039b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1040b4cdc8f6SHuang Shijie temp |= UCR4_IDDMAEN; 1041b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1042b4cdc8f6SHuang Shijie 1043b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1044b4cdc8f6SHuang Shijie } 1045b4cdc8f6SHuang Shijie 1046b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1047b4cdc8f6SHuang Shijie { 1048b4cdc8f6SHuang Shijie unsigned long temp; 1049b4cdc8f6SHuang Shijie 1050b4cdc8f6SHuang Shijie /* clear UCR1 */ 1051b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1052b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1053b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1054b4cdc8f6SHuang Shijie 1055b4cdc8f6SHuang Shijie /* clear UCR2 */ 1056b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 1057b4cdc8f6SHuang Shijie temp &= ~(UCR2_CTSC | UCR2_CTS); 1058b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1059b4cdc8f6SHuang Shijie 1060b4cdc8f6SHuang Shijie /* clear UCR4 */ 1061b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR4); 1062b4cdc8f6SHuang Shijie temp &= ~UCR4_IDDMAEN; 1063b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR4); 1064b4cdc8f6SHuang Shijie 1065b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1066b4cdc8f6SHuang Shijie } 1067b4cdc8f6SHuang Shijie 1068ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1069ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1070ab4382d2SGreg Kroah-Hartman 1071ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1072ab4382d2SGreg Kroah-Hartman { 1073ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1074772f8991SHuang Shijie int retval, i; 1075ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1076ab4382d2SGreg Kroah-Hartman 107728eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 107828eb4274SHuang Shijie if (retval) 107928eb4274SHuang Shijie goto error_out1; 108028eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 10810c375501SHuang Shijie if (retval) { 10820c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 108328eb4274SHuang Shijie goto error_out1; 10840c375501SHuang Shijie } 108528eb4274SHuang Shijie 1086ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1087ab4382d2SGreg Kroah-Hartman 1088ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1089ab4382d2SGreg Kroah-Hartman * requesting IRQs 1090ab4382d2SGreg Kroah-Hartman */ 1091ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1092ab4382d2SGreg Kroah-Hartman 1093ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1094ab4382d2SGreg Kroah-Hartman temp |= UCR4_IRSC; 1095ab4382d2SGreg Kroah-Hartman 1096ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1097ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1098ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1099ab4382d2SGreg Kroah-Hartman 1100ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1101ab4382d2SGreg Kroah-Hartman 1102772f8991SHuang Shijie /* Reset fifo's and state machines */ 1103772f8991SHuang Shijie i = 100; 1104772f8991SHuang Shijie 1105ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1106ab4382d2SGreg Kroah-Hartman temp &= ~UCR2_SRST; 1107ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1108772f8991SHuang Shijie 1109772f8991SHuang Shijie while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1110ab4382d2SGreg Kroah-Hartman udelay(1); 1111ab4382d2SGreg Kroah-Hartman 1112ab4382d2SGreg Kroah-Hartman /* 1113ab4382d2SGreg Kroah-Hartman * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 1114ab4382d2SGreg Kroah-Hartman * chips only have one interrupt. 1115ab4382d2SGreg Kroah-Hartman */ 1116ab4382d2SGreg Kroah-Hartman if (sport->txirq > 0) { 1117ab4382d2SGreg Kroah-Hartman retval = request_irq(sport->rxirq, imx_rxint, 0, 1118436e4ab5SAlexander Shiyan dev_name(port->dev), sport); 1119ab4382d2SGreg Kroah-Hartman if (retval) 1120ab4382d2SGreg Kroah-Hartman goto error_out1; 1121ab4382d2SGreg Kroah-Hartman 1122ab4382d2SGreg Kroah-Hartman retval = request_irq(sport->txirq, imx_txint, 0, 1123436e4ab5SAlexander Shiyan dev_name(port->dev), sport); 1124ab4382d2SGreg Kroah-Hartman if (retval) 1125ab4382d2SGreg Kroah-Hartman goto error_out2; 1126ab4382d2SGreg Kroah-Hartman 1127ab4382d2SGreg Kroah-Hartman /* do not use RTS IRQ on IrDA */ 1128ab4382d2SGreg Kroah-Hartman if (!USE_IRDA(sport)) { 11291ee8f65bSShawn Guo retval = request_irq(sport->rtsirq, imx_rtsint, 0, 1130436e4ab5SAlexander Shiyan dev_name(port->dev), sport); 1131ab4382d2SGreg Kroah-Hartman if (retval) 1132ab4382d2SGreg Kroah-Hartman goto error_out3; 1133ab4382d2SGreg Kroah-Hartman } 1134ab4382d2SGreg Kroah-Hartman } else { 1135ab4382d2SGreg Kroah-Hartman retval = request_irq(sport->port.irq, imx_int, 0, 1136436e4ab5SAlexander Shiyan dev_name(port->dev), sport); 1137ab4382d2SGreg Kroah-Hartman if (retval) { 1138ab4382d2SGreg Kroah-Hartman free_irq(sport->port.irq, sport); 1139ab4382d2SGreg Kroah-Hartman goto error_out1; 1140ab4382d2SGreg Kroah-Hartman } 1141ab4382d2SGreg Kroah-Hartman } 1142ab4382d2SGreg Kroah-Hartman 11439ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1144ab4382d2SGreg Kroah-Hartman /* 1145ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1146ab4382d2SGreg Kroah-Hartman */ 1147ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 1148ab4382d2SGreg Kroah-Hartman 1149ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1150ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1151ab4382d2SGreg Kroah-Hartman 1152ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1153ab4382d2SGreg Kroah-Hartman temp |= UCR1_IREN; 1154ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_RTSDEN); 1155ab4382d2SGreg Kroah-Hartman } 1156ab4382d2SGreg Kroah-Hartman 1157ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1158ab4382d2SGreg Kroah-Hartman 1159ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1160ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1161bff09b09SLucas Stach if (!sport->have_rtscts) 1162bff09b09SLucas Stach temp |= UCR2_IRTS; 1163ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1164ab4382d2SGreg Kroah-Hartman 1165a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1166ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1167b38cb7d2SFabio Estevam temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1168ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1169ab4382d2SGreg Kroah-Hartman } 1170ab4382d2SGreg Kroah-Hartman 1171ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1172ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1173ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_rx) 1174ab4382d2SGreg Kroah-Hartman temp |= UCR4_INVR; 1175ab4382d2SGreg Kroah-Hartman else 1176ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_INVR); 1177ab4382d2SGreg Kroah-Hartman writel(temp | UCR4_DREN, sport->port.membase + UCR4); 1178ab4382d2SGreg Kroah-Hartman 1179ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 1180ab4382d2SGreg Kroah-Hartman if (sport->irda_inv_tx) 1181ab4382d2SGreg Kroah-Hartman temp |= UCR3_INVT; 1182ab4382d2SGreg Kroah-Hartman else 1183ab4382d2SGreg Kroah-Hartman temp &= ~(UCR3_INVT); 1184ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1185ab4382d2SGreg Kroah-Hartman } 1186ab4382d2SGreg Kroah-Hartman 1187ab4382d2SGreg Kroah-Hartman /* 1188ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1189ab4382d2SGreg Kroah-Hartman */ 1190ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1191ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1192ab4382d2SGreg Kroah-Hartman 1193ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1194ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1195574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1196ab4382d2SGreg Kroah-Hartman sport->irda_inv_rx = pdata->irda_inv_rx; 1197ab4382d2SGreg Kroah-Hartman sport->irda_inv_tx = pdata->irda_inv_tx; 1198ab4382d2SGreg Kroah-Hartman sport->trcv_delay = pdata->transceiver_delay; 1199ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1200ab4382d2SGreg Kroah-Hartman pdata->irda_enable(1); 1201ab4382d2SGreg Kroah-Hartman } 1202ab4382d2SGreg Kroah-Hartman 1203ab4382d2SGreg Kroah-Hartman return 0; 1204ab4382d2SGreg Kroah-Hartman 1205ab4382d2SGreg Kroah-Hartman error_out3: 1206ab4382d2SGreg Kroah-Hartman if (sport->txirq) 1207ab4382d2SGreg Kroah-Hartman free_irq(sport->txirq, sport); 1208ab4382d2SGreg Kroah-Hartman error_out2: 1209ab4382d2SGreg Kroah-Hartman if (sport->rxirq) 1210ab4382d2SGreg Kroah-Hartman free_irq(sport->rxirq, sport); 1211ab4382d2SGreg Kroah-Hartman error_out1: 1212ab4382d2SGreg Kroah-Hartman return retval; 1213ab4382d2SGreg Kroah-Hartman } 1214ab4382d2SGreg Kroah-Hartman 1215ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1216ab4382d2SGreg Kroah-Hartman { 1217ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1218ab4382d2SGreg Kroah-Hartman unsigned long temp; 12199ec1882dSXinyu Chen unsigned long flags; 1220ab4382d2SGreg Kroah-Hartman 1221b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 12229ce4f8f3SGreg Kroah-Hartman /* We have to wait for the DMA to finish. */ 12239ce4f8f3SGreg Kroah-Hartman wait_event(sport->dma_wait, 12249ce4f8f3SGreg Kroah-Hartman !sport->dma_is_rxing && !sport->dma_is_txing); 1225b4cdc8f6SHuang Shijie imx_stop_rx(port); 1226b4cdc8f6SHuang Shijie imx_disable_dma(sport); 1227b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1228b4cdc8f6SHuang Shijie } 1229b4cdc8f6SHuang Shijie 12309ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1231ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1232ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1233ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 12349ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1235ab4382d2SGreg Kroah-Hartman 1236ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1237ab4382d2SGreg Kroah-Hartman struct imxuart_platform_data *pdata; 1238574de559SJingoo Han pdata = dev_get_platdata(sport->port.dev); 1239ab4382d2SGreg Kroah-Hartman if (pdata->irda_enable) 1240ab4382d2SGreg Kroah-Hartman pdata->irda_enable(0); 1241ab4382d2SGreg Kroah-Hartman } 1242ab4382d2SGreg Kroah-Hartman 1243ab4382d2SGreg Kroah-Hartman /* 1244ab4382d2SGreg Kroah-Hartman * Stop our timer. 1245ab4382d2SGreg Kroah-Hartman */ 1246ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1247ab4382d2SGreg Kroah-Hartman 1248ab4382d2SGreg Kroah-Hartman /* 1249ab4382d2SGreg Kroah-Hartman * Free the interrupts 1250ab4382d2SGreg Kroah-Hartman */ 1251ab4382d2SGreg Kroah-Hartman if (sport->txirq > 0) { 1252ab4382d2SGreg Kroah-Hartman if (!USE_IRDA(sport)) 1253ab4382d2SGreg Kroah-Hartman free_irq(sport->rtsirq, sport); 1254ab4382d2SGreg Kroah-Hartman free_irq(sport->txirq, sport); 1255ab4382d2SGreg Kroah-Hartman free_irq(sport->rxirq, sport); 1256ab4382d2SGreg Kroah-Hartman } else 1257ab4382d2SGreg Kroah-Hartman free_irq(sport->port.irq, sport); 1258ab4382d2SGreg Kroah-Hartman 1259ab4382d2SGreg Kroah-Hartman /* 1260ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1261ab4382d2SGreg Kroah-Hartman */ 1262ab4382d2SGreg Kroah-Hartman 12639ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1264ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1265ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1266ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) 1267ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_IREN); 1268ab4382d2SGreg Kroah-Hartman 1269ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 12709ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 127128eb4274SHuang Shijie 127228eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 127328eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1274ab4382d2SGreg Kroah-Hartman } 1275ab4382d2SGreg Kroah-Hartman 1276eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1277eb56b7edSHuang Shijie { 1278eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 1279eb56b7edSHuang Shijie 1280eb56b7edSHuang Shijie if (sport->dma_is_enabled) { 1281eb56b7edSHuang Shijie sport->tx_bytes = 0; 1282eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 1283eb56b7edSHuang Shijie } 1284eb56b7edSHuang Shijie } 1285eb56b7edSHuang Shijie 1286ab4382d2SGreg Kroah-Hartman static void 1287ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1288ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1289ab4382d2SGreg Kroah-Hartman { 1290ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1291ab4382d2SGreg Kroah-Hartman unsigned long flags; 1292ab4382d2SGreg Kroah-Hartman unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1293ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1294ab4382d2SGreg Kroah-Hartman unsigned int div, ufcr; 1295ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1296ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1297ab4382d2SGreg Kroah-Hartman 1298ab4382d2SGreg Kroah-Hartman /* 1299ab4382d2SGreg Kroah-Hartman * If we don't support modem control lines, don't allow 1300ab4382d2SGreg Kroah-Hartman * these to be set. 1301ab4382d2SGreg Kroah-Hartman */ 1302ab4382d2SGreg Kroah-Hartman if (0) { 1303ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); 1304ab4382d2SGreg Kroah-Hartman termios->c_cflag |= CLOCAL; 1305ab4382d2SGreg Kroah-Hartman } 1306ab4382d2SGreg Kroah-Hartman 1307ab4382d2SGreg Kroah-Hartman /* 1308ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1309ab4382d2SGreg Kroah-Hartman */ 1310ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1311ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1312ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1313ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1314ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1315ab4382d2SGreg Kroah-Hartman } 1316ab4382d2SGreg Kroah-Hartman 1317ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1318ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1319ab4382d2SGreg Kroah-Hartman else 1320ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1321ab4382d2SGreg Kroah-Hartman 1322ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1323ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1324ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 1325ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_CTSC; 1326b4cdc8f6SHuang Shijie 1327b4cdc8f6SHuang Shijie /* Can we enable the DMA support? */ 1328b4cdc8f6SHuang Shijie if (is_imx6q_uart(sport) && !uart_console(port) 1329b4cdc8f6SHuang Shijie && !sport->dma_is_inited) 1330b4cdc8f6SHuang Shijie imx_uart_dma_init(sport); 1331ab4382d2SGreg Kroah-Hartman } else { 1332ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1333ab4382d2SGreg Kroah-Hartman } 1334ab4382d2SGreg Kroah-Hartman } 1335ab4382d2SGreg Kroah-Hartman 1336ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1337ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1338ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1339ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1340ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1341ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1342ab4382d2SGreg Kroah-Hartman } 1343ab4382d2SGreg Kroah-Hartman 1344995234daSEric Miao del_timer_sync(&sport->timer); 1345995234daSEric Miao 1346ab4382d2SGreg Kroah-Hartman /* 1347ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1348ab4382d2SGreg Kroah-Hartman */ 1349ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1350ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1351ab4382d2SGreg Kroah-Hartman 1352ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1353ab4382d2SGreg Kroah-Hartman 1354ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1355ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1356ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1357ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1358ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1359ab4382d2SGreg Kroah-Hartman 1360ab4382d2SGreg Kroah-Hartman /* 1361ab4382d2SGreg Kroah-Hartman * Characters to ignore 1362ab4382d2SGreg Kroah-Hartman */ 1363ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1364ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1365ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_PRERR; 1366ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1367ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1368ab4382d2SGreg Kroah-Hartman /* 1369ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1370ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1371ab4382d2SGreg Kroah-Hartman */ 1372ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1373ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1374ab4382d2SGreg Kroah-Hartman } 1375ab4382d2SGreg Kroah-Hartman 1376ab4382d2SGreg Kroah-Hartman /* 1377ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1378ab4382d2SGreg Kroah-Hartman */ 1379ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1380ab4382d2SGreg Kroah-Hartman 1381ab4382d2SGreg Kroah-Hartman /* 1382ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1383ab4382d2SGreg Kroah-Hartman */ 1384ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1385ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1386ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1387ab4382d2SGreg Kroah-Hartman 1388ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1389ab4382d2SGreg Kroah-Hartman barrier(); 1390ab4382d2SGreg Kroah-Hartman 1391ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 1392ab4382d2SGreg Kroah-Hartman old_txrxen = readl(sport->port.membase + UCR2); 1393ab4382d2SGreg Kroah-Hartman writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1394ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 1395ab4382d2SGreg Kroah-Hartman old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1396ab4382d2SGreg Kroah-Hartman 1397ab4382d2SGreg Kroah-Hartman if (USE_IRDA(sport)) { 1398ab4382d2SGreg Kroah-Hartman /* 1399ab4382d2SGreg Kroah-Hartman * use maximum available submodule frequency to 1400ab4382d2SGreg Kroah-Hartman * avoid missing short pulses due to low sampling rate 1401ab4382d2SGreg Kroah-Hartman */ 1402ab4382d2SGreg Kroah-Hartman div = 1; 1403ab4382d2SGreg Kroah-Hartman } else { 140409bd00f6SHubert Feurstein /* custom-baudrate handling */ 140509bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 140609bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 140709bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 140809bd00f6SHubert Feurstein 1409ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1410ab4382d2SGreg Kroah-Hartman if (div > 7) 1411ab4382d2SGreg Kroah-Hartman div = 7; 1412ab4382d2SGreg Kroah-Hartman if (!div) 1413ab4382d2SGreg Kroah-Hartman div = 1; 1414ab4382d2SGreg Kroah-Hartman } 1415ab4382d2SGreg Kroah-Hartman 1416ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1417ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1418ab4382d2SGreg Kroah-Hartman 1419ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1420ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1421ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1422ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1423ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1424ab4382d2SGreg Kroah-Hartman 1425ab4382d2SGreg Kroah-Hartman num -= 1; 1426ab4382d2SGreg Kroah-Hartman denom -= 1; 1427ab4382d2SGreg Kroah-Hartman 1428ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1429ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 143020ff2fe6SHuang Shijie if (sport->dte_mode) 143120ff2fe6SHuang Shijie ufcr |= UFCR_DCEDTE; 1432ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1433ab4382d2SGreg Kroah-Hartman 1434ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1435ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1436ab4382d2SGreg Kroah-Hartman 1437a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1438ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1439fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1440ab4382d2SGreg Kroah-Hartman 1441ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1442ab4382d2SGreg Kroah-Hartman 1443ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 1444ab4382d2SGreg Kroah-Hartman writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1445ab4382d2SGreg Kroah-Hartman 1446ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1447ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1448ab4382d2SGreg Kroah-Hartman 1449b4cdc8f6SHuang Shijie if (sport->dma_is_inited && !sport->dma_is_enabled) 1450b4cdc8f6SHuang Shijie imx_enable_dma(sport); 1451ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1452ab4382d2SGreg Kroah-Hartman } 1453ab4382d2SGreg Kroah-Hartman 1454ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1455ab4382d2SGreg Kroah-Hartman { 1456ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1457ab4382d2SGreg Kroah-Hartman 1458ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1459ab4382d2SGreg Kroah-Hartman } 1460ab4382d2SGreg Kroah-Hartman 1461ab4382d2SGreg Kroah-Hartman /* 1462ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1463ab4382d2SGreg Kroah-Hartman */ 1464ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1465ab4382d2SGreg Kroah-Hartman { 1466ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1467ab4382d2SGreg Kroah-Hartman 1468da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1469ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1470ab4382d2SGreg Kroah-Hartman } 1471ab4382d2SGreg Kroah-Hartman 1472ab4382d2SGreg Kroah-Hartman /* 1473ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1474ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1475ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1476ab4382d2SGreg Kroah-Hartman */ 1477ab4382d2SGreg Kroah-Hartman static int 1478ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1479ab4382d2SGreg Kroah-Hartman { 1480ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1481ab4382d2SGreg Kroah-Hartman int ret = 0; 1482ab4382d2SGreg Kroah-Hartman 1483ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1484ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1485ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1486ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1487ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1488ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1489ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1490ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1491a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1492ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1493ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1494ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1495ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1496ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1497ab4382d2SGreg Kroah-Hartman return ret; 1498ab4382d2SGreg Kroah-Hartman } 1499ab4382d2SGreg Kroah-Hartman 150001f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 150101f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 150201f56abdSSaleem Abdulrasool { 150326c47412SDirk Behme if (!(readl(port->membase + USR2) & USR2_RDR)) 150426c47412SDirk Behme return NO_POLL_CHAR; 150501f56abdSSaleem Abdulrasool 150626c47412SDirk Behme return readl(port->membase + URXD0) & URXD_RX_DATA; 150701f56abdSSaleem Abdulrasool } 150801f56abdSSaleem Abdulrasool 150901f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 151001f56abdSSaleem Abdulrasool { 151101f56abdSSaleem Abdulrasool struct imx_port_ucrs old_ucr; 151201f56abdSSaleem Abdulrasool unsigned int status; 151301f56abdSSaleem Abdulrasool 151401f56abdSSaleem Abdulrasool /* save control registers */ 151501f56abdSSaleem Abdulrasool imx_port_ucrs_save(port, &old_ucr); 151601f56abdSSaleem Abdulrasool 151701f56abdSSaleem Abdulrasool /* disable interrupts */ 151801f56abdSSaleem Abdulrasool writel(UCR1_UARTEN, port->membase + UCR1); 151901f56abdSSaleem Abdulrasool writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), 152001f56abdSSaleem Abdulrasool port->membase + UCR2); 152101f56abdSSaleem Abdulrasool writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), 152201f56abdSSaleem Abdulrasool port->membase + UCR3); 152301f56abdSSaleem Abdulrasool 152401f56abdSSaleem Abdulrasool /* drain */ 152501f56abdSSaleem Abdulrasool do { 152601f56abdSSaleem Abdulrasool status = readl(port->membase + USR1); 152701f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 152801f56abdSSaleem Abdulrasool 152901f56abdSSaleem Abdulrasool /* write */ 153001f56abdSSaleem Abdulrasool writel(c, port->membase + URTX0); 153101f56abdSSaleem Abdulrasool 153201f56abdSSaleem Abdulrasool /* flush */ 153301f56abdSSaleem Abdulrasool do { 153401f56abdSSaleem Abdulrasool status = readl(port->membase + USR2); 153501f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 153601f56abdSSaleem Abdulrasool 153701f56abdSSaleem Abdulrasool /* restore control registers */ 153801f56abdSSaleem Abdulrasool imx_port_ucrs_restore(port, &old_ucr); 153901f56abdSSaleem Abdulrasool } 154001f56abdSSaleem Abdulrasool #endif 154101f56abdSSaleem Abdulrasool 1542ab4382d2SGreg Kroah-Hartman static struct uart_ops imx_pops = { 1543ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1544ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1545ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1546ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1547ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1548ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1549ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1550ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1551ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1552ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1553eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1554ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1555ab4382d2SGreg Kroah-Hartman .type = imx_type, 1556ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1557ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 155801f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 155901f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 156001f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 156101f56abdSSaleem Abdulrasool #endif 1562ab4382d2SGreg Kroah-Hartman }; 1563ab4382d2SGreg Kroah-Hartman 1564ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1565ab4382d2SGreg Kroah-Hartman 1566ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1567ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1568ab4382d2SGreg Kroah-Hartman { 1569ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1570ab4382d2SGreg Kroah-Hartman 1571fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1572ab4382d2SGreg Kroah-Hartman barrier(); 1573ab4382d2SGreg Kroah-Hartman 1574ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1575ab4382d2SGreg Kroah-Hartman } 1576ab4382d2SGreg Kroah-Hartman 1577ab4382d2SGreg Kroah-Hartman /* 1578ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1579ab4382d2SGreg Kroah-Hartman */ 1580ab4382d2SGreg Kroah-Hartman static void 1581ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1582ab4382d2SGreg Kroah-Hartman { 1583ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 15840ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 15850ad5a814SDirk Behme unsigned int ucr1; 1586f30e8260SShawn Guo unsigned long flags = 0; 1587677fe555SThomas Gleixner int locked = 1; 15881cf93e0dSHuang Shijie int retval; 15891cf93e0dSHuang Shijie 15901cf93e0dSHuang Shijie retval = clk_enable(sport->clk_per); 15911cf93e0dSHuang Shijie if (retval) 15921cf93e0dSHuang Shijie return; 15931cf93e0dSHuang Shijie retval = clk_enable(sport->clk_ipg); 15941cf93e0dSHuang Shijie if (retval) { 15951cf93e0dSHuang Shijie clk_disable(sport->clk_per); 15961cf93e0dSHuang Shijie return; 15971cf93e0dSHuang Shijie } 15989ec1882dSXinyu Chen 1599677fe555SThomas Gleixner if (sport->port.sysrq) 1600677fe555SThomas Gleixner locked = 0; 1601677fe555SThomas Gleixner else if (oops_in_progress) 1602677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1603677fe555SThomas Gleixner else 16049ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1605ab4382d2SGreg Kroah-Hartman 1606ab4382d2SGreg Kroah-Hartman /* 16070ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1608ab4382d2SGreg Kroah-Hartman */ 16090ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 16100ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1611ab4382d2SGreg Kroah-Hartman 1612fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1613fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1614ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1615ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1616ab4382d2SGreg Kroah-Hartman 1617ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1618ab4382d2SGreg Kroah-Hartman 16190ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1620ab4382d2SGreg Kroah-Hartman 1621ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1622ab4382d2SGreg Kroah-Hartman 1623ab4382d2SGreg Kroah-Hartman /* 1624ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 16250ad5a814SDirk Behme * and restore UCR1/2/3 1626ab4382d2SGreg Kroah-Hartman */ 1627ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1628ab4382d2SGreg Kroah-Hartman 16290ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 16309ec1882dSXinyu Chen 1631677fe555SThomas Gleixner if (locked) 16329ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 16331cf93e0dSHuang Shijie 16341cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 16351cf93e0dSHuang Shijie clk_disable(sport->clk_per); 1636ab4382d2SGreg Kroah-Hartman } 1637ab4382d2SGreg Kroah-Hartman 1638ab4382d2SGreg Kroah-Hartman /* 1639ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1640ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1641ab4382d2SGreg Kroah-Hartman */ 1642ab4382d2SGreg Kroah-Hartman static void __init 1643ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1644ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1645ab4382d2SGreg Kroah-Hartman { 1646ab4382d2SGreg Kroah-Hartman 1647ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1648ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1649ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1650ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1651ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1652ab4382d2SGreg Kroah-Hartman 1653ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1654ab4382d2SGreg Kroah-Hartman 1655ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1656ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1657ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1658ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1659ab4382d2SGreg Kroah-Hartman else 1660ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1661ab4382d2SGreg Kroah-Hartman } 1662ab4382d2SGreg Kroah-Hartman 1663ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1664ab4382d2SGreg Kroah-Hartman *bits = 8; 1665ab4382d2SGreg Kroah-Hartman else 1666ab4382d2SGreg Kroah-Hartman *bits = 7; 1667ab4382d2SGreg Kroah-Hartman 1668ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1669ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1670ab4382d2SGreg Kroah-Hartman 1671ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1672ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1673ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1674ab4382d2SGreg Kroah-Hartman else 1675ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1676ab4382d2SGreg Kroah-Hartman 16773a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1678ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1679ab4382d2SGreg Kroah-Hartman 1680ab4382d2SGreg Kroah-Hartman { /* 1681ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1682ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1683ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1684ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1685ab4382d2SGreg Kroah-Hartman */ 1686ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1687ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1688ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1689ab4382d2SGreg Kroah-Hartman 1690ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1691ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1692ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1693ab4382d2SGreg Kroah-Hartman } 1694ab4382d2SGreg Kroah-Hartman 1695ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 169650bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1697ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1698ab4382d2SGreg Kroah-Hartman } 1699ab4382d2SGreg Kroah-Hartman } 1700ab4382d2SGreg Kroah-Hartman 1701ab4382d2SGreg Kroah-Hartman static int __init 1702ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1703ab4382d2SGreg Kroah-Hartman { 1704ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1705ab4382d2SGreg Kroah-Hartman int baud = 9600; 1706ab4382d2SGreg Kroah-Hartman int bits = 8; 1707ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1708ab4382d2SGreg Kroah-Hartman int flow = 'n'; 17091cf93e0dSHuang Shijie int retval; 1710ab4382d2SGreg Kroah-Hartman 1711ab4382d2SGreg Kroah-Hartman /* 1712ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1713ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1714ab4382d2SGreg Kroah-Hartman * console support. 1715ab4382d2SGreg Kroah-Hartman */ 1716ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1717ab4382d2SGreg Kroah-Hartman co->index = 0; 1718ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1719ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1720ab4382d2SGreg Kroah-Hartman return -ENODEV; 1721ab4382d2SGreg Kroah-Hartman 17221cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 17231cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 17241cf93e0dSHuang Shijie if (retval) 17251cf93e0dSHuang Shijie goto error_console; 17261cf93e0dSHuang Shijie 1727ab4382d2SGreg Kroah-Hartman if (options) 1728ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1729ab4382d2SGreg Kroah-Hartman else 1730ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1731ab4382d2SGreg Kroah-Hartman 1732ab4382d2SGreg Kroah-Hartman imx_setup_ufcr(sport, 0); 1733ab4382d2SGreg Kroah-Hartman 17341cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 17351cf93e0dSHuang Shijie 17361cf93e0dSHuang Shijie clk_disable(sport->clk_ipg); 17371cf93e0dSHuang Shijie if (retval) { 17381cf93e0dSHuang Shijie clk_unprepare(sport->clk_ipg); 17391cf93e0dSHuang Shijie goto error_console; 17401cf93e0dSHuang Shijie } 17411cf93e0dSHuang Shijie 17421cf93e0dSHuang Shijie retval = clk_prepare(sport->clk_per); 17431cf93e0dSHuang Shijie if (retval) 17441cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 17451cf93e0dSHuang Shijie 17461cf93e0dSHuang Shijie error_console: 17471cf93e0dSHuang Shijie return retval; 1748ab4382d2SGreg Kroah-Hartman } 1749ab4382d2SGreg Kroah-Hartman 1750ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1751ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1752ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1753ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1754ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1755ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1756ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1757ab4382d2SGreg Kroah-Hartman .index = -1, 1758ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1759ab4382d2SGreg Kroah-Hartman }; 1760ab4382d2SGreg Kroah-Hartman 1761ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1762ab4382d2SGreg Kroah-Hartman #else 1763ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1764ab4382d2SGreg Kroah-Hartman #endif 1765ab4382d2SGreg Kroah-Hartman 1766ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1767ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1768ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 1769ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 1770ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 1771ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 1772ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 1773ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 1774ab4382d2SGreg Kroah-Hartman }; 1775ab4382d2SGreg Kroah-Hartman 1776ab4382d2SGreg Kroah-Hartman static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1777ab4382d2SGreg Kroah-Hartman { 1778ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1779db1a9b55SFabio Estevam unsigned int val; 1780db1a9b55SFabio Estevam 1781db1a9b55SFabio Estevam /* enable wakeup from i.MX UART */ 1782db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1783db1a9b55SFabio Estevam val |= UCR3_AWAKEN; 1784db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1785ab4382d2SGreg Kroah-Hartman 1786ab4382d2SGreg Kroah-Hartman uart_suspend_port(&imx_reg, &sport->port); 1787ab4382d2SGreg Kroah-Hartman 1788ab4382d2SGreg Kroah-Hartman return 0; 1789ab4382d2SGreg Kroah-Hartman } 1790ab4382d2SGreg Kroah-Hartman 1791ab4382d2SGreg Kroah-Hartman static int serial_imx_resume(struct platform_device *dev) 1792ab4382d2SGreg Kroah-Hartman { 1793ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(dev); 1794db1a9b55SFabio Estevam unsigned int val; 1795db1a9b55SFabio Estevam 1796db1a9b55SFabio Estevam /* disable wakeup from i.MX UART */ 1797db1a9b55SFabio Estevam val = readl(sport->port.membase + UCR3); 1798db1a9b55SFabio Estevam val &= ~UCR3_AWAKEN; 1799db1a9b55SFabio Estevam writel(val, sport->port.membase + UCR3); 1800ab4382d2SGreg Kroah-Hartman 1801ab4382d2SGreg Kroah-Hartman uart_resume_port(&imx_reg, &sport->port); 1802ab4382d2SGreg Kroah-Hartman 1803ab4382d2SGreg Kroah-Hartman return 0; 1804ab4382d2SGreg Kroah-Hartman } 1805ab4382d2SGreg Kroah-Hartman 180622698aa2SShawn Guo #ifdef CONFIG_OF 180720bb8095SUwe Kleine-König /* 180820bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 180920bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 181020bb8095SUwe Kleine-König */ 181122698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 181222698aa2SShawn Guo struct platform_device *pdev) 181322698aa2SShawn Guo { 181422698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 181522698aa2SShawn Guo const struct of_device_id *of_id = 181622698aa2SShawn Guo of_match_device(imx_uart_dt_ids, &pdev->dev); 1817ff05967aSShawn Guo int ret; 181822698aa2SShawn Guo 181922698aa2SShawn Guo if (!np) 182020bb8095SUwe Kleine-König /* no device tree device */ 182120bb8095SUwe Kleine-König return 1; 182222698aa2SShawn Guo 1823ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 1824ff05967aSShawn Guo if (ret < 0) { 1825ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1826a197a191SUwe Kleine-König return ret; 1827ff05967aSShawn Guo } 1828ff05967aSShawn Guo sport->port.line = ret; 182922698aa2SShawn Guo 183022698aa2SShawn Guo if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 183122698aa2SShawn Guo sport->have_rtscts = 1; 183222698aa2SShawn Guo 183322698aa2SShawn Guo if (of_get_property(np, "fsl,irda-mode", NULL)) 183422698aa2SShawn Guo sport->use_irda = 1; 183522698aa2SShawn Guo 183620ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 183720ff2fe6SHuang Shijie sport->dte_mode = 1; 183820ff2fe6SHuang Shijie 183922698aa2SShawn Guo sport->devdata = of_id->data; 184022698aa2SShawn Guo 184122698aa2SShawn Guo return 0; 184222698aa2SShawn Guo } 184322698aa2SShawn Guo #else 184422698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 184522698aa2SShawn Guo struct platform_device *pdev) 184622698aa2SShawn Guo { 184720bb8095SUwe Kleine-König return 1; 184822698aa2SShawn Guo } 184922698aa2SShawn Guo #endif 185022698aa2SShawn Guo 185122698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 185222698aa2SShawn Guo struct platform_device *pdev) 185322698aa2SShawn Guo { 1854574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 185522698aa2SShawn Guo 185622698aa2SShawn Guo sport->port.line = pdev->id; 185722698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 185822698aa2SShawn Guo 185922698aa2SShawn Guo if (!pdata) 186022698aa2SShawn Guo return; 186122698aa2SShawn Guo 186222698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 186322698aa2SShawn Guo sport->have_rtscts = 1; 186422698aa2SShawn Guo 186522698aa2SShawn Guo if (pdata->flags & IMXUART_IRDA) 186622698aa2SShawn Guo sport->use_irda = 1; 186722698aa2SShawn Guo } 186822698aa2SShawn Guo 1869ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 1870ab4382d2SGreg Kroah-Hartman { 1871ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1872ab4382d2SGreg Kroah-Hartman void __iomem *base; 1873ab4382d2SGreg Kroah-Hartman int ret = 0; 1874ab4382d2SGreg Kroah-Hartman struct resource *res; 1875ab4382d2SGreg Kroah-Hartman 187642d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1877ab4382d2SGreg Kroah-Hartman if (!sport) 1878ab4382d2SGreg Kroah-Hartman return -ENOMEM; 1879ab4382d2SGreg Kroah-Hartman 188022698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 188120bb8095SUwe Kleine-König if (ret > 0) 188222698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 188320bb8095SUwe Kleine-König else if (ret < 0) 188442d34191SSachin Kamat return ret; 188522698aa2SShawn Guo 1886ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1887da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 1888da82f997SAlexander Shiyan if (IS_ERR(base)) 1889da82f997SAlexander Shiyan return PTR_ERR(base); 1890ab4382d2SGreg Kroah-Hartman 1891ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 1892ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 1893ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 1894ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 1895ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 1896ab4382d2SGreg Kroah-Hartman sport->port.irq = platform_get_irq(pdev, 0); 1897ab4382d2SGreg Kroah-Hartman sport->rxirq = platform_get_irq(pdev, 0); 1898ab4382d2SGreg Kroah-Hartman sport->txirq = platform_get_irq(pdev, 1); 1899ab4382d2SGreg Kroah-Hartman sport->rtsirq = platform_get_irq(pdev, 2); 1900ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 1901ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 1902ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 1903ab4382d2SGreg Kroah-Hartman init_timer(&sport->timer); 1904ab4382d2SGreg Kroah-Hartman sport->timer.function = imx_timeout; 1905ab4382d2SGreg Kroah-Hartman sport->timer.data = (unsigned long)sport; 1906ab4382d2SGreg Kroah-Hartman 19073a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 19083a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 19093a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 1910833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 191142d34191SSachin Kamat return ret; 1912ab4382d2SGreg Kroah-Hartman } 1913ab4382d2SGreg Kroah-Hartman 19143a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 19153a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 19163a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 1917833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 191842d34191SSachin Kamat return ret; 19193a9465faSSascha Hauer } 19203a9465faSSascha Hauer 19213a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 1922ab4382d2SGreg Kroah-Hartman 192322698aa2SShawn Guo imx_ports[sport->port.line] = sport; 1924ab4382d2SGreg Kroah-Hartman 19250a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 1926ab4382d2SGreg Kroah-Hartman 192745af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 1928ab4382d2SGreg Kroah-Hartman } 1929ab4382d2SGreg Kroah-Hartman 1930ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 1931ab4382d2SGreg Kroah-Hartman { 1932ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 1933ab4382d2SGreg Kroah-Hartman 193445af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 1935ab4382d2SGreg Kroah-Hartman } 1936ab4382d2SGreg Kroah-Hartman 1937ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 1938ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 1939ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 1940ab4382d2SGreg Kroah-Hartman 1941ab4382d2SGreg Kroah-Hartman .suspend = serial_imx_suspend, 1942ab4382d2SGreg Kroah-Hartman .resume = serial_imx_resume, 1943fe6b540aSShawn Guo .id_table = imx_uart_devtype, 1944ab4382d2SGreg Kroah-Hartman .driver = { 1945ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 1946ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 194722698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 1948ab4382d2SGreg Kroah-Hartman }, 1949ab4382d2SGreg Kroah-Hartman }; 1950ab4382d2SGreg Kroah-Hartman 1951ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 1952ab4382d2SGreg Kroah-Hartman { 1953ab4382d2SGreg Kroah-Hartman int ret; 1954ab4382d2SGreg Kroah-Hartman 195550bbdba3SSachin Kamat pr_info("Serial: IMX driver\n"); 1956ab4382d2SGreg Kroah-Hartman 1957ab4382d2SGreg Kroah-Hartman ret = uart_register_driver(&imx_reg); 1958ab4382d2SGreg Kroah-Hartman if (ret) 1959ab4382d2SGreg Kroah-Hartman return ret; 1960ab4382d2SGreg Kroah-Hartman 1961ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 1962ab4382d2SGreg Kroah-Hartman if (ret != 0) 1963ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 1964ab4382d2SGreg Kroah-Hartman 1965f227824eSUwe Kleine-König return ret; 1966ab4382d2SGreg Kroah-Hartman } 1967ab4382d2SGreg Kroah-Hartman 1968ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 1969ab4382d2SGreg Kroah-Hartman { 1970ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 1971ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 1972ab4382d2SGreg Kroah-Hartman } 1973ab4382d2SGreg Kroah-Hartman 1974ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 1975ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 1976ab4382d2SGreg Kroah-Hartman 1977ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 1978ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 1979ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 1980ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 1981