1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 13ab4382d2SGreg Kroah-Hartman #endif 14ab4382d2SGreg Kroah-Hartman 15ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 23ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 24ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2922698aa2SShawn Guo #include <linux/of.h> 3022698aa2SShawn Guo #include <linux/of_device.h> 31e32a9f8fSSachin Kamat #include <linux/io.h> 32b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 3582906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 36b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 37ab4382d2SGreg Kroah-Hartman 3858362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3958362d5bSUwe Kleine-König 40ab4382d2SGreg Kroah-Hartman /* Register definitions */ 41ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 42ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 43ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 44ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 45ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 46ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 47ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 48ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 49ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 50ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 51ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 52ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 53ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 54ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 55fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 56fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 57fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 58ab4382d2SGreg Kroah-Hartman 59ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6055d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 61ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 62ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 63ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 64ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 65ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 66ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6726c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6825985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 69ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 71ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 72b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 74302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 77ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 79302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 80fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 81b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9401f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 101ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 104b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 105ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10827e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 109fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 115ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 118b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1257be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 126ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 127ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 128ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 129ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 130ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 131ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 133ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 134ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13686a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13727e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 138ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 142ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 143ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14590ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14690ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14990ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 150ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 151ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 152ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 153ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 154ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 155ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 156ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 157ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 158ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 159ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 160ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 161ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 162ab4382d2SGreg Kroah-Hartman 163ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 164ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 165ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 166ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 167ab4382d2SGreg Kroah-Hartman 168ab4382d2SGreg Kroah-Hartman /* 169ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 170ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 171ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 172ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 173ab4382d2SGreg Kroah-Hartman */ 174ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 175ab4382d2SGreg Kroah-Hartman 176ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 177ab4382d2SGreg Kroah-Hartman 178ab4382d2SGreg Kroah-Hartman #define UART_NR 8 179ab4382d2SGreg Kroah-Hartman 180f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 181fe6b540aSShawn Guo enum imx_uart_type { 182fe6b540aSShawn Guo IMX1_UART, 183fe6b540aSShawn Guo IMX21_UART, 1841c06bde6SMartyn Welch IMX53_UART, 185a496e628SHuang Shijie IMX6Q_UART, 186fe6b540aSShawn Guo }; 187fe6b540aSShawn Guo 188fe6b540aSShawn Guo /* device type dependent stuff */ 189fe6b540aSShawn Guo struct imx_uart_data { 190fe6b540aSShawn Guo unsigned uts_reg; 191fe6b540aSShawn Guo enum imx_uart_type devtype; 192fe6b540aSShawn Guo }; 193fe6b540aSShawn Guo 194ab4382d2SGreg Kroah-Hartman struct imx_port { 195ab4382d2SGreg Kroah-Hartman struct uart_port port; 196ab4382d2SGreg Kroah-Hartman struct timer_list timer; 197ab4382d2SGreg Kroah-Hartman unsigned int old_status; 198ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 1997b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20020ff2fe6SHuang Shijie unsigned int dte_mode:1; 2013a9465faSSascha Hauer struct clk *clk_ipg; 2023a9465faSSascha Hauer struct clk *clk_per; 2037d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 204b4cdc8f6SHuang Shijie 20558362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 20658362d5bSUwe Kleine-König 2073a0ab62fSUwe Kleine-König /* shadow registers */ 2083a0ab62fSUwe Kleine-König unsigned int ucr1; 2093a0ab62fSUwe Kleine-König unsigned int ucr2; 2103a0ab62fSUwe Kleine-König unsigned int ucr3; 2113a0ab62fSUwe Kleine-König unsigned int ucr4; 2123a0ab62fSUwe Kleine-König unsigned int ufcr; 2133a0ab62fSUwe Kleine-König 214b4cdc8f6SHuang Shijie /* DMA fields */ 215b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 216b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 217b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 218b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 219b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 220b4cdc8f6SHuang Shijie void *rx_buf; 2219d297239SNandor Han struct circ_buf rx_ring; 2229d297239SNandor Han unsigned int rx_periods; 2239d297239SNandor Han dma_cookie_t rx_cookie; 2247cb92fd2SHuang Shijie unsigned int tx_bytes; 225b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 22690bb6bd3SShenwei Wang unsigned int saved_reg[10]; 227c868cbb7SEduardo Valentin bool context_saved; 228ab4382d2SGreg Kroah-Hartman }; 229ab4382d2SGreg Kroah-Hartman 2300ad5a814SDirk Behme struct imx_port_ucrs { 2310ad5a814SDirk Behme unsigned int ucr1; 2320ad5a814SDirk Behme unsigned int ucr2; 2330ad5a814SDirk Behme unsigned int ucr3; 2340ad5a814SDirk Behme }; 2350ad5a814SDirk Behme 236fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 237fe6b540aSShawn Guo [IMX1_UART] = { 238fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 239fe6b540aSShawn Guo .devtype = IMX1_UART, 240fe6b540aSShawn Guo }, 241fe6b540aSShawn Guo [IMX21_UART] = { 242fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 243fe6b540aSShawn Guo .devtype = IMX21_UART, 244fe6b540aSShawn Guo }, 2451c06bde6SMartyn Welch [IMX53_UART] = { 2461c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2471c06bde6SMartyn Welch .devtype = IMX53_UART, 2481c06bde6SMartyn Welch }, 249a496e628SHuang Shijie [IMX6Q_UART] = { 250a496e628SHuang Shijie .uts_reg = IMX21_UTS, 251a496e628SHuang Shijie .devtype = IMX6Q_UART, 252a496e628SHuang Shijie }, 253fe6b540aSShawn Guo }; 254fe6b540aSShawn Guo 25531ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 256fe6b540aSShawn Guo { 257fe6b540aSShawn Guo .name = "imx1-uart", 258fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 259fe6b540aSShawn Guo }, { 260fe6b540aSShawn Guo .name = "imx21-uart", 261fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 262fe6b540aSShawn Guo }, { 2631c06bde6SMartyn Welch .name = "imx53-uart", 2641c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2651c06bde6SMartyn Welch }, { 266a496e628SHuang Shijie .name = "imx6q-uart", 267a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 268a496e628SHuang Shijie }, { 269fe6b540aSShawn Guo /* sentinel */ 270fe6b540aSShawn Guo } 271fe6b540aSShawn Guo }; 272fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 273fe6b540aSShawn Guo 274ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 275a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2761c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27722698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27822698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27922698aa2SShawn Guo { /* sentinel */ } 28022698aa2SShawn Guo }; 28122698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28222698aa2SShawn Guo 28327c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 28427c84426SUwe Kleine-König { 2853a0ab62fSUwe Kleine-König switch (offset) { 2863a0ab62fSUwe Kleine-König case UCR1: 2873a0ab62fSUwe Kleine-König sport->ucr1 = val; 2883a0ab62fSUwe Kleine-König break; 2893a0ab62fSUwe Kleine-König case UCR2: 2903a0ab62fSUwe Kleine-König sport->ucr2 = val; 2913a0ab62fSUwe Kleine-König break; 2923a0ab62fSUwe Kleine-König case UCR3: 2933a0ab62fSUwe Kleine-König sport->ucr3 = val; 2943a0ab62fSUwe Kleine-König break; 2953a0ab62fSUwe Kleine-König case UCR4: 2963a0ab62fSUwe Kleine-König sport->ucr4 = val; 2973a0ab62fSUwe Kleine-König break; 2983a0ab62fSUwe Kleine-König case UFCR: 2993a0ab62fSUwe Kleine-König sport->ufcr = val; 3003a0ab62fSUwe Kleine-König break; 3013a0ab62fSUwe Kleine-König default: 3023a0ab62fSUwe Kleine-König break; 3033a0ab62fSUwe Kleine-König } 30427c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 30527c84426SUwe Kleine-König } 30627c84426SUwe Kleine-König 30727c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30827c84426SUwe Kleine-König { 3093a0ab62fSUwe Kleine-König switch (offset) { 3103a0ab62fSUwe Kleine-König case UCR1: 3113a0ab62fSUwe Kleine-König return sport->ucr1; 3123a0ab62fSUwe Kleine-König break; 3133a0ab62fSUwe Kleine-König case UCR2: 3143a0ab62fSUwe Kleine-König /* 3153a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3163a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 3173a0ab62fSUwe Kleine-König * clears after being set, reread conditionally. 3183a0ab62fSUwe Kleine-König */ 3193a0ab62fSUwe Kleine-König if (sport->ucr2 & UCR2_SRST) 3203a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3213a0ab62fSUwe Kleine-König return sport->ucr2; 3223a0ab62fSUwe Kleine-König break; 3233a0ab62fSUwe Kleine-König case UCR3: 3243a0ab62fSUwe Kleine-König return sport->ucr3; 3253a0ab62fSUwe Kleine-König break; 3263a0ab62fSUwe Kleine-König case UCR4: 3273a0ab62fSUwe Kleine-König return sport->ucr4; 3283a0ab62fSUwe Kleine-König break; 3293a0ab62fSUwe Kleine-König case UFCR: 3303a0ab62fSUwe Kleine-König return sport->ufcr; 3313a0ab62fSUwe Kleine-König break; 3323a0ab62fSUwe Kleine-König default: 33327c84426SUwe Kleine-König return readl(sport->port.membase + offset); 33427c84426SUwe Kleine-König } 3353a0ab62fSUwe Kleine-König } 33627c84426SUwe Kleine-König 337fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 338fe6b540aSShawn Guo { 339fe6b540aSShawn Guo return sport->devdata->uts_reg; 340fe6b540aSShawn Guo } 341fe6b540aSShawn Guo 342fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 343fe6b540aSShawn Guo { 344fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 345fe6b540aSShawn Guo } 346fe6b540aSShawn Guo 347fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 348fe6b540aSShawn Guo { 349fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 350fe6b540aSShawn Guo } 351fe6b540aSShawn Guo 3521c06bde6SMartyn Welch static inline int is_imx53_uart(struct imx_port *sport) 3531c06bde6SMartyn Welch { 3541c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3551c06bde6SMartyn Welch } 3561c06bde6SMartyn Welch 357a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 358a496e628SHuang Shijie { 359a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 360a496e628SHuang Shijie } 361ab4382d2SGreg Kroah-Hartman /* 36244a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 36344a75411Sfabio.estevam@freescale.com */ 36493d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 36527c84426SUwe Kleine-König static void imx_port_ucrs_save(struct imx_port *sport, 36644a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36744a75411Sfabio.estevam@freescale.com { 36844a75411Sfabio.estevam@freescale.com /* save control registers */ 36927c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 37027c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 37127c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 37244a75411Sfabio.estevam@freescale.com } 37344a75411Sfabio.estevam@freescale.com 37427c84426SUwe Kleine-König static void imx_port_ucrs_restore(struct imx_port *sport, 37544a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37644a75411Sfabio.estevam@freescale.com { 37744a75411Sfabio.estevam@freescale.com /* restore control registers */ 37827c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 37927c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 38027c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 38144a75411Sfabio.estevam@freescale.com } 382e8bfa760SFabio Estevam #endif 38344a75411Sfabio.estevam@freescale.com 3844444dcf1SUwe Kleine-König static void imx_port_rts_active(struct imx_port *sport, u32 *ucr2) 38558362d5bSUwe Kleine-König { 386bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38758362d5bSUwe Kleine-König 388a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 389a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39058362d5bSUwe Kleine-König } 39158362d5bSUwe Kleine-König 3924444dcf1SUwe Kleine-König static void imx_port_rts_inactive(struct imx_port *sport, u32 *ucr2) 39358362d5bSUwe Kleine-König { 394bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 395bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39658362d5bSUwe Kleine-König 397a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 398a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39958362d5bSUwe Kleine-König } 40058362d5bSUwe Kleine-König 4014444dcf1SUwe Kleine-König static void imx_port_rts_auto(struct imx_port *sport, u32 *ucr2) 40258362d5bSUwe Kleine-König { 40358362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 40458362d5bSUwe Kleine-König } 40558362d5bSUwe Kleine-König 4066aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 40776821e22SUwe Kleine-König static void imx_start_rx(struct uart_port *port) 40876821e22SUwe Kleine-König { 40976821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 41076821e22SUwe Kleine-König unsigned int ucr1, ucr2; 41176821e22SUwe Kleine-König 41276821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 41376821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 41476821e22SUwe Kleine-König 41576821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41676821e22SUwe Kleine-König 41776821e22SUwe Kleine-König if (sport->dma_is_enabled) { 41876821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 41976821e22SUwe Kleine-König } else { 42076821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 42181ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 42276821e22SUwe Kleine-König } 42376821e22SUwe Kleine-König 42476821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 42576821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42676821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42776821e22SUwe Kleine-König } 42876821e22SUwe Kleine-König 42976821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 430ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 431ab4382d2SGreg Kroah-Hartman { 432ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4334444dcf1SUwe Kleine-König u32 ucr1; 434ab4382d2SGreg Kroah-Hartman 4359ce4f8f3SGreg Kroah-Hartman /* 4369ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4379ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4389ce4f8f3SGreg Kroah-Hartman */ 439686351f3SUwe Kleine-König if (sport->dma_is_txing) 4409ce4f8f3SGreg Kroah-Hartman return; 441b4cdc8f6SHuang Shijie 4424444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 4434444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1); 44417b8f2a3SUwe Kleine-König 44517b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 44617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 44727c84426SUwe Kleine-König imx_uart_readl(sport, USR2) & USR2_TXDC) { 4484444dcf1SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 44917b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4504444dcf1SUwe Kleine-König imx_port_rts_active(sport, &ucr2); 4511a613626SFabio Estevam else 4524444dcf1SUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 4534444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 45417b8f2a3SUwe Kleine-König 45576821e22SUwe Kleine-König imx_start_rx(port); 45676821e22SUwe Kleine-König 4574444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 4584444dcf1SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 4594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 46017b8f2a3SUwe Kleine-König } 461ab4382d2SGreg Kroah-Hartman } 462ab4382d2SGreg Kroah-Hartman 4636aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 464ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 465ab4382d2SGreg Kroah-Hartman { 466ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4674444dcf1SUwe Kleine-König u32 ucr1, ucr2; 468ab4382d2SGreg Kroah-Hartman 4694444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 47076821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 47176821e22SUwe Kleine-König 47276821e22SUwe Kleine-König if (sport->dma_is_enabled) { 47376821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 47476821e22SUwe Kleine-König } else { 47576821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 47681ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 47776821e22SUwe Kleine-König } 47876821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 47976821e22SUwe Kleine-König 48076821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 48176821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 482ab4382d2SGreg Kroah-Hartman } 483ab4382d2SGreg Kroah-Hartman 4846aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 485ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 486ab4382d2SGreg Kroah-Hartman { 487ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 488ab4382d2SGreg Kroah-Hartman 489ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 49058362d5bSUwe Kleine-König 49158362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 492ab4382d2SGreg Kroah-Hartman } 493ab4382d2SGreg Kroah-Hartman 49491a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 4956aed2a88SUwe Kleine-König 4966aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 497ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 498ab4382d2SGreg Kroah-Hartman { 499ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 500ab4382d2SGreg Kroah-Hartman 5015e42e9a3SPeter Hurley if (sport->port.x_char) { 5025e42e9a3SPeter Hurley /* Send next char */ 50327c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5047e2fb5aaSJiada Wang sport->port.icount.tx++; 5057e2fb5aaSJiada Wang sport->port.x_char = 0; 5065e42e9a3SPeter Hurley return; 5075e42e9a3SPeter Hurley } 5085e42e9a3SPeter Hurley 5095e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5105e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 5115e42e9a3SPeter Hurley return; 5125e42e9a3SPeter Hurley } 5135e42e9a3SPeter Hurley 51491a1a909SJiada Wang if (sport->dma_is_enabled) { 5154444dcf1SUwe Kleine-König u32 ucr1; 51691a1a909SJiada Wang /* 51791a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 51891a1a909SJiada Wang * and the TX IRQ is disabled. 51991a1a909SJiada Wang **/ 5204444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5214444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXMPTYEN; 52291a1a909SJiada Wang if (sport->dma_is_txing) { 5234444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5244444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 52591a1a909SJiada Wang } else { 5264444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 52791a1a909SJiada Wang imx_dma_tx(sport); 52891a1a909SJiada Wang } 52991a1a909SJiada Wang 5305aabd3b0SIan Jamison return; 5310c549223SUwe Kleine-König } 5325aabd3b0SIan Jamison 5335aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 53427c84426SUwe Kleine-König !(imx_uart_readl(sport, uts_reg(sport)) & UTS_TXFULL)) { 535ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 536ab4382d2SGreg Kroah-Hartman * out the port here */ 53727c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 538ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 539ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 540ab4382d2SGreg Kroah-Hartman } 541ab4382d2SGreg Kroah-Hartman 542ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 543ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 544ab4382d2SGreg Kroah-Hartman 545ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 546ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 547ab4382d2SGreg Kroah-Hartman } 548ab4382d2SGreg Kroah-Hartman 549b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 550b4cdc8f6SHuang Shijie { 551b4cdc8f6SHuang Shijie struct imx_port *sport = data; 552b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 553b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 554b4cdc8f6SHuang Shijie unsigned long flags; 5554444dcf1SUwe Kleine-König u32 ucr1; 556b4cdc8f6SHuang Shijie 55742f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 55842f752b3SDirk Behme 559b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 560b4cdc8f6SHuang Shijie 5614444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5624444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5634444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 564a2c718ceSDirk Behme 56542f752b3SDirk Behme /* update the stat */ 56642f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 56742f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 56842f752b3SDirk Behme 56942f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 57042f752b3SDirk Behme 571b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 572b4cdc8f6SHuang Shijie 573d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 574b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5759ce4f8f3SGreg Kroah-Hartman 5760bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5770bbc9b81SJiada Wang imx_dma_tx(sport); 578*18665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 579*18665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 580*18665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 581*18665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 582*18665414SUwe Kleine-König } 58364432a85SUwe Kleine-König 5840bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 585b4cdc8f6SHuang Shijie } 586b4cdc8f6SHuang Shijie 5876aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5887cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 589b4cdc8f6SHuang Shijie { 590b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 591b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 592b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 593b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 594b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 595*18665414SUwe Kleine-König u32 ucr1, ucr4; 596b4cdc8f6SHuang Shijie int ret; 597b4cdc8f6SHuang Shijie 59842f752b3SDirk Behme if (sport->dma_is_txing) 599b4cdc8f6SHuang Shijie return; 600b4cdc8f6SHuang Shijie 601*18665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 602*18665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 603*18665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 604*18665414SUwe Kleine-König 605b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 606b4cdc8f6SHuang Shijie 6077942f857SDirk Behme if (xmit->tail < xmit->head) { 6087942f857SDirk Behme sport->dma_tx_nents = 1; 6097942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6107942f857SDirk Behme } else { 611b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 612b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 613b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 614b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 615b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 616b4cdc8f6SHuang Shijie } 617b4cdc8f6SHuang Shijie 618b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 619b4cdc8f6SHuang Shijie if (ret == 0) { 620b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 621b4cdc8f6SHuang Shijie return; 622b4cdc8f6SHuang Shijie } 623b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 624b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 625b4cdc8f6SHuang Shijie if (!desc) { 62624649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 62724649821SDirk Behme DMA_TO_DEVICE); 628b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 629b4cdc8f6SHuang Shijie return; 630b4cdc8f6SHuang Shijie } 631b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 632b4cdc8f6SHuang Shijie desc->callback_param = sport; 633b4cdc8f6SHuang Shijie 634b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 635b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 636a2c718ceSDirk Behme 6374444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6384444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6394444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 640a2c718ceSDirk Behme 641b4cdc8f6SHuang Shijie /* fire it */ 642b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 643b4cdc8f6SHuang Shijie dmaengine_submit(desc); 644b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 645b4cdc8f6SHuang Shijie return; 646b4cdc8f6SHuang Shijie } 647b4cdc8f6SHuang Shijie 6486aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 649ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 650ab4382d2SGreg Kroah-Hartman { 651ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6524444dcf1SUwe Kleine-König u32 ucr1; 653ab4382d2SGreg Kroah-Hartman 65417b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 655*18665414SUwe Kleine-König u32 ucr2; 6564444dcf1SUwe Kleine-König 6574444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 65817b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6594444dcf1SUwe Kleine-König imx_port_rts_active(sport, &ucr2); 6601a613626SFabio Estevam else 6614444dcf1SUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 6624444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 66317b8f2a3SUwe Kleine-König 66476821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 66576821e22SUwe Kleine-König imx_stop_rx(port); 66676821e22SUwe Kleine-König 667*18665414SUwe Kleine-König /* 668*18665414SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA is off. 669*18665414SUwe Kleine-König * In the DMA case this is done in the tx-callback. 670*18665414SUwe Kleine-König */ 671*18665414SUwe Kleine-König if (!sport->dma_is_enabled) { 672*18665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 6734444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 6744444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 67517b8f2a3SUwe Kleine-König } 676*18665414SUwe Kleine-König } 67717b8f2a3SUwe Kleine-König 678b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 6794444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6804444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1); 681b4cdc8f6SHuang Shijie } 682ab4382d2SGreg Kroah-Hartman 683b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 68491a1a909SJiada Wang if (sport->port.x_char) { 68591a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 68691a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 6874444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6884444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 6894444dcf1SUwe Kleine-König ucr1 |= UCR1_TXMPTYEN; 6904444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 69191a1a909SJiada Wang return; 69291a1a909SJiada Wang } 69391a1a909SJiada Wang 6945e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6955e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6967cb92fd2SHuang Shijie imx_dma_tx(sport); 697b4cdc8f6SHuang Shijie return; 698b4cdc8f6SHuang Shijie } 699ab4382d2SGreg Kroah-Hartman } 700ab4382d2SGreg Kroah-Hartman 701ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 702ab4382d2SGreg Kroah-Hartman { 703ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7044444dcf1SUwe Kleine-König u32 usr1; 705ab4382d2SGreg Kroah-Hartman unsigned long flags; 706ab4382d2SGreg Kroah-Hartman 707ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 708ab4382d2SGreg Kroah-Hartman 70927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7104444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7114444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 712ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 713ab4382d2SGreg Kroah-Hartman 714ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 715ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 716ab4382d2SGreg Kroah-Hartman } 717ab4382d2SGreg Kroah-Hartman 718ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 719ab4382d2SGreg Kroah-Hartman { 720ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 721ab4382d2SGreg Kroah-Hartman unsigned long flags; 722ab4382d2SGreg Kroah-Hartman 723ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 724ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 725ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 726ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 727ab4382d2SGreg Kroah-Hartman } 728ab4382d2SGreg Kroah-Hartman 729ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 730ab4382d2SGreg Kroah-Hartman { 731ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 732ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 73392a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 7344444dcf1SUwe Kleine-König unsigned long flags; 735ab4382d2SGreg Kroah-Hartman 736ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 737ab4382d2SGreg Kroah-Hartman 73827c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 7394444dcf1SUwe Kleine-König u32 usr2; 7404444dcf1SUwe Kleine-König 741ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 742ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 743ab4382d2SGreg Kroah-Hartman 74427c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 745ab4382d2SGreg Kroah-Hartman 7464444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 7474444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 74827c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 749ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 750ab4382d2SGreg Kroah-Hartman continue; 751ab4382d2SGreg Kroah-Hartman } 752ab4382d2SGreg Kroah-Hartman 753ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 754ab4382d2SGreg Kroah-Hartman continue; 755ab4382d2SGreg Kroah-Hartman 756019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 757019dc9eaSHui Wang if (rx & URXD_BRK) 758019dc9eaSHui Wang sport->port.icount.brk++; 759019dc9eaSHui Wang else if (rx & URXD_PRERR) 760ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 761ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 762ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 763ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 764ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 765ab4382d2SGreg Kroah-Hartman 766ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 767ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 768ab4382d2SGreg Kroah-Hartman goto out; 769ab4382d2SGreg Kroah-Hartman continue; 770ab4382d2SGreg Kroah-Hartman } 771ab4382d2SGreg Kroah-Hartman 7728d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 773ab4382d2SGreg Kroah-Hartman 774019dc9eaSHui Wang if (rx & URXD_BRK) 775019dc9eaSHui Wang flg = TTY_BREAK; 776019dc9eaSHui Wang else if (rx & URXD_PRERR) 777ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 778ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 779ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 780ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 781ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 782ab4382d2SGreg Kroah-Hartman 783ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 784ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 785ab4382d2SGreg Kroah-Hartman #endif 786ab4382d2SGreg Kroah-Hartman } 787ab4382d2SGreg Kroah-Hartman 78855d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 78955d8693aSJiada Wang goto out; 79055d8693aSJiada Wang 7919b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 7929b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 793ab4382d2SGreg Kroah-Hartman } 794ab4382d2SGreg Kroah-Hartman 795ab4382d2SGreg Kroah-Hartman out: 796ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7972e124b4aSJiri Slaby tty_flip_buffer_push(port); 798ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 799ab4382d2SGreg Kroah-Hartman } 800ab4382d2SGreg Kroah-Hartman 80118a42088SPeter Senna Tschudin static void clear_rx_errors(struct imx_port *sport); 802b4cdc8f6SHuang Shijie 80366f95884SUwe Kleine-König /* 80466f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 80566f95884SUwe Kleine-König */ 80666f95884SUwe Kleine-König static unsigned int imx_get_hwmctrl(struct imx_port *sport) 80766f95884SUwe Kleine-König { 80866f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 80927c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 81027c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 81166f95884SUwe Kleine-König 81266f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 81366f95884SUwe Kleine-König tmp |= TIOCM_CTS; 81466f95884SUwe Kleine-König 81566f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 8164b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 81766f95884SUwe Kleine-König tmp |= TIOCM_CAR; 81866f95884SUwe Kleine-König 81966f95884SUwe Kleine-König if (sport->dte_mode) 82027c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 82166f95884SUwe Kleine-König tmp |= TIOCM_RI; 82266f95884SUwe Kleine-König 82366f95884SUwe Kleine-König return tmp; 82466f95884SUwe Kleine-König } 82566f95884SUwe Kleine-König 82666f95884SUwe Kleine-König /* 82766f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 82866f95884SUwe Kleine-König */ 82966f95884SUwe Kleine-König static void imx_mctrl_check(struct imx_port *sport) 83066f95884SUwe Kleine-König { 83166f95884SUwe Kleine-König unsigned int status, changed; 83266f95884SUwe Kleine-König 83366f95884SUwe Kleine-König status = imx_get_hwmctrl(sport); 83466f95884SUwe Kleine-König changed = status ^ sport->old_status; 83566f95884SUwe Kleine-König 83666f95884SUwe Kleine-König if (changed == 0) 83766f95884SUwe Kleine-König return; 83866f95884SUwe Kleine-König 83966f95884SUwe Kleine-König sport->old_status = status; 84066f95884SUwe Kleine-König 84166f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 84266f95884SUwe Kleine-König sport->port.icount.rng++; 84366f95884SUwe Kleine-König if (changed & TIOCM_DSR) 84466f95884SUwe Kleine-König sport->port.icount.dsr++; 84566f95884SUwe Kleine-König if (changed & TIOCM_CAR) 84666f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 84766f95884SUwe Kleine-König if (changed & TIOCM_CTS) 84866f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 84966f95884SUwe Kleine-König 85066f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 85166f95884SUwe Kleine-König } 85266f95884SUwe Kleine-König 853ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 854ab4382d2SGreg Kroah-Hartman { 855ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 85643776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 8574d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 858ab4382d2SGreg Kroah-Hartman 85927c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 86027c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 86127c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 86227c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 86327c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 86427c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 865ab4382d2SGreg Kroah-Hartman 86643776896SUwe Kleine-König /* 86743776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 86843776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 86943776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 87043776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 87143776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 87243776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 87343776896SUwe Kleine-König */ 87443776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 87543776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 87643776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 87743776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 87843776896SUwe Kleine-König if ((ucr1 & UCR1_TXMPTYEN) == 0) 87943776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 88043776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 88143776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 88243776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 88343776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 88443776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 88543776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 88643776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 88743776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 88843776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 88943776896SUwe Kleine-König usr2 &= ~USR2_ORE; 89043776896SUwe Kleine-König 89143776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 892ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 8934d845a62SUwe Kleine-König ret = IRQ_HANDLED; 894b4cdc8f6SHuang Shijie } 895ab4382d2SGreg Kroah-Hartman 89643776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 897ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 8984d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8994d845a62SUwe Kleine-König } 900ab4382d2SGreg Kroah-Hartman 9010399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 90227e16501SUwe Kleine-König unsigned long flags; 90327e16501SUwe Kleine-König 90427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 90527e16501SUwe Kleine-König 90627e16501SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 90727e16501SUwe Kleine-König imx_mctrl_check(sport); 90827e16501SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 90927e16501SUwe Kleine-König 91027e16501SUwe Kleine-König ret = IRQ_HANDLED; 91127e16501SUwe Kleine-König } 91227e16501SUwe Kleine-König 9130399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 914ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 9154d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9164d845a62SUwe Kleine-König } 917ab4382d2SGreg Kroah-Hartman 9180399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 91927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 9204d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9214d845a62SUwe Kleine-König } 922db1a9b55SFabio Estevam 9230399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 924f1f836e4SAlexander Stein sport->port.icount.overrun++; 92527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 9264d845a62SUwe Kleine-König ret = IRQ_HANDLED; 927f1f836e4SAlexander Stein } 928f1f836e4SAlexander Stein 9294d845a62SUwe Kleine-König return ret; 930ab4382d2SGreg Kroah-Hartman } 931ab4382d2SGreg Kroah-Hartman 932ab4382d2SGreg Kroah-Hartman /* 933ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 934ab4382d2SGreg Kroah-Hartman */ 935ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 936ab4382d2SGreg Kroah-Hartman { 937ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9381ce43e58SHuang Shijie unsigned int ret; 939ab4382d2SGreg Kroah-Hartman 94027c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 9411ce43e58SHuang Shijie 9421ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 943686351f3SUwe Kleine-König if (sport->dma_is_txing) 9441ce43e58SHuang Shijie ret = 0; 9451ce43e58SHuang Shijie 9461ce43e58SHuang Shijie return ret; 947ab4382d2SGreg Kroah-Hartman } 948ab4382d2SGreg Kroah-Hartman 9496aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 95058362d5bSUwe Kleine-König static unsigned int imx_get_mctrl(struct uart_port *port) 95158362d5bSUwe Kleine-König { 95258362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 95358362d5bSUwe Kleine-König unsigned int ret = imx_get_hwmctrl(sport); 95458362d5bSUwe Kleine-König 95558362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 95658362d5bSUwe Kleine-König 95758362d5bSUwe Kleine-König return ret; 95858362d5bSUwe Kleine-König } 95958362d5bSUwe Kleine-König 9606aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 961ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 962ab4382d2SGreg Kroah-Hartman { 963ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9644444dcf1SUwe Kleine-König u32 ucr3, uts; 965ab4382d2SGreg Kroah-Hartman 96617b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 9674444dcf1SUwe Kleine-König u32 ucr2; 9684444dcf1SUwe Kleine-König 9694444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 9704444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 971ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 9724444dcf1SUwe Kleine-König ucr2 |= UCR2_CTS | UCR2_CTSC; 9734444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 97417b8f2a3SUwe Kleine-König } 9756b471a98SHuang Shijie 9764444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 97790ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 9784444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 9794444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 98090ebc483SUwe Kleine-König 9814444dcf1SUwe Kleine-König uts = imx_uart_readl(sport, uts_reg(sport)) & ~UTS_LOOP; 9826b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 9834444dcf1SUwe Kleine-König uts |= UTS_LOOP; 9844444dcf1SUwe Kleine-König imx_uart_writel(sport, uts, uts_reg(sport)); 98558362d5bSUwe Kleine-König 98658362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 987ab4382d2SGreg Kroah-Hartman } 988ab4382d2SGreg Kroah-Hartman 989ab4382d2SGreg Kroah-Hartman /* 990ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 991ab4382d2SGreg Kroah-Hartman */ 992ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 993ab4382d2SGreg Kroah-Hartman { 994ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9954444dcf1SUwe Kleine-König unsigned long flags; 9964444dcf1SUwe Kleine-König u32 ucr1; 997ab4382d2SGreg Kroah-Hartman 998ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 999ab4382d2SGreg Kroah-Hartman 10004444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1001ab4382d2SGreg Kroah-Hartman 1002ab4382d2SGreg Kroah-Hartman if (break_state != 0) 10034444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1004ab4382d2SGreg Kroah-Hartman 10054444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1006ab4382d2SGreg Kroah-Hartman 1007ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1008ab4382d2SGreg Kroah-Hartman } 1009ab4382d2SGreg Kroah-Hartman 1010cc568849SUwe Kleine-König /* 1011cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1012cc568849SUwe Kleine-König * modem status signals. 1013cc568849SUwe Kleine-König */ 1014e99e88a9SKees Cook static void imx_timeout(struct timer_list *t) 1015cc568849SUwe Kleine-König { 1016e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1017cc568849SUwe Kleine-König unsigned long flags; 1018cc568849SUwe Kleine-König 1019cc568849SUwe Kleine-König if (sport->port.state) { 1020cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 1021cc568849SUwe Kleine-König imx_mctrl_check(sport); 1022cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1023cc568849SUwe Kleine-König 1024cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1025cc568849SUwe Kleine-König } 1026cc568849SUwe Kleine-König } 1027cc568849SUwe Kleine-König 1028351ea50dSGreg Kroah-Hartman #define RX_BUF_SIZE (PAGE_SIZE) 1029351ea50dSGreg Kroah-Hartman 1030b4cdc8f6SHuang Shijie /* 1031905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1032b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1033905c0decSLucas Stach * [2] the aging timer expires 1034b4cdc8f6SHuang Shijie * 1035905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1036905c0decSLucas Stach * for at least 8 byte durations. 1037b4cdc8f6SHuang Shijie */ 1038b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 1039b4cdc8f6SHuang Shijie { 1040b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1041b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1042b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 10437cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1044b4cdc8f6SHuang Shijie struct dma_tx_state state; 10459d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1046b4cdc8f6SHuang Shijie enum dma_status status; 10479d297239SNandor Han unsigned int w_bytes = 0; 10489d297239SNandor Han unsigned int r_bytes; 10499d297239SNandor Han unsigned int bd_size; 1050b4cdc8f6SHuang Shijie 1051f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 1052392bceedSPhilipp Zabel 10539d297239SNandor Han if (status == DMA_ERROR) { 105441d98b5dSNandor Han clear_rx_errors(sport); 10559d297239SNandor Han return; 10569d297239SNandor Han } 1057b4cdc8f6SHuang Shijie 10589b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1059976b39cdSLucas Stach 1060976b39cdSLucas Stach /* 10619d297239SNandor Han * The state-residue variable represents the empty space 10629d297239SNandor Han * relative to the entire buffer. Taking this in consideration 10639d297239SNandor Han * the head is always calculated base on the buffer total 10649d297239SNandor Han * length - DMA transaction residue. The UART script from the 10659d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 10669d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 10679d297239SNandor Han * Taking this in consideration the tail is always at the 10689d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1069976b39cdSLucas Stach */ 10709d297239SNandor Han 10719d297239SNandor Han /* Calculate the head */ 10729d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 10739d297239SNandor Han 10749d297239SNandor Han /* Calculate the tail. */ 10759d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 10769d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 10779d297239SNandor Han 10789d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 10799d297239SNandor Han rx_ring->head > rx_ring->tail) { 10809d297239SNandor Han 10819d297239SNandor Han /* Move data from tail to head */ 10829d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 10839d297239SNandor Han 10849d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 10859d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 10869d297239SNandor Han DMA_FROM_DEVICE); 10879d297239SNandor Han 10889d297239SNandor Han w_bytes = tty_insert_flip_string(port, 10899d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 10909d297239SNandor Han 10919d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 10929d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 10939d297239SNandor Han DMA_FROM_DEVICE); 10949d297239SNandor Han 10959d297239SNandor Han if (w_bytes != r_bytes) 10969d297239SNandor Han sport->port.icount.buf_overrun++; 10979d297239SNandor Han 10989d297239SNandor Han sport->port.icount.rx += w_bytes; 10999d297239SNandor Han } else { 11009d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11019d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1102ee5e7c10SRobin Gong } 11039d297239SNandor Han } 11049d297239SNandor Han 11059d297239SNandor Han if (w_bytes) { 11069d297239SNandor Han tty_flip_buffer_push(port); 11079d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 11089d297239SNandor Han } 11099d297239SNandor Han } 11109d297239SNandor Han 1111351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 1112351ea50dSGreg Kroah-Hartman #define RX_DMA_PERIODS 4 1113351ea50dSGreg Kroah-Hartman 1114b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 1115b4cdc8f6SHuang Shijie { 1116b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1117b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1118b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1119b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1120b4cdc8f6SHuang Shijie int ret; 1121b4cdc8f6SHuang Shijie 11229d297239SNandor Han sport->rx_ring.head = 0; 11239d297239SNandor Han sport->rx_ring.tail = 0; 1124351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 11259d297239SNandor Han 1126351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1127b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1128b4cdc8f6SHuang Shijie if (ret == 0) { 1129b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1130b4cdc8f6SHuang Shijie return -EINVAL; 1131b4cdc8f6SHuang Shijie } 11329d297239SNandor Han 11339d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 11349d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 11359d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 11369d297239SNandor Han 1137b4cdc8f6SHuang Shijie if (!desc) { 113824649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1139b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1140b4cdc8f6SHuang Shijie return -EINVAL; 1141b4cdc8f6SHuang Shijie } 1142b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 1143b4cdc8f6SHuang Shijie desc->callback_param = sport; 1144b4cdc8f6SHuang Shijie 1145b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 11464139fd76SRomain Perier sport->dma_is_rxing = 1; 11479d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1148b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1149b4cdc8f6SHuang Shijie return 0; 1150b4cdc8f6SHuang Shijie } 1151b4cdc8f6SHuang Shijie 115241d98b5dSNandor Han static void clear_rx_errors(struct imx_port *sport) 115341d98b5dSNandor Han { 115445ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 11554444dcf1SUwe Kleine-König u32 usr1, usr2; 115641d98b5dSNandor Han 11574444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 11584444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 115941d98b5dSNandor Han 11604444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 116141d98b5dSNandor Han sport->port.icount.brk++; 116227c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 116345ca673eSTroy Kisky uart_handle_break(&sport->port); 116445ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 116545ca673eSTroy Kisky sport->port.icount.buf_overrun++; 116645ca673eSTroy Kisky tty_flip_buffer_push(port); 116745ca673eSTroy Kisky } else { 116845ca673eSTroy Kisky dev_err(sport->port.dev, "DMA transaction error.\n"); 11694444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 117041d98b5dSNandor Han sport->port.icount.frame++; 117127c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 11724444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 117341d98b5dSNandor Han sport->port.icount.parity++; 117427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 117541d98b5dSNandor Han } 117645ca673eSTroy Kisky } 117741d98b5dSNandor Han 11784444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 117941d98b5dSNandor Han sport->port.icount.overrun++; 118027c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 118141d98b5dSNandor Han } 118241d98b5dSNandor Han 118341d98b5dSNandor Han } 118441d98b5dSNandor Han 1185cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1186cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1187184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1188184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1189cc32382dSLucas Stach 1190cc32382dSLucas Stach static void imx_setup_ufcr(struct imx_port *sport, 1191cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1192cc32382dSLucas Stach { 1193cc32382dSLucas Stach unsigned int val; 1194cc32382dSLucas Stach 1195cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 119627c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1197cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 119827c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1199cc32382dSLucas Stach } 1200cc32382dSLucas Stach 1201b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1202b4cdc8f6SHuang Shijie { 1203b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1204e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1205b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1206b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 12079d297239SNandor Han sport->rx_cookie = -EINVAL; 1208b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1209b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1210b4cdc8f6SHuang Shijie } 1211b4cdc8f6SHuang Shijie 1212b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1213e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1214b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1215b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1216b4cdc8f6SHuang Shijie } 1217b4cdc8f6SHuang Shijie } 1218b4cdc8f6SHuang Shijie 1219b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1220b4cdc8f6SHuang Shijie { 1221b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1222b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1223b4cdc8f6SHuang Shijie int ret; 1224b4cdc8f6SHuang Shijie 1225b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1226b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1227b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1228b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1229b4cdc8f6SHuang Shijie ret = -EINVAL; 1230b4cdc8f6SHuang Shijie goto err; 1231b4cdc8f6SHuang Shijie } 1232b4cdc8f6SHuang Shijie 1233b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1234b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1235b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1236184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1237184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1238b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1239b4cdc8f6SHuang Shijie if (ret) { 1240b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1241b4cdc8f6SHuang Shijie goto err; 1242b4cdc8f6SHuang Shijie } 1243b4cdc8f6SHuang Shijie 1244f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1245b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1246b4cdc8f6SHuang Shijie ret = -ENOMEM; 1247b4cdc8f6SHuang Shijie goto err; 1248b4cdc8f6SHuang Shijie } 12499d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1250b4cdc8f6SHuang Shijie 1251b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1252b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1253b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1254b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1255b4cdc8f6SHuang Shijie ret = -EINVAL; 1256b4cdc8f6SHuang Shijie goto err; 1257b4cdc8f6SHuang Shijie } 1258b4cdc8f6SHuang Shijie 1259b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1260b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1261b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1262184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1263b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1264b4cdc8f6SHuang Shijie if (ret) { 1265b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1266b4cdc8f6SHuang Shijie goto err; 1267b4cdc8f6SHuang Shijie } 1268b4cdc8f6SHuang Shijie 1269b4cdc8f6SHuang Shijie return 0; 1270b4cdc8f6SHuang Shijie err: 1271b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1272b4cdc8f6SHuang Shijie return ret; 1273b4cdc8f6SHuang Shijie } 1274b4cdc8f6SHuang Shijie 1275b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1276b4cdc8f6SHuang Shijie { 12774444dcf1SUwe Kleine-König u32 ucr1; 1278b4cdc8f6SHuang Shijie 127902b0abd3SUwe Kleine-König imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 128002b0abd3SUwe Kleine-König 1281b4cdc8f6SHuang Shijie /* set UCR1 */ 12824444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12834444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 12844444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1285b4cdc8f6SHuang Shijie 1286b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1287b4cdc8f6SHuang Shijie } 1288b4cdc8f6SHuang Shijie 1289b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1290b4cdc8f6SHuang Shijie { 12914444dcf1SUwe Kleine-König u32 ucr1, ucr2; 1292b4cdc8f6SHuang Shijie 1293b4cdc8f6SHuang Shijie /* clear UCR1 */ 12944444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12954444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 12964444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1297b4cdc8f6SHuang Shijie 1298b4cdc8f6SHuang Shijie /* clear UCR2 */ 12994444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 13004444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN); 13014444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1302b4cdc8f6SHuang Shijie 1303184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1304184bd70bSLucas Stach 1305b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1306b4cdc8f6SHuang Shijie } 1307b4cdc8f6SHuang Shijie 1308ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1309ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1310ab4382d2SGreg Kroah-Hartman 1311ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1312ab4382d2SGreg Kroah-Hartman { 1313ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1314458e2c82SFabio Estevam int retval, i; 13154444dcf1SUwe Kleine-König unsigned long flags; 13164238c00bSUwe Kleine-König int dma_is_inited = 0; 13174444dcf1SUwe Kleine-König u32 ucr1, ucr2, ucr4; 1318ab4382d2SGreg Kroah-Hartman 131928eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 132028eb4274SHuang Shijie if (retval) 1321cb0f0a5fSFabio Estevam return retval; 132228eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 13230c375501SHuang Shijie if (retval) { 13240c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1325cb0f0a5fSFabio Estevam return retval; 13260c375501SHuang Shijie } 132728eb4274SHuang Shijie 1328cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1329ab4382d2SGreg Kroah-Hartman 1330ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1331ab4382d2SGreg Kroah-Hartman * requesting IRQs 1332ab4382d2SGreg Kroah-Hartman */ 13334444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1334ab4382d2SGreg Kroah-Hartman 1335ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 13364444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 13374444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1338ab4382d2SGreg Kroah-Hartman 13394444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1340ab4382d2SGreg Kroah-Hartman 13417e11577eSLucas Stach /* Can we enable the DMA support? */ 13424238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 13434238c00bSUwe Kleine-König dma_is_inited = 1; 13447e11577eSLucas Stach 134553794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1346772f8991SHuang Shijie /* Reset fifo's and state machines */ 1347458e2c82SFabio Estevam i = 100; 1348458e2c82SFabio Estevam 13494444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 13504444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 13514444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1352458e2c82SFabio Estevam 135327c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1354458e2c82SFabio Estevam udelay(1); 1355ab4382d2SGreg Kroah-Hartman 1356ab4382d2SGreg Kroah-Hartman /* 1357ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1358ab4382d2SGreg Kroah-Hartman */ 135927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 136027c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1361ab4382d2SGreg Kroah-Hartman 13624444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 13634444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 13646376cd39SNandor Han if (sport->have_rtscts) 13654444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1366ab4382d2SGreg Kroah-Hartman 13674444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1368ab4382d2SGreg Kroah-Hartman 13694444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 13701f043572STroy Kisky if (!sport->dma_is_enabled) 13714444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 13724444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 13736f026d6bSJiada Wang 13744444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 13754444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1376bff09b09SLucas Stach if (!sport->have_rtscts) 13774444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 137816804d68SUwe Kleine-König /* 137916804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 138016804d68SUwe Kleine-König * we're using RTSD instead. 138116804d68SUwe Kleine-König */ 138216804d68SUwe Kleine-König if (!is_imx1_uart(sport)) 13834444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 13844444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1385ab4382d2SGreg Kroah-Hartman 1386a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 13874444dcf1SUwe Kleine-König u32 ucr3; 138816804d68SUwe Kleine-König 13894444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 13904444dcf1SUwe Kleine-König 13914444dcf1SUwe Kleine-König ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 139216804d68SUwe Kleine-König 139316804d68SUwe Kleine-König if (sport->dte_mode) 1394e61c38d8SUwe Kleine-König /* disable broken interrupts */ 13954444dcf1SUwe Kleine-König ucr3 &= ~(UCR3_RI | UCR3_DCD); 139616804d68SUwe Kleine-König 13974444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 1398ab4382d2SGreg Kroah-Hartman } 1399ab4382d2SGreg Kroah-Hartman 1400ab4382d2SGreg Kroah-Hartman /* 1401ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1402ab4382d2SGreg Kroah-Hartman */ 1403ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 140418a42088SPeter Senna Tschudin 140576821e22SUwe Kleine-König if (dma_is_inited) { 140676821e22SUwe Kleine-König imx_enable_dma(sport); 140718a42088SPeter Senna Tschudin start_rx_dma(sport); 140876821e22SUwe Kleine-König } else { 140976821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 141076821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 141176821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 141281ca8e82SUwe Kleine-König 141381ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 141481ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 141581ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 141676821e22SUwe Kleine-König } 141718a42088SPeter Senna Tschudin 1418ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1419ab4382d2SGreg Kroah-Hartman 1420ab4382d2SGreg Kroah-Hartman return 0; 1421ab4382d2SGreg Kroah-Hartman } 1422ab4382d2SGreg Kroah-Hartman 1423ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1424ab4382d2SGreg Kroah-Hartman { 1425ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 14269ec1882dSXinyu Chen unsigned long flags; 14274444dcf1SUwe Kleine-König u32 ucr1, ucr2; 1428ab4382d2SGreg Kroah-Hartman 1429b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1430a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1431a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1432e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1433e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 14349d297239SNandor Han 143573631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1436a4688bcdSHuang Shijie imx_stop_tx(port); 1437b4cdc8f6SHuang Shijie imx_stop_rx(port); 1438b4cdc8f6SHuang Shijie imx_disable_dma(sport); 143973631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1440b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1441b4cdc8f6SHuang Shijie } 1442b4cdc8f6SHuang Shijie 144358362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 144458362d5bSUwe Kleine-König 14459ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14464444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 144781ca8e82SUwe Kleine-König ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 14484444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 14499ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1450ab4382d2SGreg Kroah-Hartman 1451ab4382d2SGreg Kroah-Hartman /* 1452ab4382d2SGreg Kroah-Hartman * Stop our timer. 1453ab4382d2SGreg Kroah-Hartman */ 1454ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1455ab4382d2SGreg Kroah-Hartman 1456ab4382d2SGreg Kroah-Hartman /* 1457ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1458ab4382d2SGreg Kroah-Hartman */ 1459ab4382d2SGreg Kroah-Hartman 14609ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14614444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 146276821e22SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1463ab4382d2SGreg Kroah-Hartman 14644444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14659ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 146628eb4274SHuang Shijie 146728eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 146828eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1469ab4382d2SGreg Kroah-Hartman } 1470ab4382d2SGreg Kroah-Hartman 14716aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 1472eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1473eb56b7edSHuang Shijie { 1474eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 147582e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 14764444dcf1SUwe Kleine-König u32 ucr2; 14774f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1478eb56b7edSHuang Shijie 147982e86ae9SDirk Behme if (!sport->dma_chan_tx) 148082e86ae9SDirk Behme return; 148182e86ae9SDirk Behme 1482eb56b7edSHuang Shijie sport->tx_bytes = 0; 1483eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 148482e86ae9SDirk Behme if (sport->dma_is_txing) { 14854444dcf1SUwe Kleine-König u32 ucr1; 14864444dcf1SUwe Kleine-König 148782e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 148882e86ae9SDirk Behme DMA_TO_DEVICE); 14894444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 14904444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 14914444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14920f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1493eb56b7edSHuang Shijie } 1494934084a9SFabio Estevam 1495934084a9SFabio Estevam /* 1496934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1497263763c1SMartyn Welch * 1498934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1499934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1500263763c1SMartyn Welch * and UTS[6-3]". 1501263763c1SMartyn Welch * 1502263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1503263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1504263763c1SMartyn Welch * registers. 1505934084a9SFabio Estevam */ 150627c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 150727c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 150827c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1509934084a9SFabio Estevam 15104444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15114444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 15124444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1513934084a9SFabio Estevam 151427c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1515934084a9SFabio Estevam udelay(1); 1516934084a9SFabio Estevam 1517934084a9SFabio Estevam /* Restore the registers */ 151827c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 151927c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 152027c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1521eb56b7edSHuang Shijie } 1522eb56b7edSHuang Shijie 1523ab4382d2SGreg Kroah-Hartman static void 1524ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1525ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1526ab4382d2SGreg Kroah-Hartman { 1527ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1528ab4382d2SGreg Kroah-Hartman unsigned long flags; 15294444dcf1SUwe Kleine-König u32 ucr2, old_ucr1, old_ucr2, ufcr; 153058362d5bSUwe Kleine-König unsigned int baud, quot; 1531ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 15324444dcf1SUwe Kleine-König unsigned long div; 1533ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1534ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1535ab4382d2SGreg Kroah-Hartman 1536ab4382d2SGreg Kroah-Hartman /* 1537ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1538ab4382d2SGreg Kroah-Hartman */ 1539ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1540ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1541ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1542ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1543ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1544ab4382d2SGreg Kroah-Hartman } 1545ab4382d2SGreg Kroah-Hartman 1546ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1547ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1548ab4382d2SGreg Kroah-Hartman else 1549ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1550ab4382d2SGreg Kroah-Hartman 1551ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1552ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1553ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 155417b8f2a3SUwe Kleine-König 155512fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 155617b8f2a3SUwe Kleine-König /* 155717b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 155817b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 155917b8f2a3SUwe Kleine-König * disabled. 156017b8f2a3SUwe Kleine-König */ 156158362d5bSUwe Kleine-König if (port->rs485.flags & 156258362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 156358362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 15641a613626SFabio Estevam else 15651a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 156612fe59f9SFabio Estevam } else { 156758362d5bSUwe Kleine-König imx_port_rts_auto(sport, &ucr2); 156812fe59f9SFabio Estevam } 1569ab4382d2SGreg Kroah-Hartman } else { 1570ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1571ab4382d2SGreg Kroah-Hartman } 157258362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 157317b8f2a3SUwe Kleine-König /* disable transmitter */ 157458362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 157558362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 15761a613626SFabio Estevam else 15771a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 157858362d5bSUwe Kleine-König } 157958362d5bSUwe Kleine-König 1580ab4382d2SGreg Kroah-Hartman 1581ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1582ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1583ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1584ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1585ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1586ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1587ab4382d2SGreg Kroah-Hartman } 1588ab4382d2SGreg Kroah-Hartman 1589995234daSEric Miao del_timer_sync(&sport->timer); 1590995234daSEric Miao 1591ab4382d2SGreg Kroah-Hartman /* 1592ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1593ab4382d2SGreg Kroah-Hartman */ 1594ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1595ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1596ab4382d2SGreg Kroah-Hartman 1597ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1598ab4382d2SGreg Kroah-Hartman 1599ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1600ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1601ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1602ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1603ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1604ab4382d2SGreg Kroah-Hartman 1605ab4382d2SGreg Kroah-Hartman /* 1606ab4382d2SGreg Kroah-Hartman * Characters to ignore 1607ab4382d2SGreg Kroah-Hartman */ 1608ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1609ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1610865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1611ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1612ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1613ab4382d2SGreg Kroah-Hartman /* 1614ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1615ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1616ab4382d2SGreg Kroah-Hartman */ 1617ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1618ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1619ab4382d2SGreg Kroah-Hartman } 1620ab4382d2SGreg Kroah-Hartman 162155d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 162255d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 162355d8693aSJiada Wang 1624ab4382d2SGreg Kroah-Hartman /* 1625ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1626ab4382d2SGreg Kroah-Hartman */ 1627ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1628ab4382d2SGreg Kroah-Hartman 1629ab4382d2SGreg Kroah-Hartman /* 1630ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1631ab4382d2SGreg Kroah-Hartman */ 163227c84426SUwe Kleine-König old_ucr1 = imx_uart_readl(sport, UCR1); 163327c84426SUwe Kleine-König imx_uart_writel(sport, 163427c84426SUwe Kleine-König old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 163527c84426SUwe Kleine-König UCR1); 163681ca8e82SUwe Kleine-König old_ucr2 = imx_uart_readl(sport, UCR2); 163781ca8e82SUwe Kleine-König imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2); 1638ab4382d2SGreg Kroah-Hartman 163927c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)) 1640ab4382d2SGreg Kroah-Hartman barrier(); 1641ab4382d2SGreg Kroah-Hartman 1642ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 164381ca8e82SUwe Kleine-König imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2); 164486a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1645ab4382d2SGreg Kroah-Hartman 164609bd00f6SHubert Feurstein /* custom-baudrate handling */ 164709bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 164809bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 164909bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 165009bd00f6SHubert Feurstein 1651ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1652ab4382d2SGreg Kroah-Hartman if (div > 7) 1653ab4382d2SGreg Kroah-Hartman div = 7; 1654ab4382d2SGreg Kroah-Hartman if (!div) 1655ab4382d2SGreg Kroah-Hartman div = 1; 1656ab4382d2SGreg Kroah-Hartman 1657ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1658ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1659ab4382d2SGreg Kroah-Hartman 1660ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1661ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1662ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1663ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1664ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1665ab4382d2SGreg Kroah-Hartman 1666ab4382d2SGreg Kroah-Hartman num -= 1; 1667ab4382d2SGreg Kroah-Hartman denom -= 1; 1668ab4382d2SGreg Kroah-Hartman 166927c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1670ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 167127c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1672ab4382d2SGreg Kroah-Hartman 167327c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 167427c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1675ab4382d2SGreg Kroah-Hartman 1676a496e628SHuang Shijie if (!is_imx1_uart(sport)) 167727c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 167827c84426SUwe Kleine-König IMX21_ONEMS); 1679ab4382d2SGreg Kroah-Hartman 168027c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr1, UCR1); 1681ab4382d2SGreg Kroah-Hartman 1682ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 168327c84426SUwe Kleine-König imx_uart_writel(sport, ucr2 | old_ucr2, UCR2); 1684ab4382d2SGreg Kroah-Hartman 1685ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1686ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1687ab4382d2SGreg Kroah-Hartman 1688ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1689ab4382d2SGreg Kroah-Hartman } 1690ab4382d2SGreg Kroah-Hartman 1691ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1692ab4382d2SGreg Kroah-Hartman { 1693ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1694ab4382d2SGreg Kroah-Hartman 1695ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1696ab4382d2SGreg Kroah-Hartman } 1697ab4382d2SGreg Kroah-Hartman 1698ab4382d2SGreg Kroah-Hartman /* 1699ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1700ab4382d2SGreg Kroah-Hartman */ 1701ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1702ab4382d2SGreg Kroah-Hartman { 1703ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1704ab4382d2SGreg Kroah-Hartman 1705da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1706ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1707ab4382d2SGreg Kroah-Hartman } 1708ab4382d2SGreg Kroah-Hartman 1709ab4382d2SGreg Kroah-Hartman /* 1710ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1711ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1712ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1713ab4382d2SGreg Kroah-Hartman */ 1714ab4382d2SGreg Kroah-Hartman static int 1715ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1716ab4382d2SGreg Kroah-Hartman { 1717ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1718ab4382d2SGreg Kroah-Hartman int ret = 0; 1719ab4382d2SGreg Kroah-Hartman 1720ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1721ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1722ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1723ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1724ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1725ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1726ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1727ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1728a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1729ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1730ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1731ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1732ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1733ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1734ab4382d2SGreg Kroah-Hartman return ret; 1735ab4382d2SGreg Kroah-Hartman } 1736ab4382d2SGreg Kroah-Hartman 173701f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17386b8bdad9SDaniel Thompson 17396b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 17406b8bdad9SDaniel Thompson { 17416b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 17426b8bdad9SDaniel Thompson unsigned long flags; 17434444dcf1SUwe Kleine-König u32 ucr1, ucr2; 17446b8bdad9SDaniel Thompson int retval; 17456b8bdad9SDaniel Thompson 17466b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 17476b8bdad9SDaniel Thompson if (retval) 17486b8bdad9SDaniel Thompson return retval; 17496b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 17506b8bdad9SDaniel Thompson if (retval) 17516b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 17526b8bdad9SDaniel Thompson 1753cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 17546b8bdad9SDaniel Thompson 17556b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 17566b8bdad9SDaniel Thompson 175776821e22SUwe Kleine-König /* 175876821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 175976821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 176076821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 176176821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 176276821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 176376821e22SUwe Kleine-König */ 17644444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 176576821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 176676821e22SUwe Kleine-König 17676b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 17684444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 17696b8bdad9SDaniel Thompson 177076821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 177176821e22SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN); 177276821e22SUwe Kleine-König 17734444dcf1SUwe Kleine-König ucr2 |= UCR2_RXEN; 177481ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 177576821e22SUwe Kleine-König 177676821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 17774444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 17786b8bdad9SDaniel Thompson 177976821e22SUwe Kleine-König /* now enable irqs */ 178076821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 178181ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 178276821e22SUwe Kleine-König 17836b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 17846b8bdad9SDaniel Thompson 17856b8bdad9SDaniel Thompson return 0; 17866b8bdad9SDaniel Thompson } 17876b8bdad9SDaniel Thompson 178801f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 178901f56abdSSaleem Abdulrasool { 179027c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 179127c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 179226c47412SDirk Behme return NO_POLL_CHAR; 179301f56abdSSaleem Abdulrasool 179427c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 179501f56abdSSaleem Abdulrasool } 179601f56abdSSaleem Abdulrasool 179701f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 179801f56abdSSaleem Abdulrasool { 179927c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 180001f56abdSSaleem Abdulrasool unsigned int status; 180101f56abdSSaleem Abdulrasool 180201f56abdSSaleem Abdulrasool /* drain */ 180301f56abdSSaleem Abdulrasool do { 180427c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 180501f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 180601f56abdSSaleem Abdulrasool 180701f56abdSSaleem Abdulrasool /* write */ 180827c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 180901f56abdSSaleem Abdulrasool 181001f56abdSSaleem Abdulrasool /* flush */ 181101f56abdSSaleem Abdulrasool do { 181227c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 181301f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 181401f56abdSSaleem Abdulrasool } 181501f56abdSSaleem Abdulrasool #endif 181601f56abdSSaleem Abdulrasool 18176aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 181817b8f2a3SUwe Kleine-König static int imx_rs485_config(struct uart_port *port, 181917b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 182017b8f2a3SUwe Kleine-König { 182117b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 18224444dcf1SUwe Kleine-König u32 ucr2; 182317b8f2a3SUwe Kleine-König 182417b8f2a3SUwe Kleine-König /* unimplemented */ 182517b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 182617b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 182717b8f2a3SUwe Kleine-König 182817b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 18297b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 183017b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 183117b8f2a3SUwe Kleine-König 183217b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 183317b8f2a3SUwe Kleine-König /* disable transmitter */ 18344444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 183517b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 18364444dcf1SUwe Kleine-König imx_port_rts_active(sport, &ucr2); 18371a613626SFabio Estevam else 18384444dcf1SUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 18394444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 184017b8f2a3SUwe Kleine-König } 184117b8f2a3SUwe Kleine-König 18427d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 18437d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 184476821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 184576821e22SUwe Kleine-König imx_start_rx(port); 18467d1cadcaSBaruch Siach 184717b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 184817b8f2a3SUwe Kleine-König 184917b8f2a3SUwe Kleine-König return 0; 185017b8f2a3SUwe Kleine-König } 185117b8f2a3SUwe Kleine-König 1852069a47e5SJulia Lawall static const struct uart_ops imx_pops = { 1853ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1854ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1855ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1856ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1857ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1858ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1859ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1860ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1861ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1862ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1863eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1864ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1865ab4382d2SGreg Kroah-Hartman .type = imx_type, 1866ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1867ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 186801f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18696b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 187001f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 187101f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 187201f56abdSSaleem Abdulrasool #endif 1873ab4382d2SGreg Kroah-Hartman }; 1874ab4382d2SGreg Kroah-Hartman 1875ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1876ab4382d2SGreg Kroah-Hartman 1877ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1878ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1879ab4382d2SGreg Kroah-Hartman { 1880ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1881ab4382d2SGreg Kroah-Hartman 188227c84426SUwe Kleine-König while (imx_uart_readl(sport, uts_reg(sport)) & UTS_TXFULL) 1883ab4382d2SGreg Kroah-Hartman barrier(); 1884ab4382d2SGreg Kroah-Hartman 188527c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1886ab4382d2SGreg Kroah-Hartman } 1887ab4382d2SGreg Kroah-Hartman 1888ab4382d2SGreg Kroah-Hartman /* 1889ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1890ab4382d2SGreg Kroah-Hartman */ 1891ab4382d2SGreg Kroah-Hartman static void 1892ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1893ab4382d2SGreg Kroah-Hartman { 1894ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 18950ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 18960ad5a814SDirk Behme unsigned int ucr1; 1897f30e8260SShawn Guo unsigned long flags = 0; 1898677fe555SThomas Gleixner int locked = 1; 18991cf93e0dSHuang Shijie int retval; 19001cf93e0dSHuang Shijie 19010c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 19021cf93e0dSHuang Shijie if (retval) 19031cf93e0dSHuang Shijie return; 19040c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 19051cf93e0dSHuang Shijie if (retval) { 19060c727a42SFabio Estevam clk_disable(sport->clk_per); 19071cf93e0dSHuang Shijie return; 19081cf93e0dSHuang Shijie } 19099ec1882dSXinyu Chen 1910677fe555SThomas Gleixner if (sport->port.sysrq) 1911677fe555SThomas Gleixner locked = 0; 1912677fe555SThomas Gleixner else if (oops_in_progress) 1913677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1914677fe555SThomas Gleixner else 19159ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1916ab4382d2SGreg Kroah-Hartman 1917ab4382d2SGreg Kroah-Hartman /* 19180ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1919ab4382d2SGreg Kroah-Hartman */ 192027c84426SUwe Kleine-König imx_port_ucrs_save(sport, &old_ucr); 19210ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1922ab4382d2SGreg Kroah-Hartman 1923fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1924fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1925ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1926ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1927ab4382d2SGreg Kroah-Hartman 192827c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1929ab4382d2SGreg Kroah-Hartman 193027c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1931ab4382d2SGreg Kroah-Hartman 1932ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1933ab4382d2SGreg Kroah-Hartman 1934ab4382d2SGreg Kroah-Hartman /* 1935ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 19360ad5a814SDirk Behme * and restore UCR1/2/3 1937ab4382d2SGreg Kroah-Hartman */ 193827c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1939ab4382d2SGreg Kroah-Hartman 194027c84426SUwe Kleine-König imx_port_ucrs_restore(sport, &old_ucr); 19419ec1882dSXinyu Chen 1942677fe555SThomas Gleixner if (locked) 19439ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 19441cf93e0dSHuang Shijie 19450c727a42SFabio Estevam clk_disable(sport->clk_ipg); 19460c727a42SFabio Estevam clk_disable(sport->clk_per); 1947ab4382d2SGreg Kroah-Hartman } 1948ab4382d2SGreg Kroah-Hartman 1949ab4382d2SGreg Kroah-Hartman /* 1950ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1951ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1952ab4382d2SGreg Kroah-Hartman */ 1953ab4382d2SGreg Kroah-Hartman static void __init 1954ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1955ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1956ab4382d2SGreg Kroah-Hartman { 1957ab4382d2SGreg Kroah-Hartman 195827c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1959ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1960ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1961ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1962ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1963ab4382d2SGreg Kroah-Hartman 196427c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 1965ab4382d2SGreg Kroah-Hartman 1966ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1967ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1968ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1969ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1970ab4382d2SGreg Kroah-Hartman else 1971ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1972ab4382d2SGreg Kroah-Hartman } 1973ab4382d2SGreg Kroah-Hartman 1974ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1975ab4382d2SGreg Kroah-Hartman *bits = 8; 1976ab4382d2SGreg Kroah-Hartman else 1977ab4382d2SGreg Kroah-Hartman *bits = 7; 1978ab4382d2SGreg Kroah-Hartman 197927c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 198027c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 1981ab4382d2SGreg Kroah-Hartman 198227c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 1983ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1984ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1985ab4382d2SGreg Kroah-Hartman else 1986ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1987ab4382d2SGreg Kroah-Hartman 19883a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1989ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1990ab4382d2SGreg Kroah-Hartman 1991ab4382d2SGreg Kroah-Hartman { /* 1992ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1993ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1994ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1995ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1996ab4382d2SGreg Kroah-Hartman */ 1997ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1998ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1999ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2000ab4382d2SGreg Kroah-Hartman 2001ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2002ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2003ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2004ab4382d2SGreg Kroah-Hartman } 2005ab4382d2SGreg Kroah-Hartman 2006ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 200750bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 2008ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2009ab4382d2SGreg Kroah-Hartman } 2010ab4382d2SGreg Kroah-Hartman } 2011ab4382d2SGreg Kroah-Hartman 2012ab4382d2SGreg Kroah-Hartman static int __init 2013ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 2014ab4382d2SGreg Kroah-Hartman { 2015ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2016ab4382d2SGreg Kroah-Hartman int baud = 9600; 2017ab4382d2SGreg Kroah-Hartman int bits = 8; 2018ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2019ab4382d2SGreg Kroah-Hartman int flow = 'n'; 20201cf93e0dSHuang Shijie int retval; 2021ab4382d2SGreg Kroah-Hartman 2022ab4382d2SGreg Kroah-Hartman /* 2023ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2024ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2025ab4382d2SGreg Kroah-Hartman * console support. 2026ab4382d2SGreg Kroah-Hartman */ 2027ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 2028ab4382d2SGreg Kroah-Hartman co->index = 0; 2029ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 2030ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2031ab4382d2SGreg Kroah-Hartman return -ENODEV; 2032ab4382d2SGreg Kroah-Hartman 20331cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 20341cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 20351cf93e0dSHuang Shijie if (retval) 20361cf93e0dSHuang Shijie goto error_console; 20371cf93e0dSHuang Shijie 2038ab4382d2SGreg Kroah-Hartman if (options) 2039ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2040ab4382d2SGreg Kroah-Hartman else 2041ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 2042ab4382d2SGreg Kroah-Hartman 2043cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2044ab4382d2SGreg Kroah-Hartman 20451cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 20461cf93e0dSHuang Shijie 20470c727a42SFabio Estevam clk_disable(sport->clk_ipg); 20480c727a42SFabio Estevam if (retval) { 20490c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 20500c727a42SFabio Estevam goto error_console; 20510c727a42SFabio Estevam } 20520c727a42SFabio Estevam 20530c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 20540c727a42SFabio Estevam if (retval) 20551cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 20561cf93e0dSHuang Shijie 20571cf93e0dSHuang Shijie error_console: 20581cf93e0dSHuang Shijie return retval; 2059ab4382d2SGreg Kroah-Hartman } 2060ab4382d2SGreg Kroah-Hartman 2061ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 2062ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 2063ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 2064ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 2065ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 2066ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 2067ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2068ab4382d2SGreg Kroah-Hartman .index = -1, 2069ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 2070ab4382d2SGreg Kroah-Hartman }; 2071ab4382d2SGreg Kroah-Hartman 2072ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 2073913c6c0eSLucas Stach 2074913c6c0eSLucas Stach #ifdef CONFIG_OF 2075913c6c0eSLucas Stach static void imx_console_early_putchar(struct uart_port *port, int ch) 2076913c6c0eSLucas Stach { 207727c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 207827c84426SUwe Kleine-König 207927c84426SUwe Kleine-König while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2080913c6c0eSLucas Stach cpu_relax(); 2081913c6c0eSLucas Stach 208227c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 2083913c6c0eSLucas Stach } 2084913c6c0eSLucas Stach 2085913c6c0eSLucas Stach static void imx_console_early_write(struct console *con, const char *s, 2086913c6c0eSLucas Stach unsigned count) 2087913c6c0eSLucas Stach { 2088913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 2089913c6c0eSLucas Stach 2090913c6c0eSLucas Stach uart_console_write(&dev->port, s, count, imx_console_early_putchar); 2091913c6c0eSLucas Stach } 2092913c6c0eSLucas Stach 2093913c6c0eSLucas Stach static int __init 2094913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2095913c6c0eSLucas Stach { 2096913c6c0eSLucas Stach if (!dev->port.membase) 2097913c6c0eSLucas Stach return -ENODEV; 2098913c6c0eSLucas Stach 2099913c6c0eSLucas Stach dev->con->write = imx_console_early_write; 2100913c6c0eSLucas Stach 2101913c6c0eSLucas Stach return 0; 2102913c6c0eSLucas Stach } 2103913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2104913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2105913c6c0eSLucas Stach #endif 2106913c6c0eSLucas Stach 2107ab4382d2SGreg Kroah-Hartman #else 2108ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2109ab4382d2SGreg Kroah-Hartman #endif 2110ab4382d2SGreg Kroah-Hartman 2111ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 2112ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2113ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2114ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2115ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2116ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 2117ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 2118ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2119ab4382d2SGreg Kroah-Hartman }; 2120ab4382d2SGreg Kroah-Hartman 212122698aa2SShawn Guo #ifdef CONFIG_OF 212220bb8095SUwe Kleine-König /* 212320bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 212420bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 212520bb8095SUwe Kleine-König */ 212622698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 212722698aa2SShawn Guo struct platform_device *pdev) 212822698aa2SShawn Guo { 212922698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2130ff05967aSShawn Guo int ret; 213122698aa2SShawn Guo 21325f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 21335f8b9043SLABBE Corentin if (!sport->devdata) 213420bb8095SUwe Kleine-König /* no device tree device */ 213520bb8095SUwe Kleine-König return 1; 213622698aa2SShawn Guo 2137ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2138ff05967aSShawn Guo if (ret < 0) { 2139ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2140a197a191SUwe Kleine-König return ret; 2141ff05967aSShawn Guo } 2142ff05967aSShawn Guo sport->port.line = ret; 214322698aa2SShawn Guo 21441006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 21451006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 214622698aa2SShawn Guo sport->have_rtscts = 1; 214722698aa2SShawn Guo 214820ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 214920ff2fe6SHuang Shijie sport->dte_mode = 1; 215020ff2fe6SHuang Shijie 21517b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 21527b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 21537b7e8e8eSFabio Estevam 215422698aa2SShawn Guo return 0; 215522698aa2SShawn Guo } 215622698aa2SShawn Guo #else 215722698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 215822698aa2SShawn Guo struct platform_device *pdev) 215922698aa2SShawn Guo { 216020bb8095SUwe Kleine-König return 1; 216122698aa2SShawn Guo } 216222698aa2SShawn Guo #endif 216322698aa2SShawn Guo 216422698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 216522698aa2SShawn Guo struct platform_device *pdev) 216622698aa2SShawn Guo { 2167574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 216822698aa2SShawn Guo 216922698aa2SShawn Guo sport->port.line = pdev->id; 217022698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 217122698aa2SShawn Guo 217222698aa2SShawn Guo if (!pdata) 217322698aa2SShawn Guo return; 217422698aa2SShawn Guo 217522698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 217622698aa2SShawn Guo sport->have_rtscts = 1; 217722698aa2SShawn Guo } 217822698aa2SShawn Guo 2179ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 2180ab4382d2SGreg Kroah-Hartman { 2181ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2182ab4382d2SGreg Kroah-Hartman void __iomem *base; 21834444dcf1SUwe Kleine-König int ret = 0; 21844444dcf1SUwe Kleine-König u32 ucr1; 2185ab4382d2SGreg Kroah-Hartman struct resource *res; 2186842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2187ab4382d2SGreg Kroah-Hartman 218842d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2189ab4382d2SGreg Kroah-Hartman if (!sport) 2190ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2191ab4382d2SGreg Kroah-Hartman 219222698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 219320bb8095SUwe Kleine-König if (ret > 0) 219422698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 219520bb8095SUwe Kleine-König else if (ret < 0) 219642d34191SSachin Kamat return ret; 219722698aa2SShawn Guo 219856734448SGeert Uytterhoeven if (sport->port.line >= ARRAY_SIZE(imx_ports)) { 219956734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 220056734448SGeert Uytterhoeven sport->port.line); 220156734448SGeert Uytterhoeven return -EINVAL; 220256734448SGeert Uytterhoeven } 220356734448SGeert Uytterhoeven 2204ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2205da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2206da82f997SAlexander Shiyan if (IS_ERR(base)) 2207da82f997SAlexander Shiyan return PTR_ERR(base); 2208ab4382d2SGreg Kroah-Hartman 2209842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2210842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2211842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2212842633bdSUwe Kleine-König 2213ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2214ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2215ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2216ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2217ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2218842633bdSUwe Kleine-König sport->port.irq = rxirq; 2219ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2220ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 222117b8f2a3SUwe Kleine-König sport->port.rs485_config = imx_rs485_config; 2222ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 2223e99e88a9SKees Cook timer_setup(&sport->timer, imx_timeout, 0); 2224ab4382d2SGreg Kroah-Hartman 222558362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 222658362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 222758362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 222858362d5bSUwe Kleine-König 22293a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 22303a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 22313a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2232833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 223342d34191SSachin Kamat return ret; 2234ab4382d2SGreg Kroah-Hartman } 2235ab4382d2SGreg Kroah-Hartman 22363a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 22373a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 22383a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2239833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 224042d34191SSachin Kamat return ret; 22413a9465faSSascha Hauer } 22423a9465faSSascha Hauer 22433a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2244ab4382d2SGreg Kroah-Hartman 22458a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 22468a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 22471e512d45SUwe Kleine-König if (ret) { 22481e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 22498a61f0c7SFabio Estevam return ret; 22501e512d45SUwe Kleine-König } 22518a61f0c7SFabio Estevam 22523a0ab62fSUwe Kleine-König /* initialize shadow register values */ 22533a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 22543a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 22553a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 22563a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 22573a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 22583a0ab62fSUwe Kleine-König 2259743f93f8SLukas Wunner uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2260743f93f8SLukas Wunner 2261b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 2262b8f3bff0SLukas Wunner (!sport->have_rtscts || !sport->have_rtsgpio)) 2263b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2264b8f3bff0SLukas Wunner 2265b8f3bff0SLukas Wunner imx_rs485_config(&sport->port, &sport->port.rs485); 2266b8f3bff0SLukas Wunner 22678a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 22684444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 22694444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 22708a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 22714444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 22728a61f0c7SFabio Estevam 2273e61c38d8SUwe Kleine-König if (!is_imx1_uart(sport) && sport->dte_mode) { 2274e61c38d8SUwe Kleine-König /* 2275e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2276e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2277e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2278e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2279e61c38d8SUwe Kleine-König */ 22804444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 22814444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 22824444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2283e61c38d8SUwe Kleine-König 2284e61c38d8SUwe Kleine-König /* 2285e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2286e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2287e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2288e61c38d8SUwe Kleine-König */ 228927c84426SUwe Kleine-König imx_uart_writel(sport, 229027c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 229127c84426SUwe Kleine-König UCR3); 2292e61c38d8SUwe Kleine-König 2293e61c38d8SUwe Kleine-König } else { 22944444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 22954444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 22964444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 22974444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 22986df765dcSUwe Kleine-König 22996df765dcSUwe Kleine-König if (!is_imx1_uart(sport)) 23006df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 230127c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2302e61c38d8SUwe Kleine-König } 2303e61c38d8SUwe Kleine-König 23048a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 23058a61f0c7SFabio Estevam 2306c0d1c6b0SFabio Estevam /* 2307c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2308c0d1c6b0SFabio Estevam * chips only have one interrupt. 2309c0d1c6b0SFabio Estevam */ 2310842633bdSUwe Kleine-König if (txirq > 0) { 2311842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2312c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23131e512d45SUwe Kleine-König if (ret) { 23141e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 23151e512d45SUwe Kleine-König ret); 2316c0d1c6b0SFabio Estevam return ret; 23171e512d45SUwe Kleine-König } 2318c0d1c6b0SFabio Estevam 2319842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2320c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23211e512d45SUwe Kleine-König if (ret) { 23221e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 23231e512d45SUwe Kleine-König ret); 2324c0d1c6b0SFabio Estevam return ret; 23251e512d45SUwe Kleine-König } 2326c0d1c6b0SFabio Estevam } else { 2327842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2328c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 23291e512d45SUwe Kleine-König if (ret) { 23301e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2331c0d1c6b0SFabio Estevam return ret; 2332c0d1c6b0SFabio Estevam } 23331e512d45SUwe Kleine-König } 2334c0d1c6b0SFabio Estevam 233522698aa2SShawn Guo imx_ports[sport->port.line] = sport; 2336ab4382d2SGreg Kroah-Hartman 23370a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2338ab4382d2SGreg Kroah-Hartman 233945af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2340ab4382d2SGreg Kroah-Hartman } 2341ab4382d2SGreg Kroah-Hartman 2342ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2343ab4382d2SGreg Kroah-Hartman { 2344ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2345ab4382d2SGreg Kroah-Hartman 234645af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2347ab4382d2SGreg Kroah-Hartman } 2348ab4382d2SGreg Kroah-Hartman 2349c868cbb7SEduardo Valentin static void serial_imx_restore_context(struct imx_port *sport) 2350c868cbb7SEduardo Valentin { 2351c868cbb7SEduardo Valentin if (!sport->context_saved) 2352c868cbb7SEduardo Valentin return; 2353c868cbb7SEduardo Valentin 235427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 235527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 235627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 235727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 235827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 235927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 236027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 236127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 236227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 236327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2364c868cbb7SEduardo Valentin sport->context_saved = false; 2365c868cbb7SEduardo Valentin } 2366c868cbb7SEduardo Valentin 2367c868cbb7SEduardo Valentin static void serial_imx_save_context(struct imx_port *sport) 2368c868cbb7SEduardo Valentin { 2369c868cbb7SEduardo Valentin /* Save necessary regs */ 237027c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 237127c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 237227c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 237327c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 237427c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 237527c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 237627c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 237727c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 237827c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 237927c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2380c868cbb7SEduardo Valentin sport->context_saved = true; 2381c868cbb7SEduardo Valentin } 2382c868cbb7SEduardo Valentin 2383189550b8SEduardo Valentin static void serial_imx_enable_wakeup(struct imx_port *sport, bool on) 2384189550b8SEduardo Valentin { 23854444dcf1SUwe Kleine-König u32 ucr3; 2386189550b8SEduardo Valentin 23874444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 238809df0b34SMartin Kaiser if (on) { 238927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 23904444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 23914444dcf1SUwe Kleine-König } else { 23924444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 239309df0b34SMartin Kaiser } 23944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2395bc85734bSEduardo Valentin 239638b1f0fbSFabio Estevam if (sport->have_rtscts) { 23974444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2398bc85734bSEduardo Valentin if (on) 23994444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2400bc85734bSEduardo Valentin else 24014444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 24024444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2403189550b8SEduardo Valentin } 240438b1f0fbSFabio Estevam } 2405189550b8SEduardo Valentin 240690bb6bd3SShenwei Wang static int imx_serial_port_suspend_noirq(struct device *dev) 240790bb6bd3SShenwei Wang { 240890bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 240990bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 241090bb6bd3SShenwei Wang 2411c868cbb7SEduardo Valentin serial_imx_save_context(sport); 241290bb6bd3SShenwei Wang 241390bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 241490bb6bd3SShenwei Wang 241590bb6bd3SShenwei Wang return 0; 241690bb6bd3SShenwei Wang } 241790bb6bd3SShenwei Wang 241890bb6bd3SShenwei Wang static int imx_serial_port_resume_noirq(struct device *dev) 241990bb6bd3SShenwei Wang { 242090bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 242190bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 242290bb6bd3SShenwei Wang int ret; 242390bb6bd3SShenwei Wang 242490bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 242590bb6bd3SShenwei Wang if (ret) 242690bb6bd3SShenwei Wang return ret; 242790bb6bd3SShenwei Wang 2428c868cbb7SEduardo Valentin serial_imx_restore_context(sport); 242990bb6bd3SShenwei Wang 243090bb6bd3SShenwei Wang return 0; 243190bb6bd3SShenwei Wang } 243290bb6bd3SShenwei Wang 243390bb6bd3SShenwei Wang static int imx_serial_port_suspend(struct device *dev) 243490bb6bd3SShenwei Wang { 243590bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 243690bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 243709df0b34SMartin Kaiser int ret; 243890bb6bd3SShenwei Wang 243990bb6bd3SShenwei Wang uart_suspend_port(&imx_reg, &sport->port); 244081b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 244190bb6bd3SShenwei Wang 244209df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 244309df0b34SMartin Kaiser if (ret) 244409df0b34SMartin Kaiser return ret; 244509df0b34SMartin Kaiser 244609df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 244709df0b34SMartin Kaiser serial_imx_enable_wakeup(sport, true); 244809df0b34SMartin Kaiser 244909df0b34SMartin Kaiser return 0; 245090bb6bd3SShenwei Wang } 245190bb6bd3SShenwei Wang 245290bb6bd3SShenwei Wang static int imx_serial_port_resume(struct device *dev) 245390bb6bd3SShenwei Wang { 245490bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 245590bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 245690bb6bd3SShenwei Wang 245790bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 2458189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, false); 245990bb6bd3SShenwei Wang 246090bb6bd3SShenwei Wang uart_resume_port(&imx_reg, &sport->port); 246181b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 246290bb6bd3SShenwei Wang 246309df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 246429add68dSMartin Fuzzey 246590bb6bd3SShenwei Wang return 0; 246690bb6bd3SShenwei Wang } 246790bb6bd3SShenwei Wang 246894be6d74SPhilipp Zabel static int imx_serial_port_freeze(struct device *dev) 246994be6d74SPhilipp Zabel { 247094be6d74SPhilipp Zabel struct platform_device *pdev = to_platform_device(dev); 247194be6d74SPhilipp Zabel struct imx_port *sport = platform_get_drvdata(pdev); 247294be6d74SPhilipp Zabel 247394be6d74SPhilipp Zabel uart_suspend_port(&imx_reg, &sport->port); 247494be6d74SPhilipp Zabel 247509df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 247694be6d74SPhilipp Zabel } 247794be6d74SPhilipp Zabel 247894be6d74SPhilipp Zabel static int imx_serial_port_thaw(struct device *dev) 247994be6d74SPhilipp Zabel { 248094be6d74SPhilipp Zabel struct platform_device *pdev = to_platform_device(dev); 248194be6d74SPhilipp Zabel struct imx_port *sport = platform_get_drvdata(pdev); 248294be6d74SPhilipp Zabel 248394be6d74SPhilipp Zabel uart_resume_port(&imx_reg, &sport->port); 248494be6d74SPhilipp Zabel 248509df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 248694be6d74SPhilipp Zabel 248794be6d74SPhilipp Zabel return 0; 248894be6d74SPhilipp Zabel } 248994be6d74SPhilipp Zabel 249090bb6bd3SShenwei Wang static const struct dev_pm_ops imx_serial_port_pm_ops = { 249190bb6bd3SShenwei Wang .suspend_noirq = imx_serial_port_suspend_noirq, 249290bb6bd3SShenwei Wang .resume_noirq = imx_serial_port_resume_noirq, 249394be6d74SPhilipp Zabel .freeze_noirq = imx_serial_port_suspend_noirq, 249494be6d74SPhilipp Zabel .restore_noirq = imx_serial_port_resume_noirq, 249590bb6bd3SShenwei Wang .suspend = imx_serial_port_suspend, 249690bb6bd3SShenwei Wang .resume = imx_serial_port_resume, 249794be6d74SPhilipp Zabel .freeze = imx_serial_port_freeze, 249894be6d74SPhilipp Zabel .thaw = imx_serial_port_thaw, 249994be6d74SPhilipp Zabel .restore = imx_serial_port_thaw, 250090bb6bd3SShenwei Wang }; 250190bb6bd3SShenwei Wang 2502ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2503ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2504ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2505ab4382d2SGreg Kroah-Hartman 2506fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2507ab4382d2SGreg Kroah-Hartman .driver = { 2508ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 250922698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 251090bb6bd3SShenwei Wang .pm = &imx_serial_port_pm_ops, 2511ab4382d2SGreg Kroah-Hartman }, 2512ab4382d2SGreg Kroah-Hartman }; 2513ab4382d2SGreg Kroah-Hartman 2514ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2515ab4382d2SGreg Kroah-Hartman { 2516f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2517ab4382d2SGreg Kroah-Hartman 2518ab4382d2SGreg Kroah-Hartman if (ret) 2519ab4382d2SGreg Kroah-Hartman return ret; 2520ab4382d2SGreg Kroah-Hartman 2521ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2522ab4382d2SGreg Kroah-Hartman if (ret != 0) 2523ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2524ab4382d2SGreg Kroah-Hartman 2525f227824eSUwe Kleine-König return ret; 2526ab4382d2SGreg Kroah-Hartman } 2527ab4382d2SGreg Kroah-Hartman 2528ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2529ab4382d2SGreg Kroah-Hartman { 2530ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2531ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2532ab4382d2SGreg Kroah-Hartman } 2533ab4382d2SGreg Kroah-Hartman 2534ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2535ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2536ab4382d2SGreg Kroah-Hartman 2537ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2538ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2539ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2540ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2541