1ab4382d2SGreg Kroah-Hartman /* 2f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 7ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 8ab4382d2SGreg Kroah-Hartman * 9ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 10ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 11ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2 of the License, or 12ab4382d2SGreg Kroah-Hartman * (at your option) any later version. 13ab4382d2SGreg Kroah-Hartman * 14ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 15ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY; without even the implied warranty of 16ab4382d2SGreg Kroah-Hartman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17ab4382d2SGreg Kroah-Hartman * GNU General Public License for more details. 18ab4382d2SGreg Kroah-Hartman */ 19ab4382d2SGreg Kroah-Hartman 20ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 22ab4382d2SGreg Kroah-Hartman #endif 23ab4382d2SGreg Kroah-Hartman 24ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 29ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 30ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 31ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 32ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 33ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 34ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 35ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 36ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 37ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 3822698aa2SShawn Guo #include <linux/of.h> 3922698aa2SShawn Guo #include <linux/of_device.h> 40e32a9f8fSSachin Kamat #include <linux/io.h> 41b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 42ab4382d2SGreg Kroah-Hartman 43ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 4482906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 45b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 46ab4382d2SGreg Kroah-Hartman 4758362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 4858362d5bSUwe Kleine-König 49ab4382d2SGreg Kroah-Hartman /* Register definitions */ 50ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 51ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 52ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 53ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 54ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 55ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 56ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 57ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 58ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 59ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 60ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 61ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 62ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 63ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 64fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 65fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 66fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 67ab4382d2SGreg Kroah-Hartman 68ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6955d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 70ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 71ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 72ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 73ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 74ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 75ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 7626c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 7725985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 81b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 84ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 88ab4382d2SGreg Kroah-Hartman #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 89fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 90b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 91ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 92ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 100ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 101ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 102ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 10301f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 105ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 106ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 112ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 113b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 114ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 115ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 11727e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 118fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 119ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 120ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 124ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 125ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 126ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 127b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 128ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 129ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 130ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 131ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 132ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 133ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1347be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 135ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 136ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 137ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 138ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 140ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 141ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 142ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 143ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 14586a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 14627e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 147ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 149ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 150ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 151ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 152ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 153ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 15490ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 15590ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 156ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 157ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 15890ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 159ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 160ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 161ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 162ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 163ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 164ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 165ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 166ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 167ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 168ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 169ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 170ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 171ab4382d2SGreg Kroah-Hartman 172ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 173ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 174ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 175ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 176ab4382d2SGreg Kroah-Hartman 177ab4382d2SGreg Kroah-Hartman /* 178ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 179ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 180ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 181ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 182ab4382d2SGreg Kroah-Hartman */ 183ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 184ab4382d2SGreg Kroah-Hartman 185ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 186ab4382d2SGreg Kroah-Hartman 187ab4382d2SGreg Kroah-Hartman #define UART_NR 8 188ab4382d2SGreg Kroah-Hartman 189f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 190fe6b540aSShawn Guo enum imx_uart_type { 191fe6b540aSShawn Guo IMX1_UART, 192fe6b540aSShawn Guo IMX21_UART, 193a496e628SHuang Shijie IMX6Q_UART, 194fe6b540aSShawn Guo }; 195fe6b540aSShawn Guo 196fe6b540aSShawn Guo /* device type dependent stuff */ 197fe6b540aSShawn Guo struct imx_uart_data { 198fe6b540aSShawn Guo unsigned uts_reg; 199fe6b540aSShawn Guo enum imx_uart_type devtype; 200fe6b540aSShawn Guo }; 201fe6b540aSShawn Guo 202ab4382d2SGreg Kroah-Hartman struct imx_port { 203ab4382d2SGreg Kroah-Hartman struct uart_port port; 204ab4382d2SGreg Kroah-Hartman struct timer_list timer; 205ab4382d2SGreg Kroah-Hartman unsigned int old_status; 206ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 20720ff2fe6SHuang Shijie unsigned int dte_mode:1; 208ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_rx:1; 209ab4382d2SGreg Kroah-Hartman unsigned int irda_inv_tx:1; 210ab4382d2SGreg Kroah-Hartman unsigned short trcv_delay; /* transceiver delay */ 2113a9465faSSascha Hauer struct clk *clk_ipg; 2123a9465faSSascha Hauer struct clk *clk_per; 2137d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 214b4cdc8f6SHuang Shijie 21558362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21658362d5bSUwe Kleine-König 217b4cdc8f6SHuang Shijie /* DMA fields */ 218b4cdc8f6SHuang Shijie unsigned int dma_is_inited:1; 219b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 220b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 221b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 222b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 223b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 224b4cdc8f6SHuang Shijie void *rx_buf; 2259d297239SNandor Han struct circ_buf rx_ring; 2269d297239SNandor Han unsigned int rx_periods; 2279d297239SNandor Han dma_cookie_t rx_cookie; 2287cb92fd2SHuang Shijie unsigned int tx_bytes; 229b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 2309ce4f8f3SGreg Kroah-Hartman wait_queue_head_t dma_wait; 23190bb6bd3SShenwei Wang unsigned int saved_reg[10]; 232c868cbb7SEduardo Valentin bool context_saved; 233ab4382d2SGreg Kroah-Hartman }; 234ab4382d2SGreg Kroah-Hartman 2350ad5a814SDirk Behme struct imx_port_ucrs { 2360ad5a814SDirk Behme unsigned int ucr1; 2370ad5a814SDirk Behme unsigned int ucr2; 2380ad5a814SDirk Behme unsigned int ucr3; 2390ad5a814SDirk Behme }; 2400ad5a814SDirk Behme 241fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 242fe6b540aSShawn Guo [IMX1_UART] = { 243fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 244fe6b540aSShawn Guo .devtype = IMX1_UART, 245fe6b540aSShawn Guo }, 246fe6b540aSShawn Guo [IMX21_UART] = { 247fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 248fe6b540aSShawn Guo .devtype = IMX21_UART, 249fe6b540aSShawn Guo }, 250a496e628SHuang Shijie [IMX6Q_UART] = { 251a496e628SHuang Shijie .uts_reg = IMX21_UTS, 252a496e628SHuang Shijie .devtype = IMX6Q_UART, 253a496e628SHuang Shijie }, 254fe6b540aSShawn Guo }; 255fe6b540aSShawn Guo 25631ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 257fe6b540aSShawn Guo { 258fe6b540aSShawn Guo .name = "imx1-uart", 259fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 260fe6b540aSShawn Guo }, { 261fe6b540aSShawn Guo .name = "imx21-uart", 262fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 263fe6b540aSShawn Guo }, { 264a496e628SHuang Shijie .name = "imx6q-uart", 265a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 266a496e628SHuang Shijie }, { 267fe6b540aSShawn Guo /* sentinel */ 268fe6b540aSShawn Guo } 269fe6b540aSShawn Guo }; 270fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 271fe6b540aSShawn Guo 272ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 273a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 27422698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27522698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27622698aa2SShawn Guo { /* sentinel */ } 27722698aa2SShawn Guo }; 27822698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27922698aa2SShawn Guo 280fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 281fe6b540aSShawn Guo { 282fe6b540aSShawn Guo return sport->devdata->uts_reg; 283fe6b540aSShawn Guo } 284fe6b540aSShawn Guo 285fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 286fe6b540aSShawn Guo { 287fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 288fe6b540aSShawn Guo } 289fe6b540aSShawn Guo 290fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 291fe6b540aSShawn Guo { 292fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 293fe6b540aSShawn Guo } 294fe6b540aSShawn Guo 295a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 296a496e628SHuang Shijie { 297a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 298a496e628SHuang Shijie } 299ab4382d2SGreg Kroah-Hartman /* 30044a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 30144a75411Sfabio.estevam@freescale.com */ 30293d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 30344a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_save(struct uart_port *port, 30444a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 30544a75411Sfabio.estevam@freescale.com { 30644a75411Sfabio.estevam@freescale.com /* save control registers */ 30744a75411Sfabio.estevam@freescale.com ucr->ucr1 = readl(port->membase + UCR1); 30844a75411Sfabio.estevam@freescale.com ucr->ucr2 = readl(port->membase + UCR2); 30944a75411Sfabio.estevam@freescale.com ucr->ucr3 = readl(port->membase + UCR3); 31044a75411Sfabio.estevam@freescale.com } 31144a75411Sfabio.estevam@freescale.com 31244a75411Sfabio.estevam@freescale.com static void imx_port_ucrs_restore(struct uart_port *port, 31344a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 31444a75411Sfabio.estevam@freescale.com { 31544a75411Sfabio.estevam@freescale.com /* restore control registers */ 31644a75411Sfabio.estevam@freescale.com writel(ucr->ucr1, port->membase + UCR1); 31744a75411Sfabio.estevam@freescale.com writel(ucr->ucr2, port->membase + UCR2); 31844a75411Sfabio.estevam@freescale.com writel(ucr->ucr3, port->membase + UCR3); 31944a75411Sfabio.estevam@freescale.com } 320e8bfa760SFabio Estevam #endif 32144a75411Sfabio.estevam@freescale.com 32258362d5bSUwe Kleine-König static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2) 32358362d5bSUwe Kleine-König { 32458362d5bSUwe Kleine-König *ucr2 &= ~UCR2_CTSC; 32558362d5bSUwe Kleine-König *ucr2 |= UCR2_CTS; 32658362d5bSUwe Kleine-König 32758362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); 32858362d5bSUwe Kleine-König } 32958362d5bSUwe Kleine-König 33058362d5bSUwe Kleine-König static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2) 33158362d5bSUwe Kleine-König { 33258362d5bSUwe Kleine-König *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 33358362d5bSUwe Kleine-König 33458362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); 33558362d5bSUwe Kleine-König } 33658362d5bSUwe Kleine-König 33758362d5bSUwe Kleine-König static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2) 33858362d5bSUwe Kleine-König { 33958362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 34058362d5bSUwe Kleine-König } 34158362d5bSUwe Kleine-König 34244a75411Sfabio.estevam@freescale.com /* 343ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 344ab4382d2SGreg Kroah-Hartman */ 345ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 346ab4382d2SGreg Kroah-Hartman { 347ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 348ab4382d2SGreg Kroah-Hartman unsigned long temp; 349ab4382d2SGreg Kroah-Hartman 3509ce4f8f3SGreg Kroah-Hartman /* 3519ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 3529ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 3539ce4f8f3SGreg Kroah-Hartman */ 3549ce4f8f3SGreg Kroah-Hartman if (sport->dma_is_enabled && sport->dma_is_txing) 3559ce4f8f3SGreg Kroah-Hartman return; 356b4cdc8f6SHuang Shijie 35717b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR1); 35817b8f2a3SUwe Kleine-König writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); 35917b8f2a3SUwe Kleine-König 36017b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 36117b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 36217b8f2a3SUwe Kleine-König readl(port->membase + USR2) & USR2_TXDC) { 36317b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 36417b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 36558362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &temp); 36617b8f2a3SUwe Kleine-König else 36758362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 3687d1cadcaSBaruch Siach temp |= UCR2_RXEN; 36917b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 37017b8f2a3SUwe Kleine-König 37117b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 37217b8f2a3SUwe Kleine-König temp &= ~UCR4_TCEN; 37317b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 37417b8f2a3SUwe Kleine-König } 375ab4382d2SGreg Kroah-Hartman } 376ab4382d2SGreg Kroah-Hartman 377ab4382d2SGreg Kroah-Hartman /* 378ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 379ab4382d2SGreg Kroah-Hartman */ 380ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 381ab4382d2SGreg Kroah-Hartman { 382ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 383ab4382d2SGreg Kroah-Hartman unsigned long temp; 384ab4382d2SGreg Kroah-Hartman 38545564a66SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_rxing) { 38645564a66SHuang Shijie if (sport->port.suspended) { 38745564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 38845564a66SHuang Shijie sport->dma_is_rxing = 0; 38945564a66SHuang Shijie } else { 3909ce4f8f3SGreg Kroah-Hartman return; 39145564a66SHuang Shijie } 39245564a66SHuang Shijie } 393b4cdc8f6SHuang Shijie 394ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 395ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 39685878399SHuang Shijie 39785878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 39885878399SHuang Shijie temp = readl(sport->port.membase + UCR1); 39985878399SHuang Shijie writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 400ab4382d2SGreg Kroah-Hartman } 401ab4382d2SGreg Kroah-Hartman 402ab4382d2SGreg Kroah-Hartman /* 403ab4382d2SGreg Kroah-Hartman * Set the modem control timer to fire immediately. 404ab4382d2SGreg Kroah-Hartman */ 405ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 406ab4382d2SGreg Kroah-Hartman { 407ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 408ab4382d2SGreg Kroah-Hartman 409ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 41058362d5bSUwe Kleine-König 41158362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 412ab4382d2SGreg Kroah-Hartman } 413ab4382d2SGreg Kroah-Hartman 41491a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 415ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 416ab4382d2SGreg Kroah-Hartman { 417ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 41891a1a909SJiada Wang unsigned long temp; 419ab4382d2SGreg Kroah-Hartman 4205e42e9a3SPeter Hurley if (sport->port.x_char) { 4215e42e9a3SPeter Hurley /* Send next char */ 4225e42e9a3SPeter Hurley writel(sport->port.x_char, sport->port.membase + URTX0); 4237e2fb5aaSJiada Wang sport->port.icount.tx++; 4247e2fb5aaSJiada Wang sport->port.x_char = 0; 4255e42e9a3SPeter Hurley return; 4265e42e9a3SPeter Hurley } 4275e42e9a3SPeter Hurley 4285e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4295e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4305e42e9a3SPeter Hurley return; 4315e42e9a3SPeter Hurley } 4325e42e9a3SPeter Hurley 43391a1a909SJiada Wang if (sport->dma_is_enabled) { 43491a1a909SJiada Wang /* 43591a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 43691a1a909SJiada Wang * and the TX IRQ is disabled. 43791a1a909SJiada Wang **/ 43891a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 43991a1a909SJiada Wang temp &= ~UCR1_TXMPTYEN; 44091a1a909SJiada Wang if (sport->dma_is_txing) { 44191a1a909SJiada Wang temp |= UCR1_TDMAEN; 44291a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 44391a1a909SJiada Wang } else { 44491a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 44591a1a909SJiada Wang imx_dma_tx(sport); 44691a1a909SJiada Wang } 44791a1a909SJiada Wang } 44891a1a909SJiada Wang 449ab4382d2SGreg Kroah-Hartman while (!uart_circ_empty(xmit) && 4505e42e9a3SPeter Hurley !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 451ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 452ab4382d2SGreg Kroah-Hartman * out the port here */ 453ab4382d2SGreg Kroah-Hartman writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 454ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 455ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 456ab4382d2SGreg Kroah-Hartman } 457ab4382d2SGreg Kroah-Hartman 458ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 459ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 460ab4382d2SGreg Kroah-Hartman 461ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 462ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 463ab4382d2SGreg Kroah-Hartman } 464ab4382d2SGreg Kroah-Hartman 465b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 466b4cdc8f6SHuang Shijie { 467b4cdc8f6SHuang Shijie struct imx_port *sport = data; 468b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 469b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 470b4cdc8f6SHuang Shijie unsigned long flags; 471a2c718ceSDirk Behme unsigned long temp; 472b4cdc8f6SHuang Shijie 47342f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 47442f752b3SDirk Behme 475b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 476b4cdc8f6SHuang Shijie 477a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 478a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 479a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 480a2c718ceSDirk Behme 48142f752b3SDirk Behme /* update the stat */ 48242f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 48342f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 48442f752b3SDirk Behme 48542f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 48642f752b3SDirk Behme 487b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 488b4cdc8f6SHuang Shijie 489b4cdc8f6SHuang Shijie spin_unlock_irqrestore(&sport->port.lock, flags); 490b4cdc8f6SHuang Shijie 491d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 492b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 4939ce4f8f3SGreg Kroah-Hartman 4949ce4f8f3SGreg Kroah-Hartman if (waitqueue_active(&sport->dma_wait)) { 4959ce4f8f3SGreg Kroah-Hartman wake_up(&sport->dma_wait); 4969ce4f8f3SGreg Kroah-Hartman dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 4979ce4f8f3SGreg Kroah-Hartman return; 4989ce4f8f3SGreg Kroah-Hartman } 4990bbc9b81SJiada Wang 5000bbc9b81SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 5010bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5020bbc9b81SJiada Wang imx_dma_tx(sport); 5030bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 504b4cdc8f6SHuang Shijie } 505b4cdc8f6SHuang Shijie 5067cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 507b4cdc8f6SHuang Shijie { 508b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 509b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 510b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 511b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 512b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 513a2c718ceSDirk Behme unsigned long temp; 514b4cdc8f6SHuang Shijie int ret; 515b4cdc8f6SHuang Shijie 51642f752b3SDirk Behme if (sport->dma_is_txing) 517b4cdc8f6SHuang Shijie return; 518b4cdc8f6SHuang Shijie 519b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 520b4cdc8f6SHuang Shijie 5217942f857SDirk Behme if (xmit->tail < xmit->head) { 5227942f857SDirk Behme sport->dma_tx_nents = 1; 5237942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5247942f857SDirk Behme } else { 525b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 526b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 527b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 528b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 529b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 530b4cdc8f6SHuang Shijie } 531b4cdc8f6SHuang Shijie 532b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 533b4cdc8f6SHuang Shijie if (ret == 0) { 534b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 535b4cdc8f6SHuang Shijie return; 536b4cdc8f6SHuang Shijie } 537b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 538b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 539b4cdc8f6SHuang Shijie if (!desc) { 54024649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 54124649821SDirk Behme DMA_TO_DEVICE); 542b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 543b4cdc8f6SHuang Shijie return; 544b4cdc8f6SHuang Shijie } 545b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 546b4cdc8f6SHuang Shijie desc->callback_param = sport; 547b4cdc8f6SHuang Shijie 548b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 549b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 550a2c718ceSDirk Behme 551a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 552a2c718ceSDirk Behme temp |= UCR1_TDMAEN; 553a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 554a2c718ceSDirk Behme 555b4cdc8f6SHuang Shijie /* fire it */ 556b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 557b4cdc8f6SHuang Shijie dmaengine_submit(desc); 558b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 559b4cdc8f6SHuang Shijie return; 560b4cdc8f6SHuang Shijie } 561b4cdc8f6SHuang Shijie 562ab4382d2SGreg Kroah-Hartman /* 563ab4382d2SGreg Kroah-Hartman * interrupts disabled on entry 564ab4382d2SGreg Kroah-Hartman */ 565ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 566ab4382d2SGreg Kroah-Hartman { 567ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 568ab4382d2SGreg Kroah-Hartman unsigned long temp; 569ab4382d2SGreg Kroah-Hartman 57017b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 57117b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR2); 57217b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 57358362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &temp); 57417b8f2a3SUwe Kleine-König else 57558362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 5767d1cadcaSBaruch Siach if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 5777d1cadcaSBaruch Siach temp &= ~UCR2_RXEN; 57817b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR2); 57917b8f2a3SUwe Kleine-König 58058362d5bSUwe Kleine-König /* enable transmitter and shifter empty irq */ 58117b8f2a3SUwe Kleine-König temp = readl(port->membase + UCR4); 58217b8f2a3SUwe Kleine-König temp |= UCR4_TCEN; 58317b8f2a3SUwe Kleine-König writel(temp, port->membase + UCR4); 58417b8f2a3SUwe Kleine-König } 58517b8f2a3SUwe Kleine-König 586b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 587ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 588ab4382d2SGreg Kroah-Hartman writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 589b4cdc8f6SHuang Shijie } 590ab4382d2SGreg Kroah-Hartman 591b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 59291a1a909SJiada Wang if (sport->port.x_char) { 59391a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 59491a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 59591a1a909SJiada Wang temp = readl(sport->port.membase + UCR1); 59691a1a909SJiada Wang temp &= ~UCR1_TDMAEN; 59791a1a909SJiada Wang temp |= UCR1_TXMPTYEN; 59891a1a909SJiada Wang writel(temp, sport->port.membase + UCR1); 59991a1a909SJiada Wang return; 60091a1a909SJiada Wang } 60191a1a909SJiada Wang 6025e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6035e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6047cb92fd2SHuang Shijie imx_dma_tx(sport); 605b4cdc8f6SHuang Shijie return; 606b4cdc8f6SHuang Shijie } 607ab4382d2SGreg Kroah-Hartman } 608ab4382d2SGreg Kroah-Hartman 609ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 610ab4382d2SGreg Kroah-Hartman { 611ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6125680e941SUwe Kleine-König unsigned int val; 613ab4382d2SGreg Kroah-Hartman unsigned long flags; 614ab4382d2SGreg Kroah-Hartman 615ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 616ab4382d2SGreg Kroah-Hartman 617ab4382d2SGreg Kroah-Hartman writel(USR1_RTSD, sport->port.membase + USR1); 6185680e941SUwe Kleine-König val = readl(sport->port.membase + USR1) & USR1_RTSS; 619ab4382d2SGreg Kroah-Hartman uart_handle_cts_change(&sport->port, !!val); 620ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 621ab4382d2SGreg Kroah-Hartman 622ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 623ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 624ab4382d2SGreg Kroah-Hartman } 625ab4382d2SGreg Kroah-Hartman 626ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 627ab4382d2SGreg Kroah-Hartman { 628ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 629ab4382d2SGreg Kroah-Hartman unsigned long flags; 630ab4382d2SGreg Kroah-Hartman 631ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 632ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 633ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 634ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 635ab4382d2SGreg Kroah-Hartman } 636ab4382d2SGreg Kroah-Hartman 637ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 638ab4382d2SGreg Kroah-Hartman { 639ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 640ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 64192a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 642ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 643ab4382d2SGreg Kroah-Hartman 644ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 645ab4382d2SGreg Kroah-Hartman 646ab4382d2SGreg Kroah-Hartman while (readl(sport->port.membase + USR2) & USR2_RDR) { 647ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 648ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 649ab4382d2SGreg Kroah-Hartman 650ab4382d2SGreg Kroah-Hartman rx = readl(sport->port.membase + URXD0); 651ab4382d2SGreg Kroah-Hartman 652ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + USR2); 653ab4382d2SGreg Kroah-Hartman if (temp & USR2_BRCD) { 654ab4382d2SGreg Kroah-Hartman writel(USR2_BRCD, sport->port.membase + USR2); 655ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 656ab4382d2SGreg Kroah-Hartman continue; 657ab4382d2SGreg Kroah-Hartman } 658ab4382d2SGreg Kroah-Hartman 659ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 660ab4382d2SGreg Kroah-Hartman continue; 661ab4382d2SGreg Kroah-Hartman 662019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 663019dc9eaSHui Wang if (rx & URXD_BRK) 664019dc9eaSHui Wang sport->port.icount.brk++; 665019dc9eaSHui Wang else if (rx & URXD_PRERR) 666ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 667ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 668ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 669ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 670ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 671ab4382d2SGreg Kroah-Hartman 672ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 673ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 674ab4382d2SGreg Kroah-Hartman goto out; 675ab4382d2SGreg Kroah-Hartman continue; 676ab4382d2SGreg Kroah-Hartman } 677ab4382d2SGreg Kroah-Hartman 6788d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 679ab4382d2SGreg Kroah-Hartman 680019dc9eaSHui Wang if (rx & URXD_BRK) 681019dc9eaSHui Wang flg = TTY_BREAK; 682019dc9eaSHui Wang else if (rx & URXD_PRERR) 683ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 684ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 685ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 686ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 687ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 688ab4382d2SGreg Kroah-Hartman 689ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 690ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 691ab4382d2SGreg Kroah-Hartman #endif 692ab4382d2SGreg Kroah-Hartman } 693ab4382d2SGreg Kroah-Hartman 69455d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 69555d8693aSJiada Wang goto out; 69655d8693aSJiada Wang 6979b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 6989b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 699ab4382d2SGreg Kroah-Hartman } 700ab4382d2SGreg Kroah-Hartman 701ab4382d2SGreg Kroah-Hartman out: 702ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7032e124b4aSJiri Slaby tty_flip_buffer_push(port); 704ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 705ab4382d2SGreg Kroah-Hartman } 706ab4382d2SGreg Kroah-Hartman 70741d98b5dSNandor Han static void clear_rx_errors(struct imx_port *sport); 7087cb92fd2SHuang Shijie static int start_rx_dma(struct imx_port *sport); 709b4cdc8f6SHuang Shijie /* 710b4cdc8f6SHuang Shijie * If the RXFIFO is filled with some data, and then we 711b4cdc8f6SHuang Shijie * arise a DMA operation to receive them. 712b4cdc8f6SHuang Shijie */ 713b4cdc8f6SHuang Shijie static void imx_dma_rxint(struct imx_port *sport) 714b4cdc8f6SHuang Shijie { 715b4cdc8f6SHuang Shijie unsigned long temp; 71673631813SJiada Wang unsigned long flags; 71773631813SJiada Wang 71873631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 719b4cdc8f6SHuang Shijie 720b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + USR2); 721b4cdc8f6SHuang Shijie if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 722b4cdc8f6SHuang Shijie sport->dma_is_rxing = 1; 723b4cdc8f6SHuang Shijie 72486a04ba6SLucas Stach /* disable the receiver ready and aging timer interrupts */ 725b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 726b4cdc8f6SHuang Shijie temp &= ~(UCR1_RRDYEN); 727b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 728b4cdc8f6SHuang Shijie 72986a04ba6SLucas Stach temp = readl(sport->port.membase + UCR2); 73086a04ba6SLucas Stach temp &= ~(UCR2_ATEN); 73186a04ba6SLucas Stach writel(temp, sport->port.membase + UCR2); 73286a04ba6SLucas Stach 73341d98b5dSNandor Han /* disable the rx errors interrupts */ 73441d98b5dSNandor Han temp = readl(sport->port.membase + UCR4); 73541d98b5dSNandor Han temp &= ~UCR4_OREN; 73641d98b5dSNandor Han writel(temp, sport->port.membase + UCR4); 73741d98b5dSNandor Han 738b4cdc8f6SHuang Shijie /* tell the DMA to receive the data. */ 7397cb92fd2SHuang Shijie start_rx_dma(sport); 740b4cdc8f6SHuang Shijie } 74173631813SJiada Wang 74273631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 743b4cdc8f6SHuang Shijie } 744b4cdc8f6SHuang Shijie 74566f95884SUwe Kleine-König /* 74666f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 74766f95884SUwe Kleine-König */ 74866f95884SUwe Kleine-König static unsigned int imx_get_hwmctrl(struct imx_port *sport) 74966f95884SUwe Kleine-König { 75066f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 75166f95884SUwe Kleine-König unsigned usr1 = readl(sport->port.membase + USR1); 75266f95884SUwe Kleine-König 75366f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 75466f95884SUwe Kleine-König tmp |= TIOCM_CTS; 75566f95884SUwe Kleine-König 75666f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 75766f95884SUwe Kleine-König if (!(usr1 & USR2_DCDIN)) 75866f95884SUwe Kleine-König tmp |= TIOCM_CAR; 75966f95884SUwe Kleine-König 76066f95884SUwe Kleine-König if (sport->dte_mode) 76166f95884SUwe Kleine-König if (!(readl(sport->port.membase + USR2) & USR2_RIIN)) 76266f95884SUwe Kleine-König tmp |= TIOCM_RI; 76366f95884SUwe Kleine-König 76466f95884SUwe Kleine-König return tmp; 76566f95884SUwe Kleine-König } 76666f95884SUwe Kleine-König 76766f95884SUwe Kleine-König /* 76866f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 76966f95884SUwe Kleine-König */ 77066f95884SUwe Kleine-König static void imx_mctrl_check(struct imx_port *sport) 77166f95884SUwe Kleine-König { 77266f95884SUwe Kleine-König unsigned int status, changed; 77366f95884SUwe Kleine-König 77466f95884SUwe Kleine-König status = imx_get_hwmctrl(sport); 77566f95884SUwe Kleine-König changed = status ^ sport->old_status; 77666f95884SUwe Kleine-König 77766f95884SUwe Kleine-König if (changed == 0) 77866f95884SUwe Kleine-König return; 77966f95884SUwe Kleine-König 78066f95884SUwe Kleine-König sport->old_status = status; 78166f95884SUwe Kleine-König 78266f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 78366f95884SUwe Kleine-König sport->port.icount.rng++; 78466f95884SUwe Kleine-König if (changed & TIOCM_DSR) 78566f95884SUwe Kleine-König sport->port.icount.dsr++; 78666f95884SUwe Kleine-König if (changed & TIOCM_CAR) 78766f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 78866f95884SUwe Kleine-König if (changed & TIOCM_CTS) 78966f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 79066f95884SUwe Kleine-König 79166f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 79266f95884SUwe Kleine-König } 79366f95884SUwe Kleine-König 794ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 795ab4382d2SGreg Kroah-Hartman { 796ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 797ab4382d2SGreg Kroah-Hartman unsigned int sts; 798f1f836e4SAlexander Stein unsigned int sts2; 7994d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 800ab4382d2SGreg Kroah-Hartman 801ab4382d2SGreg Kroah-Hartman sts = readl(sport->port.membase + USR1); 80217b8f2a3SUwe Kleine-König sts2 = readl(sport->port.membase + USR2); 803ab4382d2SGreg Kroah-Hartman 80486a04ba6SLucas Stach if (sts & (USR1_RRDY | USR1_AGTIM)) { 805b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) 806b4cdc8f6SHuang Shijie imx_dma_rxint(sport); 807b4cdc8f6SHuang Shijie else 808ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 8094d845a62SUwe Kleine-König ret = IRQ_HANDLED; 810b4cdc8f6SHuang Shijie } 811ab4382d2SGreg Kroah-Hartman 81217b8f2a3SUwe Kleine-König if ((sts & USR1_TRDY && 81317b8f2a3SUwe Kleine-König readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || 81417b8f2a3SUwe Kleine-König (sts2 & USR2_TXDC && 8154d845a62SUwe Kleine-König readl(sport->port.membase + UCR4) & UCR4_TCEN)) { 816ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 8174d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8184d845a62SUwe Kleine-König } 819ab4382d2SGreg Kroah-Hartman 82027e16501SUwe Kleine-König if (sts & USR1_DTRD) { 82127e16501SUwe Kleine-König unsigned long flags; 82227e16501SUwe Kleine-König 82327e16501SUwe Kleine-König if (sts & USR1_DTRD) 82427e16501SUwe Kleine-König writel(USR1_DTRD, sport->port.membase + USR1); 82527e16501SUwe Kleine-König 82627e16501SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 82727e16501SUwe Kleine-König imx_mctrl_check(sport); 82827e16501SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 82927e16501SUwe Kleine-König 83027e16501SUwe Kleine-König ret = IRQ_HANDLED; 83127e16501SUwe Kleine-König } 83227e16501SUwe Kleine-König 8334d845a62SUwe Kleine-König if (sts & USR1_RTSD) { 834ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 8354d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8364d845a62SUwe Kleine-König } 837ab4382d2SGreg Kroah-Hartman 8384d845a62SUwe Kleine-König if (sts & USR1_AWAKE) { 839db1a9b55SFabio Estevam writel(USR1_AWAKE, sport->port.membase + USR1); 8404d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8414d845a62SUwe Kleine-König } 842db1a9b55SFabio Estevam 843f1f836e4SAlexander Stein if (sts2 & USR2_ORE) { 844f1f836e4SAlexander Stein sport->port.icount.overrun++; 84591555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 8464d845a62SUwe Kleine-König ret = IRQ_HANDLED; 847f1f836e4SAlexander Stein } 848f1f836e4SAlexander Stein 8494d845a62SUwe Kleine-König return ret; 850ab4382d2SGreg Kroah-Hartman } 851ab4382d2SGreg Kroah-Hartman 852ab4382d2SGreg Kroah-Hartman /* 853ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 854ab4382d2SGreg Kroah-Hartman */ 855ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 856ab4382d2SGreg Kroah-Hartman { 857ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 8581ce43e58SHuang Shijie unsigned int ret; 859ab4382d2SGreg Kroah-Hartman 8601ce43e58SHuang Shijie ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 8611ce43e58SHuang Shijie 8621ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 8631ce43e58SHuang Shijie if (sport->dma_is_enabled && sport->dma_is_txing) 8641ce43e58SHuang Shijie ret = 0; 8651ce43e58SHuang Shijie 8661ce43e58SHuang Shijie return ret; 867ab4382d2SGreg Kroah-Hartman } 868ab4382d2SGreg Kroah-Hartman 86958362d5bSUwe Kleine-König static unsigned int imx_get_mctrl(struct uart_port *port) 87058362d5bSUwe Kleine-König { 87158362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 87258362d5bSUwe Kleine-König unsigned int ret = imx_get_hwmctrl(sport); 87358362d5bSUwe Kleine-König 87458362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 87558362d5bSUwe Kleine-König 87658362d5bSUwe Kleine-König return ret; 87758362d5bSUwe Kleine-König } 87858362d5bSUwe Kleine-König 879ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 880ab4382d2SGreg Kroah-Hartman { 881ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 882ab4382d2SGreg Kroah-Hartman unsigned long temp; 883ab4382d2SGreg Kroah-Hartman 88417b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 88517b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 88617b8f2a3SUwe Kleine-König temp &= ~(UCR2_CTS | UCR2_CTSC); 887ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 888bb2f861aSFugang Duan temp |= UCR2_CTS | UCR2_CTSC; 889ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 89017b8f2a3SUwe Kleine-König } 8916b471a98SHuang Shijie 89290ebc483SUwe Kleine-König temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR; 89390ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 89490ebc483SUwe Kleine-König temp |= UCR3_DSR; 89590ebc483SUwe Kleine-König writel(temp, sport->port.membase + UCR3); 89690ebc483SUwe Kleine-König 8976b471a98SHuang Shijie temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 8986b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 8996b471a98SHuang Shijie temp |= UTS_LOOP; 9006b471a98SHuang Shijie writel(temp, sport->port.membase + uts_reg(sport)); 90158362d5bSUwe Kleine-König 90258362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 903ab4382d2SGreg Kroah-Hartman } 904ab4382d2SGreg Kroah-Hartman 905ab4382d2SGreg Kroah-Hartman /* 906ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 907ab4382d2SGreg Kroah-Hartman */ 908ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 909ab4382d2SGreg Kroah-Hartman { 910ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 911ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 912ab4382d2SGreg Kroah-Hartman 913ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 914ab4382d2SGreg Kroah-Hartman 915ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 916ab4382d2SGreg Kroah-Hartman 917ab4382d2SGreg Kroah-Hartman if (break_state != 0) 918ab4382d2SGreg Kroah-Hartman temp |= UCR1_SNDBRK; 919ab4382d2SGreg Kroah-Hartman 920ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 921ab4382d2SGreg Kroah-Hartman 922ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 923ab4382d2SGreg Kroah-Hartman } 924ab4382d2SGreg Kroah-Hartman 925cc568849SUwe Kleine-König /* 926cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 927cc568849SUwe Kleine-König * modem status signals. 928cc568849SUwe Kleine-König */ 929cc568849SUwe Kleine-König static void imx_timeout(unsigned long data) 930cc568849SUwe Kleine-König { 931cc568849SUwe Kleine-König struct imx_port *sport = (struct imx_port *)data; 932cc568849SUwe Kleine-König unsigned long flags; 933cc568849SUwe Kleine-König 934cc568849SUwe Kleine-König if (sport->port.state) { 935cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 936cc568849SUwe Kleine-König imx_mctrl_check(sport); 937cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 938cc568849SUwe Kleine-König 939cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 940cc568849SUwe Kleine-König } 941cc568849SUwe Kleine-König } 942cc568849SUwe Kleine-König 943b4cdc8f6SHuang Shijie #define RX_BUF_SIZE (PAGE_SIZE) 944b4cdc8f6SHuang Shijie 945b4cdc8f6SHuang Shijie /* 946905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 947b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 948905c0decSLucas Stach * [2] the aging timer expires 949b4cdc8f6SHuang Shijie * 950905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 951905c0decSLucas Stach * for at least 8 byte durations. 952b4cdc8f6SHuang Shijie */ 953b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 954b4cdc8f6SHuang Shijie { 955b4cdc8f6SHuang Shijie struct imx_port *sport = data; 956b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 957b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 9587cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 959b4cdc8f6SHuang Shijie struct dma_tx_state state; 9609d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 961b4cdc8f6SHuang Shijie enum dma_status status; 9629d297239SNandor Han unsigned int w_bytes = 0; 9639d297239SNandor Han unsigned int r_bytes; 9649d297239SNandor Han unsigned int bd_size; 965b4cdc8f6SHuang Shijie 966f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 967392bceedSPhilipp Zabel 9689d297239SNandor Han if (status == DMA_ERROR) { 9699d297239SNandor Han dev_err(sport->port.dev, "DMA transaction error.\n"); 97041d98b5dSNandor Han clear_rx_errors(sport); 9719d297239SNandor Han return; 9729d297239SNandor Han } 973b4cdc8f6SHuang Shijie 9749b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 975976b39cdSLucas Stach 976976b39cdSLucas Stach /* 9779d297239SNandor Han * The state-residue variable represents the empty space 9789d297239SNandor Han * relative to the entire buffer. Taking this in consideration 9799d297239SNandor Han * the head is always calculated base on the buffer total 9809d297239SNandor Han * length - DMA transaction residue. The UART script from the 9819d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 9829d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 9839d297239SNandor Han * Taking this in consideration the tail is always at the 9849d297239SNandor Han * beginning of the buffer descriptor that contains the head. 985976b39cdSLucas Stach */ 9869d297239SNandor Han 9879d297239SNandor Han /* Calculate the head */ 9889d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 9899d297239SNandor Han 9909d297239SNandor Han /* Calculate the tail. */ 9919d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 9929d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 9939d297239SNandor Han 9949d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 9959d297239SNandor Han rx_ring->head > rx_ring->tail) { 9969d297239SNandor Han 9979d297239SNandor Han /* Move data from tail to head */ 9989d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 9999d297239SNandor Han 10009d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 10019d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 10029d297239SNandor Han DMA_FROM_DEVICE); 10039d297239SNandor Han 10049d297239SNandor Han w_bytes = tty_insert_flip_string(port, 10059d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 10069d297239SNandor Han 10079d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 10089d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 10099d297239SNandor Han DMA_FROM_DEVICE); 10109d297239SNandor Han 10119d297239SNandor Han if (w_bytes != r_bytes) 10129d297239SNandor Han sport->port.icount.buf_overrun++; 10139d297239SNandor Han 10149d297239SNandor Han sport->port.icount.rx += w_bytes; 10159d297239SNandor Han } else { 10169d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 10179d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1018ee5e7c10SRobin Gong } 10199d297239SNandor Han } 10209d297239SNandor Han 10219d297239SNandor Han if (w_bytes) { 10229d297239SNandor Han tty_flip_buffer_push(port); 10239d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 10249d297239SNandor Han } 10259d297239SNandor Han } 10269d297239SNandor Han 10279d297239SNandor Han /* RX DMA buffer periods */ 10289d297239SNandor Han #define RX_DMA_PERIODS 4 1029b4cdc8f6SHuang Shijie 1030b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 1031b4cdc8f6SHuang Shijie { 1032b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1033b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1034b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1035b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1036b4cdc8f6SHuang Shijie int ret; 1037b4cdc8f6SHuang Shijie 10389d297239SNandor Han sport->rx_ring.head = 0; 10399d297239SNandor Han sport->rx_ring.tail = 0; 10409d297239SNandor Han sport->rx_periods = RX_DMA_PERIODS; 10419d297239SNandor Han 1042b4cdc8f6SHuang Shijie sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1043b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1044b4cdc8f6SHuang Shijie if (ret == 0) { 1045b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1046b4cdc8f6SHuang Shijie return -EINVAL; 1047b4cdc8f6SHuang Shijie } 10489d297239SNandor Han 10499d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 10509d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 10519d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 10529d297239SNandor Han 1053b4cdc8f6SHuang Shijie if (!desc) { 105424649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1055b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1056b4cdc8f6SHuang Shijie return -EINVAL; 1057b4cdc8f6SHuang Shijie } 1058b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 1059b4cdc8f6SHuang Shijie desc->callback_param = sport; 1060b4cdc8f6SHuang Shijie 1061b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 10629d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1063b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1064b4cdc8f6SHuang Shijie return 0; 1065b4cdc8f6SHuang Shijie } 1066b4cdc8f6SHuang Shijie 106741d98b5dSNandor Han static void clear_rx_errors(struct imx_port *sport) 106841d98b5dSNandor Han { 106941d98b5dSNandor Han unsigned int status_usr1, status_usr2; 107041d98b5dSNandor Han 107141d98b5dSNandor Han status_usr1 = readl(sport->port.membase + USR1); 107241d98b5dSNandor Han status_usr2 = readl(sport->port.membase + USR2); 107341d98b5dSNandor Han 107441d98b5dSNandor Han if (status_usr2 & USR2_BRCD) { 107541d98b5dSNandor Han sport->port.icount.brk++; 107641d98b5dSNandor Han writel(USR2_BRCD, sport->port.membase + USR2); 107741d98b5dSNandor Han } else if (status_usr1 & USR1_FRAMERR) { 107841d98b5dSNandor Han sport->port.icount.frame++; 107941d98b5dSNandor Han writel(USR1_FRAMERR, sport->port.membase + USR1); 108041d98b5dSNandor Han } else if (status_usr1 & USR1_PARITYERR) { 108141d98b5dSNandor Han sport->port.icount.parity++; 108241d98b5dSNandor Han writel(USR1_PARITYERR, sport->port.membase + USR1); 108341d98b5dSNandor Han } 108441d98b5dSNandor Han 108541d98b5dSNandor Han if (status_usr2 & USR2_ORE) { 108641d98b5dSNandor Han sport->port.icount.overrun++; 108741d98b5dSNandor Han writel(USR2_ORE, sport->port.membase + USR2); 108841d98b5dSNandor Han } 108941d98b5dSNandor Han 109041d98b5dSNandor Han } 109141d98b5dSNandor Han 1092cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1093cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1094184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1095184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1096cc32382dSLucas Stach 1097cc32382dSLucas Stach static void imx_setup_ufcr(struct imx_port *sport, 1098cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1099cc32382dSLucas Stach { 1100cc32382dSLucas Stach unsigned int val; 1101cc32382dSLucas Stach 1102cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 1103cc32382dSLucas Stach val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1104cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 1105cc32382dSLucas Stach writel(val, sport->port.membase + UFCR); 1106cc32382dSLucas Stach } 1107cc32382dSLucas Stach 1108b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1109b4cdc8f6SHuang Shijie { 1110b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 11119d297239SNandor Han dmaengine_terminate_all(sport->dma_chan_rx); 1112b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1113b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 11149d297239SNandor Han sport->rx_cookie = -EINVAL; 1115b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1116b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1117b4cdc8f6SHuang Shijie } 1118b4cdc8f6SHuang Shijie 1119b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 11209d297239SNandor Han dmaengine_terminate_all(sport->dma_chan_tx); 1121b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1122b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1123b4cdc8f6SHuang Shijie } 1124b4cdc8f6SHuang Shijie 1125b4cdc8f6SHuang Shijie sport->dma_is_inited = 0; 1126b4cdc8f6SHuang Shijie } 1127b4cdc8f6SHuang Shijie 1128b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1129b4cdc8f6SHuang Shijie { 1130b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1131b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1132b4cdc8f6SHuang Shijie int ret; 1133b4cdc8f6SHuang Shijie 1134b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1135b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1136b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1137b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1138b4cdc8f6SHuang Shijie ret = -EINVAL; 1139b4cdc8f6SHuang Shijie goto err; 1140b4cdc8f6SHuang Shijie } 1141b4cdc8f6SHuang Shijie 1142b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1143b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1144b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1145184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1146184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1147b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1148b4cdc8f6SHuang Shijie if (ret) { 1149b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1150b4cdc8f6SHuang Shijie goto err; 1151b4cdc8f6SHuang Shijie } 1152b4cdc8f6SHuang Shijie 1153b4cdc8f6SHuang Shijie sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1154b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1155b4cdc8f6SHuang Shijie ret = -ENOMEM; 1156b4cdc8f6SHuang Shijie goto err; 1157b4cdc8f6SHuang Shijie } 11589d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1159b4cdc8f6SHuang Shijie 1160b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1161b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1162b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1163b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1164b4cdc8f6SHuang Shijie ret = -EINVAL; 1165b4cdc8f6SHuang Shijie goto err; 1166b4cdc8f6SHuang Shijie } 1167b4cdc8f6SHuang Shijie 1168b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1169b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1170b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1171184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1172b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1173b4cdc8f6SHuang Shijie if (ret) { 1174b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1175b4cdc8f6SHuang Shijie goto err; 1176b4cdc8f6SHuang Shijie } 1177b4cdc8f6SHuang Shijie 1178b4cdc8f6SHuang Shijie sport->dma_is_inited = 1; 1179b4cdc8f6SHuang Shijie 1180b4cdc8f6SHuang Shijie return 0; 1181b4cdc8f6SHuang Shijie err: 1182b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1183b4cdc8f6SHuang Shijie return ret; 1184b4cdc8f6SHuang Shijie } 1185b4cdc8f6SHuang Shijie 1186b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1187b4cdc8f6SHuang Shijie { 1188b4cdc8f6SHuang Shijie unsigned long temp; 1189b4cdc8f6SHuang Shijie 11909ce4f8f3SGreg Kroah-Hartman init_waitqueue_head(&sport->dma_wait); 11919ce4f8f3SGreg Kroah-Hartman 1192b4cdc8f6SHuang Shijie /* set UCR1 */ 1193b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1194905c0decSLucas Stach temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN; 1195b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1196b4cdc8f6SHuang Shijie 119786a04ba6SLucas Stach temp = readl(sport->port.membase + UCR2); 119886a04ba6SLucas Stach temp |= UCR2_ATEN; 119986a04ba6SLucas Stach writel(temp, sport->port.membase + UCR2); 120086a04ba6SLucas Stach 1201184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1202184bd70bSLucas Stach 1203b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1204b4cdc8f6SHuang Shijie } 1205b4cdc8f6SHuang Shijie 1206b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1207b4cdc8f6SHuang Shijie { 1208b4cdc8f6SHuang Shijie unsigned long temp; 1209b4cdc8f6SHuang Shijie 1210b4cdc8f6SHuang Shijie /* clear UCR1 */ 1211b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR1); 1212b4cdc8f6SHuang Shijie temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1213b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR1); 1214b4cdc8f6SHuang Shijie 1215b4cdc8f6SHuang Shijie /* clear UCR2 */ 1216b4cdc8f6SHuang Shijie temp = readl(sport->port.membase + UCR2); 121786a04ba6SLucas Stach temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN); 1218b4cdc8f6SHuang Shijie writel(temp, sport->port.membase + UCR2); 1219b4cdc8f6SHuang Shijie 1220184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1221184bd70bSLucas Stach 1222b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1223b4cdc8f6SHuang Shijie } 1224b4cdc8f6SHuang Shijie 1225ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1226ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1227ab4382d2SGreg Kroah-Hartman 1228ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1229ab4382d2SGreg Kroah-Hartman { 1230ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1231458e2c82SFabio Estevam int retval, i; 1232ab4382d2SGreg Kroah-Hartman unsigned long flags, temp; 1233ab4382d2SGreg Kroah-Hartman 123428eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 123528eb4274SHuang Shijie if (retval) 1236cb0f0a5fSFabio Estevam return retval; 123728eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 12380c375501SHuang Shijie if (retval) { 12390c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1240cb0f0a5fSFabio Estevam return retval; 12410c375501SHuang Shijie } 124228eb4274SHuang Shijie 1243cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1244ab4382d2SGreg Kroah-Hartman 1245ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1246ab4382d2SGreg Kroah-Hartman * requesting IRQs 1247ab4382d2SGreg Kroah-Hartman */ 1248ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR4); 1249ab4382d2SGreg Kroah-Hartman 1250ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 1251ab4382d2SGreg Kroah-Hartman temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1252ab4382d2SGreg Kroah-Hartman temp |= CTSTL << UCR4_CTSTL_SHF; 1253ab4382d2SGreg Kroah-Hartman 1254ab4382d2SGreg Kroah-Hartman writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1255ab4382d2SGreg Kroah-Hartman 12567e11577eSLucas Stach /* Can we enable the DMA support? */ 12577e11577eSLucas Stach if (is_imx6q_uart(sport) && !uart_console(port) && 12587e11577eSLucas Stach !sport->dma_is_inited) 12597e11577eSLucas Stach imx_uart_dma_init(sport); 12607e11577eSLucas Stach 126153794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1262772f8991SHuang Shijie /* Reset fifo's and state machines */ 1263458e2c82SFabio Estevam i = 100; 1264458e2c82SFabio Estevam 1265458e2c82SFabio Estevam temp = readl(sport->port.membase + UCR2); 1266458e2c82SFabio Estevam temp &= ~UCR2_SRST; 1267458e2c82SFabio Estevam writel(temp, sport->port.membase + UCR2); 1268458e2c82SFabio Estevam 1269458e2c82SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1270458e2c82SFabio Estevam udelay(1); 1271ab4382d2SGreg Kroah-Hartman 1272ab4382d2SGreg Kroah-Hartman /* 1273ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1274ab4382d2SGreg Kroah-Hartman */ 127527e16501SUwe Kleine-König writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1); 127691555ce9SUwe Kleine-König writel(USR2_ORE, sport->port.membase + USR2); 1277ab4382d2SGreg Kroah-Hartman 12787e11577eSLucas Stach if (sport->dma_is_inited && !sport->dma_is_enabled) 12797e11577eSLucas Stach imx_enable_dma(sport); 12807e11577eSLucas Stach 1281ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1282ab4382d2SGreg Kroah-Hartman temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1283ab4382d2SGreg Kroah-Hartman 1284ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 1285ab4382d2SGreg Kroah-Hartman 12866f026d6bSJiada Wang temp = readl(sport->port.membase + UCR4); 12876f026d6bSJiada Wang temp |= UCR4_OREN; 12886f026d6bSJiada Wang writel(temp, sport->port.membase + UCR4); 12896f026d6bSJiada Wang 1290ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1291ab4382d2SGreg Kroah-Hartman temp |= (UCR2_RXEN | UCR2_TXEN); 1292bff09b09SLucas Stach if (!sport->have_rtscts) 1293bff09b09SLucas Stach temp |= UCR2_IRTS; 129416804d68SUwe Kleine-König /* 129516804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 129616804d68SUwe Kleine-König * we're using RTSD instead. 129716804d68SUwe Kleine-König */ 129816804d68SUwe Kleine-König if (!is_imx1_uart(sport)) 129916804d68SUwe Kleine-König temp &= ~UCR2_RTSEN; 1300ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 1301ab4382d2SGreg Kroah-Hartman 1302a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 1303ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR3); 130416804d68SUwe Kleine-König 130516804d68SUwe Kleine-König /* 130616804d68SUwe Kleine-König * The effect of RI and DCD differs depending on the UFCR_DCEDTE 130716804d68SUwe Kleine-König * bit. In DCE mode they control the outputs, in DTE mode they 130816804d68SUwe Kleine-König * enable the respective irqs. At least the DCD irq cannot be 130916804d68SUwe Kleine-König * cleared on i.MX25 at least, so it's not usable and must be 131016804d68SUwe Kleine-König * disabled. I don't have test hardware to check if RI has the 131116804d68SUwe Kleine-König * same problem but I consider this likely so it's disabled for 131216804d68SUwe Kleine-König * now, too. 131316804d68SUwe Kleine-König */ 131416804d68SUwe Kleine-König temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | 131527e16501SUwe Kleine-König UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 131616804d68SUwe Kleine-König 131716804d68SUwe Kleine-König if (sport->dte_mode) 131816804d68SUwe Kleine-König temp &= ~(UCR3_RI | UCR3_DCD); 131916804d68SUwe Kleine-König 1320ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR3); 1321ab4382d2SGreg Kroah-Hartman } 1322ab4382d2SGreg Kroah-Hartman 1323ab4382d2SGreg Kroah-Hartman /* 1324ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1325ab4382d2SGreg Kroah-Hartman */ 1326ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1327ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1328ab4382d2SGreg Kroah-Hartman 1329ab4382d2SGreg Kroah-Hartman return 0; 1330ab4382d2SGreg Kroah-Hartman } 1331ab4382d2SGreg Kroah-Hartman 1332ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1333ab4382d2SGreg Kroah-Hartman { 1334ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1335ab4382d2SGreg Kroah-Hartman unsigned long temp; 13369ec1882dSXinyu Chen unsigned long flags; 1337ab4382d2SGreg Kroah-Hartman 1338b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1339a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1340a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1341a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 1342a4688bcdSHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 13439d297239SNandor Han 134473631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1345a4688bcdSHuang Shijie imx_stop_tx(port); 1346b4cdc8f6SHuang Shijie imx_stop_rx(port); 1347b4cdc8f6SHuang Shijie imx_disable_dma(sport); 134873631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1349b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1350b4cdc8f6SHuang Shijie } 1351b4cdc8f6SHuang Shijie 135258362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 135358362d5bSUwe Kleine-König 13549ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1355ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR2); 1356ab4382d2SGreg Kroah-Hartman temp &= ~(UCR2_TXEN); 1357ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR2); 13589ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1359ab4382d2SGreg Kroah-Hartman 1360ab4382d2SGreg Kroah-Hartman /* 1361ab4382d2SGreg Kroah-Hartman * Stop our timer. 1362ab4382d2SGreg Kroah-Hartman */ 1363ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1364ab4382d2SGreg Kroah-Hartman 1365ab4382d2SGreg Kroah-Hartman /* 1366ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1367ab4382d2SGreg Kroah-Hartman */ 1368ab4382d2SGreg Kroah-Hartman 13699ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1370ab4382d2SGreg Kroah-Hartman temp = readl(sport->port.membase + UCR1); 1371ab4382d2SGreg Kroah-Hartman temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1372ab4382d2SGreg Kroah-Hartman 1373ab4382d2SGreg Kroah-Hartman writel(temp, sport->port.membase + UCR1); 13749ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 137528eb4274SHuang Shijie 137628eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 137728eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1378ab4382d2SGreg Kroah-Hartman } 1379ab4382d2SGreg Kroah-Hartman 1380eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1381eb56b7edSHuang Shijie { 1382eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 138382e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 1384a2c718ceSDirk Behme unsigned long temp; 13854f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1386eb56b7edSHuang Shijie 138782e86ae9SDirk Behme if (!sport->dma_chan_tx) 138882e86ae9SDirk Behme return; 138982e86ae9SDirk Behme 1390eb56b7edSHuang Shijie sport->tx_bytes = 0; 1391eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 139282e86ae9SDirk Behme if (sport->dma_is_txing) { 139382e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 139482e86ae9SDirk Behme DMA_TO_DEVICE); 1395a2c718ceSDirk Behme temp = readl(sport->port.membase + UCR1); 1396a2c718ceSDirk Behme temp &= ~UCR1_TDMAEN; 1397a2c718ceSDirk Behme writel(temp, sport->port.membase + UCR1); 139882e86ae9SDirk Behme sport->dma_is_txing = false; 1399eb56b7edSHuang Shijie } 1400934084a9SFabio Estevam 1401934084a9SFabio Estevam /* 1402934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1403934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1404934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1405934084a9SFabio Estevam * and UTS[6-3]". As we don't need to restore the old values from 1406934084a9SFabio Estevam * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1407934084a9SFabio Estevam */ 1408934084a9SFabio Estevam ubir = readl(sport->port.membase + UBIR); 1409934084a9SFabio Estevam ubmr = readl(sport->port.membase + UBMR); 1410934084a9SFabio Estevam uts = readl(sport->port.membase + IMX21_UTS); 1411934084a9SFabio Estevam 1412934084a9SFabio Estevam temp = readl(sport->port.membase + UCR2); 1413934084a9SFabio Estevam temp &= ~UCR2_SRST; 1414934084a9SFabio Estevam writel(temp, sport->port.membase + UCR2); 1415934084a9SFabio Estevam 1416934084a9SFabio Estevam while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1417934084a9SFabio Estevam udelay(1); 1418934084a9SFabio Estevam 1419934084a9SFabio Estevam /* Restore the registers */ 1420934084a9SFabio Estevam writel(ubir, sport->port.membase + UBIR); 1421934084a9SFabio Estevam writel(ubmr, sport->port.membase + UBMR); 1422934084a9SFabio Estevam writel(uts, sport->port.membase + IMX21_UTS); 1423eb56b7edSHuang Shijie } 1424eb56b7edSHuang Shijie 1425ab4382d2SGreg Kroah-Hartman static void 1426ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1427ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1428ab4382d2SGreg Kroah-Hartman { 1429ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1430ab4382d2SGreg Kroah-Hartman unsigned long flags; 143158362d5bSUwe Kleine-König unsigned long ucr2, old_ucr1, old_ucr2; 143258362d5bSUwe Kleine-König unsigned int baud, quot; 1433ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 143458362d5bSUwe Kleine-König unsigned long div, ufcr; 1435ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1436ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1437ab4382d2SGreg Kroah-Hartman 1438ab4382d2SGreg Kroah-Hartman /* 1439ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1440ab4382d2SGreg Kroah-Hartman */ 1441ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1442ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1443ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1444ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1445ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1446ab4382d2SGreg Kroah-Hartman } 1447ab4382d2SGreg Kroah-Hartman 1448ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1449ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1450ab4382d2SGreg Kroah-Hartman else 1451ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1452ab4382d2SGreg Kroah-Hartman 1453ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1454ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1455ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 145617b8f2a3SUwe Kleine-König 145712fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 145817b8f2a3SUwe Kleine-König /* 145917b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 146017b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 146117b8f2a3SUwe Kleine-König * disabled. 146217b8f2a3SUwe Kleine-König */ 146358362d5bSUwe Kleine-König if (port->rs485.flags & 146458362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 146558362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 146658362d5bSUwe Kleine-König else 146758362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 146812fe59f9SFabio Estevam } else { 146958362d5bSUwe Kleine-König imx_port_rts_auto(sport, &ucr2); 147012fe59f9SFabio Estevam } 1471ab4382d2SGreg Kroah-Hartman } else { 1472ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1473ab4382d2SGreg Kroah-Hartman } 147458362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 147517b8f2a3SUwe Kleine-König /* disable transmitter */ 147658362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 147758362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 147858362d5bSUwe Kleine-König else 147958362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 148058362d5bSUwe Kleine-König } 148158362d5bSUwe Kleine-König 1482ab4382d2SGreg Kroah-Hartman 1483ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1484ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1485ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1486ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1487ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1488ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1489ab4382d2SGreg Kroah-Hartman } 1490ab4382d2SGreg Kroah-Hartman 1491995234daSEric Miao del_timer_sync(&sport->timer); 1492995234daSEric Miao 1493ab4382d2SGreg Kroah-Hartman /* 1494ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1495ab4382d2SGreg Kroah-Hartman */ 1496ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1497ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1498ab4382d2SGreg Kroah-Hartman 1499ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1500ab4382d2SGreg Kroah-Hartman 1501ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1502ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1503ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1504ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1505ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1506ab4382d2SGreg Kroah-Hartman 1507ab4382d2SGreg Kroah-Hartman /* 1508ab4382d2SGreg Kroah-Hartman * Characters to ignore 1509ab4382d2SGreg Kroah-Hartman */ 1510ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1511ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1512865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1513ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1514ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1515ab4382d2SGreg Kroah-Hartman /* 1516ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1517ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1518ab4382d2SGreg Kroah-Hartman */ 1519ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1520ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1521ab4382d2SGreg Kroah-Hartman } 1522ab4382d2SGreg Kroah-Hartman 152355d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 152455d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 152555d8693aSJiada Wang 1526ab4382d2SGreg Kroah-Hartman /* 1527ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1528ab4382d2SGreg Kroah-Hartman */ 1529ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1530ab4382d2SGreg Kroah-Hartman 1531ab4382d2SGreg Kroah-Hartman /* 1532ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1533ab4382d2SGreg Kroah-Hartman */ 1534ab4382d2SGreg Kroah-Hartman old_ucr1 = readl(sport->port.membase + UCR1); 1535ab4382d2SGreg Kroah-Hartman writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1536ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR1); 1537ab4382d2SGreg Kroah-Hartman 1538ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1539ab4382d2SGreg Kroah-Hartman barrier(); 1540ab4382d2SGreg Kroah-Hartman 1541ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 154286a04ba6SLucas Stach old_ucr2 = readl(sport->port.membase + UCR2); 154386a04ba6SLucas Stach writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN), 1544ab4382d2SGreg Kroah-Hartman sport->port.membase + UCR2); 154586a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1546ab4382d2SGreg Kroah-Hartman 154709bd00f6SHubert Feurstein /* custom-baudrate handling */ 154809bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 154909bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 155009bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 155109bd00f6SHubert Feurstein 1552ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1553ab4382d2SGreg Kroah-Hartman if (div > 7) 1554ab4382d2SGreg Kroah-Hartman div = 7; 1555ab4382d2SGreg Kroah-Hartman if (!div) 1556ab4382d2SGreg Kroah-Hartman div = 1; 1557ab4382d2SGreg Kroah-Hartman 1558ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1559ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1560ab4382d2SGreg Kroah-Hartman 1561ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1562ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1563ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1564ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1565ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1566ab4382d2SGreg Kroah-Hartman 1567ab4382d2SGreg Kroah-Hartman num -= 1; 1568ab4382d2SGreg Kroah-Hartman denom -= 1; 1569ab4382d2SGreg Kroah-Hartman 1570ab4382d2SGreg Kroah-Hartman ufcr = readl(sport->port.membase + UFCR); 1571ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 157220ff2fe6SHuang Shijie if (sport->dte_mode) 157320ff2fe6SHuang Shijie ufcr |= UFCR_DCEDTE; 1574ab4382d2SGreg Kroah-Hartman writel(ufcr, sport->port.membase + UFCR); 1575ab4382d2SGreg Kroah-Hartman 1576ab4382d2SGreg Kroah-Hartman writel(num, sport->port.membase + UBIR); 1577ab4382d2SGreg Kroah-Hartman writel(denom, sport->port.membase + UBMR); 1578ab4382d2SGreg Kroah-Hartman 1579a496e628SHuang Shijie if (!is_imx1_uart(sport)) 1580ab4382d2SGreg Kroah-Hartman writel(sport->port.uartclk / div / 1000, 1581fe6b540aSShawn Guo sport->port.membase + IMX21_ONEMS); 1582ab4382d2SGreg Kroah-Hartman 1583ab4382d2SGreg Kroah-Hartman writel(old_ucr1, sport->port.membase + UCR1); 1584ab4382d2SGreg Kroah-Hartman 1585ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 158686a04ba6SLucas Stach writel(ucr2 | old_ucr2, sport->port.membase + UCR2); 1587ab4382d2SGreg Kroah-Hartman 1588ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1589ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1590ab4382d2SGreg Kroah-Hartman 1591ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1592ab4382d2SGreg Kroah-Hartman } 1593ab4382d2SGreg Kroah-Hartman 1594ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1595ab4382d2SGreg Kroah-Hartman { 1596ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1597ab4382d2SGreg Kroah-Hartman 1598ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1599ab4382d2SGreg Kroah-Hartman } 1600ab4382d2SGreg Kroah-Hartman 1601ab4382d2SGreg Kroah-Hartman /* 1602ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1603ab4382d2SGreg Kroah-Hartman */ 1604ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1605ab4382d2SGreg Kroah-Hartman { 1606ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1607ab4382d2SGreg Kroah-Hartman 1608da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1609ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1610ab4382d2SGreg Kroah-Hartman } 1611ab4382d2SGreg Kroah-Hartman 1612ab4382d2SGreg Kroah-Hartman /* 1613ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1614ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1615ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1616ab4382d2SGreg Kroah-Hartman */ 1617ab4382d2SGreg Kroah-Hartman static int 1618ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1619ab4382d2SGreg Kroah-Hartman { 1620ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1621ab4382d2SGreg Kroah-Hartman int ret = 0; 1622ab4382d2SGreg Kroah-Hartman 1623ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1624ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1625ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1626ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1627ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1628ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1629ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1630ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1631a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1632ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1633ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1634ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1635ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1636ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1637ab4382d2SGreg Kroah-Hartman return ret; 1638ab4382d2SGreg Kroah-Hartman } 1639ab4382d2SGreg Kroah-Hartman 164001f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 16416b8bdad9SDaniel Thompson 16426b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 16436b8bdad9SDaniel Thompson { 16446b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 16456b8bdad9SDaniel Thompson unsigned long flags; 16466b8bdad9SDaniel Thompson unsigned long temp; 16476b8bdad9SDaniel Thompson int retval; 16486b8bdad9SDaniel Thompson 16496b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 16506b8bdad9SDaniel Thompson if (retval) 16516b8bdad9SDaniel Thompson return retval; 16526b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 16536b8bdad9SDaniel Thompson if (retval) 16546b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 16556b8bdad9SDaniel Thompson 1656cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 16576b8bdad9SDaniel Thompson 16586b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 16596b8bdad9SDaniel Thompson 16606b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR1); 16616b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 16626b8bdad9SDaniel Thompson temp |= IMX1_UCR1_UARTCLKEN; 16636b8bdad9SDaniel Thompson temp |= UCR1_UARTEN | UCR1_RRDYEN; 16646b8bdad9SDaniel Thompson temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 16656b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR1); 16666b8bdad9SDaniel Thompson 16676b8bdad9SDaniel Thompson temp = readl(sport->port.membase + UCR2); 16686b8bdad9SDaniel Thompson temp |= UCR2_RXEN; 16696b8bdad9SDaniel Thompson writel(temp, sport->port.membase + UCR2); 16706b8bdad9SDaniel Thompson 16716b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 16726b8bdad9SDaniel Thompson 16736b8bdad9SDaniel Thompson return 0; 16746b8bdad9SDaniel Thompson } 16756b8bdad9SDaniel Thompson 167601f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 167701f56abdSSaleem Abdulrasool { 1678f968ef34SDaniel Thompson if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 167926c47412SDirk Behme return NO_POLL_CHAR; 168001f56abdSSaleem Abdulrasool 1681f968ef34SDaniel Thompson return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 168201f56abdSSaleem Abdulrasool } 168301f56abdSSaleem Abdulrasool 168401f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 168501f56abdSSaleem Abdulrasool { 168601f56abdSSaleem Abdulrasool unsigned int status; 168701f56abdSSaleem Abdulrasool 168801f56abdSSaleem Abdulrasool /* drain */ 168901f56abdSSaleem Abdulrasool do { 1690f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR1); 169101f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 169201f56abdSSaleem Abdulrasool 169301f56abdSSaleem Abdulrasool /* write */ 1694f968ef34SDaniel Thompson writel_relaxed(c, port->membase + URTX0); 169501f56abdSSaleem Abdulrasool 169601f56abdSSaleem Abdulrasool /* flush */ 169701f56abdSSaleem Abdulrasool do { 1698f968ef34SDaniel Thompson status = readl_relaxed(port->membase + USR2); 169901f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 170001f56abdSSaleem Abdulrasool } 170101f56abdSSaleem Abdulrasool #endif 170201f56abdSSaleem Abdulrasool 170317b8f2a3SUwe Kleine-König static int imx_rs485_config(struct uart_port *port, 170417b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 170517b8f2a3SUwe Kleine-König { 170617b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 17077d1cadcaSBaruch Siach unsigned long temp; 170817b8f2a3SUwe Kleine-König 170917b8f2a3SUwe Kleine-König /* unimplemented */ 171017b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 171117b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 171217b8f2a3SUwe Kleine-König 171317b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 171417b8f2a3SUwe Kleine-König if (!sport->have_rtscts) 171517b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 171617b8f2a3SUwe Kleine-König 171717b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 171817b8f2a3SUwe Kleine-König /* disable transmitter */ 171917b8f2a3SUwe Kleine-König temp = readl(sport->port.membase + UCR2); 172017b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 172158362d5bSUwe Kleine-König imx_port_rts_inactive(sport, &temp); 172217b8f2a3SUwe Kleine-König else 172358362d5bSUwe Kleine-König imx_port_rts_active(sport, &temp); 172417b8f2a3SUwe Kleine-König writel(temp, sport->port.membase + UCR2); 172517b8f2a3SUwe Kleine-König } 172617b8f2a3SUwe Kleine-König 17277d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 17287d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 17297d1cadcaSBaruch Siach rs485conf->flags & SER_RS485_RX_DURING_TX) { 17307d1cadcaSBaruch Siach temp = readl(sport->port.membase + UCR2); 17317d1cadcaSBaruch Siach temp |= UCR2_RXEN; 17327d1cadcaSBaruch Siach writel(temp, sport->port.membase + UCR2); 17337d1cadcaSBaruch Siach } 17347d1cadcaSBaruch Siach 173517b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 173617b8f2a3SUwe Kleine-König 173717b8f2a3SUwe Kleine-König return 0; 173817b8f2a3SUwe Kleine-König } 173917b8f2a3SUwe Kleine-König 1740069a47e5SJulia Lawall static const struct uart_ops imx_pops = { 1741ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1742ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1743ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1744ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1745ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1746ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1747ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1748ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1749ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1750ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1751eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1752ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1753ab4382d2SGreg Kroah-Hartman .type = imx_type, 1754ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1755ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 175601f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17576b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 175801f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 175901f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 176001f56abdSSaleem Abdulrasool #endif 1761ab4382d2SGreg Kroah-Hartman }; 1762ab4382d2SGreg Kroah-Hartman 1763ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1764ab4382d2SGreg Kroah-Hartman 1765ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1766ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1767ab4382d2SGreg Kroah-Hartman { 1768ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1769ab4382d2SGreg Kroah-Hartman 1770fe6b540aSShawn Guo while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1771ab4382d2SGreg Kroah-Hartman barrier(); 1772ab4382d2SGreg Kroah-Hartman 1773ab4382d2SGreg Kroah-Hartman writel(ch, sport->port.membase + URTX0); 1774ab4382d2SGreg Kroah-Hartman } 1775ab4382d2SGreg Kroah-Hartman 1776ab4382d2SGreg Kroah-Hartman /* 1777ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1778ab4382d2SGreg Kroah-Hartman */ 1779ab4382d2SGreg Kroah-Hartman static void 1780ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1781ab4382d2SGreg Kroah-Hartman { 1782ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 17830ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 17840ad5a814SDirk Behme unsigned int ucr1; 1785f30e8260SShawn Guo unsigned long flags = 0; 1786677fe555SThomas Gleixner int locked = 1; 17871cf93e0dSHuang Shijie int retval; 17881cf93e0dSHuang Shijie 17890c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 17901cf93e0dSHuang Shijie if (retval) 17911cf93e0dSHuang Shijie return; 17920c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 17931cf93e0dSHuang Shijie if (retval) { 17940c727a42SFabio Estevam clk_disable(sport->clk_per); 17951cf93e0dSHuang Shijie return; 17961cf93e0dSHuang Shijie } 17979ec1882dSXinyu Chen 1798677fe555SThomas Gleixner if (sport->port.sysrq) 1799677fe555SThomas Gleixner locked = 0; 1800677fe555SThomas Gleixner else if (oops_in_progress) 1801677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1802677fe555SThomas Gleixner else 18039ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1804ab4382d2SGreg Kroah-Hartman 1805ab4382d2SGreg Kroah-Hartman /* 18060ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1807ab4382d2SGreg Kroah-Hartman */ 18080ad5a814SDirk Behme imx_port_ucrs_save(&sport->port, &old_ucr); 18090ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1810ab4382d2SGreg Kroah-Hartman 1811fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1812fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1813ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1814ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1815ab4382d2SGreg Kroah-Hartman 1816ab4382d2SGreg Kroah-Hartman writel(ucr1, sport->port.membase + UCR1); 1817ab4382d2SGreg Kroah-Hartman 18180ad5a814SDirk Behme writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1819ab4382d2SGreg Kroah-Hartman 1820ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1821ab4382d2SGreg Kroah-Hartman 1822ab4382d2SGreg Kroah-Hartman /* 1823ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 18240ad5a814SDirk Behme * and restore UCR1/2/3 1825ab4382d2SGreg Kroah-Hartman */ 1826ab4382d2SGreg Kroah-Hartman while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1827ab4382d2SGreg Kroah-Hartman 18280ad5a814SDirk Behme imx_port_ucrs_restore(&sport->port, &old_ucr); 18299ec1882dSXinyu Chen 1830677fe555SThomas Gleixner if (locked) 18319ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 18321cf93e0dSHuang Shijie 18330c727a42SFabio Estevam clk_disable(sport->clk_ipg); 18340c727a42SFabio Estevam clk_disable(sport->clk_per); 1835ab4382d2SGreg Kroah-Hartman } 1836ab4382d2SGreg Kroah-Hartman 1837ab4382d2SGreg Kroah-Hartman /* 1838ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1839ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1840ab4382d2SGreg Kroah-Hartman */ 1841ab4382d2SGreg Kroah-Hartman static void __init 1842ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1843ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1844ab4382d2SGreg Kroah-Hartman { 1845ab4382d2SGreg Kroah-Hartman 1846ab4382d2SGreg Kroah-Hartman if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1847ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1848ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1849ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1850ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1851ab4382d2SGreg Kroah-Hartman 1852ab4382d2SGreg Kroah-Hartman ucr2 = readl(sport->port.membase + UCR2); 1853ab4382d2SGreg Kroah-Hartman 1854ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1855ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1856ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1857ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1858ab4382d2SGreg Kroah-Hartman else 1859ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1860ab4382d2SGreg Kroah-Hartman } 1861ab4382d2SGreg Kroah-Hartman 1862ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1863ab4382d2SGreg Kroah-Hartman *bits = 8; 1864ab4382d2SGreg Kroah-Hartman else 1865ab4382d2SGreg Kroah-Hartman *bits = 7; 1866ab4382d2SGreg Kroah-Hartman 1867ab4382d2SGreg Kroah-Hartman ubir = readl(sport->port.membase + UBIR) & 0xffff; 1868ab4382d2SGreg Kroah-Hartman ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1869ab4382d2SGreg Kroah-Hartman 1870ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1871ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1872ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1873ab4382d2SGreg Kroah-Hartman else 1874ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1875ab4382d2SGreg Kroah-Hartman 18763a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1877ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1878ab4382d2SGreg Kroah-Hartman 1879ab4382d2SGreg Kroah-Hartman { /* 1880ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1881ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1882ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1883ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1884ab4382d2SGreg Kroah-Hartman */ 1885ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1886ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1887ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1888ab4382d2SGreg Kroah-Hartman 1889ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1890ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1891ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1892ab4382d2SGreg Kroah-Hartman } 1893ab4382d2SGreg Kroah-Hartman 1894ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 189550bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1896ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1897ab4382d2SGreg Kroah-Hartman } 1898ab4382d2SGreg Kroah-Hartman } 1899ab4382d2SGreg Kroah-Hartman 1900ab4382d2SGreg Kroah-Hartman static int __init 1901ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1902ab4382d2SGreg Kroah-Hartman { 1903ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1904ab4382d2SGreg Kroah-Hartman int baud = 9600; 1905ab4382d2SGreg Kroah-Hartman int bits = 8; 1906ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1907ab4382d2SGreg Kroah-Hartman int flow = 'n'; 19081cf93e0dSHuang Shijie int retval; 1909ab4382d2SGreg Kroah-Hartman 1910ab4382d2SGreg Kroah-Hartman /* 1911ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1912ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1913ab4382d2SGreg Kroah-Hartman * console support. 1914ab4382d2SGreg Kroah-Hartman */ 1915ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1916ab4382d2SGreg Kroah-Hartman co->index = 0; 1917ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1918ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1919ab4382d2SGreg Kroah-Hartman return -ENODEV; 1920ab4382d2SGreg Kroah-Hartman 19211cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 19221cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 19231cf93e0dSHuang Shijie if (retval) 19241cf93e0dSHuang Shijie goto error_console; 19251cf93e0dSHuang Shijie 1926ab4382d2SGreg Kroah-Hartman if (options) 1927ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1928ab4382d2SGreg Kroah-Hartman else 1929ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1930ab4382d2SGreg Kroah-Hartman 1931cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1932ab4382d2SGreg Kroah-Hartman 19331cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 19341cf93e0dSHuang Shijie 19350c727a42SFabio Estevam clk_disable(sport->clk_ipg); 19360c727a42SFabio Estevam if (retval) { 19370c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 19380c727a42SFabio Estevam goto error_console; 19390c727a42SFabio Estevam } 19400c727a42SFabio Estevam 19410c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 19420c727a42SFabio Estevam if (retval) 19431cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 19441cf93e0dSHuang Shijie 19451cf93e0dSHuang Shijie error_console: 19461cf93e0dSHuang Shijie return retval; 1947ab4382d2SGreg Kroah-Hartman } 1948ab4382d2SGreg Kroah-Hartman 1949ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 1950ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 1951ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 1952ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 1953ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 1954ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 1955ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 1956ab4382d2SGreg Kroah-Hartman .index = -1, 1957ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 1958ab4382d2SGreg Kroah-Hartman }; 1959ab4382d2SGreg Kroah-Hartman 1960ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 1961913c6c0eSLucas Stach 1962913c6c0eSLucas Stach #ifdef CONFIG_OF 1963913c6c0eSLucas Stach static void imx_console_early_putchar(struct uart_port *port, int ch) 1964913c6c0eSLucas Stach { 1965913c6c0eSLucas Stach while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL) 1966913c6c0eSLucas Stach cpu_relax(); 1967913c6c0eSLucas Stach 1968913c6c0eSLucas Stach writel_relaxed(ch, port->membase + URTX0); 1969913c6c0eSLucas Stach } 1970913c6c0eSLucas Stach 1971913c6c0eSLucas Stach static void imx_console_early_write(struct console *con, const char *s, 1972913c6c0eSLucas Stach unsigned count) 1973913c6c0eSLucas Stach { 1974913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 1975913c6c0eSLucas Stach 1976913c6c0eSLucas Stach uart_console_write(&dev->port, s, count, imx_console_early_putchar); 1977913c6c0eSLucas Stach } 1978913c6c0eSLucas Stach 1979913c6c0eSLucas Stach static int __init 1980913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 1981913c6c0eSLucas Stach { 1982913c6c0eSLucas Stach if (!dev->port.membase) 1983913c6c0eSLucas Stach return -ENODEV; 1984913c6c0eSLucas Stach 1985913c6c0eSLucas Stach dev->con->write = imx_console_early_write; 1986913c6c0eSLucas Stach 1987913c6c0eSLucas Stach return 0; 1988913c6c0eSLucas Stach } 1989913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 1990913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 1991913c6c0eSLucas Stach #endif 1992913c6c0eSLucas Stach 1993ab4382d2SGreg Kroah-Hartman #else 1994ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 1995ab4382d2SGreg Kroah-Hartman #endif 1996ab4382d2SGreg Kroah-Hartman 1997ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 1998ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 1999ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2000ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2001ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2002ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 2003ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 2004ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2005ab4382d2SGreg Kroah-Hartman }; 2006ab4382d2SGreg Kroah-Hartman 200722698aa2SShawn Guo #ifdef CONFIG_OF 200820bb8095SUwe Kleine-König /* 200920bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 201020bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 201120bb8095SUwe Kleine-König */ 201222698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 201322698aa2SShawn Guo struct platform_device *pdev) 201422698aa2SShawn Guo { 201522698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2016ff05967aSShawn Guo int ret; 201722698aa2SShawn Guo 20185f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 20195f8b9043SLABBE Corentin if (!sport->devdata) 202020bb8095SUwe Kleine-König /* no device tree device */ 202120bb8095SUwe Kleine-König return 1; 202222698aa2SShawn Guo 2023ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2024ff05967aSShawn Guo if (ret < 0) { 2025ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2026a197a191SUwe Kleine-König return ret; 2027ff05967aSShawn Guo } 2028ff05967aSShawn Guo sport->port.line = ret; 202922698aa2SShawn Guo 20301006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 20311006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 203222698aa2SShawn Guo sport->have_rtscts = 1; 203322698aa2SShawn Guo 203420ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 203520ff2fe6SHuang Shijie sport->dte_mode = 1; 203620ff2fe6SHuang Shijie 203722698aa2SShawn Guo return 0; 203822698aa2SShawn Guo } 203922698aa2SShawn Guo #else 204022698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 204122698aa2SShawn Guo struct platform_device *pdev) 204222698aa2SShawn Guo { 204320bb8095SUwe Kleine-König return 1; 204422698aa2SShawn Guo } 204522698aa2SShawn Guo #endif 204622698aa2SShawn Guo 204722698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 204822698aa2SShawn Guo struct platform_device *pdev) 204922698aa2SShawn Guo { 2050574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 205122698aa2SShawn Guo 205222698aa2SShawn Guo sport->port.line = pdev->id; 205322698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 205422698aa2SShawn Guo 205522698aa2SShawn Guo if (!pdata) 205622698aa2SShawn Guo return; 205722698aa2SShawn Guo 205822698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 205922698aa2SShawn Guo sport->have_rtscts = 1; 206022698aa2SShawn Guo } 206122698aa2SShawn Guo 2062ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 2063ab4382d2SGreg Kroah-Hartman { 2064ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2065ab4382d2SGreg Kroah-Hartman void __iomem *base; 20668a61f0c7SFabio Estevam int ret = 0, reg; 2067ab4382d2SGreg Kroah-Hartman struct resource *res; 2068842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2069ab4382d2SGreg Kroah-Hartman 207042d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2071ab4382d2SGreg Kroah-Hartman if (!sport) 2072ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2073ab4382d2SGreg Kroah-Hartman 207422698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 207520bb8095SUwe Kleine-König if (ret > 0) 207622698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 207720bb8095SUwe Kleine-König else if (ret < 0) 207842d34191SSachin Kamat return ret; 207922698aa2SShawn Guo 2080ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2081da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2082da82f997SAlexander Shiyan if (IS_ERR(base)) 2083da82f997SAlexander Shiyan return PTR_ERR(base); 2084ab4382d2SGreg Kroah-Hartman 2085842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2086842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2087842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2088842633bdSUwe Kleine-König 2089ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2090ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2091ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2092ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2093ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2094842633bdSUwe Kleine-König sport->port.irq = rxirq; 2095ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2096ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 209717b8f2a3SUwe Kleine-König sport->port.rs485_config = imx_rs485_config; 209817b8f2a3SUwe Kleine-König sport->port.rs485.flags = 209917b8f2a3SUwe Kleine-König SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX; 2100ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 2101ab4382d2SGreg Kroah-Hartman init_timer(&sport->timer); 2102ab4382d2SGreg Kroah-Hartman sport->timer.function = imx_timeout; 2103ab4382d2SGreg Kroah-Hartman sport->timer.data = (unsigned long)sport; 2104ab4382d2SGreg Kroah-Hartman 210558362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 210658362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 210758362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 210858362d5bSUwe Kleine-König 21093a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 21103a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 21113a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2112833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 211342d34191SSachin Kamat return ret; 2114ab4382d2SGreg Kroah-Hartman } 2115ab4382d2SGreg Kroah-Hartman 21163a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 21173a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 21183a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2119833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 212042d34191SSachin Kamat return ret; 21213a9465faSSascha Hauer } 21223a9465faSSascha Hauer 21233a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2124ab4382d2SGreg Kroah-Hartman 21258a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 21268a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 21278a61f0c7SFabio Estevam if (ret) 21288a61f0c7SFabio Estevam return ret; 21298a61f0c7SFabio Estevam 21308a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 21318a61f0c7SFabio Estevam reg = readl_relaxed(sport->port.membase + UCR1); 21328a61f0c7SFabio Estevam reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 21338a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 21348a61f0c7SFabio Estevam writel_relaxed(reg, sport->port.membase + UCR1); 21358a61f0c7SFabio Estevam 21368a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 21378a61f0c7SFabio Estevam 2138c0d1c6b0SFabio Estevam /* 2139c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2140c0d1c6b0SFabio Estevam * chips only have one interrupt. 2141c0d1c6b0SFabio Estevam */ 2142842633bdSUwe Kleine-König if (txirq > 0) { 2143842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2144c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2145c0d1c6b0SFabio Estevam if (ret) 2146c0d1c6b0SFabio Estevam return ret; 2147c0d1c6b0SFabio Estevam 2148842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2149c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2150c0d1c6b0SFabio Estevam if (ret) 2151c0d1c6b0SFabio Estevam return ret; 2152c0d1c6b0SFabio Estevam } else { 2153842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2154c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 2155c0d1c6b0SFabio Estevam if (ret) 2156c0d1c6b0SFabio Estevam return ret; 2157c0d1c6b0SFabio Estevam } 2158c0d1c6b0SFabio Estevam 215922698aa2SShawn Guo imx_ports[sport->port.line] = sport; 2160ab4382d2SGreg Kroah-Hartman 21610a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2162ab4382d2SGreg Kroah-Hartman 216345af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2164ab4382d2SGreg Kroah-Hartman } 2165ab4382d2SGreg Kroah-Hartman 2166ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2167ab4382d2SGreg Kroah-Hartman { 2168ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2169ab4382d2SGreg Kroah-Hartman 217045af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2171ab4382d2SGreg Kroah-Hartman } 2172ab4382d2SGreg Kroah-Hartman 2173c868cbb7SEduardo Valentin static void serial_imx_restore_context(struct imx_port *sport) 2174c868cbb7SEduardo Valentin { 2175c868cbb7SEduardo Valentin if (!sport->context_saved) 2176c868cbb7SEduardo Valentin return; 2177c868cbb7SEduardo Valentin 2178c868cbb7SEduardo Valentin writel(sport->saved_reg[4], sport->port.membase + UFCR); 2179c868cbb7SEduardo Valentin writel(sport->saved_reg[5], sport->port.membase + UESC); 2180c868cbb7SEduardo Valentin writel(sport->saved_reg[6], sport->port.membase + UTIM); 2181c868cbb7SEduardo Valentin writel(sport->saved_reg[7], sport->port.membase + UBIR); 2182c868cbb7SEduardo Valentin writel(sport->saved_reg[8], sport->port.membase + UBMR); 2183c868cbb7SEduardo Valentin writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS); 2184c868cbb7SEduardo Valentin writel(sport->saved_reg[0], sport->port.membase + UCR1); 2185c868cbb7SEduardo Valentin writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2); 2186c868cbb7SEduardo Valentin writel(sport->saved_reg[2], sport->port.membase + UCR3); 2187c868cbb7SEduardo Valentin writel(sport->saved_reg[3], sport->port.membase + UCR4); 2188c868cbb7SEduardo Valentin sport->context_saved = false; 2189c868cbb7SEduardo Valentin } 2190c868cbb7SEduardo Valentin 2191c868cbb7SEduardo Valentin static void serial_imx_save_context(struct imx_port *sport) 2192c868cbb7SEduardo Valentin { 2193c868cbb7SEduardo Valentin /* Save necessary regs */ 2194c868cbb7SEduardo Valentin sport->saved_reg[0] = readl(sport->port.membase + UCR1); 2195c868cbb7SEduardo Valentin sport->saved_reg[1] = readl(sport->port.membase + UCR2); 2196c868cbb7SEduardo Valentin sport->saved_reg[2] = readl(sport->port.membase + UCR3); 2197c868cbb7SEduardo Valentin sport->saved_reg[3] = readl(sport->port.membase + UCR4); 2198c868cbb7SEduardo Valentin sport->saved_reg[4] = readl(sport->port.membase + UFCR); 2199c868cbb7SEduardo Valentin sport->saved_reg[5] = readl(sport->port.membase + UESC); 2200c868cbb7SEduardo Valentin sport->saved_reg[6] = readl(sport->port.membase + UTIM); 2201c868cbb7SEduardo Valentin sport->saved_reg[7] = readl(sport->port.membase + UBIR); 2202c868cbb7SEduardo Valentin sport->saved_reg[8] = readl(sport->port.membase + UBMR); 2203c868cbb7SEduardo Valentin sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS); 2204c868cbb7SEduardo Valentin sport->context_saved = true; 2205c868cbb7SEduardo Valentin } 2206c868cbb7SEduardo Valentin 2207189550b8SEduardo Valentin static void serial_imx_enable_wakeup(struct imx_port *sport, bool on) 2208189550b8SEduardo Valentin { 2209189550b8SEduardo Valentin unsigned int val; 2210189550b8SEduardo Valentin 2211189550b8SEduardo Valentin val = readl(sport->port.membase + UCR3); 2212189550b8SEduardo Valentin if (on) 2213189550b8SEduardo Valentin val |= UCR3_AWAKEN; 2214189550b8SEduardo Valentin else 2215189550b8SEduardo Valentin val &= ~UCR3_AWAKEN; 2216189550b8SEduardo Valentin writel(val, sport->port.membase + UCR3); 2217bc85734bSEduardo Valentin 2218bc85734bSEduardo Valentin val = readl(sport->port.membase + UCR1); 2219bc85734bSEduardo Valentin if (on) 2220bc85734bSEduardo Valentin val |= UCR1_RTSDEN; 2221bc85734bSEduardo Valentin else 2222bc85734bSEduardo Valentin val &= ~UCR1_RTSDEN; 2223bc85734bSEduardo Valentin writel(val, sport->port.membase + UCR1); 2224189550b8SEduardo Valentin } 2225189550b8SEduardo Valentin 222690bb6bd3SShenwei Wang static int imx_serial_port_suspend_noirq(struct device *dev) 222790bb6bd3SShenwei Wang { 222890bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 222990bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 223090bb6bd3SShenwei Wang int ret; 223190bb6bd3SShenwei Wang 223290bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 223390bb6bd3SShenwei Wang if (ret) 223490bb6bd3SShenwei Wang return ret; 223590bb6bd3SShenwei Wang 2236c868cbb7SEduardo Valentin serial_imx_save_context(sport); 223790bb6bd3SShenwei Wang 223890bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 223990bb6bd3SShenwei Wang 224090bb6bd3SShenwei Wang return 0; 224190bb6bd3SShenwei Wang } 224290bb6bd3SShenwei Wang 224390bb6bd3SShenwei Wang static int imx_serial_port_resume_noirq(struct device *dev) 224490bb6bd3SShenwei Wang { 224590bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 224690bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 224790bb6bd3SShenwei Wang int ret; 224890bb6bd3SShenwei Wang 224990bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 225090bb6bd3SShenwei Wang if (ret) 225190bb6bd3SShenwei Wang return ret; 225290bb6bd3SShenwei Wang 2253c868cbb7SEduardo Valentin serial_imx_restore_context(sport); 225490bb6bd3SShenwei Wang 225590bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 225690bb6bd3SShenwei Wang 225790bb6bd3SShenwei Wang return 0; 225890bb6bd3SShenwei Wang } 225990bb6bd3SShenwei Wang 226090bb6bd3SShenwei Wang static int imx_serial_port_suspend(struct device *dev) 226190bb6bd3SShenwei Wang { 226290bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 226390bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 226490bb6bd3SShenwei Wang 226590bb6bd3SShenwei Wang /* enable wakeup from i.MX UART */ 2266189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, true); 226790bb6bd3SShenwei Wang 226890bb6bd3SShenwei Wang uart_suspend_port(&imx_reg, &sport->port); 226990bb6bd3SShenwei Wang 227029add68dSMartin Fuzzey /* Needed to enable clock in suspend_noirq */ 227129add68dSMartin Fuzzey return clk_prepare(sport->clk_ipg); 227290bb6bd3SShenwei Wang } 227390bb6bd3SShenwei Wang 227490bb6bd3SShenwei Wang static int imx_serial_port_resume(struct device *dev) 227590bb6bd3SShenwei Wang { 227690bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 227790bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 227890bb6bd3SShenwei Wang 227990bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 2280189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, false); 228190bb6bd3SShenwei Wang 228290bb6bd3SShenwei Wang uart_resume_port(&imx_reg, &sport->port); 228390bb6bd3SShenwei Wang 228429add68dSMartin Fuzzey clk_unprepare(sport->clk_ipg); 228529add68dSMartin Fuzzey 228690bb6bd3SShenwei Wang return 0; 228790bb6bd3SShenwei Wang } 228890bb6bd3SShenwei Wang 228990bb6bd3SShenwei Wang static const struct dev_pm_ops imx_serial_port_pm_ops = { 229090bb6bd3SShenwei Wang .suspend_noirq = imx_serial_port_suspend_noirq, 229190bb6bd3SShenwei Wang .resume_noirq = imx_serial_port_resume_noirq, 229290bb6bd3SShenwei Wang .suspend = imx_serial_port_suspend, 229390bb6bd3SShenwei Wang .resume = imx_serial_port_resume, 229490bb6bd3SShenwei Wang }; 229590bb6bd3SShenwei Wang 2296ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2297ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2298ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2299ab4382d2SGreg Kroah-Hartman 2300fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2301ab4382d2SGreg Kroah-Hartman .driver = { 2302ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 230322698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 230490bb6bd3SShenwei Wang .pm = &imx_serial_port_pm_ops, 2305ab4382d2SGreg Kroah-Hartman }, 2306ab4382d2SGreg Kroah-Hartman }; 2307ab4382d2SGreg Kroah-Hartman 2308ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2309ab4382d2SGreg Kroah-Hartman { 2310f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2311ab4382d2SGreg Kroah-Hartman 2312ab4382d2SGreg Kroah-Hartman if (ret) 2313ab4382d2SGreg Kroah-Hartman return ret; 2314ab4382d2SGreg Kroah-Hartman 2315ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2316ab4382d2SGreg Kroah-Hartman if (ret != 0) 2317ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2318ab4382d2SGreg Kroah-Hartman 2319f227824eSUwe Kleine-König return ret; 2320ab4382d2SGreg Kroah-Hartman } 2321ab4382d2SGreg Kroah-Hartman 2322ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2323ab4382d2SGreg Kroah-Hartman { 2324ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2325ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2326ab4382d2SGreg Kroah-Hartman } 2327ab4382d2SGreg Kroah-Hartman 2328ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2329ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2330ab4382d2SGreg Kroah-Hartman 2331ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2332ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2333ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2334ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2335