1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12ab4382d2SGreg Kroah-Hartman #define SUPPORT_SYSRQ 13ab4382d2SGreg Kroah-Hartman #endif 14ab4382d2SGreg Kroah-Hartman 15ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 23ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 24ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 27ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 28ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2922698aa2SShawn Guo #include <linux/of.h> 3022698aa2SShawn Guo #include <linux/of_device.h> 31e32a9f8fSSachin Kamat #include <linux/io.h> 32b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 33ab4382d2SGreg Kroah-Hartman 34ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 3582906b13SArnd Bergmann #include <linux/platform_data/serial-imx.h> 36b4cdc8f6SHuang Shijie #include <linux/platform_data/dma-imx.h> 37ab4382d2SGreg Kroah-Hartman 3858362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3958362d5bSUwe Kleine-König 40ab4382d2SGreg Kroah-Hartman /* Register definitions */ 41ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 42ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 43ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 44ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 45ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 46ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 47ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 48ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 49ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 50ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 51ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 52ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 53ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 54ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 55fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 56fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 57fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 58ab4382d2SGreg Kroah-Hartman 59ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 6055d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 61ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 62ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 63ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 64ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 65ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 66ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6726c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6825985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 69ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 71ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 72b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 74302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 76ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 77ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 78ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 79302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 80fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 81b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 83ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 91ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9401f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 95ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 96ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 97ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 101ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 104b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 105ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 106ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10827e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 109fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 110ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 111ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 115ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 118b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 122ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 123ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1257be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 126ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 127ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 128ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 129ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 130ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 131ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 133ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 134ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13686a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13727e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 138ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 139ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 140ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 142ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 143ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14590ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14690ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14990ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 150ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 151ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 152ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 153ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 154ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 155ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 156ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 157ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 158ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 159ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 160ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 161ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 162ab4382d2SGreg Kroah-Hartman 163ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 164ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 165ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 166ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 167ab4382d2SGreg Kroah-Hartman 168ab4382d2SGreg Kroah-Hartman /* 169ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 170ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 171ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 172ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 173ab4382d2SGreg Kroah-Hartman */ 174ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 175ab4382d2SGreg Kroah-Hartman 176ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 177ab4382d2SGreg Kroah-Hartman 178ab4382d2SGreg Kroah-Hartman #define UART_NR 8 179ab4382d2SGreg Kroah-Hartman 180f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 181fe6b540aSShawn Guo enum imx_uart_type { 182fe6b540aSShawn Guo IMX1_UART, 183fe6b540aSShawn Guo IMX21_UART, 1841c06bde6SMartyn Welch IMX53_UART, 185a496e628SHuang Shijie IMX6Q_UART, 186fe6b540aSShawn Guo }; 187fe6b540aSShawn Guo 188fe6b540aSShawn Guo /* device type dependent stuff */ 189fe6b540aSShawn Guo struct imx_uart_data { 190fe6b540aSShawn Guo unsigned uts_reg; 191fe6b540aSShawn Guo enum imx_uart_type devtype; 192fe6b540aSShawn Guo }; 193fe6b540aSShawn Guo 194ab4382d2SGreg Kroah-Hartman struct imx_port { 195ab4382d2SGreg Kroah-Hartman struct uart_port port; 196ab4382d2SGreg Kroah-Hartman struct timer_list timer; 197ab4382d2SGreg Kroah-Hartman unsigned int old_status; 198ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 1997b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20020ff2fe6SHuang Shijie unsigned int dte_mode:1; 2013a9465faSSascha Hauer struct clk *clk_ipg; 2023a9465faSSascha Hauer struct clk *clk_per; 2037d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 204b4cdc8f6SHuang Shijie 20558362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 20658362d5bSUwe Kleine-König 2073a0ab62fSUwe Kleine-König /* shadow registers */ 2083a0ab62fSUwe Kleine-König unsigned int ucr1; 2093a0ab62fSUwe Kleine-König unsigned int ucr2; 2103a0ab62fSUwe Kleine-König unsigned int ucr3; 2113a0ab62fSUwe Kleine-König unsigned int ucr4; 2123a0ab62fSUwe Kleine-König unsigned int ufcr; 2133a0ab62fSUwe Kleine-König 214b4cdc8f6SHuang Shijie /* DMA fields */ 215b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 216b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 217b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 218b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 219b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 220b4cdc8f6SHuang Shijie void *rx_buf; 2219d297239SNandor Han struct circ_buf rx_ring; 2229d297239SNandor Han unsigned int rx_periods; 2239d297239SNandor Han dma_cookie_t rx_cookie; 2247cb92fd2SHuang Shijie unsigned int tx_bytes; 225b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 22690bb6bd3SShenwei Wang unsigned int saved_reg[10]; 227c868cbb7SEduardo Valentin bool context_saved; 228ab4382d2SGreg Kroah-Hartman }; 229ab4382d2SGreg Kroah-Hartman 2300ad5a814SDirk Behme struct imx_port_ucrs { 2310ad5a814SDirk Behme unsigned int ucr1; 2320ad5a814SDirk Behme unsigned int ucr2; 2330ad5a814SDirk Behme unsigned int ucr3; 2340ad5a814SDirk Behme }; 2350ad5a814SDirk Behme 236fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 237fe6b540aSShawn Guo [IMX1_UART] = { 238fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 239fe6b540aSShawn Guo .devtype = IMX1_UART, 240fe6b540aSShawn Guo }, 241fe6b540aSShawn Guo [IMX21_UART] = { 242fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 243fe6b540aSShawn Guo .devtype = IMX21_UART, 244fe6b540aSShawn Guo }, 2451c06bde6SMartyn Welch [IMX53_UART] = { 2461c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2471c06bde6SMartyn Welch .devtype = IMX53_UART, 2481c06bde6SMartyn Welch }, 249a496e628SHuang Shijie [IMX6Q_UART] = { 250a496e628SHuang Shijie .uts_reg = IMX21_UTS, 251a496e628SHuang Shijie .devtype = IMX6Q_UART, 252a496e628SHuang Shijie }, 253fe6b540aSShawn Guo }; 254fe6b540aSShawn Guo 25531ada047SKrzysztof Kozlowski static const struct platform_device_id imx_uart_devtype[] = { 256fe6b540aSShawn Guo { 257fe6b540aSShawn Guo .name = "imx1-uart", 258fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 259fe6b540aSShawn Guo }, { 260fe6b540aSShawn Guo .name = "imx21-uart", 261fe6b540aSShawn Guo .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 262fe6b540aSShawn Guo }, { 2631c06bde6SMartyn Welch .name = "imx53-uart", 2641c06bde6SMartyn Welch .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 2651c06bde6SMartyn Welch }, { 266a496e628SHuang Shijie .name = "imx6q-uart", 267a496e628SHuang Shijie .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 268a496e628SHuang Shijie }, { 269fe6b540aSShawn Guo /* sentinel */ 270fe6b540aSShawn Guo } 271fe6b540aSShawn Guo }; 272fe6b540aSShawn Guo MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 273fe6b540aSShawn Guo 274ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 275a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2761c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27722698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27822698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27922698aa2SShawn Guo { /* sentinel */ } 28022698aa2SShawn Guo }; 28122698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 28222698aa2SShawn Guo 28327c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 28427c84426SUwe Kleine-König { 2853a0ab62fSUwe Kleine-König switch (offset) { 2863a0ab62fSUwe Kleine-König case UCR1: 2873a0ab62fSUwe Kleine-König sport->ucr1 = val; 2883a0ab62fSUwe Kleine-König break; 2893a0ab62fSUwe Kleine-König case UCR2: 2903a0ab62fSUwe Kleine-König sport->ucr2 = val; 2913a0ab62fSUwe Kleine-König break; 2923a0ab62fSUwe Kleine-König case UCR3: 2933a0ab62fSUwe Kleine-König sport->ucr3 = val; 2943a0ab62fSUwe Kleine-König break; 2953a0ab62fSUwe Kleine-König case UCR4: 2963a0ab62fSUwe Kleine-König sport->ucr4 = val; 2973a0ab62fSUwe Kleine-König break; 2983a0ab62fSUwe Kleine-König case UFCR: 2993a0ab62fSUwe Kleine-König sport->ufcr = val; 3003a0ab62fSUwe Kleine-König break; 3013a0ab62fSUwe Kleine-König default: 3023a0ab62fSUwe Kleine-König break; 3033a0ab62fSUwe Kleine-König } 30427c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 30527c84426SUwe Kleine-König } 30627c84426SUwe Kleine-König 30727c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30827c84426SUwe Kleine-König { 3093a0ab62fSUwe Kleine-König switch (offset) { 3103a0ab62fSUwe Kleine-König case UCR1: 3113a0ab62fSUwe Kleine-König return sport->ucr1; 3123a0ab62fSUwe Kleine-König break; 3133a0ab62fSUwe Kleine-König case UCR2: 3143a0ab62fSUwe Kleine-König /* 3153a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3163a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 3173a0ab62fSUwe Kleine-König * clears after being set, reread conditionally. 3183a0ab62fSUwe Kleine-König */ 3193a0ab62fSUwe Kleine-König if (sport->ucr2 & UCR2_SRST) 3203a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3213a0ab62fSUwe Kleine-König return sport->ucr2; 3223a0ab62fSUwe Kleine-König break; 3233a0ab62fSUwe Kleine-König case UCR3: 3243a0ab62fSUwe Kleine-König return sport->ucr3; 3253a0ab62fSUwe Kleine-König break; 3263a0ab62fSUwe Kleine-König case UCR4: 3273a0ab62fSUwe Kleine-König return sport->ucr4; 3283a0ab62fSUwe Kleine-König break; 3293a0ab62fSUwe Kleine-König case UFCR: 3303a0ab62fSUwe Kleine-König return sport->ufcr; 3313a0ab62fSUwe Kleine-König break; 3323a0ab62fSUwe Kleine-König default: 33327c84426SUwe Kleine-König return readl(sport->port.membase + offset); 33427c84426SUwe Kleine-König } 3353a0ab62fSUwe Kleine-König } 33627c84426SUwe Kleine-König 337fe6b540aSShawn Guo static inline unsigned uts_reg(struct imx_port *sport) 338fe6b540aSShawn Guo { 339fe6b540aSShawn Guo return sport->devdata->uts_reg; 340fe6b540aSShawn Guo } 341fe6b540aSShawn Guo 342fe6b540aSShawn Guo static inline int is_imx1_uart(struct imx_port *sport) 343fe6b540aSShawn Guo { 344fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 345fe6b540aSShawn Guo } 346fe6b540aSShawn Guo 347fe6b540aSShawn Guo static inline int is_imx21_uart(struct imx_port *sport) 348fe6b540aSShawn Guo { 349fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 350fe6b540aSShawn Guo } 351fe6b540aSShawn Guo 3521c06bde6SMartyn Welch static inline int is_imx53_uart(struct imx_port *sport) 3531c06bde6SMartyn Welch { 3541c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3551c06bde6SMartyn Welch } 3561c06bde6SMartyn Welch 357a496e628SHuang Shijie static inline int is_imx6q_uart(struct imx_port *sport) 358a496e628SHuang Shijie { 359a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 360a496e628SHuang Shijie } 361ab4382d2SGreg Kroah-Hartman /* 36244a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 36344a75411Sfabio.estevam@freescale.com */ 36493d94b37SFabio Estevam #if defined(CONFIG_SERIAL_IMX_CONSOLE) 36527c84426SUwe Kleine-König static void imx_port_ucrs_save(struct imx_port *sport, 36644a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36744a75411Sfabio.estevam@freescale.com { 36844a75411Sfabio.estevam@freescale.com /* save control registers */ 36927c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 37027c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 37127c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 37244a75411Sfabio.estevam@freescale.com } 37344a75411Sfabio.estevam@freescale.com 37427c84426SUwe Kleine-König static void imx_port_ucrs_restore(struct imx_port *sport, 37544a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37644a75411Sfabio.estevam@freescale.com { 37744a75411Sfabio.estevam@freescale.com /* restore control registers */ 37827c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 37927c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 38027c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 38144a75411Sfabio.estevam@freescale.com } 382e8bfa760SFabio Estevam #endif 38344a75411Sfabio.estevam@freescale.com 3844444dcf1SUwe Kleine-König static void imx_port_rts_active(struct imx_port *sport, u32 *ucr2) 38558362d5bSUwe Kleine-König { 386bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38758362d5bSUwe Kleine-König 388a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 389a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39058362d5bSUwe Kleine-König } 39158362d5bSUwe Kleine-König 3924444dcf1SUwe Kleine-König static void imx_port_rts_inactive(struct imx_port *sport, u32 *ucr2) 39358362d5bSUwe Kleine-König { 394bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 395bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39658362d5bSUwe Kleine-König 397a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 398a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39958362d5bSUwe Kleine-König } 40058362d5bSUwe Kleine-König 4014444dcf1SUwe Kleine-König static void imx_port_rts_auto(struct imx_port *sport, u32 *ucr2) 40258362d5bSUwe Kleine-König { 40358362d5bSUwe Kleine-König *ucr2 |= UCR2_CTSC; 40458362d5bSUwe Kleine-König } 40558362d5bSUwe Kleine-König 4066aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 407ab4382d2SGreg Kroah-Hartman static void imx_stop_tx(struct uart_port *port) 408ab4382d2SGreg Kroah-Hartman { 409ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4104444dcf1SUwe Kleine-König u32 ucr1; 411ab4382d2SGreg Kroah-Hartman 4129ce4f8f3SGreg Kroah-Hartman /* 4139ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4149ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4159ce4f8f3SGreg Kroah-Hartman */ 416686351f3SUwe Kleine-König if (sport->dma_is_txing) 4179ce4f8f3SGreg Kroah-Hartman return; 418b4cdc8f6SHuang Shijie 4194444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 4204444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1); 42117b8f2a3SUwe Kleine-König 42217b8f2a3SUwe Kleine-König /* in rs485 mode disable transmitter if shifter is empty */ 42317b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED && 42427c84426SUwe Kleine-König imx_uart_readl(sport, USR2) & USR2_TXDC) { 4254444dcf1SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 42617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4274444dcf1SUwe Kleine-König imx_port_rts_active(sport, &ucr2); 4281a613626SFabio Estevam else 4294444dcf1SUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 4304444dcf1SUwe Kleine-König ucr2 |= UCR2_RXEN; 4314444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 43217b8f2a3SUwe Kleine-König 4334444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 4344444dcf1SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 4354444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 43617b8f2a3SUwe Kleine-König } 437ab4382d2SGreg Kroah-Hartman } 438ab4382d2SGreg Kroah-Hartman 4396aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 440ab4382d2SGreg Kroah-Hartman static void imx_stop_rx(struct uart_port *port) 441ab4382d2SGreg Kroah-Hartman { 442ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 4434444dcf1SUwe Kleine-König u32 ucr1, ucr2; 444ab4382d2SGreg Kroah-Hartman 445686351f3SUwe Kleine-König if (sport->dma_is_rxing) { 44645564a66SHuang Shijie if (sport->port.suspended) { 44745564a66SHuang Shijie dmaengine_terminate_all(sport->dma_chan_rx); 44845564a66SHuang Shijie sport->dma_is_rxing = 0; 44945564a66SHuang Shijie } else { 4509ce4f8f3SGreg Kroah-Hartman return; 45145564a66SHuang Shijie } 45245564a66SHuang Shijie } 453b4cdc8f6SHuang Shijie 4544444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 4554444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2 & ~UCR2_RXEN, UCR2); 45685878399SHuang Shijie 45785878399SHuang Shijie /* disable the `Receiver Ready Interrrupt` */ 4584444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 4594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 & ~UCR1_RRDYEN, UCR1); 460ab4382d2SGreg Kroah-Hartman } 461ab4382d2SGreg Kroah-Hartman 4626aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 463ab4382d2SGreg Kroah-Hartman static void imx_enable_ms(struct uart_port *port) 464ab4382d2SGreg Kroah-Hartman { 465ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 466ab4382d2SGreg Kroah-Hartman 467ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 46858362d5bSUwe Kleine-König 46958362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 470ab4382d2SGreg Kroah-Hartman } 471ab4382d2SGreg Kroah-Hartman 47291a1a909SJiada Wang static void imx_dma_tx(struct imx_port *sport); 4736aed2a88SUwe Kleine-König 4746aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 475ab4382d2SGreg Kroah-Hartman static inline void imx_transmit_buffer(struct imx_port *sport) 476ab4382d2SGreg Kroah-Hartman { 477ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 478ab4382d2SGreg Kroah-Hartman 4795e42e9a3SPeter Hurley if (sport->port.x_char) { 4805e42e9a3SPeter Hurley /* Send next char */ 48127c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 4827e2fb5aaSJiada Wang sport->port.icount.tx++; 4837e2fb5aaSJiada Wang sport->port.x_char = 0; 4845e42e9a3SPeter Hurley return; 4855e42e9a3SPeter Hurley } 4865e42e9a3SPeter Hurley 4875e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 4885e42e9a3SPeter Hurley imx_stop_tx(&sport->port); 4895e42e9a3SPeter Hurley return; 4905e42e9a3SPeter Hurley } 4915e42e9a3SPeter Hurley 49291a1a909SJiada Wang if (sport->dma_is_enabled) { 4934444dcf1SUwe Kleine-König u32 ucr1; 49491a1a909SJiada Wang /* 49591a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 49691a1a909SJiada Wang * and the TX IRQ is disabled. 49791a1a909SJiada Wang **/ 4984444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 4994444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXMPTYEN; 50091a1a909SJiada Wang if (sport->dma_is_txing) { 5014444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5024444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 50391a1a909SJiada Wang } else { 5044444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 50591a1a909SJiada Wang imx_dma_tx(sport); 50691a1a909SJiada Wang } 50791a1a909SJiada Wang 5085aabd3b0SIan Jamison return; 5090c549223SUwe Kleine-König } 5105aabd3b0SIan Jamison 5115aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 51227c84426SUwe Kleine-König !(imx_uart_readl(sport, uts_reg(sport)) & UTS_TXFULL)) { 513ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 514ab4382d2SGreg Kroah-Hartman * out the port here */ 51527c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 516ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 517ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 518ab4382d2SGreg Kroah-Hartman } 519ab4382d2SGreg Kroah-Hartman 520ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 521ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 522ab4382d2SGreg Kroah-Hartman 523ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 524ab4382d2SGreg Kroah-Hartman imx_stop_tx(&sport->port); 525ab4382d2SGreg Kroah-Hartman } 526ab4382d2SGreg Kroah-Hartman 527b4cdc8f6SHuang Shijie static void dma_tx_callback(void *data) 528b4cdc8f6SHuang Shijie { 529b4cdc8f6SHuang Shijie struct imx_port *sport = data; 530b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 531b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 532b4cdc8f6SHuang Shijie unsigned long flags; 5334444dcf1SUwe Kleine-König u32 ucr1; 534b4cdc8f6SHuang Shijie 53542f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 53642f752b3SDirk Behme 537b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 538b4cdc8f6SHuang Shijie 5394444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5404444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5414444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 542a2c718ceSDirk Behme 54342f752b3SDirk Behme /* update the stat */ 54442f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 54542f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 54642f752b3SDirk Behme 54742f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 54842f752b3SDirk Behme 549b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 550b4cdc8f6SHuang Shijie 551d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 552b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 5539ce4f8f3SGreg Kroah-Hartman 5540bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 5550bbc9b81SJiada Wang imx_dma_tx(sport); 55664432a85SUwe Kleine-König 5570bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 558b4cdc8f6SHuang Shijie } 559b4cdc8f6SHuang Shijie 5606aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5617cb92fd2SHuang Shijie static void imx_dma_tx(struct imx_port *sport) 562b4cdc8f6SHuang Shijie { 563b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 564b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 565b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 566b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 567b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 5684444dcf1SUwe Kleine-König u32 ucr1; 569b4cdc8f6SHuang Shijie int ret; 570b4cdc8f6SHuang Shijie 57142f752b3SDirk Behme if (sport->dma_is_txing) 572b4cdc8f6SHuang Shijie return; 573b4cdc8f6SHuang Shijie 574b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 575b4cdc8f6SHuang Shijie 5767942f857SDirk Behme if (xmit->tail < xmit->head) { 5777942f857SDirk Behme sport->dma_tx_nents = 1; 5787942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 5797942f857SDirk Behme } else { 580b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 581b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 582b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 583b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 584b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 585b4cdc8f6SHuang Shijie } 586b4cdc8f6SHuang Shijie 587b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 588b4cdc8f6SHuang Shijie if (ret == 0) { 589b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 590b4cdc8f6SHuang Shijie return; 591b4cdc8f6SHuang Shijie } 592b4cdc8f6SHuang Shijie desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 593b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 594b4cdc8f6SHuang Shijie if (!desc) { 59524649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 59624649821SDirk Behme DMA_TO_DEVICE); 597b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 598b4cdc8f6SHuang Shijie return; 599b4cdc8f6SHuang Shijie } 600b4cdc8f6SHuang Shijie desc->callback = dma_tx_callback; 601b4cdc8f6SHuang Shijie desc->callback_param = sport; 602b4cdc8f6SHuang Shijie 603b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 604b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 605a2c718ceSDirk Behme 6064444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6074444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6084444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 609a2c718ceSDirk Behme 610b4cdc8f6SHuang Shijie /* fire it */ 611b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 612b4cdc8f6SHuang Shijie dmaengine_submit(desc); 613b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 614b4cdc8f6SHuang Shijie return; 615b4cdc8f6SHuang Shijie } 616b4cdc8f6SHuang Shijie 6176aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 618ab4382d2SGreg Kroah-Hartman static void imx_start_tx(struct uart_port *port) 619ab4382d2SGreg Kroah-Hartman { 620ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6214444dcf1SUwe Kleine-König u32 ucr1; 622ab4382d2SGreg Kroah-Hartman 62317b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 6244444dcf1SUwe Kleine-König u32 ucr2, ucr4; 6254444dcf1SUwe Kleine-König 6264444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 62717b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6284444dcf1SUwe Kleine-König imx_port_rts_active(sport, &ucr2); 6291a613626SFabio Estevam else 6304444dcf1SUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 6317d1cadcaSBaruch Siach if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 6324444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 6334444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 63417b8f2a3SUwe Kleine-König 63558362d5bSUwe Kleine-König /* enable transmitter and shifter empty irq */ 6364444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 6374444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 6384444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 63917b8f2a3SUwe Kleine-König } 64017b8f2a3SUwe Kleine-König 641b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 6424444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6434444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1); 644b4cdc8f6SHuang Shijie } 645ab4382d2SGreg Kroah-Hartman 646b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 64791a1a909SJiada Wang if (sport->port.x_char) { 64891a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 64991a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 6504444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6514444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 6524444dcf1SUwe Kleine-König ucr1 |= UCR1_TXMPTYEN; 6534444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 65491a1a909SJiada Wang return; 65591a1a909SJiada Wang } 65691a1a909SJiada Wang 6575e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 6585e42e9a3SPeter Hurley !uart_tx_stopped(port)) 6597cb92fd2SHuang Shijie imx_dma_tx(sport); 660b4cdc8f6SHuang Shijie return; 661b4cdc8f6SHuang Shijie } 662ab4382d2SGreg Kroah-Hartman } 663ab4382d2SGreg Kroah-Hartman 664ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rtsint(int irq, void *dev_id) 665ab4382d2SGreg Kroah-Hartman { 666ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 6674444dcf1SUwe Kleine-König u32 usr1; 668ab4382d2SGreg Kroah-Hartman unsigned long flags; 669ab4382d2SGreg Kroah-Hartman 670ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 671ab4382d2SGreg Kroah-Hartman 67227c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 6734444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 6744444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 675ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 676ab4382d2SGreg Kroah-Hartman 677ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 678ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 679ab4382d2SGreg Kroah-Hartman } 680ab4382d2SGreg Kroah-Hartman 681ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_txint(int irq, void *dev_id) 682ab4382d2SGreg Kroah-Hartman { 683ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 684ab4382d2SGreg Kroah-Hartman unsigned long flags; 685ab4382d2SGreg Kroah-Hartman 686ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 687ab4382d2SGreg Kroah-Hartman imx_transmit_buffer(sport); 688ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 689ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 690ab4382d2SGreg Kroah-Hartman } 691ab4382d2SGreg Kroah-Hartman 692ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_rxint(int irq, void *dev_id) 693ab4382d2SGreg Kroah-Hartman { 694ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 695ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 69692a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 6974444dcf1SUwe Kleine-König unsigned long flags; 698ab4382d2SGreg Kroah-Hartman 699ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 700ab4382d2SGreg Kroah-Hartman 70127c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 7024444dcf1SUwe Kleine-König u32 usr2; 7034444dcf1SUwe Kleine-König 704ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 705ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 706ab4382d2SGreg Kroah-Hartman 70727c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 708ab4382d2SGreg Kroah-Hartman 7094444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 7104444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 71127c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 712ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 713ab4382d2SGreg Kroah-Hartman continue; 714ab4382d2SGreg Kroah-Hartman } 715ab4382d2SGreg Kroah-Hartman 716ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 717ab4382d2SGreg Kroah-Hartman continue; 718ab4382d2SGreg Kroah-Hartman 719019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 720019dc9eaSHui Wang if (rx & URXD_BRK) 721019dc9eaSHui Wang sport->port.icount.brk++; 722019dc9eaSHui Wang else if (rx & URXD_PRERR) 723ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 724ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 725ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 726ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 727ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 728ab4382d2SGreg Kroah-Hartman 729ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 730ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 731ab4382d2SGreg Kroah-Hartman goto out; 732ab4382d2SGreg Kroah-Hartman continue; 733ab4382d2SGreg Kroah-Hartman } 734ab4382d2SGreg Kroah-Hartman 7358d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 736ab4382d2SGreg Kroah-Hartman 737019dc9eaSHui Wang if (rx & URXD_BRK) 738019dc9eaSHui Wang flg = TTY_BREAK; 739019dc9eaSHui Wang else if (rx & URXD_PRERR) 740ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 741ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 742ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 743ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 744ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 745ab4382d2SGreg Kroah-Hartman 746ab4382d2SGreg Kroah-Hartman #ifdef SUPPORT_SYSRQ 747ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 748ab4382d2SGreg Kroah-Hartman #endif 749ab4382d2SGreg Kroah-Hartman } 750ab4382d2SGreg Kroah-Hartman 75155d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 75255d8693aSJiada Wang goto out; 75355d8693aSJiada Wang 7549b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 7559b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 756ab4382d2SGreg Kroah-Hartman } 757ab4382d2SGreg Kroah-Hartman 758ab4382d2SGreg Kroah-Hartman out: 759ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 7602e124b4aSJiri Slaby tty_flip_buffer_push(port); 761ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 762ab4382d2SGreg Kroah-Hartman } 763ab4382d2SGreg Kroah-Hartman 76418a42088SPeter Senna Tschudin static void clear_rx_errors(struct imx_port *sport); 765b4cdc8f6SHuang Shijie 76666f95884SUwe Kleine-König /* 76766f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 76866f95884SUwe Kleine-König */ 76966f95884SUwe Kleine-König static unsigned int imx_get_hwmctrl(struct imx_port *sport) 77066f95884SUwe Kleine-König { 77166f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 77227c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 77327c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 77466f95884SUwe Kleine-König 77566f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 77666f95884SUwe Kleine-König tmp |= TIOCM_CTS; 77766f95884SUwe Kleine-König 77866f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 7794b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 78066f95884SUwe Kleine-König tmp |= TIOCM_CAR; 78166f95884SUwe Kleine-König 78266f95884SUwe Kleine-König if (sport->dte_mode) 78327c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 78466f95884SUwe Kleine-König tmp |= TIOCM_RI; 78566f95884SUwe Kleine-König 78666f95884SUwe Kleine-König return tmp; 78766f95884SUwe Kleine-König } 78866f95884SUwe Kleine-König 78966f95884SUwe Kleine-König /* 79066f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 79166f95884SUwe Kleine-König */ 79266f95884SUwe Kleine-König static void imx_mctrl_check(struct imx_port *sport) 79366f95884SUwe Kleine-König { 79466f95884SUwe Kleine-König unsigned int status, changed; 79566f95884SUwe Kleine-König 79666f95884SUwe Kleine-König status = imx_get_hwmctrl(sport); 79766f95884SUwe Kleine-König changed = status ^ sport->old_status; 79866f95884SUwe Kleine-König 79966f95884SUwe Kleine-König if (changed == 0) 80066f95884SUwe Kleine-König return; 80166f95884SUwe Kleine-König 80266f95884SUwe Kleine-König sport->old_status = status; 80366f95884SUwe Kleine-König 80466f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 80566f95884SUwe Kleine-König sport->port.icount.rng++; 80666f95884SUwe Kleine-König if (changed & TIOCM_DSR) 80766f95884SUwe Kleine-König sport->port.icount.dsr++; 80866f95884SUwe Kleine-König if (changed & TIOCM_CAR) 80966f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 81066f95884SUwe Kleine-König if (changed & TIOCM_CTS) 81166f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 81266f95884SUwe Kleine-König 81366f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 81466f95884SUwe Kleine-König } 81566f95884SUwe Kleine-König 816ab4382d2SGreg Kroah-Hartman static irqreturn_t imx_int(int irq, void *dev_id) 817ab4382d2SGreg Kroah-Hartman { 818ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 81943776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 8204d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 821ab4382d2SGreg Kroah-Hartman 82227c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 82327c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 82427c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 82527c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 82627c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 82727c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 828ab4382d2SGreg Kroah-Hartman 82943776896SUwe Kleine-König /* 83043776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 83143776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 83243776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 83343776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 83443776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 83543776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 83643776896SUwe Kleine-König */ 83743776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 83843776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 83943776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 84043776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 84143776896SUwe Kleine-König if ((ucr1 & UCR1_TXMPTYEN) == 0) 84243776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 84343776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 84443776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 84543776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 84643776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 84743776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 84843776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 84943776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 85043776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 85143776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 85243776896SUwe Kleine-König usr2 &= ~USR2_ORE; 85343776896SUwe Kleine-König 85443776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 855ab4382d2SGreg Kroah-Hartman imx_rxint(irq, dev_id); 8564d845a62SUwe Kleine-König ret = IRQ_HANDLED; 857b4cdc8f6SHuang Shijie } 858ab4382d2SGreg Kroah-Hartman 85943776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 860ab4382d2SGreg Kroah-Hartman imx_txint(irq, dev_id); 8614d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8624d845a62SUwe Kleine-König } 863ab4382d2SGreg Kroah-Hartman 8640399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 86527e16501SUwe Kleine-König unsigned long flags; 86627e16501SUwe Kleine-König 86727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 86827e16501SUwe Kleine-König 86927e16501SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 87027e16501SUwe Kleine-König imx_mctrl_check(sport); 87127e16501SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 87227e16501SUwe Kleine-König 87327e16501SUwe Kleine-König ret = IRQ_HANDLED; 87427e16501SUwe Kleine-König } 87527e16501SUwe Kleine-König 8760399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 877ab4382d2SGreg Kroah-Hartman imx_rtsint(irq, dev_id); 8784d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8794d845a62SUwe Kleine-König } 880ab4382d2SGreg Kroah-Hartman 8810399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 88227c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 8834d845a62SUwe Kleine-König ret = IRQ_HANDLED; 8844d845a62SUwe Kleine-König } 885db1a9b55SFabio Estevam 8860399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 887f1f836e4SAlexander Stein sport->port.icount.overrun++; 88827c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 8894d845a62SUwe Kleine-König ret = IRQ_HANDLED; 890f1f836e4SAlexander Stein } 891f1f836e4SAlexander Stein 8924d845a62SUwe Kleine-König return ret; 893ab4382d2SGreg Kroah-Hartman } 894ab4382d2SGreg Kroah-Hartman 895ab4382d2SGreg Kroah-Hartman /* 896ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 897ab4382d2SGreg Kroah-Hartman */ 898ab4382d2SGreg Kroah-Hartman static unsigned int imx_tx_empty(struct uart_port *port) 899ab4382d2SGreg Kroah-Hartman { 900ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9011ce43e58SHuang Shijie unsigned int ret; 902ab4382d2SGreg Kroah-Hartman 90327c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 9041ce43e58SHuang Shijie 9051ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 906686351f3SUwe Kleine-König if (sport->dma_is_txing) 9071ce43e58SHuang Shijie ret = 0; 9081ce43e58SHuang Shijie 9091ce43e58SHuang Shijie return ret; 910ab4382d2SGreg Kroah-Hartman } 911ab4382d2SGreg Kroah-Hartman 9126aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 91358362d5bSUwe Kleine-König static unsigned int imx_get_mctrl(struct uart_port *port) 91458362d5bSUwe Kleine-König { 91558362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 91658362d5bSUwe Kleine-König unsigned int ret = imx_get_hwmctrl(sport); 91758362d5bSUwe Kleine-König 91858362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 91958362d5bSUwe Kleine-König 92058362d5bSUwe Kleine-König return ret; 92158362d5bSUwe Kleine-König } 92258362d5bSUwe Kleine-König 9236aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 924ab4382d2SGreg Kroah-Hartman static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 925ab4382d2SGreg Kroah-Hartman { 926ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9274444dcf1SUwe Kleine-König u32 ucr3, uts; 928ab4382d2SGreg Kroah-Hartman 92917b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 9304444dcf1SUwe Kleine-König u32 ucr2; 9314444dcf1SUwe Kleine-König 9324444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 9334444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 934ab4382d2SGreg Kroah-Hartman if (mctrl & TIOCM_RTS) 9354444dcf1SUwe Kleine-König ucr2 |= UCR2_CTS | UCR2_CTSC; 9364444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 93717b8f2a3SUwe Kleine-König } 9386b471a98SHuang Shijie 9394444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 94090ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 9414444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 9424444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 94390ebc483SUwe Kleine-König 9444444dcf1SUwe Kleine-König uts = imx_uart_readl(sport, uts_reg(sport)) & ~UTS_LOOP; 9456b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 9464444dcf1SUwe Kleine-König uts |= UTS_LOOP; 9474444dcf1SUwe Kleine-König imx_uart_writel(sport, uts, uts_reg(sport)); 94858362d5bSUwe Kleine-König 94958362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 950ab4382d2SGreg Kroah-Hartman } 951ab4382d2SGreg Kroah-Hartman 952ab4382d2SGreg Kroah-Hartman /* 953ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 954ab4382d2SGreg Kroah-Hartman */ 955ab4382d2SGreg Kroah-Hartman static void imx_break_ctl(struct uart_port *port, int break_state) 956ab4382d2SGreg Kroah-Hartman { 957ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 9584444dcf1SUwe Kleine-König unsigned long flags; 9594444dcf1SUwe Kleine-König u32 ucr1; 960ab4382d2SGreg Kroah-Hartman 961ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 962ab4382d2SGreg Kroah-Hartman 9634444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 964ab4382d2SGreg Kroah-Hartman 965ab4382d2SGreg Kroah-Hartman if (break_state != 0) 9664444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 967ab4382d2SGreg Kroah-Hartman 9684444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 969ab4382d2SGreg Kroah-Hartman 970ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 971ab4382d2SGreg Kroah-Hartman } 972ab4382d2SGreg Kroah-Hartman 973cc568849SUwe Kleine-König /* 974cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 975cc568849SUwe Kleine-König * modem status signals. 976cc568849SUwe Kleine-König */ 977e99e88a9SKees Cook static void imx_timeout(struct timer_list *t) 978cc568849SUwe Kleine-König { 979e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 980cc568849SUwe Kleine-König unsigned long flags; 981cc568849SUwe Kleine-König 982cc568849SUwe Kleine-König if (sport->port.state) { 983cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 984cc568849SUwe Kleine-König imx_mctrl_check(sport); 985cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 986cc568849SUwe Kleine-König 987cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 988cc568849SUwe Kleine-König } 989cc568849SUwe Kleine-König } 990cc568849SUwe Kleine-König 991351ea50dSGreg Kroah-Hartman #define RX_BUF_SIZE (PAGE_SIZE) 992351ea50dSGreg Kroah-Hartman 993b4cdc8f6SHuang Shijie /* 994905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 995b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 996905c0decSLucas Stach * [2] the aging timer expires 997b4cdc8f6SHuang Shijie * 998905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 999905c0decSLucas Stach * for at least 8 byte durations. 1000b4cdc8f6SHuang Shijie */ 1001b4cdc8f6SHuang Shijie static void dma_rx_callback(void *data) 1002b4cdc8f6SHuang Shijie { 1003b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1004b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1005b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 10067cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1007b4cdc8f6SHuang Shijie struct dma_tx_state state; 10089d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1009b4cdc8f6SHuang Shijie enum dma_status status; 10109d297239SNandor Han unsigned int w_bytes = 0; 10119d297239SNandor Han unsigned int r_bytes; 10129d297239SNandor Han unsigned int bd_size; 1013b4cdc8f6SHuang Shijie 1014f0ef8834SHuang Shijie status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 1015392bceedSPhilipp Zabel 10169d297239SNandor Han if (status == DMA_ERROR) { 101741d98b5dSNandor Han clear_rx_errors(sport); 10189d297239SNandor Han return; 10199d297239SNandor Han } 1020b4cdc8f6SHuang Shijie 10219b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1022976b39cdSLucas Stach 1023976b39cdSLucas Stach /* 10249d297239SNandor Han * The state-residue variable represents the empty space 10259d297239SNandor Han * relative to the entire buffer. Taking this in consideration 10269d297239SNandor Han * the head is always calculated base on the buffer total 10279d297239SNandor Han * length - DMA transaction residue. The UART script from the 10289d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 10299d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 10309d297239SNandor Han * Taking this in consideration the tail is always at the 10319d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1032976b39cdSLucas Stach */ 10339d297239SNandor Han 10349d297239SNandor Han /* Calculate the head */ 10359d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 10369d297239SNandor Han 10379d297239SNandor Han /* Calculate the tail. */ 10389d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 10399d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 10409d297239SNandor Han 10419d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 10429d297239SNandor Han rx_ring->head > rx_ring->tail) { 10439d297239SNandor Han 10449d297239SNandor Han /* Move data from tail to head */ 10459d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 10469d297239SNandor Han 10479d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 10489d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 10499d297239SNandor Han DMA_FROM_DEVICE); 10509d297239SNandor Han 10519d297239SNandor Han w_bytes = tty_insert_flip_string(port, 10529d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 10539d297239SNandor Han 10549d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 10559d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 10569d297239SNandor Han DMA_FROM_DEVICE); 10579d297239SNandor Han 10589d297239SNandor Han if (w_bytes != r_bytes) 10599d297239SNandor Han sport->port.icount.buf_overrun++; 10609d297239SNandor Han 10619d297239SNandor Han sport->port.icount.rx += w_bytes; 10629d297239SNandor Han } else { 10639d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 10649d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1065ee5e7c10SRobin Gong } 10669d297239SNandor Han } 10679d297239SNandor Han 10689d297239SNandor Han if (w_bytes) { 10699d297239SNandor Han tty_flip_buffer_push(port); 10709d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 10719d297239SNandor Han } 10729d297239SNandor Han } 10739d297239SNandor Han 1074351ea50dSGreg Kroah-Hartman /* RX DMA buffer periods */ 1075351ea50dSGreg Kroah-Hartman #define RX_DMA_PERIODS 4 1076351ea50dSGreg Kroah-Hartman 1077b4cdc8f6SHuang Shijie static int start_rx_dma(struct imx_port *sport) 1078b4cdc8f6SHuang Shijie { 1079b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1080b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1081b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1082b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1083b4cdc8f6SHuang Shijie int ret; 1084b4cdc8f6SHuang Shijie 10859d297239SNandor Han sport->rx_ring.head = 0; 10869d297239SNandor Han sport->rx_ring.tail = 0; 1087351ea50dSGreg Kroah-Hartman sport->rx_periods = RX_DMA_PERIODS; 10889d297239SNandor Han 1089351ea50dSGreg Kroah-Hartman sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1090b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1091b4cdc8f6SHuang Shijie if (ret == 0) { 1092b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1093b4cdc8f6SHuang Shijie return -EINVAL; 1094b4cdc8f6SHuang Shijie } 10959d297239SNandor Han 10969d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 10979d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 10989d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 10999d297239SNandor Han 1100b4cdc8f6SHuang Shijie if (!desc) { 110124649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1102b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1103b4cdc8f6SHuang Shijie return -EINVAL; 1104b4cdc8f6SHuang Shijie } 1105b4cdc8f6SHuang Shijie desc->callback = dma_rx_callback; 1106b4cdc8f6SHuang Shijie desc->callback_param = sport; 1107b4cdc8f6SHuang Shijie 1108b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 11094139fd76SRomain Perier sport->dma_is_rxing = 1; 11109d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1111b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1112b4cdc8f6SHuang Shijie return 0; 1113b4cdc8f6SHuang Shijie } 1114b4cdc8f6SHuang Shijie 111541d98b5dSNandor Han static void clear_rx_errors(struct imx_port *sport) 111641d98b5dSNandor Han { 111745ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 11184444dcf1SUwe Kleine-König u32 usr1, usr2; 111941d98b5dSNandor Han 11204444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 11214444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 112241d98b5dSNandor Han 11234444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 112441d98b5dSNandor Han sport->port.icount.brk++; 112527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 112645ca673eSTroy Kisky uart_handle_break(&sport->port); 112745ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 112845ca673eSTroy Kisky sport->port.icount.buf_overrun++; 112945ca673eSTroy Kisky tty_flip_buffer_push(port); 113045ca673eSTroy Kisky } else { 113145ca673eSTroy Kisky dev_err(sport->port.dev, "DMA transaction error.\n"); 11324444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 113341d98b5dSNandor Han sport->port.icount.frame++; 113427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 11354444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 113641d98b5dSNandor Han sport->port.icount.parity++; 113727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 113841d98b5dSNandor Han } 113945ca673eSTroy Kisky } 114041d98b5dSNandor Han 11414444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 114241d98b5dSNandor Han sport->port.icount.overrun++; 114327c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 114441d98b5dSNandor Han } 114541d98b5dSNandor Han 114641d98b5dSNandor Han } 114741d98b5dSNandor Han 1148cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 1149cc32382dSLucas Stach #define RXTL_DEFAULT 1 /* reset default */ 1150184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1151184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1152cc32382dSLucas Stach 1153cc32382dSLucas Stach static void imx_setup_ufcr(struct imx_port *sport, 1154cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1155cc32382dSLucas Stach { 1156cc32382dSLucas Stach unsigned int val; 1157cc32382dSLucas Stach 1158cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 115927c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1160cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 116127c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1162cc32382dSLucas Stach } 1163cc32382dSLucas Stach 1164b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1165b4cdc8f6SHuang Shijie { 1166b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1167e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1168b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1169b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 11709d297239SNandor Han sport->rx_cookie = -EINVAL; 1171b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1172b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1173b4cdc8f6SHuang Shijie } 1174b4cdc8f6SHuang Shijie 1175b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1176e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1177b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1178b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1179b4cdc8f6SHuang Shijie } 1180b4cdc8f6SHuang Shijie } 1181b4cdc8f6SHuang Shijie 1182b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1183b4cdc8f6SHuang Shijie { 1184b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1185b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1186b4cdc8f6SHuang Shijie int ret; 1187b4cdc8f6SHuang Shijie 1188b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1189b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1190b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1191b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1192b4cdc8f6SHuang Shijie ret = -EINVAL; 1193b4cdc8f6SHuang Shijie goto err; 1194b4cdc8f6SHuang Shijie } 1195b4cdc8f6SHuang Shijie 1196b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1197b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1198b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1199184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1200184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1201b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1202b4cdc8f6SHuang Shijie if (ret) { 1203b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1204b4cdc8f6SHuang Shijie goto err; 1205b4cdc8f6SHuang Shijie } 1206b4cdc8f6SHuang Shijie 1207f654b23cSMartyn Welch sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1208b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1209b4cdc8f6SHuang Shijie ret = -ENOMEM; 1210b4cdc8f6SHuang Shijie goto err; 1211b4cdc8f6SHuang Shijie } 12129d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1213b4cdc8f6SHuang Shijie 1214b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1215b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1216b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1217b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1218b4cdc8f6SHuang Shijie ret = -EINVAL; 1219b4cdc8f6SHuang Shijie goto err; 1220b4cdc8f6SHuang Shijie } 1221b4cdc8f6SHuang Shijie 1222b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1223b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1224b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1225184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1226b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1227b4cdc8f6SHuang Shijie if (ret) { 1228b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1229b4cdc8f6SHuang Shijie goto err; 1230b4cdc8f6SHuang Shijie } 1231b4cdc8f6SHuang Shijie 1232b4cdc8f6SHuang Shijie return 0; 1233b4cdc8f6SHuang Shijie err: 1234b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1235b4cdc8f6SHuang Shijie return ret; 1236b4cdc8f6SHuang Shijie } 1237b4cdc8f6SHuang Shijie 1238b4cdc8f6SHuang Shijie static void imx_enable_dma(struct imx_port *sport) 1239b4cdc8f6SHuang Shijie { 12404444dcf1SUwe Kleine-König u32 ucr1; 1241b4cdc8f6SHuang Shijie 124202b0abd3SUwe Kleine-König imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 124302b0abd3SUwe Kleine-König 1244b4cdc8f6SHuang Shijie /* set UCR1 */ 12454444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12464444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 12474444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1248b4cdc8f6SHuang Shijie 1249b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1250b4cdc8f6SHuang Shijie } 1251b4cdc8f6SHuang Shijie 1252b4cdc8f6SHuang Shijie static void imx_disable_dma(struct imx_port *sport) 1253b4cdc8f6SHuang Shijie { 12544444dcf1SUwe Kleine-König u32 ucr1, ucr2; 1255b4cdc8f6SHuang Shijie 1256b4cdc8f6SHuang Shijie /* clear UCR1 */ 12574444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 12584444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 12594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1260b4cdc8f6SHuang Shijie 1261b4cdc8f6SHuang Shijie /* clear UCR2 */ 12624444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 12634444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN); 12644444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1265b4cdc8f6SHuang Shijie 1266184bd70bSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1267184bd70bSLucas Stach 1268b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1269b4cdc8f6SHuang Shijie } 1270b4cdc8f6SHuang Shijie 1271ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1272ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1273ab4382d2SGreg Kroah-Hartman 1274ab4382d2SGreg Kroah-Hartman static int imx_startup(struct uart_port *port) 1275ab4382d2SGreg Kroah-Hartman { 1276ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1277458e2c82SFabio Estevam int retval, i; 12784444dcf1SUwe Kleine-König unsigned long flags; 12794238c00bSUwe Kleine-König int dma_is_inited = 0; 12804444dcf1SUwe Kleine-König u32 ucr1, ucr2, ucr4; 1281ab4382d2SGreg Kroah-Hartman 128228eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 128328eb4274SHuang Shijie if (retval) 1284cb0f0a5fSFabio Estevam return retval; 128528eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 12860c375501SHuang Shijie if (retval) { 12870c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1288cb0f0a5fSFabio Estevam return retval; 12890c375501SHuang Shijie } 129028eb4274SHuang Shijie 1291cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1292ab4382d2SGreg Kroah-Hartman 1293ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1294ab4382d2SGreg Kroah-Hartman * requesting IRQs 1295ab4382d2SGreg Kroah-Hartman */ 12964444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1297ab4382d2SGreg Kroah-Hartman 1298ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 12994444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 13004444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1301ab4382d2SGreg Kroah-Hartman 13024444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1303ab4382d2SGreg Kroah-Hartman 13047e11577eSLucas Stach /* Can we enable the DMA support? */ 13054238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 13064238c00bSUwe Kleine-König dma_is_inited = 1; 13077e11577eSLucas Stach 130853794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1309772f8991SHuang Shijie /* Reset fifo's and state machines */ 1310458e2c82SFabio Estevam i = 100; 1311458e2c82SFabio Estevam 13124444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 13134444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 13144444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1315458e2c82SFabio Estevam 131627c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1317458e2c82SFabio Estevam udelay(1); 1318ab4382d2SGreg Kroah-Hartman 1319ab4382d2SGreg Kroah-Hartman /* 1320ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1321ab4382d2SGreg Kroah-Hartman */ 132227c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 132327c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1324ab4382d2SGreg Kroah-Hartman 132542afa627SUwe Kleine-König if (dma_is_inited) 13267e11577eSLucas Stach imx_enable_dma(sport); 13277e11577eSLucas Stach 13284444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 13291f043572STroy Kisky if (!sport->dma_is_enabled) 13304444dcf1SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 13314444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 13326376cd39SNandor Han if (sport->have_rtscts) 13334444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1334ab4382d2SGreg Kroah-Hartman 13354444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1336ab4382d2SGreg Kroah-Hartman 13374444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 13381f043572STroy Kisky if (!sport->dma_is_enabled) 13394444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 13404444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 13416f026d6bSJiada Wang 13424444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 13434444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1344bff09b09SLucas Stach if (!sport->have_rtscts) 13454444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 134616804d68SUwe Kleine-König /* 134716804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 134816804d68SUwe Kleine-König * we're using RTSD instead. 134916804d68SUwe Kleine-König */ 135016804d68SUwe Kleine-König if (!is_imx1_uart(sport)) 13514444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 13524444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1353ab4382d2SGreg Kroah-Hartman 1354a496e628SHuang Shijie if (!is_imx1_uart(sport)) { 13554444dcf1SUwe Kleine-König u32 ucr3; 135616804d68SUwe Kleine-König 13574444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 13584444dcf1SUwe Kleine-König 13594444dcf1SUwe Kleine-König ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 136016804d68SUwe Kleine-König 136116804d68SUwe Kleine-König if (sport->dte_mode) 1362e61c38d8SUwe Kleine-König /* disable broken interrupts */ 13634444dcf1SUwe Kleine-König ucr3 &= ~(UCR3_RI | UCR3_DCD); 136416804d68SUwe Kleine-König 13654444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 1366ab4382d2SGreg Kroah-Hartman } 1367ab4382d2SGreg Kroah-Hartman 1368ab4382d2SGreg Kroah-Hartman /* 1369ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1370ab4382d2SGreg Kroah-Hartman */ 1371ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 137218a42088SPeter Senna Tschudin 137318a42088SPeter Senna Tschudin /* 13744dec2f11SPeter Senna Tschudin * Start RX DMA immediately instead of waiting for RX FIFO interrupts. 13754dec2f11SPeter Senna Tschudin * In our iMX53 the average delay for the first reception dropped from 13764dec2f11SPeter Senna Tschudin * approximately 35000 microseconds to 1000 microseconds. 137718a42088SPeter Senna Tschudin */ 13781f043572STroy Kisky if (sport->dma_is_enabled) 137918a42088SPeter Senna Tschudin start_rx_dma(sport); 138018a42088SPeter Senna Tschudin 1381ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1382ab4382d2SGreg Kroah-Hartman 1383ab4382d2SGreg Kroah-Hartman return 0; 1384ab4382d2SGreg Kroah-Hartman } 1385ab4382d2SGreg Kroah-Hartman 1386ab4382d2SGreg Kroah-Hartman static void imx_shutdown(struct uart_port *port) 1387ab4382d2SGreg Kroah-Hartman { 1388ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 13899ec1882dSXinyu Chen unsigned long flags; 13904444dcf1SUwe Kleine-König u32 ucr1, ucr2; 1391ab4382d2SGreg Kroah-Hartman 1392b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1393a4688bcdSHuang Shijie sport->dma_is_rxing = 0; 1394a4688bcdSHuang Shijie sport->dma_is_txing = 0; 1395e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1396e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 13979d297239SNandor Han 139873631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1399a4688bcdSHuang Shijie imx_stop_tx(port); 1400b4cdc8f6SHuang Shijie imx_stop_rx(port); 1401b4cdc8f6SHuang Shijie imx_disable_dma(sport); 140273631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1403b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1404b4cdc8f6SHuang Shijie } 1405b4cdc8f6SHuang Shijie 140658362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 140758362d5bSUwe Kleine-König 14089ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14094444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14104444dcf1SUwe Kleine-König ucr2 &= ~UCR2_TXEN; 14114444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 14129ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1413ab4382d2SGreg Kroah-Hartman 1414ab4382d2SGreg Kroah-Hartman /* 1415ab4382d2SGreg Kroah-Hartman * Stop our timer. 1416ab4382d2SGreg Kroah-Hartman */ 1417ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1418ab4382d2SGreg Kroah-Hartman 1419ab4382d2SGreg Kroah-Hartman /* 1420ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1421ab4382d2SGreg Kroah-Hartman */ 1422ab4382d2SGreg Kroah-Hartman 14239ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 14244444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 14254444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1426ab4382d2SGreg Kroah-Hartman 14274444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14289ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 142928eb4274SHuang Shijie 143028eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 143128eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1432ab4382d2SGreg Kroah-Hartman } 1433ab4382d2SGreg Kroah-Hartman 14346aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 1435eb56b7edSHuang Shijie static void imx_flush_buffer(struct uart_port *port) 1436eb56b7edSHuang Shijie { 1437eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 143882e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 14394444dcf1SUwe Kleine-König u32 ucr2; 14404f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1441eb56b7edSHuang Shijie 144282e86ae9SDirk Behme if (!sport->dma_chan_tx) 144382e86ae9SDirk Behme return; 144482e86ae9SDirk Behme 1445eb56b7edSHuang Shijie sport->tx_bytes = 0; 1446eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 144782e86ae9SDirk Behme if (sport->dma_is_txing) { 14484444dcf1SUwe Kleine-König u32 ucr1; 14494444dcf1SUwe Kleine-König 145082e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 145182e86ae9SDirk Behme DMA_TO_DEVICE); 14524444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 14534444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 14544444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 14550f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1456eb56b7edSHuang Shijie } 1457934084a9SFabio Estevam 1458934084a9SFabio Estevam /* 1459934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1460263763c1SMartyn Welch * 1461934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1462934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1463263763c1SMartyn Welch * and UTS[6-3]". 1464263763c1SMartyn Welch * 1465263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1466263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1467263763c1SMartyn Welch * registers. 1468934084a9SFabio Estevam */ 146927c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 147027c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 147127c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1472934084a9SFabio Estevam 14734444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14744444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 14754444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1476934084a9SFabio Estevam 147727c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1478934084a9SFabio Estevam udelay(1); 1479934084a9SFabio Estevam 1480934084a9SFabio Estevam /* Restore the registers */ 148127c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 148227c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 148327c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1484eb56b7edSHuang Shijie } 1485eb56b7edSHuang Shijie 1486ab4382d2SGreg Kroah-Hartman static void 1487ab4382d2SGreg Kroah-Hartman imx_set_termios(struct uart_port *port, struct ktermios *termios, 1488ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1489ab4382d2SGreg Kroah-Hartman { 1490ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1491ab4382d2SGreg Kroah-Hartman unsigned long flags; 14924444dcf1SUwe Kleine-König u32 ucr2, old_ucr1, old_ucr2, ufcr; 149358362d5bSUwe Kleine-König unsigned int baud, quot; 1494ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 14954444dcf1SUwe Kleine-König unsigned long div; 1496ab4382d2SGreg Kroah-Hartman unsigned long num, denom; 1497ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1498ab4382d2SGreg Kroah-Hartman 1499ab4382d2SGreg Kroah-Hartman /* 1500ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1501ab4382d2SGreg Kroah-Hartman */ 1502ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1503ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1504ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1505ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1506ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1507ab4382d2SGreg Kroah-Hartman } 1508ab4382d2SGreg Kroah-Hartman 1509ab4382d2SGreg Kroah-Hartman if ((termios->c_cflag & CSIZE) == CS8) 1510ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1511ab4382d2SGreg Kroah-Hartman else 1512ab4382d2SGreg Kroah-Hartman ucr2 = UCR2_SRST | UCR2_IRTS; 1513ab4382d2SGreg Kroah-Hartman 1514ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CRTSCTS) { 1515ab4382d2SGreg Kroah-Hartman if (sport->have_rtscts) { 1516ab4382d2SGreg Kroah-Hartman ucr2 &= ~UCR2_IRTS; 151717b8f2a3SUwe Kleine-König 151812fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 151917b8f2a3SUwe Kleine-König /* 152017b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 152117b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 152217b8f2a3SUwe Kleine-König * disabled. 152317b8f2a3SUwe Kleine-König */ 152458362d5bSUwe Kleine-König if (port->rs485.flags & 152558362d5bSUwe Kleine-König SER_RS485_RTS_AFTER_SEND) 152658362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 15271a613626SFabio Estevam else 15281a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 152912fe59f9SFabio Estevam } else { 153058362d5bSUwe Kleine-König imx_port_rts_auto(sport, &ucr2); 153112fe59f9SFabio Estevam } 1532ab4382d2SGreg Kroah-Hartman } else { 1533ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CRTSCTS; 1534ab4382d2SGreg Kroah-Hartman } 153558362d5bSUwe Kleine-König } else if (port->rs485.flags & SER_RS485_ENABLED) { 153617b8f2a3SUwe Kleine-König /* disable transmitter */ 153758362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 153858362d5bSUwe Kleine-König imx_port_rts_active(sport, &ucr2); 15391a613626SFabio Estevam else 15401a613626SFabio Estevam imx_port_rts_inactive(sport, &ucr2); 154158362d5bSUwe Kleine-König } 154258362d5bSUwe Kleine-König 1543ab4382d2SGreg Kroah-Hartman 1544ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1545ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1546ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1547ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1548ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1549ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1550ab4382d2SGreg Kroah-Hartman } 1551ab4382d2SGreg Kroah-Hartman 1552995234daSEric Miao del_timer_sync(&sport->timer); 1553995234daSEric Miao 1554ab4382d2SGreg Kroah-Hartman /* 1555ab4382d2SGreg Kroah-Hartman * Ask the core to calculate the divisor for us. 1556ab4382d2SGreg Kroah-Hartman */ 1557ab4382d2SGreg Kroah-Hartman baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1558ab4382d2SGreg Kroah-Hartman quot = uart_get_divisor(port, baud); 1559ab4382d2SGreg Kroah-Hartman 1560ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1561ab4382d2SGreg Kroah-Hartman 1562ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1563ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1564ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1565ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1566ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1567ab4382d2SGreg Kroah-Hartman 1568ab4382d2SGreg Kroah-Hartman /* 1569ab4382d2SGreg Kroah-Hartman * Characters to ignore 1570ab4382d2SGreg Kroah-Hartman */ 1571ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1572ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1573865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1574ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1575ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1576ab4382d2SGreg Kroah-Hartman /* 1577ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1578ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1579ab4382d2SGreg Kroah-Hartman */ 1580ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1581ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1582ab4382d2SGreg Kroah-Hartman } 1583ab4382d2SGreg Kroah-Hartman 158455d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 158555d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 158655d8693aSJiada Wang 1587ab4382d2SGreg Kroah-Hartman /* 1588ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1589ab4382d2SGreg Kroah-Hartman */ 1590ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1591ab4382d2SGreg Kroah-Hartman 1592ab4382d2SGreg Kroah-Hartman /* 1593ab4382d2SGreg Kroah-Hartman * disable interrupts and drain transmitter 1594ab4382d2SGreg Kroah-Hartman */ 159527c84426SUwe Kleine-König old_ucr1 = imx_uart_readl(sport, UCR1); 159627c84426SUwe Kleine-König imx_uart_writel(sport, 159727c84426SUwe Kleine-König old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 159827c84426SUwe Kleine-König UCR1); 1599ab4382d2SGreg Kroah-Hartman 160027c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)) 1601ab4382d2SGreg Kroah-Hartman barrier(); 1602ab4382d2SGreg Kroah-Hartman 1603ab4382d2SGreg Kroah-Hartman /* then, disable everything */ 160427c84426SUwe Kleine-König old_ucr2 = imx_uart_readl(sport, UCR2); 160527c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN), UCR2); 160686a04ba6SLucas Stach old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN); 1607ab4382d2SGreg Kroah-Hartman 160809bd00f6SHubert Feurstein /* custom-baudrate handling */ 160909bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 161009bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 161109bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 161209bd00f6SHubert Feurstein 1613ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1614ab4382d2SGreg Kroah-Hartman if (div > 7) 1615ab4382d2SGreg Kroah-Hartman div = 7; 1616ab4382d2SGreg Kroah-Hartman if (!div) 1617ab4382d2SGreg Kroah-Hartman div = 1; 1618ab4382d2SGreg Kroah-Hartman 1619ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1620ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1621ab4382d2SGreg Kroah-Hartman 1622ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1623ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1624ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1625ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1626ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1627ab4382d2SGreg Kroah-Hartman 1628ab4382d2SGreg Kroah-Hartman num -= 1; 1629ab4382d2SGreg Kroah-Hartman denom -= 1; 1630ab4382d2SGreg Kroah-Hartman 163127c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1632ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 163327c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1634ab4382d2SGreg Kroah-Hartman 163527c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 163627c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1637ab4382d2SGreg Kroah-Hartman 1638a496e628SHuang Shijie if (!is_imx1_uart(sport)) 163927c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 164027c84426SUwe Kleine-König IMX21_ONEMS); 1641ab4382d2SGreg Kroah-Hartman 164227c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr1, UCR1); 1643ab4382d2SGreg Kroah-Hartman 1644ab4382d2SGreg Kroah-Hartman /* set the parity, stop bits and data size */ 164527c84426SUwe Kleine-König imx_uart_writel(sport, ucr2 | old_ucr2, UCR2); 1646ab4382d2SGreg Kroah-Hartman 1647ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1648ab4382d2SGreg Kroah-Hartman imx_enable_ms(&sport->port); 1649ab4382d2SGreg Kroah-Hartman 1650ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1651ab4382d2SGreg Kroah-Hartman } 1652ab4382d2SGreg Kroah-Hartman 1653ab4382d2SGreg Kroah-Hartman static const char *imx_type(struct uart_port *port) 1654ab4382d2SGreg Kroah-Hartman { 1655ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1656ab4382d2SGreg Kroah-Hartman 1657ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1658ab4382d2SGreg Kroah-Hartman } 1659ab4382d2SGreg Kroah-Hartman 1660ab4382d2SGreg Kroah-Hartman /* 1661ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1662ab4382d2SGreg Kroah-Hartman */ 1663ab4382d2SGreg Kroah-Hartman static void imx_config_port(struct uart_port *port, int flags) 1664ab4382d2SGreg Kroah-Hartman { 1665ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1666ab4382d2SGreg Kroah-Hartman 1667da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1668ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1669ab4382d2SGreg Kroah-Hartman } 1670ab4382d2SGreg Kroah-Hartman 1671ab4382d2SGreg Kroah-Hartman /* 1672ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1673ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1674ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1675ab4382d2SGreg Kroah-Hartman */ 1676ab4382d2SGreg Kroah-Hartman static int 1677ab4382d2SGreg Kroah-Hartman imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1678ab4382d2SGreg Kroah-Hartman { 1679ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1680ab4382d2SGreg Kroah-Hartman int ret = 0; 1681ab4382d2SGreg Kroah-Hartman 1682ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1683ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1684ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1685ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1686ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1687ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1688ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1689ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1690a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1691ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1692ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1693ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1694ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1695ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1696ab4382d2SGreg Kroah-Hartman return ret; 1697ab4382d2SGreg Kroah-Hartman } 1698ab4382d2SGreg Kroah-Hartman 169901f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 17006b8bdad9SDaniel Thompson 17016b8bdad9SDaniel Thompson static int imx_poll_init(struct uart_port *port) 17026b8bdad9SDaniel Thompson { 17036b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 17046b8bdad9SDaniel Thompson unsigned long flags; 17054444dcf1SUwe Kleine-König u32 ucr1, ucr2; 17066b8bdad9SDaniel Thompson int retval; 17076b8bdad9SDaniel Thompson 17086b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 17096b8bdad9SDaniel Thompson if (retval) 17106b8bdad9SDaniel Thompson return retval; 17116b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 17126b8bdad9SDaniel Thompson if (retval) 17136b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 17146b8bdad9SDaniel Thompson 1715cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 17166b8bdad9SDaniel Thompson 17176b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 17186b8bdad9SDaniel Thompson 17194444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 17206b8bdad9SDaniel Thompson if (is_imx1_uart(sport)) 17214444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 17224444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN | UCR1_RRDYEN; 17234444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 17244444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 17256b8bdad9SDaniel Thompson 17264444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 17274444dcf1SUwe Kleine-König ucr2 |= UCR2_RXEN; 17284444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 17296b8bdad9SDaniel Thompson 17306b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 17316b8bdad9SDaniel Thompson 17326b8bdad9SDaniel Thompson return 0; 17336b8bdad9SDaniel Thompson } 17346b8bdad9SDaniel Thompson 173501f56abdSSaleem Abdulrasool static int imx_poll_get_char(struct uart_port *port) 173601f56abdSSaleem Abdulrasool { 173727c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 173827c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 173926c47412SDirk Behme return NO_POLL_CHAR; 174001f56abdSSaleem Abdulrasool 174127c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 174201f56abdSSaleem Abdulrasool } 174301f56abdSSaleem Abdulrasool 174401f56abdSSaleem Abdulrasool static void imx_poll_put_char(struct uart_port *port, unsigned char c) 174501f56abdSSaleem Abdulrasool { 174627c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 174701f56abdSSaleem Abdulrasool unsigned int status; 174801f56abdSSaleem Abdulrasool 174901f56abdSSaleem Abdulrasool /* drain */ 175001f56abdSSaleem Abdulrasool do { 175127c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 175201f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 175301f56abdSSaleem Abdulrasool 175401f56abdSSaleem Abdulrasool /* write */ 175527c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 175601f56abdSSaleem Abdulrasool 175701f56abdSSaleem Abdulrasool /* flush */ 175801f56abdSSaleem Abdulrasool do { 175927c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 176001f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 176101f56abdSSaleem Abdulrasool } 176201f56abdSSaleem Abdulrasool #endif 176301f56abdSSaleem Abdulrasool 17646aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 176517b8f2a3SUwe Kleine-König static int imx_rs485_config(struct uart_port *port, 176617b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 176717b8f2a3SUwe Kleine-König { 176817b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 17694444dcf1SUwe Kleine-König u32 ucr2; 177017b8f2a3SUwe Kleine-König 177117b8f2a3SUwe Kleine-König /* unimplemented */ 177217b8f2a3SUwe Kleine-König rs485conf->delay_rts_before_send = 0; 177317b8f2a3SUwe Kleine-König rs485conf->delay_rts_after_send = 0; 177417b8f2a3SUwe Kleine-König 177517b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 17767b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 177717b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 177817b8f2a3SUwe Kleine-König 177917b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 178017b8f2a3SUwe Kleine-König /* disable transmitter */ 17814444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 178217b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 17834444dcf1SUwe Kleine-König imx_port_rts_active(sport, &ucr2); 17841a613626SFabio Estevam else 17854444dcf1SUwe Kleine-König imx_port_rts_inactive(sport, &ucr2); 17864444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 178717b8f2a3SUwe Kleine-König } 178817b8f2a3SUwe Kleine-König 17897d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 17907d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 17917d1cadcaSBaruch Siach rs485conf->flags & SER_RS485_RX_DURING_TX) { 17924444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 17934444dcf1SUwe Kleine-König ucr2 |= UCR2_RXEN; 17944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 17957d1cadcaSBaruch Siach } 17967d1cadcaSBaruch Siach 179717b8f2a3SUwe Kleine-König port->rs485 = *rs485conf; 179817b8f2a3SUwe Kleine-König 179917b8f2a3SUwe Kleine-König return 0; 180017b8f2a3SUwe Kleine-König } 180117b8f2a3SUwe Kleine-König 1802069a47e5SJulia Lawall static const struct uart_ops imx_pops = { 1803ab4382d2SGreg Kroah-Hartman .tx_empty = imx_tx_empty, 1804ab4382d2SGreg Kroah-Hartman .set_mctrl = imx_set_mctrl, 1805ab4382d2SGreg Kroah-Hartman .get_mctrl = imx_get_mctrl, 1806ab4382d2SGreg Kroah-Hartman .stop_tx = imx_stop_tx, 1807ab4382d2SGreg Kroah-Hartman .start_tx = imx_start_tx, 1808ab4382d2SGreg Kroah-Hartman .stop_rx = imx_stop_rx, 1809ab4382d2SGreg Kroah-Hartman .enable_ms = imx_enable_ms, 1810ab4382d2SGreg Kroah-Hartman .break_ctl = imx_break_ctl, 1811ab4382d2SGreg Kroah-Hartman .startup = imx_startup, 1812ab4382d2SGreg Kroah-Hartman .shutdown = imx_shutdown, 1813eb56b7edSHuang Shijie .flush_buffer = imx_flush_buffer, 1814ab4382d2SGreg Kroah-Hartman .set_termios = imx_set_termios, 1815ab4382d2SGreg Kroah-Hartman .type = imx_type, 1816ab4382d2SGreg Kroah-Hartman .config_port = imx_config_port, 1817ab4382d2SGreg Kroah-Hartman .verify_port = imx_verify_port, 181801f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18196b8bdad9SDaniel Thompson .poll_init = imx_poll_init, 182001f56abdSSaleem Abdulrasool .poll_get_char = imx_poll_get_char, 182101f56abdSSaleem Abdulrasool .poll_put_char = imx_poll_put_char, 182201f56abdSSaleem Abdulrasool #endif 1823ab4382d2SGreg Kroah-Hartman }; 1824ab4382d2SGreg Kroah-Hartman 1825ab4382d2SGreg Kroah-Hartman static struct imx_port *imx_ports[UART_NR]; 1826ab4382d2SGreg Kroah-Hartman 1827ab4382d2SGreg Kroah-Hartman #ifdef CONFIG_SERIAL_IMX_CONSOLE 1828ab4382d2SGreg Kroah-Hartman static void imx_console_putchar(struct uart_port *port, int ch) 1829ab4382d2SGreg Kroah-Hartman { 1830ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1831ab4382d2SGreg Kroah-Hartman 183227c84426SUwe Kleine-König while (imx_uart_readl(sport, uts_reg(sport)) & UTS_TXFULL) 1833ab4382d2SGreg Kroah-Hartman barrier(); 1834ab4382d2SGreg Kroah-Hartman 183527c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1836ab4382d2SGreg Kroah-Hartman } 1837ab4382d2SGreg Kroah-Hartman 1838ab4382d2SGreg Kroah-Hartman /* 1839ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1840ab4382d2SGreg Kroah-Hartman */ 1841ab4382d2SGreg Kroah-Hartman static void 1842ab4382d2SGreg Kroah-Hartman imx_console_write(struct console *co, const char *s, unsigned int count) 1843ab4382d2SGreg Kroah-Hartman { 1844ab4382d2SGreg Kroah-Hartman struct imx_port *sport = imx_ports[co->index]; 18450ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 18460ad5a814SDirk Behme unsigned int ucr1; 1847f30e8260SShawn Guo unsigned long flags = 0; 1848677fe555SThomas Gleixner int locked = 1; 18491cf93e0dSHuang Shijie int retval; 18501cf93e0dSHuang Shijie 18510c727a42SFabio Estevam retval = clk_enable(sport->clk_per); 18521cf93e0dSHuang Shijie if (retval) 18531cf93e0dSHuang Shijie return; 18540c727a42SFabio Estevam retval = clk_enable(sport->clk_ipg); 18551cf93e0dSHuang Shijie if (retval) { 18560c727a42SFabio Estevam clk_disable(sport->clk_per); 18571cf93e0dSHuang Shijie return; 18581cf93e0dSHuang Shijie } 18599ec1882dSXinyu Chen 1860677fe555SThomas Gleixner if (sport->port.sysrq) 1861677fe555SThomas Gleixner locked = 0; 1862677fe555SThomas Gleixner else if (oops_in_progress) 1863677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1864677fe555SThomas Gleixner else 18659ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1866ab4382d2SGreg Kroah-Hartman 1867ab4382d2SGreg Kroah-Hartman /* 18680ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 1869ab4382d2SGreg Kroah-Hartman */ 187027c84426SUwe Kleine-König imx_port_ucrs_save(sport, &old_ucr); 18710ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 1872ab4382d2SGreg Kroah-Hartman 1873fe6b540aSShawn Guo if (is_imx1_uart(sport)) 1874fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 1875ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 1876ab4382d2SGreg Kroah-Hartman ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1877ab4382d2SGreg Kroah-Hartman 187827c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1879ab4382d2SGreg Kroah-Hartman 188027c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1881ab4382d2SGreg Kroah-Hartman 1882ab4382d2SGreg Kroah-Hartman uart_console_write(&sport->port, s, count, imx_console_putchar); 1883ab4382d2SGreg Kroah-Hartman 1884ab4382d2SGreg Kroah-Hartman /* 1885ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 18860ad5a814SDirk Behme * and restore UCR1/2/3 1887ab4382d2SGreg Kroah-Hartman */ 188827c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1889ab4382d2SGreg Kroah-Hartman 189027c84426SUwe Kleine-König imx_port_ucrs_restore(sport, &old_ucr); 18919ec1882dSXinyu Chen 1892677fe555SThomas Gleixner if (locked) 18939ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 18941cf93e0dSHuang Shijie 18950c727a42SFabio Estevam clk_disable(sport->clk_ipg); 18960c727a42SFabio Estevam clk_disable(sport->clk_per); 1897ab4382d2SGreg Kroah-Hartman } 1898ab4382d2SGreg Kroah-Hartman 1899ab4382d2SGreg Kroah-Hartman /* 1900ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 1901ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 1902ab4382d2SGreg Kroah-Hartman */ 1903ab4382d2SGreg Kroah-Hartman static void __init 1904ab4382d2SGreg Kroah-Hartman imx_console_get_options(struct imx_port *sport, int *baud, 1905ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 1906ab4382d2SGreg Kroah-Hartman { 1907ab4382d2SGreg Kroah-Hartman 190827c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1909ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 1910ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 1911ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 1912ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 1913ab4382d2SGreg Kroah-Hartman 191427c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 1915ab4382d2SGreg Kroah-Hartman 1916ab4382d2SGreg Kroah-Hartman *parity = 'n'; 1917ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 1918ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 1919ab4382d2SGreg Kroah-Hartman *parity = 'o'; 1920ab4382d2SGreg Kroah-Hartman else 1921ab4382d2SGreg Kroah-Hartman *parity = 'e'; 1922ab4382d2SGreg Kroah-Hartman } 1923ab4382d2SGreg Kroah-Hartman 1924ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 1925ab4382d2SGreg Kroah-Hartman *bits = 8; 1926ab4382d2SGreg Kroah-Hartman else 1927ab4382d2SGreg Kroah-Hartman *bits = 7; 1928ab4382d2SGreg Kroah-Hartman 192927c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 193027c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 1931ab4382d2SGreg Kroah-Hartman 193227c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 1933ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 1934ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 1935ab4382d2SGreg Kroah-Hartman else 1936ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 1937ab4382d2SGreg Kroah-Hartman 19383a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 1939ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 1940ab4382d2SGreg Kroah-Hartman 1941ab4382d2SGreg Kroah-Hartman { /* 1942ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 1943ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1944ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 1945ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 1946ab4382d2SGreg Kroah-Hartman */ 1947ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 1948ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 1949ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 1950ab4382d2SGreg Kroah-Hartman 1951ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 1952ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 1953ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 1954ab4382d2SGreg Kroah-Hartman } 1955ab4382d2SGreg Kroah-Hartman 1956ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 195750bbdba3SSachin Kamat pr_info("Console IMX rounded baud rate from %d to %d\n", 1958ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 1959ab4382d2SGreg Kroah-Hartman } 1960ab4382d2SGreg Kroah-Hartman } 1961ab4382d2SGreg Kroah-Hartman 1962ab4382d2SGreg Kroah-Hartman static int __init 1963ab4382d2SGreg Kroah-Hartman imx_console_setup(struct console *co, char *options) 1964ab4382d2SGreg Kroah-Hartman { 1965ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 1966ab4382d2SGreg Kroah-Hartman int baud = 9600; 1967ab4382d2SGreg Kroah-Hartman int bits = 8; 1968ab4382d2SGreg Kroah-Hartman int parity = 'n'; 1969ab4382d2SGreg Kroah-Hartman int flow = 'n'; 19701cf93e0dSHuang Shijie int retval; 1971ab4382d2SGreg Kroah-Hartman 1972ab4382d2SGreg Kroah-Hartman /* 1973ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 1974ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 1975ab4382d2SGreg Kroah-Hartman * console support. 1976ab4382d2SGreg Kroah-Hartman */ 1977ab4382d2SGreg Kroah-Hartman if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1978ab4382d2SGreg Kroah-Hartman co->index = 0; 1979ab4382d2SGreg Kroah-Hartman sport = imx_ports[co->index]; 1980ab4382d2SGreg Kroah-Hartman if (sport == NULL) 1981ab4382d2SGreg Kroah-Hartman return -ENODEV; 1982ab4382d2SGreg Kroah-Hartman 19831cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 19841cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 19851cf93e0dSHuang Shijie if (retval) 19861cf93e0dSHuang Shijie goto error_console; 19871cf93e0dSHuang Shijie 1988ab4382d2SGreg Kroah-Hartman if (options) 1989ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 1990ab4382d2SGreg Kroah-Hartman else 1991ab4382d2SGreg Kroah-Hartman imx_console_get_options(sport, &baud, &parity, &bits); 1992ab4382d2SGreg Kroah-Hartman 1993cc32382dSLucas Stach imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1994ab4382d2SGreg Kroah-Hartman 19951cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 19961cf93e0dSHuang Shijie 19970c727a42SFabio Estevam clk_disable(sport->clk_ipg); 19980c727a42SFabio Estevam if (retval) { 19990c727a42SFabio Estevam clk_unprepare(sport->clk_ipg); 20000c727a42SFabio Estevam goto error_console; 20010c727a42SFabio Estevam } 20020c727a42SFabio Estevam 20030c727a42SFabio Estevam retval = clk_prepare(sport->clk_per); 20040c727a42SFabio Estevam if (retval) 20051cf93e0dSHuang Shijie clk_disable_unprepare(sport->clk_ipg); 20061cf93e0dSHuang Shijie 20071cf93e0dSHuang Shijie error_console: 20081cf93e0dSHuang Shijie return retval; 2009ab4382d2SGreg Kroah-Hartman } 2010ab4382d2SGreg Kroah-Hartman 2011ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg; 2012ab4382d2SGreg Kroah-Hartman static struct console imx_console = { 2013ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 2014ab4382d2SGreg Kroah-Hartman .write = imx_console_write, 2015ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 2016ab4382d2SGreg Kroah-Hartman .setup = imx_console_setup, 2017ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2018ab4382d2SGreg Kroah-Hartman .index = -1, 2019ab4382d2SGreg Kroah-Hartman .data = &imx_reg, 2020ab4382d2SGreg Kroah-Hartman }; 2021ab4382d2SGreg Kroah-Hartman 2022ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE &imx_console 2023913c6c0eSLucas Stach 2024913c6c0eSLucas Stach #ifdef CONFIG_OF 2025913c6c0eSLucas Stach static void imx_console_early_putchar(struct uart_port *port, int ch) 2026913c6c0eSLucas Stach { 202727c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 202827c84426SUwe Kleine-König 202927c84426SUwe Kleine-König while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2030913c6c0eSLucas Stach cpu_relax(); 2031913c6c0eSLucas Stach 203227c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 2033913c6c0eSLucas Stach } 2034913c6c0eSLucas Stach 2035913c6c0eSLucas Stach static void imx_console_early_write(struct console *con, const char *s, 2036913c6c0eSLucas Stach unsigned count) 2037913c6c0eSLucas Stach { 2038913c6c0eSLucas Stach struct earlycon_device *dev = con->data; 2039913c6c0eSLucas Stach 2040913c6c0eSLucas Stach uart_console_write(&dev->port, s, count, imx_console_early_putchar); 2041913c6c0eSLucas Stach } 2042913c6c0eSLucas Stach 2043913c6c0eSLucas Stach static int __init 2044913c6c0eSLucas Stach imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2045913c6c0eSLucas Stach { 2046913c6c0eSLucas Stach if (!dev->port.membase) 2047913c6c0eSLucas Stach return -ENODEV; 2048913c6c0eSLucas Stach 2049913c6c0eSLucas Stach dev->con->write = imx_console_early_write; 2050913c6c0eSLucas Stach 2051913c6c0eSLucas Stach return 0; 2052913c6c0eSLucas Stach } 2053913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2054913c6c0eSLucas Stach OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2055913c6c0eSLucas Stach #endif 2056913c6c0eSLucas Stach 2057ab4382d2SGreg Kroah-Hartman #else 2058ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2059ab4382d2SGreg Kroah-Hartman #endif 2060ab4382d2SGreg Kroah-Hartman 2061ab4382d2SGreg Kroah-Hartman static struct uart_driver imx_reg = { 2062ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2063ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2064ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2065ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2066ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 2067ab4382d2SGreg Kroah-Hartman .nr = ARRAY_SIZE(imx_ports), 2068ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2069ab4382d2SGreg Kroah-Hartman }; 2070ab4382d2SGreg Kroah-Hartman 207122698aa2SShawn Guo #ifdef CONFIG_OF 207220bb8095SUwe Kleine-König /* 207320bb8095SUwe Kleine-König * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 207420bb8095SUwe Kleine-König * could successfully get all information from dt or a negative errno. 207520bb8095SUwe Kleine-König */ 207622698aa2SShawn Guo static int serial_imx_probe_dt(struct imx_port *sport, 207722698aa2SShawn Guo struct platform_device *pdev) 207822698aa2SShawn Guo { 207922698aa2SShawn Guo struct device_node *np = pdev->dev.of_node; 2080ff05967aSShawn Guo int ret; 208122698aa2SShawn Guo 20825f8b9043SLABBE Corentin sport->devdata = of_device_get_match_data(&pdev->dev); 20835f8b9043SLABBE Corentin if (!sport->devdata) 208420bb8095SUwe Kleine-König /* no device tree device */ 208520bb8095SUwe Kleine-König return 1; 208622698aa2SShawn Guo 2087ff05967aSShawn Guo ret = of_alias_get_id(np, "serial"); 2088ff05967aSShawn Guo if (ret < 0) { 2089ff05967aSShawn Guo dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2090a197a191SUwe Kleine-König return ret; 2091ff05967aSShawn Guo } 2092ff05967aSShawn Guo sport->port.line = ret; 209322698aa2SShawn Guo 20941006ed7eSGeert Uytterhoeven if (of_get_property(np, "uart-has-rtscts", NULL) || 20951006ed7eSGeert Uytterhoeven of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 209622698aa2SShawn Guo sport->have_rtscts = 1; 209722698aa2SShawn Guo 209820ff2fe6SHuang Shijie if (of_get_property(np, "fsl,dte-mode", NULL)) 209920ff2fe6SHuang Shijie sport->dte_mode = 1; 210020ff2fe6SHuang Shijie 21017b7e8e8eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 21027b7e8e8eSFabio Estevam sport->have_rtsgpio = 1; 21037b7e8e8eSFabio Estevam 210422698aa2SShawn Guo return 0; 210522698aa2SShawn Guo } 210622698aa2SShawn Guo #else 210722698aa2SShawn Guo static inline int serial_imx_probe_dt(struct imx_port *sport, 210822698aa2SShawn Guo struct platform_device *pdev) 210922698aa2SShawn Guo { 211020bb8095SUwe Kleine-König return 1; 211122698aa2SShawn Guo } 211222698aa2SShawn Guo #endif 211322698aa2SShawn Guo 211422698aa2SShawn Guo static void serial_imx_probe_pdata(struct imx_port *sport, 211522698aa2SShawn Guo struct platform_device *pdev) 211622698aa2SShawn Guo { 2117574de559SJingoo Han struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 211822698aa2SShawn Guo 211922698aa2SShawn Guo sport->port.line = pdev->id; 212022698aa2SShawn Guo sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 212122698aa2SShawn Guo 212222698aa2SShawn Guo if (!pdata) 212322698aa2SShawn Guo return; 212422698aa2SShawn Guo 212522698aa2SShawn Guo if (pdata->flags & IMXUART_HAVE_RTSCTS) 212622698aa2SShawn Guo sport->have_rtscts = 1; 212722698aa2SShawn Guo } 212822698aa2SShawn Guo 2129ab4382d2SGreg Kroah-Hartman static int serial_imx_probe(struct platform_device *pdev) 2130ab4382d2SGreg Kroah-Hartman { 2131ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2132ab4382d2SGreg Kroah-Hartman void __iomem *base; 21334444dcf1SUwe Kleine-König int ret = 0; 21344444dcf1SUwe Kleine-König u32 ucr1; 2135ab4382d2SGreg Kroah-Hartman struct resource *res; 2136842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2137ab4382d2SGreg Kroah-Hartman 213842d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2139ab4382d2SGreg Kroah-Hartman if (!sport) 2140ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2141ab4382d2SGreg Kroah-Hartman 214222698aa2SShawn Guo ret = serial_imx_probe_dt(sport, pdev); 214320bb8095SUwe Kleine-König if (ret > 0) 214422698aa2SShawn Guo serial_imx_probe_pdata(sport, pdev); 214520bb8095SUwe Kleine-König else if (ret < 0) 214642d34191SSachin Kamat return ret; 214722698aa2SShawn Guo 214856734448SGeert Uytterhoeven if (sport->port.line >= ARRAY_SIZE(imx_ports)) { 214956734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 215056734448SGeert Uytterhoeven sport->port.line); 215156734448SGeert Uytterhoeven return -EINVAL; 215256734448SGeert Uytterhoeven } 215356734448SGeert Uytterhoeven 2154ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2155da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2156da82f997SAlexander Shiyan if (IS_ERR(base)) 2157da82f997SAlexander Shiyan return PTR_ERR(base); 2158ab4382d2SGreg Kroah-Hartman 2159842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2160842633bdSUwe Kleine-König txirq = platform_get_irq(pdev, 1); 2161842633bdSUwe Kleine-König rtsirq = platform_get_irq(pdev, 2); 2162842633bdSUwe Kleine-König 2163ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2164ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2165ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 2166ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX, 2167ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2168842633bdSUwe Kleine-König sport->port.irq = rxirq; 2169ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2170ab4382d2SGreg Kroah-Hartman sport->port.ops = &imx_pops; 217117b8f2a3SUwe Kleine-König sport->port.rs485_config = imx_rs485_config; 2172ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 2173e99e88a9SKees Cook timer_setup(&sport->timer, imx_timeout, 0); 2174ab4382d2SGreg Kroah-Hartman 217558362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 217658362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 217758362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 217858362d5bSUwe Kleine-König 21793a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 21803a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 21813a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2182833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 218342d34191SSachin Kamat return ret; 2184ab4382d2SGreg Kroah-Hartman } 2185ab4382d2SGreg Kroah-Hartman 21863a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 21873a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 21883a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2189833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 219042d34191SSachin Kamat return ret; 21913a9465faSSascha Hauer } 21923a9465faSSascha Hauer 21933a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2194ab4382d2SGreg Kroah-Hartman 21958a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 21968a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 21971e512d45SUwe Kleine-König if (ret) { 21981e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 21998a61f0c7SFabio Estevam return ret; 22001e512d45SUwe Kleine-König } 22018a61f0c7SFabio Estevam 22023a0ab62fSUwe Kleine-König /* initialize shadow register values */ 22033a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 22043a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 22053a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 22063a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 22073a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 22083a0ab62fSUwe Kleine-König 2209743f93f8SLukas Wunner uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2210743f93f8SLukas Wunner 2211b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 2212b8f3bff0SLukas Wunner (!sport->have_rtscts || !sport->have_rtsgpio)) 2213b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2214b8f3bff0SLukas Wunner 2215b8f3bff0SLukas Wunner imx_rs485_config(&sport->port, &sport->port.rs485); 2216b8f3bff0SLukas Wunner 22178a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 22184444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 22194444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 22208a61f0c7SFabio Estevam UCR1_TXMPTYEN | UCR1_RTSDEN); 22214444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 22228a61f0c7SFabio Estevam 2223e61c38d8SUwe Kleine-König if (!is_imx1_uart(sport) && sport->dte_mode) { 2224e61c38d8SUwe Kleine-König /* 2225e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2226e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2227e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2228e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2229e61c38d8SUwe Kleine-König */ 22304444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 22314444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 22324444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2233e61c38d8SUwe Kleine-König 2234e61c38d8SUwe Kleine-König /* 2235e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2236e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2237e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2238e61c38d8SUwe Kleine-König */ 223927c84426SUwe Kleine-König imx_uart_writel(sport, 224027c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 224127c84426SUwe Kleine-König UCR3); 2242e61c38d8SUwe Kleine-König 2243e61c38d8SUwe Kleine-König } else { 22444444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 22454444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 22464444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 22474444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 22486df765dcSUwe Kleine-König 22496df765dcSUwe Kleine-König if (!is_imx1_uart(sport)) 22506df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 225127c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2252e61c38d8SUwe Kleine-König } 2253e61c38d8SUwe Kleine-König 22548a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 22558a61f0c7SFabio Estevam 2256c0d1c6b0SFabio Estevam /* 2257c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2258c0d1c6b0SFabio Estevam * chips only have one interrupt. 2259c0d1c6b0SFabio Estevam */ 2260842633bdSUwe Kleine-König if (txirq > 0) { 2261842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 2262c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 22631e512d45SUwe Kleine-König if (ret) { 22641e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 22651e512d45SUwe Kleine-König ret); 2266c0d1c6b0SFabio Estevam return ret; 22671e512d45SUwe Kleine-König } 2268c0d1c6b0SFabio Estevam 2269842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 2270c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 22711e512d45SUwe Kleine-König if (ret) { 22721e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 22731e512d45SUwe Kleine-König ret); 2274c0d1c6b0SFabio Estevam return ret; 22751e512d45SUwe Kleine-König } 2276c0d1c6b0SFabio Estevam } else { 2277842633bdSUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 2278c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 22791e512d45SUwe Kleine-König if (ret) { 22801e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2281c0d1c6b0SFabio Estevam return ret; 2282c0d1c6b0SFabio Estevam } 22831e512d45SUwe Kleine-König } 2284c0d1c6b0SFabio Estevam 228522698aa2SShawn Guo imx_ports[sport->port.line] = sport; 2286ab4382d2SGreg Kroah-Hartman 22870a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2288ab4382d2SGreg Kroah-Hartman 228945af780aSAlexander Shiyan return uart_add_one_port(&imx_reg, &sport->port); 2290ab4382d2SGreg Kroah-Hartman } 2291ab4382d2SGreg Kroah-Hartman 2292ab4382d2SGreg Kroah-Hartman static int serial_imx_remove(struct platform_device *pdev) 2293ab4382d2SGreg Kroah-Hartman { 2294ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2295ab4382d2SGreg Kroah-Hartman 229645af780aSAlexander Shiyan return uart_remove_one_port(&imx_reg, &sport->port); 2297ab4382d2SGreg Kroah-Hartman } 2298ab4382d2SGreg Kroah-Hartman 2299c868cbb7SEduardo Valentin static void serial_imx_restore_context(struct imx_port *sport) 2300c868cbb7SEduardo Valentin { 2301c868cbb7SEduardo Valentin if (!sport->context_saved) 2302c868cbb7SEduardo Valentin return; 2303c868cbb7SEduardo Valentin 230427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 230527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 230627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 230727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 230827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 230927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 231027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 231127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 231227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 231327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2314c868cbb7SEduardo Valentin sport->context_saved = false; 2315c868cbb7SEduardo Valentin } 2316c868cbb7SEduardo Valentin 2317c868cbb7SEduardo Valentin static void serial_imx_save_context(struct imx_port *sport) 2318c868cbb7SEduardo Valentin { 2319c868cbb7SEduardo Valentin /* Save necessary regs */ 232027c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 232127c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 232227c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 232327c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 232427c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 232527c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 232627c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 232727c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 232827c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 232927c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2330c868cbb7SEduardo Valentin sport->context_saved = true; 2331c868cbb7SEduardo Valentin } 2332c868cbb7SEduardo Valentin 2333189550b8SEduardo Valentin static void serial_imx_enable_wakeup(struct imx_port *sport, bool on) 2334189550b8SEduardo Valentin { 23354444dcf1SUwe Kleine-König u32 ucr3; 2336189550b8SEduardo Valentin 23374444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 233809df0b34SMartin Kaiser if (on) { 233927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 23404444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 23414444dcf1SUwe Kleine-König } else { 23424444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 234309df0b34SMartin Kaiser } 23444444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2345bc85734bSEduardo Valentin 234638b1f0fbSFabio Estevam if (sport->have_rtscts) { 23474444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2348bc85734bSEduardo Valentin if (on) 23494444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2350bc85734bSEduardo Valentin else 23514444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 23524444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2353189550b8SEduardo Valentin } 235438b1f0fbSFabio Estevam } 2355189550b8SEduardo Valentin 235690bb6bd3SShenwei Wang static int imx_serial_port_suspend_noirq(struct device *dev) 235790bb6bd3SShenwei Wang { 235890bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 235990bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 236090bb6bd3SShenwei Wang 2361c868cbb7SEduardo Valentin serial_imx_save_context(sport); 236290bb6bd3SShenwei Wang 236390bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 236490bb6bd3SShenwei Wang 236590bb6bd3SShenwei Wang return 0; 236690bb6bd3SShenwei Wang } 236790bb6bd3SShenwei Wang 236890bb6bd3SShenwei Wang static int imx_serial_port_resume_noirq(struct device *dev) 236990bb6bd3SShenwei Wang { 237090bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 237190bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 237290bb6bd3SShenwei Wang int ret; 237390bb6bd3SShenwei Wang 237490bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 237590bb6bd3SShenwei Wang if (ret) 237690bb6bd3SShenwei Wang return ret; 237790bb6bd3SShenwei Wang 2378c868cbb7SEduardo Valentin serial_imx_restore_context(sport); 237990bb6bd3SShenwei Wang 238090bb6bd3SShenwei Wang return 0; 238190bb6bd3SShenwei Wang } 238290bb6bd3SShenwei Wang 238390bb6bd3SShenwei Wang static int imx_serial_port_suspend(struct device *dev) 238490bb6bd3SShenwei Wang { 238590bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 238690bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 238709df0b34SMartin Kaiser int ret; 238890bb6bd3SShenwei Wang 238990bb6bd3SShenwei Wang uart_suspend_port(&imx_reg, &sport->port); 239081b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 239190bb6bd3SShenwei Wang 239209df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 239309df0b34SMartin Kaiser if (ret) 239409df0b34SMartin Kaiser return ret; 239509df0b34SMartin Kaiser 239609df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 239709df0b34SMartin Kaiser serial_imx_enable_wakeup(sport, true); 239809df0b34SMartin Kaiser 239909df0b34SMartin Kaiser return 0; 240090bb6bd3SShenwei Wang } 240190bb6bd3SShenwei Wang 240290bb6bd3SShenwei Wang static int imx_serial_port_resume(struct device *dev) 240390bb6bd3SShenwei Wang { 240490bb6bd3SShenwei Wang struct platform_device *pdev = to_platform_device(dev); 240590bb6bd3SShenwei Wang struct imx_port *sport = platform_get_drvdata(pdev); 240690bb6bd3SShenwei Wang 240790bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 2408189550b8SEduardo Valentin serial_imx_enable_wakeup(sport, false); 240990bb6bd3SShenwei Wang 241090bb6bd3SShenwei Wang uart_resume_port(&imx_reg, &sport->port); 241181b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 241290bb6bd3SShenwei Wang 241309df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 241429add68dSMartin Fuzzey 241590bb6bd3SShenwei Wang return 0; 241690bb6bd3SShenwei Wang } 241790bb6bd3SShenwei Wang 241894be6d74SPhilipp Zabel static int imx_serial_port_freeze(struct device *dev) 241994be6d74SPhilipp Zabel { 242094be6d74SPhilipp Zabel struct platform_device *pdev = to_platform_device(dev); 242194be6d74SPhilipp Zabel struct imx_port *sport = platform_get_drvdata(pdev); 242294be6d74SPhilipp Zabel 242394be6d74SPhilipp Zabel uart_suspend_port(&imx_reg, &sport->port); 242494be6d74SPhilipp Zabel 242509df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 242694be6d74SPhilipp Zabel } 242794be6d74SPhilipp Zabel 242894be6d74SPhilipp Zabel static int imx_serial_port_thaw(struct device *dev) 242994be6d74SPhilipp Zabel { 243094be6d74SPhilipp Zabel struct platform_device *pdev = to_platform_device(dev); 243194be6d74SPhilipp Zabel struct imx_port *sport = platform_get_drvdata(pdev); 243294be6d74SPhilipp Zabel 243394be6d74SPhilipp Zabel uart_resume_port(&imx_reg, &sport->port); 243494be6d74SPhilipp Zabel 243509df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 243694be6d74SPhilipp Zabel 243794be6d74SPhilipp Zabel return 0; 243894be6d74SPhilipp Zabel } 243994be6d74SPhilipp Zabel 244090bb6bd3SShenwei Wang static const struct dev_pm_ops imx_serial_port_pm_ops = { 244190bb6bd3SShenwei Wang .suspend_noirq = imx_serial_port_suspend_noirq, 244290bb6bd3SShenwei Wang .resume_noirq = imx_serial_port_resume_noirq, 244394be6d74SPhilipp Zabel .freeze_noirq = imx_serial_port_suspend_noirq, 244494be6d74SPhilipp Zabel .restore_noirq = imx_serial_port_resume_noirq, 244590bb6bd3SShenwei Wang .suspend = imx_serial_port_suspend, 244690bb6bd3SShenwei Wang .resume = imx_serial_port_resume, 244794be6d74SPhilipp Zabel .freeze = imx_serial_port_freeze, 244894be6d74SPhilipp Zabel .thaw = imx_serial_port_thaw, 244994be6d74SPhilipp Zabel .restore = imx_serial_port_thaw, 245090bb6bd3SShenwei Wang }; 245190bb6bd3SShenwei Wang 2452ab4382d2SGreg Kroah-Hartman static struct platform_driver serial_imx_driver = { 2453ab4382d2SGreg Kroah-Hartman .probe = serial_imx_probe, 2454ab4382d2SGreg Kroah-Hartman .remove = serial_imx_remove, 2455ab4382d2SGreg Kroah-Hartman 2456fe6b540aSShawn Guo .id_table = imx_uart_devtype, 2457ab4382d2SGreg Kroah-Hartman .driver = { 2458ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 245922698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 246090bb6bd3SShenwei Wang .pm = &imx_serial_port_pm_ops, 2461ab4382d2SGreg Kroah-Hartman }, 2462ab4382d2SGreg Kroah-Hartman }; 2463ab4382d2SGreg Kroah-Hartman 2464ab4382d2SGreg Kroah-Hartman static int __init imx_serial_init(void) 2465ab4382d2SGreg Kroah-Hartman { 2466f0fd1b73SFabio Estevam int ret = uart_register_driver(&imx_reg); 2467ab4382d2SGreg Kroah-Hartman 2468ab4382d2SGreg Kroah-Hartman if (ret) 2469ab4382d2SGreg Kroah-Hartman return ret; 2470ab4382d2SGreg Kroah-Hartman 2471ab4382d2SGreg Kroah-Hartman ret = platform_driver_register(&serial_imx_driver); 2472ab4382d2SGreg Kroah-Hartman if (ret != 0) 2473ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2474ab4382d2SGreg Kroah-Hartman 2475f227824eSUwe Kleine-König return ret; 2476ab4382d2SGreg Kroah-Hartman } 2477ab4382d2SGreg Kroah-Hartman 2478ab4382d2SGreg Kroah-Hartman static void __exit imx_serial_exit(void) 2479ab4382d2SGreg Kroah-Hartman { 2480ab4382d2SGreg Kroah-Hartman platform_driver_unregister(&serial_imx_driver); 2481ab4382d2SGreg Kroah-Hartman uart_unregister_driver(&imx_reg); 2482ab4382d2SGreg Kroah-Hartman } 2483ab4382d2SGreg Kroah-Hartman 2484ab4382d2SGreg Kroah-Hartman module_init(imx_serial_init); 2485ab4382d2SGreg Kroah-Hartman module_exit(imx_serial_exit); 2486ab4382d2SGreg Kroah-Hartman 2487ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2488ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2489ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2490ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2491